Bit Allocation Method, Device, Equipment and Medium for LED Dual-Latch Chip

Abstract

The embodiments of the present invention disclose a bit allocation method, device, equipment and medium for an LED dual-latch chip, belonging to the technical field of LED display. Among them, the method includes: determining the number of sub-frame disassembly segments according to the control parameters of the target dual-latch chip; wherein, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reservation time and reservation width; determining a plurality of target gray bits according to the gray level of the target dual-latch chip, and determining the corresponding number of sub-frames associated with each target gray bit based on the refresh magnification and the number of sub-frame disassembly segments of the target dual-latch chip; performing bit allocation on the target dual-latch chip according to the corresponding number of sub-frames, refresh magnification and number of sub-frame disassembly segments. This technical solution can effectively improve the photographing and display effects of the dual-latch chip by adopting the multi-bit disassembly method, solve the problems of poor photographing effect and uneven display effect of the dual-latch chip, so as to better meet the user's requirements for the display effect.

Description

Technical Field

[0001] The present invention relates to the technical field of LED display, and particularly to a bit allocation method, device, equipment and medium for an LED dual-latch chip. Background Art

[0002] LED (Light Emitting Diode) display technology plays a crucial role in modern information dissemination and visual display with its high brightness, high definition, energy conservation and environmental protection, as well as flexible and variable display modes. As a column drive chip, the dual-latch chip ensures the picture quality by providing stable current control and precise brightness adjustment, promoting the further development of LED display technology.

[0003] For the dual-latch chip, the traditional display scheme is to cooperate high-order data and low-order data. After the high-order data transmission is completed, an LE (data latch) signal is generated to latch the high-order data, then the OE (display data enable) signal is turned on to start displaying the high-order data, and while the high-order data is being displayed, the low-order data is transmitted. After the low-order data transmission is completed, the low-order data is latched and the low-order data is started to be displayed, that is, the extra time for displaying the high-order data is utilized to transmit the low-order data.

[0004] However, adopting the dual-latch method of combining high-order data and low-order data pairwise will result in a large difference between the high-order data and the low-order data. Due to the low refresh rate, obvious horizontal stripes can be seen when taking pictures with a mobile phone or camera with a high frame rate, causing problems of poor photo-taking effect and uneven display effect, and unable to meet the user's requirements for the display effect. Summary of the Invention

[0005] The present invention provides a bit allocation method, device, equipment and medium for an LED dual-latch chip, which can effectively improve the photo-taking and display effects of the dual-latch chip by adopting a multi-bit scattering method, solve the problems of poor photo-taking effect and uneven display effect of the dual-latch chip, so as to better meet the user's requirements for the display effect.

[0006] According to one aspect of the present invention, there is provided a bit allocation method for an LED dual-latch chip, the method comprising:

[0007] Determining the number of sub-frame scattering segments according to the control parameters of the target dual-latch chip; wherein, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reserved time and reserved width;

[0008] Determining a plurality of target gray bits according to the gray level of the target dual-latch chip, and determining the corresponding number of sub-frames associated with each target gray bit based on the refresh magnification of the target dual-latch chip and the number of sub-frame scattering segments;

[0009] Perform bit allocation for the target dual-latch chip according to the corresponding number of sub-frames, the refresh magnification, and the number of sub-frame fragmentation segments.

[0010] According to another aspect of the present invention, there is provided a bit allocation device for an LED dual-latch chip, the device comprising:

[0011] A sub-frame fragmentation segment number determination module, configured to determine the number of sub-frame fragmentation segments according to the control parameters of the target dual-latch chip; wherein, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reserved time, and reserved width;

[0012] A sub-frame corresponding number determination module, configured to determine a plurality of target gray bits according to the gray level of the target dual-latch chip, and determine the corresponding number of sub-frames associated with each target gray bit based on the refresh magnification of the target dual-latch chip and the number of sub-frame fragmentation segments;

[0013] A chip bit allocation module, configured to perform bit allocation for the target dual-latch chip according to the corresponding number of sub-frames, the refresh magnification, and the number of sub-frame fragmentation segments.

[0014] According to another aspect of the present invention, there is provided an electronic device, the electronic device comprising:

[0015] At least one processor; and,

[0016] A memory communicatively connected to the at least one processor; wherein,

[0017] The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the bit allocation method for the LED dual-latch chip according to any embodiment of the present invention.

[0018] According to another aspect of the present invention, there is provided a computer-readable storage medium, the computer-readable storage medium stores computer instructions, and the computer instructions are used to implement the bit allocation method for the LED dual-latch chip according to any embodiment of the present invention when executed by a processor.

[0019] The technical solution of the embodiment of the present invention determines the number of sub-frame fragmentation segments according to the control parameters of the target dual-latch chip; wherein, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reserved time, and reserved width; determines a plurality of target gray bits according to the gray level of the target dual-latch chip, and determines the corresponding number of sub-frames associated with each target gray bit based on the refresh magnification and the number of sub-frame fragmentation segments of the target dual-latch chip; performs bit allocation on the target dual-latch chip according to the corresponding number of sub-frames, refresh magnification, and number of sub-frame fragmentation segments. This technical solution can adopt the multi-bit fragmentation method to reduce the display time difference of data of different bits, thereby effectively improving the photographing and display effects of the dual-latch chip, solving the problems of poor photographing effect and uneven display effect of the dual-latch chip, so as to better meet the user's requirements for the display effect.

[0020] It should be understood that the content described in this part is not intended to identify the key or important features of the embodiments of the present invention, nor is it used to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0022] Figure 1 is a flowchart of a method for bit allocation of an LED dual-latch chip according to Embodiment 1 of the present invention;

[0023] Figure 2 is a flowchart of a method for bit allocation of an LED dual-latch chip according to Embodiment 2 of the present invention;

[0024] Figure 3 is a schematic structural diagram of a device for bit allocation of an LED dual-latch chip according to Embodiment 3 of the present invention;

[0025] Figure 4 is a schematic structural diagram of an electronic device for implementing the method for bit allocation of an LED dual-latch chip according to the embodiment of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0026] To enable those skilled in the art to better understand the solution of the present invention, the following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present invention.

[0027] It should be noted that the terms "first", "second", "target", etc. in the description and claims of the present invention and the above-mentioned accompanying drawings are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system, product or device comprising a series of steps or units does not necessarily have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.

[0028] Embodiment 1

[0029] Figure 1 It is a flowchart of a bit allocation method for an LED dual-latch chip provided in Embodiment 1 of the present invention. This embodiment is applicable to the situation of improving the photographing and display effects of a dual-latch chip by means of multi-bit scattering. This method can be executed by a bit allocation device of the LED dual-latch chip. The bit allocation device of the LED dual-latch chip can be implemented in the form of hardware and / or software, and the bit allocation device of the LED dual-latch chip can be configured in an electronic device with data processing capabilities. As Figure 1 shown, the method includes:

[0030] S110. Determine the number of sub-frame scattering segments according to the control parameters of the target dual-latch chip.

[0031] Among them, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reserved time, and reserved width. Specifically, the clock frequency refers to the clock frequency of the serial input clock, that is, the clock frequency corresponding to data transmission; the data width refers to the width size of the module (display single board); the number of scans refers to the maximum number of rows carried by a set of data, which is generally related to the number of row chips; the synchronous reserved time refers to the rest time between frames, which can be understood as the fault tolerance time corresponding to the clock frequency; the reserved width can be understood as the fault tolerance width corresponding to the data width. The number of segments for sub-frame disaggregation can be understood as the highest number of segments that each sub-frame can be disaggregated into. Among them, the number of sub-frames (i.e., the refresh magnification) can be used to describe how many small sub-frames can be divided in one frame. For example, when the refresh magnification is 16, that is, the number of sub-frames is 16, indicating that one frame can be divided into 16 small sub-frames.

[0032] It should be noted that each control parameter can be set according to actual needs, and this embodiment does not make specific limitations on this. Exemplarily, the control parameters can be set as follows: the frame frequency is 60Hz, the clock frequency is 12.5Mhz, the data width is 64, the number of scans is 32, the synchronous reserved time is 26667ns, and the reserved width is 4. In addition, the higher the clock frequency, the larger the data volume, and the more segments each sub-frame can be disaggregated into.

[0033] In this embodiment, first, the control parameters of the target dual-latch chip are obtained, and then the number of segments for sub-frame disaggregation is determined according to the control parameters of the target dual-latch chip. Optionally, determining the number of segments for sub-frame disaggregation according to the control parameters of the target dual-latch chip includes: determining a first parameter according to the difference between the reciprocal of the frame frequency and the synchronous reserved time; determining a second parameter according to the sum of the data width and the reserved width; determining a third parameter according to the product of the reciprocal of the clock frequency, the number of scans, and the second parameter; determining the number of segments for sub-frame disaggregation according to the ratio of the first parameter to the third parameter.

[0034] Among them, the reciprocal of the frame frequency is the display time of one frame. For example, when the frame frequency is 60Hz, the display time of one frame is 1 / 60Hz = 16.6ms. The reciprocal of the clock frequency is the clock cycle time. For example, when the clock frequency is 12.5Mhz, the clock cycle time is 1 / 12.5Mhz = 80ns.

[0035] Exemplarily, the number of segments for sub-frame disaggregation can be determined by the following formula:

[0036] ;

[0037] Among them, represents the number of segments for sub-frame disaggregation, represents the reciprocal of the frame frequency (i.e., the display time of one frame), represents the synchronous reserved time, represents the number of scans, Represents the reciprocal of the clock frequency (i.e., the clock cycle time), Represents the data width, Represents the reserved width, Represents for Floor down, Represents the first parameter, Represents the second parameter, Represents the third parameter.

[0038] Through such settings in this solution, the highest number of segments that each sub-frame can be broken into (i.e., the sub-frame break-up segment number) can be quickly determined.

[0039] S120. Determine multiple target gray bits according to the gray level of the target dual-latch chip, and determine the corresponding number of sub-frames associated with each target gray bit based on the refresh magnification of the target dual-latch chip and the sub-frame break-up segment number.

[0040] In this embodiment, it is necessary to obtain the gray level of the target dual-latch chip and determine multiple target gray bits according to this gray level. Exemplarily, assuming the gray level is 12bit, then each target gray bit can be determined as bit0, bit1, …, bit10, bit11. After determining multiple target gray bits, the corresponding number of sub-frames associated with each target gray bit can be further determined based on the refresh magnification of the target dual-latch chip and the sub-frame break-up segment number. Among them, the corresponding number of sub-frames can be used to describe how many sub-frames the target gray bit associated with it occupies in a frame of picture data. Exemplarily, assuming the corresponding number of sub-frames associated with bit11 is 32, it indicates that bit11 occupies 32 sub-frames in a frame of picture data.

[0041] In this embodiment, optionally, determining the corresponding number of sub-frames associated with each target gray bit based on the refresh magnification of the target dual-latch chip and the sub-frame break-up segment number includes: determining the total number of segments corresponding to the refresh magnification according to the product of the refresh magnification and the sub-frame break-up segment number; determining the corresponding number of sub-frames associated with each target gray bit based on a preset limit condition; where the preset limit condition includes that the corresponding number of sub-frames associated with the subsequent target gray bit among adjacent target gray bits is greater than or equal to the corresponding number of sub-frames associated with the previous target gray bit, the OE multiple corresponding to the subsequent target gray bit among adjacent target gray bits is greater than or equal to the OE multiple corresponding to the previous target gray bit, the sum of the corresponding numbers of sub-frames associated with each target gray bit is less than or equal to the total number of segments corresponding to the refresh magnification, the total OE width corresponding to the subsequent target gray bit among adjacent target gray bits is twice the total OE width corresponding to the previous target gray bit, the total OE width is determined based on the product of the OE multiple, the corresponding number of sub-frames, and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

[0042] Among them, the preset limitation condition can refer to the limitation condition preset according to the actual situation for solving the corresponding number of sub - frames associated with the target gray - level bit. The previous target gray - level bit and the subsequent target gray - level bit can respectively refer to the smaller target gray - level bit and the larger target gray - level bit among adjacent target gray - level bits. Exemplarily, for a pair of adjacent target gray - level bits bit10 and bit11, since bit10 < bit11, bit10 can be determined as the previous target gray - level bit and bit11 can be determined as the subsequent target gray - level bit. OE is the display data enable signal. The minimum OE width can refer to the OE width corresponding to the unit emission time. The OE multiple refers to the multiple of the minimum OE width. The total OE width can be expressed as the product of the OE multiple, the corresponding number of sub - frames, and the minimum OE width.

[0043] Specifically, when determining the corresponding number of sub - frames associated with each target gray - level bit, first multiply the refresh magnification by the number of sub - frame fragmentation segments, and use the product as the total number of segments corresponding to the refresh magnification. Exemplarily, assume that the refresh magnification is 16 and the number of sub - frame fragmentation segments is 6, then the total number of segments corresponding to the refresh magnification can be determined as 16×6 = 96.

[0044] After determining the total number of segments corresponding to the refresh magnification, the corresponding number of sub - frames associated with each target gray - level bit can be determined based on the following four preset limitation conditions: 1. The corresponding number of sub - frames associated with the subsequent target gray - level bit among adjacent target gray - level bits is greater than or equal to the corresponding number of sub - frames associated with the previous target gray - level bit (for example, the corresponding number of sub - frames associated with bit11 ≥ the corresponding number of sub - frames associated with bit10); 2. The OE multiple corresponding to the subsequent target gray - level bit among adjacent target gray - level bits is greater than or equal to the OE multiple corresponding to the previous target gray - level bit (for example, the OE multiple corresponding to bit11 ≥ the OE multiple corresponding to bit10); 3. The sum of the corresponding number of sub - frames associated with each target gray - level bit is less than or equal to the total number of segments corresponding to the refresh magnification (for example, the target gray - level bits are bit0…bit11, and the total number of segments corresponding to the refresh magnification is 96, then the sum of the corresponding number of sub - frames associated with bit0…bit11 ≤ 96), which can ensure that the data corresponding to each target gray - level bit can be displayed in one frame; 4. The total OE width corresponding to the subsequent target gray - level bit among adjacent target gray - level bits is equal to twice the total OE width corresponding to the previous target gray - level bit (for example, the total OE width corresponding to bit11 = the total OE width corresponding to bit10×2).

[0045] Exemplarily, assume that the gray - level is 12bit, the refresh magnification is 16, and the number of sub - frame fragmentation segments is 6. Then the corresponding number of sub - frames associated with each target gray - level bit (i.e., bit0…bit11) is shown in Table 1:

[0046] Table 1 Association between Target Gray Bits and Corresponding Number of Sub - frames

[0047]

[0048] It should be noted that the data in Table 1 above is only for illustration purposes and does not play any restrictive role. If multiple groups of associations between target gray bits and the corresponding number of sub - frames are determined based on the above four preset restrictive conditions, then a random method or other preset methods can be used to select one group of associations as the final association, and the corresponding number of sub - frames associated with each target gray bit can be determined according to the final association.

[0049] In addition, in the above - mentioned 4th preset restrictive condition, only the double - relationship of the total OE width of adjacent target gray bits is used, and the total OE width = OE multiple × corresponding number of sub - frames × minimum OE width. Among them, the OE multiple and the corresponding number of sub - frames may change with different target gray bits, but the minimum OE width corresponding to different target gray bits will always remain unchanged (equal to 1 when making a ratio), and the minimum OE width needs to be calculated separately. At this time, in order to reduce the computational complexity, there is no need to calculate the specific value of the minimum OE width, that is, there is no need to calculate the specific value of the total OE width of each target gray bit, and it is only necessary to ensure that the product of the OE multiple and the corresponding number of sub - frames of adjacent target gray bits satisfies the double - relationship. Exemplarily, taking Table 1 above as an example, the total OE width corresponding to bit11 = 64×32×Toe, and the total OE width corresponding to bit10 = 64×16×Toe, where Toe represents the minimum OE width. At this time, the ratio of the total OE width corresponding to bit11 to that corresponding to bit10 can be obtained as 64×32×Toe / (64×16×Toe)=2, that is, the total OE width corresponding to bit11 is twice that corresponding to bit10.

[0050] S130, perform bit allocation on the target dual - latch chip according to the corresponding number of sub - frames, refresh magnification, and number of sub - frame disassembly segments.

[0051] In this embodiment, after determining the corresponding number of sub-frames associated with each target gray bit, the target dual-latch chip can be bit-allocated according to the corresponding number of sub-frames, the refresh magnification, and the number of sub-frame scattering segments. Specifically, first, determine the proportion of the data corresponding to each target gray bit in the total number of sub-frames according to the corresponding number of sub-frames associated with each target gray bit and the refresh magnification. Then, perform bit-allocation on the target dual-latch chip according to the proportion and the preset arrangement rule, so as to determine the gray bit data of each segment corresponding to the number of sub-frame scattering segments in each sub-frame. Among them, the preset arrangement rule can be used to describe the arrangement method of the gray bit data of each segment corresponding to the number of sub-frame scattering segments in each sub-frame. Exemplarily, the preset arrangement rule can be set that the high-gray-bit data and the low-gray-bit data are arranged alternately, and the sum of the differences of the gray bit data of each segment is minimized.

[0052] Exemplarily, taking the data in Table 1 above as an example, the corresponding number of sub-frames associated with bit11 is 32, which indicates that bit11 occupies 32 sub-frames in one frame of picture data. Since the refresh magnification is 16 (i.e., the number of sub-frames is 16), that is, the corresponding number of sub-frames associated with bit11 is twice the refresh magnification. At this time, two bit11 data need to be allocated in each sub-frame. The corresponding number of sub-frames associated with bit9 and bit10 are both 16, which indicates that bit9 and bit10 both occupy 16 sub-frames in one frame of picture data. That is, the corresponding number of sub-frames associated with bit9 and bit10 is equal to the refresh magnification. At this time, one bit9 and one bit10 data need to be allocated in each sub-frame. The corresponding number of sub-frames associated with bit7 and bit8 are both 8, which indicates that bit7 and bit8 both occupy 8 sub-frames in one frame of picture data. That is, the corresponding number of sub-frames associated with bit7 and bit8 is half of the refresh magnification. At this time, one bit7 and one bit8 data need to be allocated in every two sub-frames. In this case, the odd-even frame method can be used for arrangement. The corresponding number of sub-frames associated with bit6 is 4, which indicates that bit6 occupies 4 sub-frames in one frame of picture data. That is, the corresponding number of sub-frames associated with bit6 is 1 / 4 of the refresh magnification. At this time, one bit6 data needs to be allocated in every four sub-frames. The arrangement methods of bit5-bit0 are similar.

[0053] Exemplarily, taking the gray level of 12 bits, the refresh magnification of 16, and the number of sub-frame scattering segments of 6 as an example, the following method can be used to determine the gray bit data of each segment corresponding to each sub-frame:

[0054]

[0055] Among them, the low-order bit represents one of bit0-bit6, and bit7 / bit8 represents one of the two and is arranged in an odd-even frame manner. It can be understood that in the 16 sub-frames, the gray-scale bit data corresponding to each sub-frame may be the same or different, and specifically needs to be determined according to the actual situation.

[0056] In the technical solution of the embodiment of the present invention, the number of sub-frame scattered segments is determined according to the control parameters of the target dual-latch chip; wherein, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reserved time, and reserved width; multiple target gray-scale bits are determined according to the gray-scale level of the target dual-latch chip, and the corresponding number of sub-frames associated with each target gray-scale bit is determined based on the refresh magnification of the target dual-latch chip and the number of sub-frame scattered segments; bit allocation is performed on the target dual-latch chip according to the corresponding number of sub-frames, refresh magnification, and number of sub-frame scattered segments. This technical solution can optimize the traditional two-segment gray-scale bit combination into a multi-segment gray-scale bit combination by using the multi-bit scattered method, thereby reducing the display time gap of different bit data, effectively improving the photographing and display effects of the dual-latch chip, solving the problems of poor photographing effect and uneven display effect of the dual-latch chip, and better meeting the user's requirements for the display effect.

[0057] In this embodiment, optionally, the determination method of the minimum OE width includes: determining a first parameter according to the difference between the reciprocal of the frame frequency and the synchronous reserved time; determining the maximum OE multiple corresponding to the number of sub-frame scattered segments according to the bit allocation result; determining a fourth parameter according to the product of the number of scans, refresh magnification, and maximum OE multiple; and determining the minimum OE width according to the ratio of the first parameter to the fourth parameter.

[0058] Specifically, when calculating the minimum OE width, first calculate the reciprocal of the frame frequency (i.e., the display time of one frame), then subtract the synchronous reserved time from the reciprocal of the frame frequency, and use the difference as the first parameter. Then, according to the bit allocation result, determine the maximum gray-scale bit combination corresponding to the number of sub-frame scattered segments, and add up the OE multiples corresponding to the maximum gray-scale bit combination and multiply by 2 to obtain the maximum OE multiple. Exemplarily, taking the gray-scale level of 12 bits and the number of sub-frame scattered segments of 6 as an example, the maximum gray-scale bit combination can be determined as bit11, bit6, bit11, bit8, bit10, and bit9. Combining the data in Table 1 above, the maximum OE multiple can be calculated as Toe_max=(64 + 16 + 64 + 32 + 64 + 32)×2 = 544. Further, multiply the number of scans, refresh magnification, and maximum OE multiple to obtain the fourth parameter, and finally determine the ratio of the first parameter to the fourth parameter as the minimum OE width.

[0059] Through such settings, the minimum OE width of the target dual-latch chip can be quickly determined, so as to control the opening and closing widths of OE based on the minimum OE width, the OE multiples corresponding to each target gray bit, and the invalid OE multiples, thereby controlling the display of data of each target gray bit according to the opening and closing widths of OE.

[0060] Embodiment 2

[0061] Figure 2 The figure is a flowchart of a bit allocation method for an LED dual-latch chip provided in Embodiment 2 of the present invention. This embodiment is optimized based on the above embodiment. The specific optimization is as follows: after performing bit allocation on the target dual-latch chip according to the number of sub-frames, the refresh magnification, and the number of sub-frame disassembly segments, it further includes: converting the bit allocation result into scan table data by using a preset conversion method; sending the scan table data to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

[0062] As Figure 2 shown, the method of this embodiment specifically includes the following steps:

[0063] S210, determining the number of sub-frame disassembly segments according to the control parameters of the target dual-latch chip.

[0064] Among them, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronous reservation time, and reservation width.

[0065] S220, determining a plurality of target gray bits according to the gray level of the target dual-latch chip, and determining the number of sub-frames corresponding to each target gray bit associated based on the refresh magnification and the number of sub-frame disassembly segments of the target dual-latch chip.

[0066] S230, performing bit allocation on the target dual-latch chip according to the number of sub-frames corresponding, the refresh magnification, and the number of sub-frame disassembly segments.

[0067] Among them, the specific implementation manners of S210-S230 can refer to the relevant descriptions of Embodiment 1 above, and will not be elaborated here.

[0068] S240, converting the bit allocation result into scan table data by using a preset conversion method.

[0069] Among them, the preset conversion method can refer to a data format conversion method preset according to actual requirements, and can be specifically set based on the data reception characteristics of the receiving card. Exemplarily, binary data that can be processed by a host computer (such as a PC) can be converted into hexadecimal data. For example, the converted scan table data is as follows:

[0070]

[0071] Among them, in hexadecimal data, bits 15 - 12 represent gray bits (e.g., bit11 corresponds to B in hexadecimal), bits 11 - 8 represent the invalid OE multiple, bit 2 is the sub - frame end flag, and bit 0 is the frame end flag. Among them, the invalid OE multiple can be expressed as the difference between the maximum gray bit and the current gray bit. Exemplarily, taking 12 - bit gray scale as an example, the maximum gray bit is bit11. If the current gray bit is bit6, then the invalid OE multiple corresponding to bit6 can be determined as 11 - 6 = 5.

[0072] It should be noted that if the binary data directly processed by the host computer is used for data transmission, it may lead to a slow data transmission speed due to the large amount of data transmission, and it will cause waste of transmission resources. To address the above problems, in this embodiment, a preset conversion method is used to perform data format conversion on the bit allocation result to obtain scan table data, thereby effectively reducing the amount of data transmission, improving the data transmission efficiency, and reducing resource waste at the same time.

[0073] S250, send the scan table data to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

[0074] In this embodiment, after obtaining the scan table data, the scan table data can be sent to the sending card through a serial port instruction, and then packaged into network port data by the sending card and forwarded to the receiving card. Exemplarily, the scan table data can be sent to the sending card in the RGB888 format through a DVI interface. After receiving the network port data, the receiving card first parses the network port data to obtain the scan table data, and then outputs the corresponding data to the scan control module of the receiving card according to the corresponding gray bit. The scan control module can finally determine the width of OE opening and closing based on the gray bit and the invalid OE multiple parsed from the scan table and the minimum OE width issued by the host computer, so as to control the display of each gray bit data based on the width of OE opening and closing.

[0075] The technical solution of the embodiment of the present invention, after performing bit allocation on the target dual - latch chip according to the corresponding number of sub - frames, the refresh multiple, and the number of sub - frame disassembly segments, uses a preset conversion method to perform data format conversion on the bit allocation result to obtain scan table data; sends the scan table data to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card. This technical solution can effectively reduce the amount of data transmission, improve the data transmission efficiency, and reduce resource waste by performing data format conversion operations on the bit allocation result, and forwards the converted data to the receiving card through the sending card, so that the receiving card controls the display of each gray bit data.

[0076] Embodiment Three

[0077] Figure 3 The structural schematic diagram of a bit allocation device for an LED dual-latch chip provided in Embodiment 3 of the present invention. This device can execute the bit allocation method of the LED dual-latch chip provided in any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method. As Figure 3 shown, the device includes:

[0078] A sub-frame disassembly segment number determination module 310, configured to determine the number of sub-frame disassembly segments according to the control parameters of the target dual-latch chip; wherein, the control parameters include frame frequency, clock frequency, data width, number of scans, synchronization reservation time, and reservation width;

[0079] A sub-frame corresponding number determination module 320, configured to determine a plurality of target gray bits according to the gray level of the target dual-latch chip, and determine the number of sub-frames corresponding to each target gray bit based on the refresh magnification of the target dual-latch chip and the number of sub-frame disassembly segments;

[0080] A chip bit allocation module 330, configured to perform bit allocation on the target dual-latch chip according to the number of sub-frames corresponding, the refresh magnification, and the number of sub-frame disassembly segments.

[0081] Optionally, the sub-frame disassembly segment number determination module 310 is configured to:

[0082] Determine a first parameter according to the difference between the reciprocal of the frame frequency and the synchronization reservation time;

[0083] Determine a second parameter according to the sum of the data width and the reservation width;

[0084] Determine a third parameter according to the product of the reciprocal of the clock frequency, the number of scans, and the second parameter;

[0085] Determine the number of sub-frame disassembly segments according to the ratio of the first parameter to the third parameter.

[0086] Optionally, the sub-frame corresponding number determination module 320 is configured to:

[0087] Determine the total number of segments corresponding to the refresh magnification according to the product of the refresh magnification and the number of sub-frame disassembly segments;

[0088] Determine the number of sub-frames corresponding to each target gray bit based on a preset limitation condition;

[0089] Among them, the preset limiting conditions include that the corresponding number of sub-frames associated with the subsequent target gray bit among adjacent target gray bits is greater than or equal to the corresponding number of sub-frames associated with the previous target gray bit, the OE multiple corresponding to the subsequent target gray bit among adjacent target gray bits is greater than or equal to the OE multiple corresponding to the previous target gray bit, the sum of the corresponding numbers of sub-frames associated with each target gray bit is less than or equal to the total number of segments corresponding to the refresh magnification, and the total OE width corresponding to the subsequent target gray bit among adjacent target gray bits is twice the total OE width corresponding to the previous target gray bit. The total OE width is determined based on the product of the OE multiple, the corresponding number of sub-frames, and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

[0090] Optionally, the device further includes: a minimum OE width determination module, configured to:

[0091] Determine a first parameter according to the difference between the reciprocal of the frame frequency and the synchronization reserved time;

[0092] Determine the maximum OE multiple corresponding to the number of sub-frame scattered segments according to the bit allocation result;

[0093] Determine a fourth parameter according to the product of the number of scans, the refresh magnification, and the maximum OE multiple;

[0094] Determine the minimum OE width according to the ratio of the first parameter to the fourth parameter.

[0095] Optionally, the device further includes: a bit allocation result processing module, configured to:

[0096] After performing bit allocation on the target dual-latch chip according to the corresponding number of sub-frames, the refresh magnification, and the number of sub-frame scattered segments, perform data format conversion on the bit allocation result by using a preset conversion method to obtain scan table data;

[0097] Send the scan table data to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

[0098] The bit allocation device of an LED dual-latch chip provided by an embodiment of the present invention can execute the bit allocation method of an LED dual-latch chip provided by any embodiment of the present invention, and has corresponding functional modules and beneficial effects for executing the method.

[0099] Embodiment 4

[0100] Figure 4The structural schematic diagram of the electronic device 10 that can be used to implement the embodiments of the present invention is shown. The electronic device is intended to represent various forms of digital computers, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as personal digital processors, cellular phones, smart phones, wearable devices (such as helmets, glasses, watches, etc.) and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely examples and are not intended to limit the implementation of the present invention described and / or claimed herein.

[0101] As Figure 4 shown, the electronic device 10 includes at least one processor 11, and a memory communicatively connected to the at least one processor 11, such as a read-only memory (ROM) 12, a random access memory (RAM) 13, etc. Among them, the memory stores a computer program executable by the at least one processor. The processor 11 can perform various appropriate actions and processes according to the computer program stored in the read-only memory (ROM) 12 or the computer program loaded from the storage unit 18 into the random access memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 can also be stored. The processor 11, the ROM 12, and the RAM 13 are connected to each other through a bus 14. The input / output (I / O) interface 15 is also connected to the bus 14.

[0102] Multiple components in the electronic device 10 are connected to the I / O interface 15, including: an input unit 16, such as a keyboard, a mouse, etc.; an output unit 17, such as various types of displays, speakers, etc.; a storage unit 18, such as a magnetic disk, an optical disc, etc.; and a communication unit 19, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information / data with other devices through a computer network such as the Internet and / or various telecommunication networks.

[0103] The processor 11 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the processor 11 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various processors running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The processor 11 executes the various methods and processes described above, such as the bit allocation method of the LED dual-latch chip.

[0104] In some embodiments, the bit allocation method of the LED dual-latch chip can be implemented as a computer program tangibly embodied in a computer-readable storage medium, such as storage unit 18. In some embodiments, part or all of the computer program can be loaded and / or installed onto the electronic device 10 via the ROM 12 and / or the communication unit 19. When the computer program is loaded into the RAM 13 and executed by the processor 11, one or more steps of the above-described bit allocation method of the LED dual-latch chip can be performed. Alternatively, in other embodiments, the processor 11 can be configured to perform the bit allocation method of the LED dual-latch chip by any other suitable means (e.g., by means of firmware).

[0105] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGA), application specific integrated circuits (ASIC), application specific standard products (ASSP), system on a chip (SOC), complex programmable logic devices (CPLD), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that can be executed and / or interpreted on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0106] The computer program for implementing the method of the present invention can be written in any combination of one or more programming languages. These computer programs can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the computer program is executed by the processor, the functions / operations specified in the flowchart and / or block diagram are implemented. The computer program can be executed entirely on the machine, partially on the machine, as a stand-alone software package partially on the machine and partially on a remote machine, or entirely on a remote machine or server.

[0107] In the context of the present invention, a computer-readable storage medium can be a tangible medium that can contain or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer-readable storage medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. Alternatively, the computer-readable storage medium can be a machine-readable signal medium. More specific examples of the machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or Flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

[0108] In order to provide interaction with a user, the systems and techniques described herein can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to the user; and a keyboard and a pointing device (e.g., a mouse or a trackball) by which the user can provide input to the electronic device. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, speech input, or tactile input).

[0109] The systems and techniques described herein can be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), blockchain network, and the Internet.

[0110] A computing system may include a client and a server. The client and the server are generally far from each other and usually interact via a communication network. The client-server relationship is created by computer programs running on respective computers and having a client-server relationship with each other. The server can be a cloud server, also known as a cloud computing server or a cloud host, which is a host product in the cloud computing service system, solving the defects of difficult management and weak business scalability existing in traditional physical hosts and VPS services.

[0111] It should be understood that various forms of the processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in the present invention can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of the present invention can be achieved, and no limitation is made herein.

[0112] The above specific embodiments do not constitute a limitation on the protection scope of the present invention. Those skilled in the art should understand that various modifications, combinations, sub-combinations, and substitutions can be made according to design requirements and other factors. Any modifications, equivalent substitutions, and improvements made within the spirit and principle of the present invention shall be included within the protection scope of the present invention.

Claims

1. A bit allocation method for an LED dual latch chip, characterized in that: The method comprises: Determine the number of subframe fragmentation segments according to the control parameters of the target dual latch chip; wherein the control parameters include frame rate, clock frequency, data width, scan number, synchronization reserved time and reserved width; Determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments; Allocate bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments; The number of subframe fragmentation segments is determined according to the control parameters of the target dual latch chip, including: Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time; Determine a second parameter according to the sum of the data width and the reserved width; determining a third parameter according to the product of the reciprocal of the clock frequency, the scan number and the second parameter; The number of subframe fragmentation segments is determined according to the ratio of the first parameter to the third parameter.

2. The method according to claim 1, characterized in that Determining the corresponding number of subframes associated with each target grayscale bit based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments includes: Determine the total number of segments corresponding to the refresh rate according to the product of the refresh rate and the number of segments of the subframes; Determine the corresponding number of subframes associated with each of the target grayscale bits based on a preset restriction condition; Among them, the preset restriction conditions include that the corresponding number of subframes associated with the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bits, the OE multiple corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bits, the sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate, and the total OE width corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bits, and the total OE width is determined based on the product of the OE multiple, the corresponding number of subframes and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

3. The method according to claim 2, characterized in that The minimum OE width is determined by: Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time; Determine the maximum OE multiple corresponding to the number of subframe fragmentation segments according to the bit allocation result; Determine a fourth parameter according to the product of the scan number, the refresh rate and the maximum OE multiple; The minimum OE width is determined according to the ratio of the first parameter to the fourth parameter.

4. The method according to any one of claims 1 to 3, characterized in that After allocating bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments, the method further includes: Using a preset conversion method to convert the bit allocation result into a data format to obtain scan table data; The scan table data is sent to the sending card through a serial port instruction, so that the sending card converts the scan table data into network port data and sends it to the receiving card.

5. A bit allocation device for a LED dual latch chip, characterized in that: The device comprises: A subframe scattering segment number determination module is used to determine the subframe scattering segment number according to the control parameters of the target dual latch chip; wherein the control parameters include frame frequency, clock frequency, data width, scan number, synchronization reserved time and reserved width; A subframe corresponding number determination module, used to determine a plurality of target grayscale bits according to the grayscale level of the target dual latch chip, and determine the corresponding number of subframes associated with each of the target grayscale bits based on the refresh rate of the target dual latch chip and the number of subframe fragmentation segments; A chip bit allocation module, used for allocating bits to the target dual latch chip according to the corresponding number of subframes, the refresh rate and the number of subframe fragmentation segments; The subframe fragmentation segment number determination module is used to: Determine a first parameter according to a difference between the reciprocal of the frame rate and the synchronization reserved time; Determine a second parameter according to the sum of the data width and the reserved width; determining a third parameter according to the product of the reciprocal of the clock frequency, the scan number and the second parameter; The number of subframe fragmentation segments is determined according to the ratio of the first parameter to the third parameter.

6. The device according to claim 5, characterized in that The subframe corresponding quantity determination module is used to: Determine the total number of segments corresponding to the refresh rate according to the product of the refresh rate and the number of segments of the subframes; Determine the corresponding number of subframes associated with each of the target grayscale bits based on a preset restriction condition; Among them, the preset restriction conditions include that the corresponding number of subframes associated with the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the corresponding number of subframes associated with the previous target grayscale bits, the OE multiple corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is greater than or equal to the OE multiple corresponding to the previous target grayscale bits, the sum of the corresponding numbers of subframes associated with each target grayscale bit is less than or equal to the total number of segments corresponding to the refresh rate, and the total OE width corresponding to the subsequent target grayscale bits in adjacent target grayscale bits is equal to twice the total OE width corresponding to the previous target grayscale bits, and the total OE width is determined based on the product of the OE multiple, the corresponding number of subframes and the minimum OE width, and the OE multiple is a multiple of the minimum OE width.

7. An electronic device, characterized in that: The electronic device comprises: at least one processor; and, a memory communicatively connected to the at least one processor; wherein, The memory stores a computer program executable by the at least one processor, and the computer program is executed by the at least one processor so that the at least one processor can execute the bit allocation method for the LED dual latch chip according to any one of claims 1 to 4.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the bit allocation method of the LED dual-latch chip according to any one of claims 1 to 4 when executed.

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