Display panel and electronic device

Abstract

This application provides a display panel and an electronic device that can reduce power consumption. The display panel includes multiple screen update cycles and multiple pixels. The screen update cycle includes a reset, data writing, and light emission phases. The reset phase includes a selection sub-phase and a reset sub-phase. Each pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit includes a pixel driving module, a gating module, a control module, a data signal terminal, and a reset signal terminal. The gating module is electrically connected to both the control module and the pixel driving module. The control module is electrically connected to the data signal terminal. In the selection sub-phase, the control module controls the gating module to be turned on or off according to the data signal written by the data signal terminal. When the gating module is turned on, in the reset sub-phase, a reset signal resets the pixel driving module. In the data writing phase, the data signal is written to the pixel driving module, and the pixel driving module generates a driving current. In the light emission phase, the driving current is provided to the light-emitting element.

Description

Technical Field

[0001] This application relates to the field of display technology, and more particularly to a display panel and an electronic device. Background Technology

[0002] The main component of an electronic device that enables display functionality is the display panel. The display panel includes a display area and a non-display area. The display area comprises multiple pixels arranged in an array. Each pixel includes a pixel driving circuit and a light-emitting element. The pixel driving circuit drives the light-emitting element to emit light, displaying images or videos. The non-display area is equipped with a scan driving circuit, which provides scan signals to the pixel driving circuit, causing the light-emitting elements to light up line by line under the drive of the pixel driving circuit.

[0003] Currently, electronic devices typically display images with the same refresh rate across all areas, meaning all pixels in the display area refresh at the same frequency. This results in relatively high power consumption for the display panel, which is detrimental to improving the battery life of electronic devices and reduces the user experience. Summary of the Invention

[0004] To address the aforementioned technical problems, this application provides a display panel and an electronic device that can reduce power consumption.

[0005] In a first aspect, embodiments of this application provide a display panel, which includes: a plurality of pixels, each pixel including a pixel driving circuit and a light-emitting element; the pixel driving circuit includes a pixel driving module, a gating module, a control module, a data signal terminal, and a reset signal terminal, the gating module being electrically connected to the control module and the pixel driving module respectively, and the control module being electrically connected to the data signal terminal; the data signal terminal being used to transmit data signals; the reset signal terminal being used to transmit reset signals; the display panel also includes a plurality of screen update cycles, each screen update cycle including a reset phase, a data writing phase, and a light-emitting phase; the reset phase including a selection sub-phase and a reset sub-phase; in the selection sub-phase, the control module is used to control the gating module to be turned on or off according to the data signal written by the data signal terminal; when the gating module is turned on, in the reset sub-phase, a reset signal is written to the pixel driving module to reset the pixel driving module; in the data writing phase, a data signal is written to the pixel driving module to generate a driving current, and in the light-emitting phase, a driving current is provided to the light-emitting element to make the light-emitting element emit light corresponding to the driving current.

[0006] The settings of the gating module and control module can control whether the pixel driving module generates driving current. When the gating module and control module control the pixel driving module to generate driving current, the pixel can be refreshed; when the gating module and control module control the pixel driving module to not generate driving current, the pixel cannot be refreshed. In this way, the refresh frequency of the pixel is controlled. Furthermore, since the control module controls the gating module to be on or off based on the data signal, it controls whether the pixel driving module generates driving current. For example, when the data signal is the first data signal, the gating module is on, and the pixel driving module generates driving current; when the data signal is the second data signal, the gating module is off, and the pixel driving module cannot generate driving current. Therefore, the data signal can control whether each pixel is refreshed. This allows for the refresh of any area and any position on the display panel, that is, the refresh of any single pixel on the display panel, no longer limited to partial refresh of a certain area, nor refreshing all pixels, which helps reduce power consumption.

[0007] Furthermore, the gating module and control module provided in this application embodiment are located in the display area of ​​the display panel and will not occupy the non-display area of ​​the display panel, which is beneficial to the narrow bezel design of the display panel.

[0008] For example, in the selection sub-stage, the data signal is a first-level signal; in the reset sub-stage, data writing sub-stage, and light emission sub-stage, the data signal is a second-level signal. The first-level signal and the second-level signal are out of phase; for example, the first-level signal can be a low-level signal, and the second-level signal can be a high-level signal.

[0009] For example, when the turn-on module is turned on, in the reset sub-stage, a reset signal is written to the pixel driver module to reset the pixel driver module; in the data writing stage, a data signal is written to the pixel driver module to generate a drive current; and in the light-emitting stage, a drive current is provided to the light-emitting element to make the light-emitting element emit light corresponding to the drive current, and the pixel can be refreshed.

[0010] When the strobe module is turned off, the reset signal cannot be written to the pixel driver module during the reset sub-stage; during the data writing stage, the data signal cannot be written to the pixel driver module, and the pixel cannot be refreshed.

[0011] According to the second aspect, the gating module includes a first gating unit, a second gating unit, and a third gating unit; the pixel driving module includes a driving module; the control module, the control terminal of the first gating unit, the control terminal of the second gating unit, and the control terminal of the third gating unit are coupled to the first node; the control module is used to send control signals to the control terminals of the first gating unit, the second gating unit, and the third gating unit in the selection sub-stage according to the data signal written by the data signal terminal, so as to control the first gating unit, the second gating unit, and the third gating unit to be turned on or off; when the first gating unit is turned on, in the reset sub-stage, a reset signal is written to the control terminal of the driving module to reset the control terminal of the driving module; when the second gating unit and the third gating unit are turned on, in the data writing stage, the driving module generates a driving current according to the data signal.

[0012] The settings of the first gating unit can select whether the reset signal resets the control terminal of the drive module. The settings of the second and third gating units can select whether the data signal will cause the drive module to generate a new drive current to drive the light-emitting element to emit light. By setting the gating modules separately, it is possible to more flexibly control whether the control terminal of the drive module is reset and whether the drive module will generate a new drive current to drive the light-emitting element to emit light.

[0013] For example, the driving module is the driving transistor M1 described below.

[0014] According to the first aspect, or any implementation of the first aspect above, the pixel driving module further includes a first reset module, a threshold compensation module, and a data writing module. The pixel driving circuit further includes a first scan signal terminal, a second scan signal terminal, and a third scan signal terminal. The first terminal of the first reset module is electrically connected to the reset signal terminal, the second terminal of the first reset module is electrically connected to the first terminal of the first gating unit, and the control terminal of the first reset module is electrically connected to the first scan signal terminal. The second terminal of the first gating unit, the control terminal of the driving module, and the first terminal of the threshold compensation module are coupled to a second node. The first terminal of the data writing module is electrically connected to the data signal terminal, the second terminal of the data writing module is electrically connected to the first terminal of the second gating unit, the control terminal of the data writing module is electrically connected to the second scan signal terminal, the second terminal of the second gating unit is electrically connected to the first terminal of the driving module, and the second terminal of the driving module is electrically connected to the second terminal of the threshold compensation module. The control terminal of the threshold compensation module is electrically connected to the first terminal of the third gating unit, and the second terminal of the third gating unit is electrically connected to the third scan signal terminal.

[0015] Specifically, a first gating unit is provided between the first reset module and the second node, a second gating unit is provided between the data writing module and the first end of the drive module, and a third gating unit is provided between the control end of the threshold compensation module and the third scan signal end. This configuration can better intercept reset signals and data signals, and facilitate the control of the control module.

[0016] For example, the first reset module is the reset transistor M4 described below.

[0017] For example, the threshold compensation module is the threshold compensation transistor M3 described below.

[0018] For example, the data writing module is the data writing transistor M2 as described below.

[0019] According to the first aspect, or any implementation of the first aspect above, the first gating unit includes a first transistor; the gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor is electrically connected to the second terminal of the first reset module, and the second terminal of the first transistor is electrically connected to the second node.

[0020] The reset signal (i.e. whether to transmit the reset signal to the control terminal of the driver module) can be controlled by a single transistor. The structure of the first gating unit is simple, which in turn makes the structure of the pixel driving circuit simple. While achieving single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0021] According to the first aspect, or any implementation of the first aspect above, the second gating unit includes a second transistor; the gate of the second transistor is electrically connected to the first node, the first terminal of the second transistor is electrically connected to the second terminal of the data writing module, and the second terminal of the second transistor is electrically connected to the first terminal of the driving module.

[0022] The control of the data signal (i.e. whether the data signal will generate a new driving current through the driving module) can be achieved with a single transistor. The structure of the second gating unit is simple, which in turn makes the structure of the pixel driving circuit simple. While achieving single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0023] According to the first aspect, or any implementation of the first aspect above, the third gating unit includes a third transistor; the gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control terminal of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal terminal.

[0024] The control of the data signal (i.e. whether the data signal will generate a new driving current through the driving module) can be achieved with a single transistor. The structure of the third gating unit is simple, which in turn makes the structure of the pixel driving circuit simple. While achieving single pixel refresh, it is beneficial to improve the pixel aperture ratio.

[0025] According to the first aspect, or any implementation of the first aspect above, the control module includes a data writing unit, a first control unit, and a second control unit; the data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; in the selection sub-stage, the data writing unit is used to control the gating module to conduct according to the first data signal written at the data signal terminal; when the gating module is conducted in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue conducting; in the light emission stage, the second control unit is used to control the gating module to be cut off.

[0026] The configuration of the data writing unit, the first control unit, and the second control unit allows for more flexible control over the gating module's on / off state, while also avoiding the influence of other signals on the gating module's state, thus improving the circuit's reliability.

[0027] According to the first aspect, or any implementation of the first aspect above, the control module further includes a voltage regulator unit, the first terminal of the voltage regulator unit, the data writing unit, the first control unit and the second control unit are coupled to the third node, and the second terminal of the voltage regulator unit, the first control unit, the second control unit and the gating module are coupled to the first node.

[0028] The voltage regulator unit makes the signal output to the gating module more stable.

[0029] According to the first aspect, or any implementation of the first aspect above, the voltage regulator unit includes a first capacitor, the first electrode of the first capacitor, a data writing unit, a first control unit and a second control unit coupled to a third node, and the second electrode of the first capacitor, the first control unit, the second control unit and the gating module coupled to the first node.

[0030] The voltage regulator unit has a simple structure, which in turn makes the pixel driving circuit simple. This allows for single-pixel refresh while improving the pixel aperture ratio.

[0031] According to the first aspect, or any implementation of the first aspect above, the pixel driving circuit further includes a fourth scanning signal terminal; the data writing unit includes a fourth transistor and a fifth transistor, the gate of the fourth transistor is electrically connected to the fourth scanning signal terminal, the first terminal of the fourth transistor is electrically connected to the data signal terminal, the second terminal of the fourth transistor is electrically connected to the first terminal and the gate of the fifth transistor, and the second terminal of the fifth transistor is electrically connected to the third node.

[0032] The selection of the gating module state (on or off) can be achieved by using two transistors in the selection sub-stage. The data writing unit has a simple structure, which in turn simplifies the structure of the pixel driving circuit. This allows for single-pixel refresh while improving the pixel aperture ratio.

[0033] According to the first aspect, or any implementation of the first aspect above, the pixel driving circuit further includes a fourth scanning signal terminal; the first control unit includes a sixth transistor and a seventh transistor, the first terminal and the gate of the sixth transistor are electrically connected to the fourth scanning signal terminal, the second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor, the second terminal of the seventh transistor is electrically connected to the gating module, and the gate of the seventh transistor is electrically connected to the third node.

[0034] The state (on or off) of the gating module can be maintained in the reset and data writing stages using only two transistors. The structure of the first control unit is simple, which in turn simplifies the structure of the pixel driving circuit. This allows for single-pixel refresh while improving the pixel aperture ratio.

[0035] According to the first aspect, or any implementation of the first aspect above, the pixel driving circuit further includes a fourth scanning signal terminal and a fifth scanning signal terminal; the second control unit includes an eighth transistor and a ninth transistor, the gate of the eighth transistor and the gate of the ninth transistor are both electrically connected to the fifth scanning signal terminal, the first terminal of the eighth transistor is electrically connected to the fourth scanning signal terminal, the second terminal of the eighth transistor is electrically connected to the third node, the first terminal of the ninth transistor is electrically connected to the third node, and the second terminal of the ninth transistor is electrically connected to the gating module.

[0036] The state of the gating module can be restored during the light-emitting stage using only two transistors. Regardless of whether the gating module is in the off state or the on state during the reset and data writing stages, the eighth and ninth transistors will control the gating module to return to the off state, thus avoiding any impact on whether the next frame is refreshed. The structure of the second control unit is simple, which in turn simplifies the structure of the pixel driving circuit. This allows for the refreshing of a single pixel while improving the pixel aperture ratio.

[0037] According to the first aspect, or any implementation of the first aspect above, the effective level duration of the selection sub-stage is less than the effective level duration of the reset sub-stage.

[0038] This setting allows for a longer reset time for the previous frame signal, preventing the previous frame signal from affecting the current frame signal and improving display uniformity.

[0039] According to the first aspect, or any implementation of the first aspect above, multiple pixel arrays are arranged; the display panel further includes a driving circuit and multiple scan line groups; the driving circuit includes at least a first scan driving circuit and a second scan driving circuit, and the scan line groups include at least a first scan signal line and a second scan signal line; the first scan driving circuit includes multiple first scan signal output terminals, the second scan driving circuit includes multiple second scan signal output terminals, the multiple first scan signal output terminals are electrically connected to multiple first scan signal lines one-to-one, and the multiple second scan signal output terminals are electrically connected to multiple second scan signal lines one-to-one; the pixel driving circuit further includes a first scan signal terminal, a second scan signal line, a third ... The system includes a second scan signal terminal, a third scan signal terminal, a fourth scan signal terminal, and a fifth scan signal terminal. In the pixel driving circuit of the same pixel row, the second scan signal terminal is electrically connected to the same first scan signal line; the third scan signal terminal is electrically connected to the same second scan signal line; the first scan signal terminal is electrically connected to the corresponding second scan signal lines of other pixel rows; the fourth scan signal terminal is electrically connected to the corresponding first scan signal lines of other pixel rows; and the fifth scan signal terminal is electrically connected to the corresponding first scan signal lines of other pixel rows.

[0040] This configuration reduces the number of scan drive circuits in the drive circuit, eliminating the need for a separate scan drive circuit for each scan signal terminal. This simplifies the structure of the drive circuit and reduces the area occupied by the drive circuit in the non-display area, which is beneficial for the narrow bezel design of the display panel and also reduces costs.

[0041] According to the first aspect, or any implementation of the first aspect above, the first scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scan signal line corresponding to the previous pixel row, the fourth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to the previous pixel row, and the fifth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to the next pixel row.

[0042] This configuration results in a shorter signal line connecting the first scan signal terminal to the second scan signal line corresponding to the previous pixel row, avoiding excessive occupation of the light-emitting area by the signal line and improving the pixel aperture ratio.

[0043] Of course, this does not constitute a limitation of this application. Optionally, the fourth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to the two previous pixel rows. Accordingly, when the input of the fourth scan signal terminal is an effective level (a level that can turn on the structure or transistor electrically connected to the fourth scan signal terminal), at this moment, the data signal input of the data signal terminal is also an effective data signal (that is, the signal that the gating module is turned on).

[0044] Secondly, embodiments of this application provide an electronic device, which includes a display panel according to the first aspect and any implementation thereof, and the second aspect corresponds to the first aspect and any implementation thereof. The technical effects corresponding to the second aspect are similar to those corresponding to the first aspect and any implementation thereof, and will not be repeated here. Attached Figure Description

[0045] Figure 1a This is one of the application scenarios for an electronic device provided in the embodiments of this application;

[0046] Figure 1b This is one of the application scenarios for an electronic device provided in the embodiments of this application;

[0047] Figure 2 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application;

[0048] Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application;

[0049] Figure 4 This is a schematic diagram of a pixel driving circuit provided in an embodiment of this application;

[0050] Figure 5 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application;

[0051] Figure 6 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application;

[0052] Figure 7 A timing diagram of the signals of the pixel driving circuit provided in the embodiments of this application;

[0053] Figure 8 This is a diagram showing the operating state of each transistor in the first sub-stage of the pixel driving circuit during the reset phase.

[0054] Figure 9 This is a diagram showing the operating states of each transistor in the second sub-stage of the pixel driving circuit during the reset phase.

[0055] Figure 10 This is a diagram showing the operating state of each transistor in the first sub-stage of the data writing phase of the pixel driving circuit.

[0056] Figure 11 This is a diagram showing the operating states of each transistor in the second sub-stage of the data writing phase of the pixel driving circuit.

[0057] Figure 12 This is a diagram showing the operating states of each transistor in the first sub-stage of the light-emitting phase of the pixel driving circuit.

[0058] Figure 13 This is a diagram showing the operating states of each transistor in the second sub-stage of the light-emitting phase of the pixel driving circuit.

[0059] Figure 14 Another timing diagram of the signals of the pixel driving circuit provided in the embodiments of this application;

[0060] Figure 15 This is a diagram showing the operating state of each transistor in the first sub-stage of the pixel driving circuit during the reset phase.

[0061] Figure 16 This is a diagram showing the operating states of each transistor in the second sub-stage of the pixel driving circuit during the reset phase.

[0062] Figure 17 This is a diagram showing the operating state of each transistor in the first sub-stage of the data writing phase of the pixel driving circuit.

[0063] Figure 18 This is a diagram showing the operating states of each transistor in the second sub-stage of the data writing phase of the pixel driving circuit.

[0064] Figure 19 This is a diagram showing the operating states of each transistor in the first sub-stage of the light-emitting phase of the pixel driving circuit.

[0065] Figure 20 This is a diagram showing the operating states of each transistor in the second sub-stage of the light-emitting phase of the pixel driving circuit.

[0066] Figure 21 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application;

[0067] Figure 22 This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application;

[0068] Figure 23 Another timing diagram of the signals of the pixel driving circuit provided in the embodiments of this application;

[0069] Figure 24 Another timing diagram of the signals of the pixel driving circuit provided in the embodiments of this application;

[0070] Figure 25 This application provides a refresh process for the display screen in an embodiment of the present application.

[0071] Figure 26 This is one of the application scenarios for an electronic device provided in the embodiments of this application. Detailed Implementation

[0072] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of this application.

[0073] In this article, the term "and / or" is merely a description of the relationship between related objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone.

[0074] The terms "first" and "second," etc., used in the specification and claims of this application are used to distinguish different objects, not to describe a specific order of objects. For example, "first target object" and "second target object," etc., are used to distinguish different target objects, not to describe a specific order of target objects.

[0075] In the embodiments of this application, the terms "exemplary" or "for example" are used to indicate that something is an example, illustration, or description. Any embodiment or design that is described as "exemplary" or "for example" in the embodiments of this application should not be construed as being more preferred or advantageous than other embodiments or design. Specifically, the use of the terms "exemplary" or "for example" is intended to present the relevant concepts in a specific manner.

[0076] In the description of the embodiments in this application, unless otherwise stated, "multiple" means two or more. For example, multiple processing units means two or more processing units; multiple systems means two or more systems.

[0077] Figure 1a and Figure 1b This is a schematic diagram illustrating an exemplary application scenario. For example... Figure 1a As shown, the electronic device 100 (such as a mobile phone) displays various content through a display panel; such as Figure 1b As shown, the electronic device 100 (such as a laptop computer) displays various content via a display panel. Figure 1a and Figure 1bThe display panel is divided into three areas: a status bar 101, a video playback area 102, and a static content display area 103. The status bar 101 displays status information, such as remaining battery power and time; the video playback area 102 displays dynamic content, such as playing videos; and the static content display area 103 displays static content, such as text and images.

[0078] In similar Figure 1a and Figure 1b In the scenario shown, if the same refresh rate is used to refresh the display content in all areas, it will result in relatively high power consumption of the display panel, but will not significantly improve the display quality.

[0079] Based on this, embodiments of this application propose a display panel and an electronic device using the display panel. The electronic device may be a mobile phone, tablet computer, laptop computer, personal digital assistant (PDA), in-vehicle computer, smart wearable device, smart home device, or other smart terminal including the display panel. Embodiments of this application do not limit the specific form of the above-mentioned electronic device.

[0080] By using a relatively low refresh rate for areas displaying static content such as text and images, and a relatively high refresh rate for areas displaying dynamic content such as video, different refresh rates are selected based on the content displayed in different areas. This results in areas displaying static content such as text and images having a relatively low refresh rate. Since the refresh rate is lower in these areas, the display quality is not significantly affected, allowing the display panel to maintain display quality while reducing power consumption, thereby improving the battery life of electronic devices.

[0081] The following describes, in conjunction with an electronic device, the various structures within the display panel provided in this application, and the principles by which different areas and positions achieve different refresh rates. See also... Figure 2 Let's take a mobile phone as an example to illustrate this.

[0082] like Figure 2As shown, the mobile phone 100 includes a display panel 10, a back cover 20, and a mid-frame 30. The display panel 10, back cover 20, and mid-frame 30 can form a receiving cavity. A printed circuit board, a battery, and functional components (not shown) are disposed within the receiving cavity. The functional components include, for example, a display driver chip and a processor. The display driver chip and processor are disposed on the printed circuit board, and are electrically connected through the printed circuit board. The processor sends corresponding signals to the display driver chip to cause the display driver chip to drive the display panel 10 to display a screen.

[0083] The material of the back cover 20 may include, for example, opaque materials such as plastic, vegan leather, and fiberglass; or it may include light-transmitting materials such as glass. This application does not limit the material of the back cover 20.

[0084] Display panel 10 may include a liquid crystal display (LCD) panel, an organic light-emitting diode (OLED) display panel, and an LED display panel, etc., wherein the LED display panel may include a micro-LED display panel, a mini-LED display panel, etc. This application embodiment does not limit the type of display panel 10. The following description uses an OLED display panel as an example.

[0085] See Figure 3 , Figure 3 This is a schematic diagram of the structure of a display panel provided in an embodiment of this application. Figure 3 As shown, the display panel 10 includes a display area AA and a non-display area NAA, wherein the non-display area NAA is located on at least one side of the display area AA. Figure 3 The explanation uses the non-display area NAA surrounding the display area AA as an example. The display area AA of the display panel 10 has multiple pixels 11 arranged in an array, multiple scan line groups 12, and multiple data lines 13. Each pixel 11 includes a pixel driving circuit 111 and a light-emitting element 112. Each data line 13 corresponds one-to-one with a pixel driving circuit 111 in a column of pixels 11; that is, one data line 13 corresponds to one pixel driving circuit 111 in one column of pixels 11. Each scan line group 12 corresponds one-to-one with a pixel driving circuit 111 in a row of pixels 11; that is, one scan line group 12 corresponds to one pixel driving circuit 111 in one row of pixels 11.

[0086] Combination Figure 4 , Figure 4The diagram shows the structure of the pixel driving circuit. The pixel driving circuit 111 may include a pixel driving module, which includes 8T1C (8 transistors and 1 storage capacitor). That is, the pixel driving module may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4, M5 and M8, light emission control transistors M6 and M7, and a storage capacitor Cst.

[0087] It is understood that the specific structure of the pixel driving module includes, but is not limited to, the example described above. In other optional embodiments, the pixel driving module can also be configured in other ways (i.e., including more or fewer transistors, and including more or fewer storage capacitors), as long as it can drive the light-emitting element 112 to emit light. For example, as shown... Figure 5 As shown, the pixel driving module may also include 7T1C (7 transistors and 1 storage capacitor), that is, the pixel driving module may include driving transistor M1, data writing transistor M2, threshold compensation transistor M3, reset transistors M4 and M5, light emission control transistors M6 and M7, and storage capacitor Cst.

[0088] It should be noted that the embodiments of this application are illustrated by taking as an example that the pixel driving module may include a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4, M5 and M8, light emission control transistors M6 and M7, and a storage capacitor Cst.

[0089] In some embodiments, the reset transistor M4 and threshold compensation transistor M3 can be transistors with oxide semiconductor material as the active layer. The oxide semiconductor material may include indium gallium zinc oxide (IGZO), and the transistor is, for example, an N-type transistor. The driving transistor M1, data writing transistor M2, reset transistors M5 and M8, and light-emitting control transistors M6 and M7 are transistors with silicon material as the active layer, and the transistor is, for example, a P-type transistor. That is, LTPS transistors and IGZO transistors are integrated on a single substrate to form a low-temperature polycrystalline oxide (LTPO) display panel 10.

[0090] Low-temperature polysilicon transistors (LTPS transistors) have advantages such as high carrier mobility, fast response, and low power consumption, while oxide semiconductor transistors (OSTs) have the advantage of low leakage current. Therefore, when the pixel driving circuit 111 includes both LTPS transistors and IGZO transistors as active layers, it can ensure that the pixel driving circuit 111 has better performance. For example, OSTs have the advantage of low leakage current, so at low refresh rates, the gate potential of the driving transistor M1 can be kept stable and not leaked, thereby preventing the image from flickering at low frequencies.

[0091] Furthermore, the combination of N-type and P-type transistors will effectively reduce the number of thin-film transistors required for the pixel driving circuit 111, making the structure of the pixel driving circuit 111 simpler.

[0092] Of course, this is not intended to limit this application. In other alternative embodiments of this application, the aforementioned driving transistor M1, data writing transistor M2, threshold compensation transistor M3, reset transistors M4, M5 and M8, and light-emitting control transistors M6 and M7 can all be transistors with silicon as the active layer. The silicon material can include polycrystalline silicon, and the polycrystalline silicon material can include low-temperature polycrystalline silicon (LTPS). Furthermore, the transistor is, for example, a P-type transistor.

[0093] When the pixel driving module includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light-emitting control transistors M6 and M7, and a storage capacitor Cst, all of these transistors can have silicon as their active layer. Alternatively, the reset transistor M4 and the threshold compensation transistor M3 can have oxide semiconductor as their active layer, while the driving transistor M1, data writing transistor M2, reset transistor M5, and light-emitting control transistors M6 and M7 can all have silicon as their active layer.

[0094] It should be noted that the embodiments of this application are all described with the example that the reset transistor M4 and the threshold compensation transistor M3 can be transistors with oxide semiconductor material as the active layer, and the transistor is, for example, an N-type transistor; and the driving transistor M1, the data writing transistor M2, the reset transistors M5 and M8, and the light-emitting control transistors M6 and M7 are transistors with silicon material as the active layer, and the transistor is, for example, a P-type transistor.

[0095] See also Figure 4The pixel driving circuit 111 also includes initialization signal terminals Vref1, Vref2 and Vref3, a first power supply terminal PVDD, a second power supply terminal PVEE, a data signal terminal Data, a first scan signal terminal Scan1, a second scan signal terminal Scan2, a third scan signal terminal Scan3, a sixth scan signal terminal Scan6 and an emission control signal terminal Emit. The first terminal of the light-emitting control transistor M6 is electrically connected to the first power supply terminal PVDD. The first terminal of the data writing transistor M2 is electrically connected to the data signal terminal Data. The gate of the data writing transistor M2 is electrically connected to the second scan signal terminal Scan2. The gate of the threshold compensation transistor M3 is electrically connected to the third scan signal terminal Scan3. The first terminals of the reset transistors M4, M5, and M8 are electrically connected to the initialization signal terminals Vref1, Vref2, and Vref3, respectively (the initialization signal terminals for the three can be the same or different). The gate of the reset transistor M4 can be electrically connected to the first scan signal terminal Scan1. The gates of the reset transistors M5 and M8 can be electrically connected to the sixth scan signal terminal Scan6. The gates of the light-emitting control transistors M6 and M7 can be electrically connected to the light-emitting control signal terminal Emit, respectively. The light-emitting control transistor M7 is electrically connected to the anode of the light-emitting element 112. The cathode of the light-emitting element 112 is electrically connected to the second power supply terminal PVEE.

[0096] See also Figure 3 Each scan line group 12 includes a first scan signal line 121, a second scan signal line 122, a third scan signal line 123, and a light emission control signal line 122.

[0097] The pixel driving circuit 111 in a column of pixels 11 described above corresponds to a data line 13, that is, the data signal terminal Data in the pixel driving circuit 111 of each pixel 11 in the same column is electrically connected to the same data line 13. The pixel driving circuit 111 in a row of pixels 11 corresponds to a scan line group 12. That is, the second scan signal terminal Scan2 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the first scan signal line 121 corresponding to the pixel in that row. The third scan signal terminal Scan3 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the second scan signal line 122 corresponding to the pixel in that row. The sixth scan signal terminal Scan6 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the third scan signal line 123 corresponding to the pixel in that row. The light emission control signal terminal Emit in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the light emission control signal line 124 corresponding to the pixel in that row. The first scan signal terminal Scan1 in the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the second scan signal line 122 corresponding to the pixels in other rows (such as the previous row).

[0098] It should be noted that, in order to ensure the simplicity and clarity of the circuit, Figure 3 The first scan signal terminal Scan1 in the pixel driving circuit 111 of each pixel 11 in the same row is not shown in the figure. It is electrically connected to the second scan signal line 122 corresponding to the pixels in other rows.

[0099] In other words, the first scan signal transmitted by the first scan signal line 121 can control the data writing transistor M2 to turn on or off; the second scan signal transmitted by the second scan signal line 122 can control the threshold compensation transistor M3 to turn on or off; and the third scan signal transmitted by the third scan signal line 123 can control the reset transistors M5 and M8 to turn on or off. The second scan signal transmitted by the second scan signal line 122 in other rows (such as the previous row) controls the reset transistor M4 to turn on or off; the light emission control signal transmitted by the light emission control signal line 124 can control the light emission control transistors M6 and M7 on the light emission branch to turn on or off.

[0100] When the second scan signal line 122 and the third scan signal line 123 provide the second scan signal and the third scan signal to the corresponding row of pixels 11, the gate of the driving transistor M1, the first electrode of the driving transistor M1, and the anode of the light-emitting element 112 can be refreshed, avoiding the influence of the previous frame signal on the current frame signal and improving the uniformity of the display. When the first scan signal line 121 provides the first scan signal to the corresponding row of pixels 11, the pixels 11 that need to be refreshed can be selected. The data line 13 provides a data signal to the pixel driving circuit 111 of the corresponding column, and refreshes the data signal for the pixels 11 selected by the scan signal. The light-emitting control signal line provides a light-emitting control signal to the corresponding row of pixels 11 to control the light-emitting time of the pixels 11. Under the action of the scan signal, the light-emitting control signal, and the data signal, the pixel driving circuit 111 generates a driving current to drive the light-emitting element 112 to emit light. The specific principle by which the pixel driving circuit 111 generates a driving current based on data signals, light emission control signals, and scanning signals to drive the light-emitting element 112 to emit light is similar to the principle by which the pixel driving circuit of the existing 8T1C generates a driving current to drive the light-emitting element to emit light, and will not be described in detail here.

[0101] See also Figure 3A driving circuit 14 is provided in the non-display area NAA of the display panel 10. The driving circuit 14 may include a first scanning driving circuit, a second scanning driving circuit, a third scanning driving circuit, and a light emission control driving circuit (all not shown in the figure). The first scanning driving circuit, the second scanning driving circuit, and the third scanning driving circuit each include multiple scanning signal output terminals (i.e., the first scanning driving circuit includes multiple first scanning signal output terminals, the second scanning driving circuit includes multiple second scanning signal output terminals, and the third scanning driving circuit includes multiple third scanning signal output terminals). The light emission control driving circuit includes multiple light emission control signal output terminals. The multiple scanning signal output terminals of the first scanning driving circuit are electrically connected one-to-one with multiple first scanning signal lines 121 of the display area AA; the multiple scanning signal output terminals of the second scanning driving circuit are electrically connected one-to-one with multiple second scanning signal lines 122 of the display area AA; the multiple scanning signal output terminals of the third scanning driving circuit are electrically connected one-to-one with multiple third scanning signal lines 123 of the display area AA; and the multiple light emission control signal output terminals of the light emission control driving circuit are electrically connected one-to-one with the light emission control signal lines 124 of the display area AA. The first scanning drive circuit transmits the first scanning signal to the first scanning signal line 121 through its scanning signal output terminal; the second scanning drive circuit transmits the second scanning signal to the second scanning signal line 122 through its scanning signal output terminal; the third scanning drive circuit transmits the third scanning signal to the third scanning signal line 123 through its scanning signal output terminal; and the light emission control drive circuit transmits the light emission control signal to the light emission control signal line 122 through its light emission control signal output terminal.

[0102] It should be noted that the driving circuit 14 can be located on one side of the display area AA, such as... Figure 3As shown. The driving circuit 14 can also be disposed on both opposite sides of the display area AA, that is, driving circuit 14 is disposed on both opposite sides of the display area AA. In other words, the first scanning driving circuit can be disposed on one side of the display area AA or on both opposite sides of the display area AA; the second scanning driving circuit can be disposed on one side of the display area AA or on both opposite sides of the display area AA; the third scanning driving circuit can be disposed on one side of the display area AA or on both opposite sides of the display area AA; the light emission control driving circuit can be disposed on one side of the display area AA or on both opposite sides of the display area AA. For example, when the first scanning driving circuit in the driving circuit 14 is disposed on both opposite sides of the display area AA (that is, the first scanning driving circuit is disposed on both opposite sides of the display area AA), the scanning signal output terminals of the two first scanning driving circuits are electrically connected to a first scanning signal line 121 to provide a first scanning signal to the first scanning signal line 121. This arrangement can reduce the voltage drop of the first scanning signal. When the second scan drive circuit in drive circuit 14 is positioned on opposite sides of display area AA (i.e., a first scan drive circuit is positioned on both sides of display area AA), the scan signal output terminals of both second scan drive circuits are electrically connected to a second scan signal line 122 to provide a second scan signal to the second scan signal line 122. This configuration reduces the voltage drop of the second scan signal. When the third scan drive circuit in drive circuit 14 is positioned on opposite sides of display area AA (i.e., a third scan drive circuit is positioned on both sides of display area AA), the scan signal output terminals of both third scan drive circuits are electrically connected to a third scan signal line 123 to provide a third scan signal to the third scan signal line 123. This configuration also reduces the voltage drop of the third scan signal. When the light-emitting control driving circuit in the driving circuit 14 is set on both sides opposite to the display area AA (i.e., both sides opposite to the display area AA are equipped with light-emitting control driving circuits), the light-emitting control signal output terminals of the two light-emitting control driving circuits are electrically connected to a light-emitting control signal line 122 so as to provide light-emitting control signals to the light-emitting control signal line 122. This setting can reduce the voltage drop of the light-emitting control signal.

[0103] It should be noted that in this embodiment, the first scan signal terminal Scan1 of the pixel driving circuit 111 of each pixel 11 in the same row is electrically connected to the second scan signal line 122 corresponding to pixels in other rows (such as the previous row). That is, the scan signal of the first scan signal terminal Scan1 is provided by the second scan driving circuit electrically connected to the second scan signal line 122. In this way, there is no need to set a separate scan driving circuit for the first scan signal terminal Scan1 in the pixel driving circuit 111, that is, the number of scan driving circuits in the driving circuit 14 is reduced, which is beneficial to the narrow bezel design of the display panel. Of course, this does not constitute a limitation of this application. In other optional embodiments of this application, a fourth scan driving circuit can also be set separately. Correspondingly, the scan line group 12 can also include a fourth scan signal line. The fourth scan driving circuit provides a fourth scan signal to the first scan signal terminal Scan1 of the pixel driving circuit 111 of each pixel 11 in the same row through the fourth scan signal line.

[0104] The aforementioned refresh of different areas and positions of the display panel refers to refreshing individual pixels 11 in different areas and positions of the display panel. This involves resetting the pixel driving circuit 111 of the pixel 11 in that area and position, and providing new data signals to the pixel driving circuit 111 of the pixel 11 in that area and position, thereby updating the data signals in the pixel driving circuit 111 (i.e., refreshing the gate potential of the driving transistor M1), and thus refreshing the driving current of the driving transistor M1. When pixels 11 are not refreshed, the pixel driving circuit 111 of the pixel 11 in that area is not reset, the data signals in the pixel driving circuit 111 of the pixel 11 remain the data signals of the previous frame, and the driving current remains the driving current of the previous frame when emitting light. When pixels 11 are not refreshed, the corresponding transistors remain off, no current flows, and therefore power consumption is reduced.

[0105] However, based on the above pixel driving circuit 111 (such as...) Figure 4 or Figure 5 The pixel driving circuit 111 shown can only refresh the display content of all areas using the same refresh rate.

[0106] In order to achieve different refresh rates for individual pixels 11 in different regions and positions, combined with Figure 6 , Figure 6This is a schematic diagram of another pixel driving circuit provided in an embodiment of this application. The pixel driving circuit 111 includes not only a pixel driving module, initialization signal terminals Vref1, Vref2 and Vref3, a first power supply terminal PVDD, a second power supply terminal PVEE, a data signal terminal Data, a first scan signal terminal Scan1, a second scan signal terminal Scan2, a third scan signal terminal Scan3, a sixth scan signal terminal Scan6 and an emission control signal terminal Emit, but also a fourth scan signal terminal Scan4, a fifth scan signal terminal Scan5, a control module 1111 and a gating module 1112.

[0107] The gating module 1111 includes a first gating unit 1111a, a second gating unit 1111b, and a third gating unit 1111c.

[0108] The first gating unit 1111a includes a first transistor T1, the second gating unit 1111b includes a second transistor T2, and the third gating unit 1111c includes a third transistor T3.

[0109] The control module 1112 includes a data writing unit 1112a, a first control unit 1112b, a second control unit 1112c, and a voltage regulating unit 1112d.

[0110] The data writing unit 1112a includes a fourth transistor T4 and a fifth transistor T5, the first control unit 1112b includes a sixth transistor T6 and a seventh transistor T7, the second control unit 1112c includes an eighth transistor T8 and a ninth transistor T9, and the voltage regulation unit 1112d includes a first capacitor C1.

[0111] The gates of the first transistor T1, the second transistor T2, and the third transistor T3 are coupled to the first node N1. The first terminal of the first transistor T1 is electrically connected to the second terminal of the reset transistor M4, and the second terminal of the first transistor T1 is electrically connected to the second node N2. The first terminal of the second transistor T2 is electrically connected to the second terminal of the data write transistor T2, and the second terminal of the second transistor T2 is electrically connected to the first terminal of the drive transistor M1. The first terminal of the third transistor T3 is electrically connected to the gate of the threshold compensation transistor M3, and the second terminal of the third transistor T3 is electrically connected to the third scan signal terminal Scan3.

[0112] The first terminal of the fourth transistor T4 is electrically connected to the data signal terminal Data. The second terminal of the fourth transistor T4 is electrically connected to the first terminal and the gate of the fifth transistor T5. The second terminal of the fifth transistor T5 is electrically connected to the third node N3. The gate of the fourth transistor T4 is electrically connected to the fourth scan signal terminal Scan4. The fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to other pixel rows (such as the previous pixel row). In this way, there is no need to set up a separate scan driving circuit for the fourth scan signal terminal Scan4.

[0113] The first terminal and gate of the sixth transistor T6 are also electrically connected to the fourth scan signal terminal Scan4. The second terminal of the sixth transistor T6 is electrically connected to the first terminal of the seventh transistor T7. The second terminal of the seventh transistor T7 is electrically connected to the first node N1. The gate of the seventh transistor T1 is electrically connected to the third node N3.

[0114] The first terminal of the eighth transistor T8 is also electrically connected to the fourth scan signal terminal Scan4. The second terminal of the eighth transistor T8 is electrically connected to the third node N3. The first terminal of the ninth transistor T9 is electrically connected to the third node N3. The second terminal of the ninth transistor T9 is electrically connected to the first node N1. The gates of the eighth transistor T8 and the ninth transistor T9 are both electrically connected to the fifth scan signal terminal Scan5. The fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to other pixel rows (such as the next pixel row). In this way, there is no need to set up a separate scan driving circuit for the fifth scan signal terminal Scan5.

[0115] The first terminal of the first capacitor C1 is electrically connected to the third node N3, and the second terminal of the first capacitor C1 is electrically connected to the first node N1.

[0116] For example, in the pixel driving circuit 111 of the same row of pixels 11, the first scan signal terminal Scan1 is electrically connected to the second scan signal line 122 corresponding to the previous pixel row; the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the previous pixel row; and the fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the next pixel row. That is, the scan signal input to the first scan signal terminal Scan1 and the third scan signal terminal Scan3 are output by the same scan driving circuit; the scan signal input to the fourth scan signal terminal Scan4, the scan signal input to the fifth scan signal terminal Scan5, and the second scan signal terminal Scan2 are output by the same scan driving circuit. This reduces the number of scan driving circuits and allows for shorter signal lines connecting the first scan signal terminal to the second scan signal line corresponding to the previous pixel row, avoiding excessive occupation of the light-emitting area by the signal lines and improving the pixel aperture ratio.

[0117] The structure of the pixel driving circuit 111 has been described in detail above. It should be noted that the structures of the control module 1111 and the gating module 1112 are not limited to the above examples. The structures of the first gating unit 1111a, the second gating unit 1111b, and the third gating unit 1111c in the gating module 1112, as well as the structures of the data writing unit 1112a, the first control unit 1112b, the second control unit 1112c, and the voltage regulating unit 1112d in the control module 1111, are not limited to the above examples. Those skilled in the art can set the specific structures of the control module 1111 and the gating module 1112, the specific structures of the first gating unit 1111a, the second gating unit 1111b, the third gating unit 1111c, and the specific structures of the data writing unit 1112a, the first control unit 1112b, the second control unit 1112c, and the voltage regulating unit 1112d according to the actual situation. As long as the control module 1111 cooperates with the data signal to control the gating module 1112, thereby realizing the control of the refresh frequency of a single pixel 11, all are within the protection scope of this application.

[0118] The following describes the working process of the pixel driving circuit 111 in refreshing a single pixel. Specifically, it uses P-type transistors as an example, where the first transistor T1, second transistor T2, third transistor T3, fourth transistor T4, fifth transistor T5, sixth transistor T6, seventh transistor T7, eighth transistor T8, and ninth transistor T9 are all P-type transistors. The first scan signal terminal Scan1 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the second scan signal line 122 corresponding to the previous pixel row (i.e., the scan signal line electrically connected to the third scan signal terminal Scan3 of the previous pixel row); the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the previous pixel row (i.e., the scan signal line electrically connected to the second scan signal terminal Scan2 of the previous pixel row); and the fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the next pixel row (i.e., the scan signal line electrically connected to the second scan signal terminal Scan2 of the next pixel row).

[0119] First, the specific process of refreshing pixel 11 in row N and column M will be explained.

[0120] Figure 7 A timing diagram of the signals in the pixel driving circuit is shown. It can be understood that the display panel may include multiple screen update cycles, each corresponding to one frame, and each frame corresponding to one refresh. When each pixel is refreshed, it can be divided into a reset phase T1, a data writing phase T2, and a light emission phase T3. The reset phase prevents the previous frame from affecting the current frame. The data writing phase writes new data signals into pixel 11 to generate a driving current different from the previous frame. The light emission phase emits light corresponding to the driving current generated in the current frame, thereby completing the display and refresh of the current frame. In this embodiment of the application, in order to refresh a single pixel, the reset phase T1, the data writing phase T2, and the light emission phase T3 are each divided into two sub-phases. Specifically, the reset phase T1 is divided into a first sub-phase (also called the selection sub-phase) T1-1 and a second sub-phase (also called the reset sub-phase) T1-2; the data writing phase T2 is divided into a first sub-phase T2-1 and a second sub-phase T2-2; and the light emission phase T3 is divided into a first sub-phase T3-1 and a second sub-phase T3-2. Furthermore, Figure 7In this diagram, ScanN represents the scan signal received by the third scan signal terminal Scan3, ScanN-1 represents the scan signal received by the first scan signal terminal Scan1, and ScanN+1 represents the scan signal received by the third scan signal terminal Scan3 for the next row of pixels 11. ScanN-1, ScanN, and ScanN+1 are the scan signals output by the (N-1), N, and (N+1)th scan signal output terminals of the aforementioned second scan driving circuit, respectively. ScanP represents the scan signal received by the second scan signal terminal Scan2, ScanP-1 represents the scan signal received by the fourth scan signal terminal Scan4, and ScanP+1 represents the scan signal received by the fifth scan signal terminal Scan5. ScanP-1, ScanP, and ScanP+1 are the scan signals output by the (P-1), P, and (P+1)th scan signal output terminals of the aforementioned first scan driving circuit, respectively. Vdata represents the data signal received by the data signal terminal Data.

[0121] The following section, based on this timing diagram, discusses... Figure 6 The operation of the pixel driving circuit 111 shown will be explained.

[0122] In the first sub-phase T1-1 of reset phase T1: see [link / details] Figure 8 , Figure 8 This diagram illustrates the operating states of each transistor in the first sub-stage of the pixel driving circuit during the reset phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the fourth scan signal terminal Scan4 receives a low-level scan signal ScanP-1, turning on transistors T4 and T6. In pixel 11 of column M, the data signal Vdata (sent from the display driver chip to the corresponding data line 13 of pixel 11) provided by the data signal terminal Data is low. This data is written to the gate of transistor T5 through the conducting fourth transistor T4, turning on transistor T5. The low-level data signal is then written to node N3, turning on transistor T7. The signal at the second terminal of transistor T7 is low. In other words, the signals at both terminals of capacitor C1 are low. In pixel 11 of row N, the fifth scan signal terminal Scan5 receives a high-level scan signal ScanP+1, turning off transistors T8 and T9. At this time, the signal at the first node N1 is a low-level signal, and the first transistor T1, the second transistor T2 and the third transistor T3 are turned on.

[0123] The first scan signal terminal Scan1 receives a high-level scan signal ScanN-1, and the second scan signal terminal Scan2 receives a high-level scan signal ScanP. Reset transistor M4 is turned on, and data writing transistor M2 is turned off. The initialization signal from the initialization signal terminal Vref1 is written to the gate of driving transistor M1 (i.e., the control terminal of the driving module) through the turned-on reset transistor M4 and the first transistor T1 to initialize the storage capacitor Cst and the gate of driving transistor M1. The initialization signal provided by the initialization signal terminal Vref1 is a low-level signal to ensure that driving transistor M1 can be turned on in the next stage.

[0124] In addition, the light emission control signal provided by the Emit terminal is a high-level signal (not shown in the figure), and the scan signal provided by the sixth scan signal terminal Scan6 is a high-level signal (not shown in the figure). The light emission control transistors M6 and M7 are turned off, and the gates of the reset transistors M5 and M8 are turned off.

[0125] In the second sub-phase T1-2 of reset phase T1: see [link / details] Figure 9 , Figure 9 This diagram illustrates the operating states of each transistor in the second sub-stage of the pixel driving circuit during the reset phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the scan signal ScanP-1 received by the fourth scan signal terminal Scan4 remains low, and transistors T4 and T6 continue to conduct. In pixel 11 of column M, the data signal Vdata (sent from the display driver chip to the data line 13 corresponding to pixel 11 of column M) provided by the data signal terminal Data is high. This high-level signal is written to the gate of transistor T5 through the conducting fourth transistor T4. With transistor T5 off, the high-level data signal cannot be written to the third node N3. Due to the presence of capacitor C1, transistor T7 continues to conduct. In pixel 11 of row N, the scan signal ScanP+1 received by the fifth scan signal terminal Scan5 remains high, and transistors T8 and T9 remain off. At this time, the signal at the first node N1 is still a low-level signal, and the first transistor T1, the second transistor T2 and the third transistor T3 continue to conduct.

[0126] The scan signal ScanN-1 received by the first scan signal terminal Scan1 remains high, and the scan signal ScanP received by the second scan signal terminal Scan2 remains high. The reset transistor M4 remains on, and the data writing transistor M2 remains off. The initialization signal from the initialization signal terminal Vref1 continues to be written to the gate of the driving transistor M1 (i.e., the control terminal of the driving module) through the on-state reset transistor M4 and the first transistor T1, to further initialize the storage capacitor Cst and the gate of the driving transistor M1. That is, in the first sub-stage T1-1 and the second sub-stage T2-1 of the reset phase T1, the storage capacitor Cst and the gate of the driving transistor M1 are both initialized.

[0127] In some embodiments, the duration of the first sub-stage T1-1 of the reset phase T1 is shorter than the duration of the second sub-stage T2-1 of the reset phase T1, which can better initialize the storage capacitor Cst and the gate of the driving transistor M1.

[0128] In addition, the light emission control signal provided by the Emit terminal is still a high-level signal, and the scan signal provided by the sixth scan signal terminal Scan6 is still a high-level signal. The light emission control transistors M6 and M7 are still off, and the reset transistors M5 and M8 are still off.

[0129] It is understandable that in the second sub-stage T1-2 of the reset phase T1, the data signal terminal Data in the M-th column pixel 11 provides a high-level data signal Vdata. Since the N-1 row of pixels is in the data writing stage at this time, the high-level data signal Vdata charges the pixel 11 in the M-th column of the N-1 row. However, since the pixels in this row (i.e. the N-th row) are in the reset stage, the high-level data signal Vdata will not affect the pixel 11 in this row.

[0130] In the first sub-stage T2-1 of the data writing phase T2: see [link / details]. Figure 10 , Figure 10This diagram illustrates the operating states of each transistor in the first sub-stage of the data writing phase of the pixel driving circuit. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the fourth scan signal terminal Scan4 receives a high-level scan signal ScanP-1, causing transistors T4, T5, and T6 to be off. Due to the presence of capacitor C1, the signal at node N3 remains low, and transistor T7 is on. In pixel 11 of row N, the fifth scan signal terminal Scan5 receives a high-level scan signal ScanP+1, causing transistors T8 and T9 to be off. Due to the presence of capacitor C1, the signal at node N1 is low, and transistors T1, T2, and T3 are on.

[0131] When the first scan signal terminal Scan1 receives a low scan signal ScanN-1, and the second scan signal terminal Scan2 receives a low scan signal ScanP, the reset transistor M4 is turned off, and the data writing transistor M2 is turned on. When the third scan signal terminal Scan3 receives a high scan signal ScanN, the threshold compensation transistor M3 is turned on.

[0132] The data signal Vdata provided by the data signal terminal Data in the Mth column pixel 11 (the data signal sent from the display driver chip to the data line 13 corresponding to the Mth column pixel 11) is a high-level signal. The high-level signal is written to the gate of the driving transistor M1 and the storage capacitor Cst through the conducting data writing transistor M2, driving transistor M1, and threshold compensation transistor M3, so that the gate voltage of the driving transistor M1 gradually increases.

[0133] It is understandable that the first sub-stage T2-1 of the data writing stage T2 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 for pixel 11 in row (N+1) and column (M). The data signal Vdata provided by the data signal terminal Data at this time can be either a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a high-level signal, this high-level signal can be a charging signal for pixel 11, or it can not be a charging signal for pixel 11. This is because the setting of the first sub-stage T2-1 of the data writing stage T2 is mainly to determine whether pixel 11 in row (N+1) and column (M) needs to be refreshed. If the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, this low-level signal makes the state of each transistor in pixel 11 in row (N+1) and column (M) the same as in the first sub-stage T1-1 of the reset stage T1 for pixel 11 in row (N+1) and the second sub-stage T1-2 of the reset stage T1, thus determining that pixel 11 in row (N+1) and column (M) needs to be refreshed.

[0134] In addition, during this sub-stage, the light emission control signal provided by the Emit terminal is still a high-level signal (not shown in the figure), and the scan signal provided by the sixth scan signal terminal Scan6 is still a high-level signal (not shown in the figure). The light emission control transistors M6 and M7 are still off, and the reset transistors M5 and M8 are still off.

[0135] In the second sub-stage T2-2 of the data writing phase T2, this sub-stage is the actual charging phase: see [link / reference] Figure 11 , Figure 11 This diagram illustrates the operating states of the transistors in the second sub-stage of the data writing phase of the pixel driving circuit. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the scan signal ScanP-1 received by the fourth scan signal terminal Scan4 is still high, and transistors T4, T5, and T6 remain off. Due to the presence of capacitor C1, the signal at node N3 remains low, and transistor T7 is conducting. In pixel 11 of row N, the scan signal ScanP+1 received by the fifth scan signal terminal Scan5 is high, and transistors T8 and T9 are off. Due to the presence of capacitor C1, the signal at node N1 remains low, and transistors T1, T2, and T3 continue to conduct.

[0136] When the first scan signal terminal Scan1 receives a low scan signal ScanN-1, and the second scan signal terminal Scan2 receives a low scan signal ScanP, the reset transistor M4 remains off, while the data writing transistor M2 remains on. When the third scan signal terminal Scan3 receives a high scan signal ScanN, the threshold compensation transistor M3 remains on.

[0137] The data signal Vdata provided by the data signal terminal Data in the Mth column pixel 11 (the data signal sent from the display driver chip to the data line 13 corresponding to the Mth column pixel 11) is a high-level signal. This high-level signal is the signal that the Nth row and Mth column pixel 11 actually needs to be charged. This high-level signal is written to the gate of the driving transistor M1 and the storage capacitor Cst through the conducting data writing transistor M2, driving transistor M1, and threshold compensation transistor M3, causing the gate voltage of the driving transistor M1 to gradually increase. Until the voltage difference between the gate voltage of the driving transistor M1 and the first terminal of the driving transistor M1 equals the threshold voltage V of the driving transistor M1. th That is, the gate voltage V of the driving transistor M1 N2 =V d -|V th |, where V d The data signal Vdata is provided to the data signal terminal Data; the gate voltage of the driving transistor M1 is stored in the storage capacitor Cst.

[0138] In addition, during this sub-stage, the light emission control signal provided by the Emit terminal is still a high-level signal (not shown in the figure), and the scan signal provided by the sixth scan signal terminal Scan6 is still a high-level signal (not shown in the figure). The light emission control transistors M6 and M7 are still off, and the reset transistors M5 and M8 are still off.

[0139] In the first sub-stage T3-1 of luminescence stage T3: see [link / reference] Figure 12 , Figure 12This diagram illustrates the operating states of each transistor in the first sub-stage of the pixel driving circuit during the light-emitting phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the fourth scan signal terminal Scan4 receives a high-level scan signal ScanP-1, causing transistors T4, T5, and T6 to be off. In pixel 11 of row N, the fifth scan signal terminal Scan5 receives a low-level scan signal ScanP+1, causing transistors T8 and T9 to be on. The high-level scan signal ScanP-1 received by the fourth scan signal terminal Scan4 is written to the first node N1 through the on-state transistors T8 and T9. The high-level signal at the first node N1 causes transistors T1, T2, and T3 to be off, and capacitor C1 to have a high-level signal, preventing transistors T1, T2, and T3 from accidentally turning on in the next frame.

[0140] The first scan signal terminal Scan1 receives a low-level scan signal ScanN-1, and the second scan signal terminal Scan2 receives a high-level scan signal ScanP. Reset transistor M4 is off, and data write transistor M2 is off. The light emission control signal provided by the Emit terminal is a low-level signal (not shown in the figure), and light emission control transistors M6 and M7 are turned on. The power supply signal voltage V at the first power supply terminal PVDD... pvdd The light-emitting control transistor M6 writes to the first terminal of the driving transistor M1, at which point the voltage difference V between the first terminal and the gate of the driving transistor M1 is... sg =V pvdd -V d +|V th The driving transistor M1 generates a driving current, which flows into the light-emitting element 112 through the light-emitting control transistor M7, driving the light-emitting element 112 to emit light. This driving current I... d for:

[0141]

[0142] Where μ is the carrier mobility, and C ox Let W / L be the channel capacitance per unit area of ​​the driving transistor M1, and W / L be the width-to-length ratio of the driving transistor M1. Therefore, the driving current I generated by the driving transistor M1 can be determined. d With the threshold voltage V of the driving transistor M1 th Unrelated. Threshold voltage compensation for the driving transistor M1 was implemented, resolving the display anomaly caused by threshold voltage drift of the driving transistor M1.

[0143] It is understandable that the first sub-stage T3-1 of the light-emitting stage T3 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 for the N+2 row and M column pixel 11. The data signal Vdata provided by the data signal terminal Data at this time can be either a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, this low-level signal makes the state of each transistor in the N+2 row and M column pixel 11 the same as in the first sub-stage T1-1 of the reset stage T1 for the N+2 row and M column pixel 11 and in the second sub-stage T1-2 of the reset stage T1, thus determining that the N+2 row and M column pixel 11 needs to be refreshed.

[0144] In addition, during this sub-stage, the scan signal provided by the sixth scan signal terminal Scan6 remains a high-level signal (not shown in the figure), and the reset transistors M5 and M8 remain off.

[0145] In the second sub-stage T3-2 of luminescent stage T3: see [link / reference] Figure 13 , Figure 13 This diagram illustrates the operating states of each transistor in the second sub-stage of the pixel driving circuit during the light-emitting phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. The operating states of the transistors and the flow of signals in this sub-stage are the same as those in the first sub-stage T3-1 of the light-emitting phase T3. For details, please refer to the description of the first sub-stage T3-1 of the light-emitting phase T3; it will not be repeated here.

[0146] In other words, during the light-emitting stage, the driving current I generated by the driving transistor M1 of pixel 11 in the Mth column of the current row (i.e., the Nth row) is... d While driving the light-emitting element 112 to emit light and completing the refresh of pixel 11 in row N and column M, since the next row (row N+1) of pixel 11 is in the data writing stage, the scan signal ScanP+1 received by the fifth scan signal terminal Scan5 in this stage is a low-level signal. The low-level signal turns on the eighth transistor T8 and the ninth transistor T9, and the high-level scan signal ScanP-1 received by the fourth scan signal terminal Scan4 is written to the first node N1 through the turned-on eighth transistor T8 and ninth transistor T9. The high-level signal at the first node N1 turns off the first transistor T1, the second transistor T2, and the third transistor T3, and the two poles of the first capacitor C1 are high-level signals to prevent the first transistor T1, the second transistor T2, and the third transistor T3 from being accidentally turned on in the next frame.

[0147] It should be noted that the scan signal provided by the sixth scan signal terminal Scan6 turns on the reset transistors M5 and M8, thereby causing the initialization signal of the initialization signal terminal Vref2 to be written to the anode of the light-emitting element 112 through the turned-on reset transistor M5, and initializing the anode potential of the light-emitting element 40 (in order to reduce the influence of the voltage of the anode of the light-emitting element 40 in the previous frame on the voltage of the anode of the light-emitting element 40 in the next frame). Also, the initialization signal of the initialization signal terminal Vref3 is written to the first terminal of the driving transistor M1 through the turned-on reset transistor M8. The time for initializing the first terminal of the driving transistor M1 is not limited in the embodiments of this application, and those skilled in the art can set it according to the actual situation.

[0148] The above describes the process of refreshing pixel 11 in the Nth row and Mth column. It should be noted that N and M can be any number.

[0149] The following describes the process of not refreshing pixel 11 in row N and column M.

[0150] Figure 14 Another timing diagram of the signals of the pixel driving circuit is shown. Figure 14 The meaning of each signal in the middle and Figure 7 Same as above, see details. Figure 7 The description will not be repeated here.

[0151] The following section, based on this timing diagram, discusses... Figure 6 The operation of the pixel driving circuit 111 shown will be explained.

[0152] In the first sub-phase T1-1 of reset phase T1: see [link / details] Figure 15 , Figure 15 This diagram illustrates the operating states of each transistor in the first sub-stage of the pixel driving circuit during the reset phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the fourth scan signal terminal Scan4 receives a low-level scan signal ScanP-1, causing transistors T4 and T6 to conduct. The data signal Vdata provided by the data signal terminal Data in pixel 11 of column M (the data signal sent from the display driver chip to the corresponding data line 13 of pixel 11 in column M) is either the actual required data signal Vdata or a high-impedance signal. This data is written to the gate of transistor T5 through the conducting fourth transistor T4. Since transistor T5 cannot be turned on, transistors T7, T1, T2, and T3 are turned off.

[0153] The first scan signal terminal Scan1 receives a high-level scan signal ScanN-1, and the second scan signal terminal Scan2 receives a high-level scan signal ScanP. Reset transistor M4 is turned on, and data writing transistor M2 is turned off. Because the first transistor T1 is turned off, the initialization signal at the initialization signal terminal Vref1 cannot be written to the gate of the driving transistor M1 (i.e., the control terminal of the driving module) through the turned-on reset transistor M4. Therefore, the voltage at the gate of the driving transistor M1 remains the same as in the previous frame.

[0154] In addition, the light emission control signal provided by the Emit terminal is a high-level signal (not shown in the figure), and the scan signal provided by the sixth scan signal terminal Scan6 is a high-level signal (not shown in the figure). The light emission control transistors M6 and M7 are turned off, and the gates of the reset transistors M5 and M8 are turned off.

[0155] In the second sub-phase T1-2 of reset phase T1: see [link / details] Figure 16 , Figure 16 This diagram shows the operating states of each transistor in the second sub-stage of the pixel driving circuit during the reset phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. The operating states of each transistor and the direction of each signal in this sub-stage are the same as those in the first sub-stage T1-1 of the reset phase T1. For details, please refer to the description of the first sub-stage T1-1 of the reset phase T1; it will not be repeated here.

[0156] In the first sub-stage T2-1 of the data writing phase T2: see [link / details]. Figure 17 , Figure 17 This diagram illustrates the operating states of each transistor in the first sub-stage of the data writing phase of the pixel driving circuit. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the fourth scan signal terminal Scan4 receives a high-level scan signal ScanP-1, causing transistors T4, T5, and T6 to be off. Furthermore, since the signal at node N3 has not changed to a low-level signal, transistor T7 cannot conduct. In pixel 11 of row N, the fifth scan signal terminal Scan5 receives a high-level scan signal ScanP+1, causing transistors T8 and T9 to be off. Furthermore, since the signal at node N1 has not changed to a low-level signal, transistors T1, T2, and T3 cannot conduct. Also, since the signal at the gate of threshold compensation transistor M3 has not changed to a low-level signal, threshold compensation transistor M3 cannot conduct.

[0157] When the first scan signal terminal Scan1 receives the scan signal ScanN-1 at a low level, and the second scan signal terminal Scan2 receives the scan signal ScanP at a low level, the reset transistor M4 is turned off, and the data writing transistor M2 is turned on.

[0158] The data signal Vdata provided by the data signal terminal Data in the Mth column pixel 11 (the data signal sent from the display driver chip side to the data line 13 corresponding to the Mth column pixel 11) cannot be written to the gate of the driving transistor M1, and the voltage of the gate of the driving transistor M1 is the same as that of the previous frame.

[0159] It is understandable that the first sub-stage T2-1 of the data writing stage T2 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 for pixel 11 in row (N+1) and column (M). The data signal Vdata provided by the data signal terminal Data at this time can be either a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a high-level signal, this high-level signal can be a charging signal for pixel 11, or it can not be a charging signal for pixel 11. This is because the setting of the first sub-stage T2-1 of the data writing stage T2 is mainly to determine whether pixel 11 in row (N+1) and column (M) needs to be refreshed. If the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, this low-level signal makes the state of each transistor in pixel 11 in row (N+1) and column (M) the same as in the first sub-stage T1-1 of the reset stage T1 for pixel 11 in row (N+1) and the second sub-stage T1-2 of the reset stage T1, thus determining that pixel 11 in row (N+1) and column (M) needs to be refreshed.

[0160] In addition, during this sub-stage, the light emission control signal provided by the Emit terminal is still a high-level signal (not shown in the figure), and the scan signal provided by the sixth scan signal terminal Scan6 is still a high-level signal (not shown in the figure). The light emission control transistors M6 and M7 are still off, and the reset transistors M5 and M8 are still off.

[0161] In the second sub-stage T2-2 of the data writing phase T2, this sub-stage is the actual charging phase: see [link / reference] Figure 18 , Figure 18 This diagram illustrates the operating states of each transistor in the second sub-stage of the data writing phase of the pixel driving circuit. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. The operating states of the transistors and the flow of signals in this sub-stage are the same as those in the first sub-stage T2-1 of the data writing phase T2. For details, please refer to the description of the first sub-stage T2-1 of the data writing phase T2; it will not be repeated here.

[0162] In the first sub-stage T3-1 of luminescence stage T3: see [link / reference] Figure 19 , Figure 19 This diagram illustrates the operating states of each transistor in the first sub-stage of the pixel driving circuit during the light-emitting phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. In pixel 11 of row N, the fourth scan signal terminal Scan4 receives a high-level scan signal ScanP-1, causing transistors T4, T5, and T6 to be off. In pixel 11 of row N, the fifth scan signal terminal Scan5 receives a low-level scan signal ScanP+1, causing transistors T8 and T9 to be on. The high-level scan signal ScanP-1 received by the fourth scan signal terminal Scan4 is written to the first node N1 through the on-state transistors T8 and T9. The high-level signal at the first node N1 keeps transistors T1, T2, and T3 off, and the terminals of the first capacitor C1 remain high, preventing transistors T1, T2, and T3 from accidentally turning on in the next frame.

[0163] The first scan signal terminal Scan1 receives a low-level scan signal ScanN-1, and the second scan signal terminal Scan2 receives a high-level scan signal ScanP. Reset transistor M4 is off, and data write transistor M2 is off. The light emission control signal provided by the Emit terminal is a low-level signal (not shown in the figure), and light emission control transistors M6 and M7 are turned on. The power supply signal voltage V at the first power supply terminal PVDD... pvdd The light-emitting control transistor M6 writes to the first terminal of the driving transistor M1, but since the voltage at the gate of the driving transistor M1 is the same as in the previous frame, the voltage difference V between the first terminal and the gate of the driving transistor M1 is... sg =V pvdd -V d +|V th The driving current generated by the driving transistor M1 remains unchanged. This driving current flows into the light-emitting element 112 through the light-emitting control transistor M7, driving the light-emitting element 112 to emit light, thus maintaining the display of the previous frame.

[0164] It is understandable that the first sub-stage T3-1 of the light-emitting stage T3 is also the first sub-stage T1-1 (selection sub-stage) of the reset stage T1 for the N+2 row and M column pixel 11. The data signal Vdata provided by the data signal terminal Data at this time can be either a high-level signal or a low-level signal. If the data signal Vdata provided by the data signal terminal Data at this time is a low-level signal, this low-level signal makes the state of each transistor in the N+2 row and M column pixel 11 the same as in the first sub-stage T1-1 of the reset stage T1 for the N+2 row and M column pixel 11 and in the second sub-stage T1-2 of the reset stage T1, thus determining that the N+2 row and M column pixel 11 needs to be refreshed.

[0165] In addition, during this sub-stage, the scan signal provided by the sixth scan signal terminal Scan6 remains a high-level signal (not shown in the figure), and the reset transistors M5 and M8 remain off.

[0166] In the second sub-stage T3-2 of luminescent stage T3: see [link / reference] Figure 20 , Figure 20 This diagram illustrates the operating states of each transistor in the second sub-stage of the pixel driving circuit during the light-emitting phase. Transistors covered by "×" are non-conducting, while those not covered by "×" are conducting. The operating states of the transistors and the flow of signals in this sub-stage are the same as those in the first sub-stage T3-1 of the light-emitting phase T3. For details, please refer to the description of the first sub-stage T3-1 of the light-emitting phase T3; it will not be repeated here.

[0167] In other words, during the light-emitting phase, although the gate voltage of the driving transistor M1 of pixel 11 in the current row (i.e., row N, column M) is the same as in the previous frame, the next row (row N+1) of pixel 11 is in the data writing phase. Therefore, the scan signal ScanP+1 received by the fifth scan signal terminal Scan5 in this phase is a low-level signal. The low-level signal turns on the eighth transistor T8 and the ninth transistor T9, and the high-level scan signal ScanP-1 received by the fourth scan signal terminal Scan4 is written to the first node N1 through the turned-on eighth transistor T8 and ninth transistor T9. The high-level signal at the first node N1 turns off the first transistor T1, the second transistor T2, and the third transistor T3, and the two poles of the first capacitor C1 are high-level signals, preventing the first transistor T1, the second transistor T2, and the third transistor T3 from being accidentally turned on in the next frame.

[0168] It should be understood that, Figure 7 and Figure 14 This is merely an illustrative example of how the pixel driving circuit 111 controls whether each row of pixels 11 is refreshed. In practical applications, the waveforms and timing of each signal are not limited to... Figure 7 and14 As shown.

[0169] As described above, Vdata is the waveform received by the data signal terminal Data in the Mth column. Each row scanning phase (i.e., the time period during which the scanning drive circuit outputs the scanning signal) is divided into two sub-phases: the first sub-phase and the second sub-phase. The first sub-phase of the current row controls whether the display of pixel 11 in the next row of that column is refreshed. If Vdata in the first sub-phase is a preset low-level signal (turning on the negative voltage of the first transistor T1, the second transistor T2, and the third transistor T3), then the display content of pixel 11 in the next row of that column is refreshed. If Vdata in the first sub-phase maintains other signals (such as floating or other non-preset low-level signals), then the display content of pixel 11 in the next row of that column is not refreshed. If the display content of pixel 11 in the current row needs to be refreshed, then Vdata in the second sub-phase is the actual Vdata required by pixel 11. If the display content of pixel 11 in the current row does not need to be refreshed, then Vdata in the second sub-phase can be the Vdata of the previous frame at that position, or it can be floating, thus saving power consumption.

[0170] It should be noted that the above description is based on the following example: the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the previous pixel row (i.e., the scan signal line electrically connected to the second scan signal terminal Scan2 of the previous pixel row), and the fifth scan signal terminal Scan5 in the pixel driving circuit 111 of the same row of pixels 11 is electrically connected to the first scan signal line 121 corresponding to the next pixel row (i.e., the scan signal line electrically connected to the second scan signal terminal Scan2 of the next pixel row). Accordingly, when the scan signal transmitted by the first scan signal line 121 corresponding to the previous pixel row is a low-level signal, the data signal terminal Data of the pixel 11 is also a low-level signal, thereby completing the refresh of the pixel 11. This configuration results in a shorter signal line connecting the fourth scan signal terminal Scan4 to the first scan signal line 121 corresponding to the previous pixel row, and a shorter signal line connecting the fifth scan signal terminal Scan5 to the first scan signal line 121 corresponding to the next pixel row. This avoids excessive occupation of the light-emitting area by the signal lines and helps to improve the pixel aperture ratio.

[0171] Of course, this does not constitute a limitation of this application. Optionally, the fourth scan signal terminal Scan4 in the pixel driving circuit 111 of the same row of pixels 11 can also be electrically connected to the first scan signal line 121 corresponding to the two previous pixel rows (i.e., the scan signal line to which the second scan signal terminal Scan2 of the two previous pixel rows is electrically connected). Accordingly, the scan signal transmitted on the first scan signal line 121 corresponding to the two previous pixel rows is a low-level signal. At this moment, the data signal terminal Data of the pixel 11 also transmits a low-level signal, thereby completing the refresh of the pixel 11.

[0172] As can be seen from the foregoing, when the reset transistor M4 and the threshold compensation transistor M3 are transistors with oxide semiconductor material as the active layer, and the transistor is, for example, an N-type transistor, and the driving transistor M1, the data writing transistor M2, the reset transistors M5 and M8, and the light-emitting control transistors M6 and M7 are transistors with silicon material as the active layer, and the transistor is, for example, a P-type transistor, the operation of the pixel driving circuit is as described above.

[0173] Understandably, see Figure 21 When the pixel driving module includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light-emitting control transistors M6 and M7, and a storage capacitor Cst, and the reset transistor M4 and the threshold compensation transistor M3 are transistors with oxide semiconductor material as the active layer, while the driving transistor M1, the data writing transistor M2, the reset transistor M5, and the light-emitting control transistors M6 and M7 are all transistors with silicon material as the active layer, the timing of the pixel refresh is the same as... Figure 7 The timing of this pixel not being refreshed is the same as... Figure 14 same.

[0174] See Figure 22 When the pixel driving module includes a driving transistor M1, a data writing transistor M2, a threshold compensation transistor M3, reset transistors M4 and M5, light-emitting control transistors M6 and M7, and a storage capacitor Cst, and when the driving transistor M1, data writing transistor M2, threshold compensation transistor M3, reset transistors M4 and M5, and light-emitting control transistors M6 and M7 are all transistors with silicon as the active layer, the timing sequence for pixel refresh is as follows: Figure 23 As shown, the timing of this pixel not refreshing is related to... Figure 24 As shown, the specific implementation process is similar to the above content, which can be found above and will not be repeated here.

[0175] Based on the above structure and working process, Figure 1bThis document describes the process of implementing different refresh rates in the three areas: status bar 101, video playback area 102, and static content display area 103. The example used is a video playback area 102 playing an advertisement, a static content display area 103 displaying a paused video, and a status bar 101 displaying no content. The refresh rate for status bar 101 is 1Hz, for video playback area 102 it is 60Hz, and for static content display area 103 it is 30Hz. Specifically, status bar 101 includes areas A and E, video playback area 102 includes area C, and static content display area 103 includes areas B, G, D, and F.

[0176] See Figure 25 , Figure 25 This application provides a refresh process for a display screen in an embodiment of the present application, wherein the refresh process is the process by which the display driver chip provides data signals to the display panel. For example... Figure 25 As shown, in the first frame, the scanning drive circuit completes the scanning of all pixel rows, and the data signal terminals corresponding to each pixel 11 are all at a low level in the first sub-stage T1-1 of the reset phase T1, completing the refresh of all pixels. That is, in the first frame, the status bar 101, video playback area 102, and static content display area 103 are all refreshed. In the second frame, when the scanning drive circuit scans the pixel row corresponding to area C, the data signal terminals corresponding to the pixel columns in area C are all at a low level in the first sub-stage T1-1 of the reset phase T1, completing the refresh of the pixels in area C. That is, in the second frame, only the image in video playback area 102 is refreshed. In the third frame, when the scanning drive circuit scans the pixel row corresponding to the large area of ​​area C, area B, area G, area D, and area F (i.e., all pixel rows), the data signal terminals corresponding to the pixel columns in the large area of ​​area C, area B, area G, area D, and area F are all at a low level. During the reset phase T1, the first sub-phase T1-1 is at a low level, completing the refresh of pixels in regions C, B, G, D, and F. That is, in the third frame, the video playback area 102 and the static content display area 103 are partially refreshed. In the fourth frame, when the scanning drive circuit scans the pixel row corresponding to region C, the data signal terminal corresponding to the pixel column in region C is at a low level during the first sub-phase T1-1 of the reset phase T1, completing the refresh of pixels in region C. That is, in the fourth frame, only the video playback area 102 is refreshed. ... That is, the refresh method of the second and third frames is cyclically repeated until the sixty-first frame, when the refresh method of the first to sixtieth frames is cyclically repeated again, so that different areas are displayed with different refresh rates. That is, the refresh frequency of the status bar 101 is 1 Hz, the refresh frequency of the video playback area 102 is 60 Hz, and the refresh frequency of the static content display area 103 is 30 Hz.

[0177] It should be noted that the refresh rates described above are merely examples and do not constitute a limitation on this application. Those skilled in the art can set different refresh rates for different regions according to actual circumstances.

[0178] It should also be noted that the above example illustrates three regions corresponding to different refresh frequencies, but does not constitute a limitation of this application. Since the pixel driving circuit provided in the embodiments of this application can realize the refresh of any single pixel, in other optional embodiments of this application, there can also be four regions corresponding to different refresh frequencies, five regions corresponding to different refresh frequencies, etc., and there can also be refreshes of regions with the same refresh frequency for two non-adjacent regions, and regions formed by arbitrary shapes, etc. For example, as shown... Figure 26 As shown, only the pixels within region E are refreshed. Specifically, when the pixel row corresponding to region E is scanned, the data signal terminal corresponding to the pixel column within region E is at a low level during the first sub-stage T1-1 of the reset phase T1, thus completing the refresh of the pixels within region E.

[0179] In summary, without altering the scanning drive circuit and the light emission control drive circuit, the pixel drive circuit provided in this application embodiment allows any single pixel 11 within the display panel 10 to refresh data signals at different refresh rates. This means that different areas and positions of the display panel 10 refresh the displayed content at different refresh rates. For areas displaying static images / text, a lower refresh rate can be used, such as 1Hz or 10Hz. For areas displaying real-time changes, such as video, a higher refresh rate can be used, such as 60Hz. This reduces the power consumption of the display panel by lowering the refresh rate across different areas. Furthermore, the pixel drive circuit provided in this application embodiment can not only achieve localized refresh of localized areas but also localized refresh of areas of arbitrary shapes.

[0180] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit it. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

Claims

1. A display panel, characterized in that, include: Multiple pixels, wherein each pixel includes a pixel driving circuit and a light-emitting element; The pixel driving circuit includes a pixel driving module, a gating module, a control module, a data signal terminal, and a reset signal terminal. The gating module is electrically connected to both the control module and the pixel driving module, and the control module is electrically connected to the data signal terminal. The data signal terminal is used to transmit data signals; The reset signal terminal is used to transmit a reset signal; The display panel also includes multiple screen update cycles, which include a reset phase, a data writing phase, and a light emission phase; the reset phase includes a selection sub-phase and a reset sub-phase. In the selection sub-stage, the control module is used to control the gating module to be turned on or off according to the data signal written by the data signal terminal; When the gating module is turned on, in the reset sub-stage, the reset signal is written to the pixel driving module to reset the pixel driving module; in the data writing stage, the data signal is written to the pixel driving module to generate a driving current, and in the light emission stage, the driving current is provided to the light emission element to make the light emission element emit light corresponding to the driving current; The gating module includes a first gating unit, a second gating unit, and a third gating unit; the control module, the control terminal of the first gating unit, the control terminal of the second gating unit, and the control terminal of the third gating unit are coupled to a first node; the control module includes a data writing unit, a first control unit, a second control unit, and a voltage regulating unit; the first terminal of the voltage regulating unit, the data writing unit, the first control unit, and the second control unit are coupled to a third node, and the second terminal of the voltage regulating unit, the first control unit, the second control unit, and the gating module are coupled to the first node.

2. The display panel according to claim 1, characterized in that, The pixel driving module includes a driving module; The control module is used to send control signals to the control terminals of the first gating unit, the second gating unit, and the third gating unit in the selection sub-stage according to the data signal written by the data signal terminal, so as to control the first gating unit, the second gating unit, and the third gating unit to be turned on or off. When the first gating unit is turned on, during the reset sub-stage, the reset signal is written to the control terminal of the drive module to reset the control terminal of the drive module; when the second gating unit and the third gating unit are turned on, during the data writing stage, the drive module generates a drive current according to the data signal.

3. The display panel according to claim 2, characterized in that, The pixel driving module further includes a first reset module, a threshold compensation module, and a data writing module; the pixel driving circuit further includes a first scan signal terminal, a second scan signal terminal, and a third scan signal terminal. The first terminal of the first reset module is electrically connected to the reset signal terminal, the second terminal of the first reset module is electrically connected to the first terminal of the first gating unit, the control terminal of the first reset module is electrically connected to the first scan signal terminal, and the second terminal of the first gating unit, the control terminal of the driving module, and the first terminal of the threshold compensation module are coupled to the second node. The first end of the data writing module is electrically connected to the data signal end, the second end of the data writing module is electrically connected to the first end of the second gating unit, the control end of the data writing module is electrically connected to the second scanning signal end, the second end of the second gating unit is electrically connected to the first end of the driving module, and the second end of the driving module is electrically connected to the second end of the threshold compensation module. The control terminal of the threshold compensation module is electrically connected to the first terminal of the third gating unit, and the second terminal of the third gating unit is electrically connected to the third scanning signal terminal.

4. The display panel according to claim 3, characterized in that, The first gating unit includes a first transistor; The gate of the first transistor is electrically connected to the first node, the first terminal of the first transistor is electrically connected to the second terminal of the first reset module, and the second terminal of the first transistor is electrically connected to the second node.

5. The display panel according to claim 3, characterized in that, The second gating unit includes a second transistor; The gate of the second transistor is electrically connected to the first node, the first terminal of the second transistor is electrically connected to the second terminal of the data writing module, and the second terminal of the second transistor is electrically connected to the first terminal of the driving module.

6. The display panel according to claim 4, characterized in that, The second gating unit includes a second transistor; The gate of the second transistor is electrically connected to the first node, the first terminal of the second transistor is electrically connected to the second terminal of the data writing module, and the second terminal of the second transistor is electrically connected to the first terminal of the driving module.

7. The display panel according to claim 3, characterized in that, The third gating unit includes a third transistor; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control terminal of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal terminal.

8. The display panel according to claim 4, characterized in that, The third gating unit includes a third transistor; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control terminal of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal terminal.

9. The display panel according to claim 5, characterized in that, The third gating unit includes a third transistor; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control terminal of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal terminal.

10. The display panel according to claim 6, characterized in that, The third gating unit includes a third transistor; The gate of the third transistor is electrically connected to the first node, the first electrode of the third transistor is electrically connected to the control terminal of the threshold compensation module, and the second electrode of the third transistor is electrically connected to the third scan signal terminal.

11. The display panel according to claim 1, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

12. The display panel according to claim 2, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

13. The display panel according to claim 3, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

14. The display panel according to claim 4, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

15. The display panel according to claim 5, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

16. The display panel according to claim 6, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

17. The display panel according to claim 7, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

18. The display panel according to claim 8, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

19. The display panel according to claim 9, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

20. The display panel according to claim 10, characterized in that, The data writing unit, the first control unit, and the second control unit are all electrically connected to the gating module; In the selection sub-stage, the data writing unit is used to control the gating module to be turned on according to the first data signal written by the data signal terminal; When the gating module is turned on in the selection sub-stage, in the reset sub-stage and the data writing stage, the first control unit is used to control the gating module to continue to be turned on; During the light-emitting phase, the second control unit is used to control the gating module to turn off.

21. The display panel according to claim 1, characterized in that, The voltage regulation unit includes a first capacitor, the first terminal of the first capacitor, the data writing unit, the first control unit and the second control unit are coupled to the third node, and the second terminal of the first capacitor, the first control unit, the second control unit and the gating module are coupled to the first node.

22. The display panel according to claim 1, characterized in that, The pixel driving circuit also includes a fourth scanning signal terminal; The data writing unit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is electrically connected to the fourth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the data signal terminal, the second terminal of the fourth transistor is electrically connected to the first terminal and the gate of the fifth transistor, and the second terminal of the fifth transistor is electrically connected to the third node.

23. The display panel according to claim 21, characterized in that, The pixel driving circuit also includes a fourth scanning signal terminal; The data writing unit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is electrically connected to the fourth scan signal terminal, the first terminal of the fourth transistor is electrically connected to the data signal terminal, the second terminal of the fourth transistor is electrically connected to the first terminal and the gate of the fifth transistor, and the second terminal of the fifth transistor is electrically connected to the third node.

24. The display panel according to claim 1, characterized in that, The pixel driving circuit also includes a fourth scanning signal terminal; The first control unit includes a sixth transistor and a seventh transistor. The first terminal and the gate of the sixth transistor are electrically connected to the fourth scan signal terminal. The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor. The second terminal of the seventh transistor is electrically connected to the gating module. The gate of the seventh transistor is electrically connected to the third node.

25. The display panel according to claim 22, characterized in that, The pixel driving circuit also includes a fourth scanning signal terminal; The first control unit includes a sixth transistor and a seventh transistor. The first terminal and the gate of the sixth transistor are electrically connected to the fourth scan signal terminal. The second terminal of the sixth transistor is electrically connected to the first terminal of the seventh transistor. The second terminal of the seventh transistor is electrically connected to the gating module. The gate of the seventh transistor is electrically connected to the third node.

26. The display panel according to claim 1, characterized in that, The pixel driving circuit further includes a fourth scan signal terminal and a fifth scan signal terminal; The second control unit includes an eighth transistor and a ninth transistor. The gates of the eighth transistor and the ninth transistor are both electrically connected to the fifth scan signal terminal. The first terminal of the eighth transistor is electrically connected to the fourth scan signal terminal. The second terminal of the eighth transistor is electrically connected to the third node. The first terminal of the ninth transistor is electrically connected to the third node. The second terminal of the ninth transistor is electrically connected to the gating module.

27. The display panel according to claim 24, characterized in that, The pixel driving circuit further includes a fourth scan signal terminal and a fifth scan signal terminal; The second control unit includes an eighth transistor and a ninth transistor. The gates of the eighth transistor and the ninth transistor are both electrically connected to the fifth scan signal terminal. The first terminal of the eighth transistor is electrically connected to the fourth scan signal terminal. The second terminal of the eighth transistor is electrically connected to the third node. The first terminal of the ninth transistor is electrically connected to the third node. The second terminal of the ninth transistor is electrically connected to the gating module.

28. The display panel according to any one of claims 1-27, characterized in that, The effective level duration of the selection sub-stage is less than the effective level duration of the reset sub-stage.

29. The display panel according to any one of claims 1-27, characterized in that, Multiple pixel arrays arranged; The display panel also includes a driving circuit and multiple scan line groups; The driving circuit includes at least a first scanning driving circuit and a second scanning driving circuit, and the scan line group includes at least a first scan signal line and a second scan signal line; The first scan driving circuit includes multiple first scan signal output terminals, and the second scan driving circuit includes multiple second scan signal output terminals. The multiple first scan signal output terminals are electrically connected to multiple first scan signal lines in a one-to-one correspondence, and the multiple second scan signal output terminals are electrically connected to multiple second scan signal lines in a one-to-one correspondence. The pixel driving circuit further includes a first scan signal terminal, a second scan signal terminal, a third scan signal terminal, a fourth scan signal terminal, and a fifth scan signal terminal; The second scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the same first scan signal line; the third scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the same second scan signal line; the first scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scan signal line corresponding to other pixel rows; the fourth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to other pixel rows; and the fifth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to other pixel rows.

30. The display panel according to claim 29, characterized in that, The first scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the second scan signal line corresponding to the previous pixel row, the fourth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to the previous pixel row, and the fifth scan signal terminal in the pixel driving circuit of the same pixel row is electrically connected to the first scan signal line corresponding to the next pixel row.

31. An electronic device, characterized in that, Includes the display panel as described in any one of claims 1-30.

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