Display device, method of manufacturing the same, and head mounted display device

Abstract

A display device, a method of manufacturing the display device, and a head-mounted display device are provided. The display device includes a semiconductor substrate including a display area including a transistor and a non-display area around the display area in plan view, a light emitting element layer over the semiconductor substrate and including a light emitting element in the display area, an encapsulation layer, a color filter layer, a lens array layer, and a capping layer, the display device includes a light-emitting element layer, an encapsulation layer over the light-emitting element layer, a color filter layer over the encapsulation layer and including color filters overlapping the light-emitting elements, respectively, a lens array layer over the color filter layer and including lenses in a display area, a cover layer over the lens array layer, the cover layer having a flat top surface and side surfaces, and the capping layer surrounds the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer in a plan view.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0149151 filed in the Korean Intellectual Property Office on November 1, 2023, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a display device, a method of manufacturing the display device, and a head-mounted display device including the display device. Background Art

[0004] A head mounted display device (HMD) is an image display device that is worn on a user's head in the form of glasses or a helmet to form a focus at a relatively close distance in front of the user's eyes. The head mounted display device can realize virtual reality (VR) or augmented reality (AR).

[0005] The head-mounted display device enlarges the image displayed on the small display device by using a plurality of lenses, and displays the enlarged image. Therefore, the display device applied to the head-mounted display device needs to provide a high-resolution image, for example, an image with a resolution of 3000PPI (pixels per inch) or more. For this reason, an organic light-emitting diode on silicon (OLEDoS), which is a small organic light-emitting display device with high resolution, is used as a display device applied to the head-mounted display device. OLEDoS is an image display device in which an organic light-emitting diode (OLED) is positioned on a semiconductor wafer substrate on which a complementary metal oxide semiconductor (CMOS) is positioned. Summary of the invention

[0006] Aspects of the present disclosure provide a display device including a cover layer including a resin and having a smooth top surface without an additional hard cover member, and a method of manufacturing the display device.

[0007] Aspects of the present disclosure also provide a head-mounted display device including a display device.

[0008] However, the aspects of the present disclosure are not limited to those described herein. The above and other aspects of the present disclosure will become more apparent to those skilled in the art to which the present disclosure belongs by referring to the detailed description of the present disclosure given below.

[0009] According to one or more embodiments of the present disclosure, a display device includes a semiconductor substrate, a light emitting element layer, a packaging layer, a color filter layer, a lens array layer and a covering layer, the semiconductor substrate including a display area including a transistor and a non-display area around the display area in a plan view, the light emitting element layer is located above the semiconductor substrate and includes a light emitting element in the display area, the packaging layer is located above the light emitting element layer, the color filter layer is located above the packaging layer and includes color filters respectively overlapping the light emitting elements, the lens array layer is located above the color filter layer and includes lenses located in the display area, the covering layer is located above the lens array layer, the covering layer has a flat top surface and side surfaces, and the covering layer surrounds the light emitting element layer, the packaging layer, the color filter layer and the lens array layer in a plan view.

[0010] The display device may further include a pad in the non-display area, wherein the cover layer does not overlap the pad.

[0011] The display device may further include a sealing dam in the non-display area and surrounding the cover layer in plan view, wherein a plan area of ​​a region surrounded by the sealing dam is equal to a plan area of ​​the cover layer.

[0012] The sealing dam may contact a side surface of the cover layer, wherein a height of the sealing dam is equal to a height of the cover layer.

[0013] The display device may further include a gate driver and a scan driver in the non-display area, wherein the sealing dam surrounds the gate driver and the scan driver in a plan view, and wherein the cover layer overlaps the gate driver and the scan driver.

[0014] The sealing dam and the cover layer may comprise a polymer resin.

[0015] The encapsulation layer may include a first inorganic encapsulation layer, an organic encapsulation layer located above the first inorganic encapsulation layer, and a second inorganic encapsulation layer located above the organic encapsulation layer, wherein the cover layer overlaps an inorganic bonding region where the first and second inorganic encapsulation layers contact each other in the non-display region.

[0016] The cover layer may directly contact the lenses of the lens array layer.

[0017] According to one or more embodiments of the present disclosure, a method for manufacturing a display device includes: preparing a wafer substrate including a transistor and having a unit area defined therein, forming a light emitting element layer including a light emitting element in the unit area of ​​the wafer substrate, forming an encapsulation layer above the light emitting element layer, forming a color filter layer above the encapsulation layer, forming a lens array layer above the color filter layer, applying a resin layer on the lens array layer, flattening the top surface of the resin layer, curing the resin layer to form a covering layer surrounding the light emitting element layer, the encapsulation layer, the color filter layer and the lens array layer in a plan view, and dividing the wafer substrate into unit areas to form a display panel.

[0018] The method may further include forming a sealing dam surrounding the light emitting element layer for a unit area of ​​the wafer substrate, wherein the resin layer is applied within a region surrounded by the sealing dam.

[0019] The planarization of the top surface of the resin layer may include attaching a release film having a flat bottom surface onto the sealing dam and the resin layer, wherein the resin layer fills a space defined by the sealing dam and the release film.

[0020] In the attachment of the release film, the resin layer may surround the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer within a unit area of ​​the wafer substrate in a plan view.

[0021] The cover layer may include a flat top surface and side surfaces directly contacting the sealing dam.

[0022] The planarization of the top surface of the resin layer includes placing a mold including a recessed portion corresponding to a unit area where the light emitting element layer is located, wherein the resin layer fills a space defined by the wafer substrate and the mold.

[0023] The depth of the recessed portion of the mold may be equal to the thickness of the covering layer.

[0024] The mold may include a transparent material.

[0025] The method may also include placing a mask including holes corresponding to the unit areas respectively on the wafer substrate, wherein planarizing the top surface of the resin layer includes placing a mold on the mask, and wherein the resin layer fills a space defined by the wafer substrate, the mask and the mold.

[0026] The resin layer may surround the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer.

[0027] The thickness of the mask may be greater than the height of the lens array layer, wherein the mold has a bottom surface having protrusions respectively corresponding to the holes of the mask, and wherein a thickness of the protrusions of the mold is less than a thickness of the mask.

[0028] The mask may include a metallic material, wherein the mold includes a flexible material.

[0029] The mask may comprise a flexible material, wherein the mold is a transparent hard mold.

[0030] The method may also include placing a soft mask having holes respectively corresponding to the unit areas on a wafer substrate, wherein planarizing the top surface of the resin layer includes placing a stripping film having a flat bottom surface on the soft mask, and wherein the resin layer fills the space defined by the wafer substrate, the soft mask and the stripping film.

[0031] The thickness of the soft mask may be substantially equal to the thickness of the capping layer.

[0032] According to one or more embodiments of the present disclosure, a head-mounted display device includes a frame mounted on a user's body and corresponding to a left eye and a right eye, a display device located in the frame, and an eyepiece located above the display device, wherein the display device includes a semiconductor substrate, a light-emitting element layer, a packaging layer, a color filter layer, a lens array layer, and a covering layer, the semiconductor substrate including a display area including a transistor and a non-display area around the display area in a plan view, the light-emitting element layer is located above the semiconductor substrate and includes light-emitting elements in the display area, the packaging layer is located above the light-emitting element layer, the color filter layer is located above the packaging layer and includes color filters respectively overlapping the light-emitting elements, the lens array layer is located above the color filter layer and includes lenses located in the display area, the covering layer is located above the lens array layer, the covering layer has a flat top surface and side surfaces, and the covering layer surrounds the light-emitting element layer, the packaging layer, the color filter layer, and the lens array layer in a plan view.

[0033] The display device may further include a sealing dam surrounding the cover layer in a plan view in the non-display area, wherein the sealing dam directly contacts a side surface of the cover layer.

[0034] A method for manufacturing a display device according to one or more embodiments may include planarizing a top surface and a side surface of a resin layer applied on a light emitting element layer on a wafer substrate, and curing the resin layer to form a cover layer. The display device may include a cover layer having a smooth top surface capable of protecting a display panel without a separate hard cover member.

[0035] The display device according to one or more embodiments may reduce or prevent damage to a hard cover member during a manufacturing process and may have a smooth surface quality by including a cover layer made of a transparent resin.

[0036] However, aspects according to the embodiments of the present disclosure are not limited to those exemplified above, and various other aspects are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] The above and other aspects of the present disclosure will become more apparent by describing in detail embodiments of the present disclosure with reference to the accompanying drawings, in which:

[0038] Figure 1 is an exploded perspective view of a display device according to one or more embodiments;

[0039] Figure 2 is a block diagram showing a display device according to one or more embodiments;

[0040] Figure 3 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments;

[0041] Figure 4is a diagram showing a display panel according to one or more embodiments;

[0042] Figure 5 is a view showing a layout of a sealing dam and a cover layer positioned in a display panel according to one or more embodiments;

[0043] Figure 6 It is shown that the positioning Figure 4 A plan view of first electrodes and emission regions of a plurality of pixels in a display area and a pixel defining layer;

[0044] Figure 7 is a plan view showing first electrodes and emission regions of a plurality of sub-pixels and a pixel defining layer according to one or more other embodiments;

[0045] Figure 8 is along Figure 6 A schematic cross-sectional view taken along line AA';

[0046] Fig. 9 It is shown Figure 4 An enlarged view of region X;

[0047] Fig.10 is along Fig. 9 A schematic cross-sectional view taken along line BB';

[0048] Fig.11 It is shown Figure 4 An enlarged view of region Y;

[0049] Fig.12 is along Fig.11 A schematic cross-sectional view taken along line CC';

[0050] Fig.13 is a schematic cross-sectional view of a display panel along a second direction according to one or more embodiments;

[0051] Figures 14 to 24 are diagrams sequentially showing a manufacturing process of a display device according to one or more embodiments;

[0052] Fig.25 is a schematic cross-sectional view of a display panel of a display device along a second direction according to one or more other embodiments;

[0053] Figure 26 to Figure 31 is a cross-sectional view showing a portion of a manufacturing process of a display device according to one or more other embodiments;

[0054] Figure 32 to Figure 36 is a cross-sectional view showing a portion of a manufacturing process of a display device according to yet one or more other embodiments;

[0055] Fig.37 is a cross-sectional view illustrating one operation in a process of manufacturing a display device according to yet one or more other embodiments;

[0056] Figures 38 to 41 is a cross-sectional view showing a portion of a manufacturing process of a display device according to yet one or more other embodiments;

[0057] Fig.42 is a perspective view showing a head mounted display device according to one or more embodiments;

[0058] Fig.43 It is shown Fig.42 An exploded perspective view of an example of a head mounted display device; and

[0059] Fig.44 is a perspective view showing a head mounted display device according to one or more embodiments. DETAILED DESCRIPTION

[0060] By referring to the detailed description and drawings of the embodiments, various aspects of some embodiments of the present disclosure and methods for realizing these aspects can be more easily understood. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey various aspects of the present disclosure to those skilled in the art. Therefore, redundant, irrelevant or unrelated to the description of the embodiments, or unnecessary processes, elements and techniques for fully understanding various aspects of the present disclosure for those of ordinary skill in the art can be omitted. Unless otherwise stated, the same reference numerals, characters or combinations thereof represent the same elements throughout the drawings and written descriptions, and therefore their repeated descriptions can be omitted.

[0061] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The use of "can", "may" or "may not" when describing the embodiments corresponds to one or more embodiments of the present disclosure. The present disclosure encompasses all modifications, equivalents and alternatives within the scope of the ideas and techniques of the present disclosure. In addition, each of the features of the various embodiments of the present disclosure may be combined with each other in part or in whole, and various technical interlocks and drives are possible. Each embodiment may be implemented independently of one another, or may be implemented together in association.

[0062] In the drawings, the relative sizes of elements, layers, and regions may be exaggerated for clarity and / or descriptive purposes. In addition, the use of cross-hatching and / or shading in the drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for specific materials, material properties, dimensions, proportions, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements.

[0063] Various embodiments are described herein with reference to schematic cross-sectional illustrations as embodiments and / or intermediate structures. Thus, variations in the shapes of the illustrations caused by, for example, manufacturing techniques and / or tolerances are expected. In addition, for the purpose of describing embodiments according to the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Therefore, the embodiments disclosed herein should not be interpreted as being limited to the shapes of the elements, layers, or regions shown, but include deviations in shapes caused by, for example, manufacturing.

[0064] For example, an implanted region illustrated as a rectangle will, typically, have rounded or curved features and / or a gradient of implant concentration at its edges rather than a binary change from implanted to non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation takes place.

[0065] Spatial relative terms, such as "below", "below", "lower", "lower side", "below", "above", "upper side", etc., can be used in this article for the convenience of explanation, to describe the relationship between an element or feature and another (some) element or feature as shown in the figure. It should be understood that, in addition to the orientation depicted in the figure, spatial relative terms are intended to also cover the different orientations of the device in use or in operation. For example, if the device in the figure is turned over, the element described as "below", "below" or "below" other elements or features will be subsequently oriented to "above" other elements or features. Therefore, the example terms "below" and "below" can cover both the orientations of above and below. The device can be oriented in other ways (for example, rotated 90 degrees or in other orientations), and the spatial relative descriptors used in this article should be interpreted accordingly. Similarly, when the first part is described as being arranged "on" the second part, this indicates that the first part is arranged at the upper side or lower side of the second part, without being limited to its upper side based on the direction of gravity.

[0066] In addition, the phrase "in a plan view" means when observing the object portion from above, and the phrase "in a schematic cross-sectional view" means when observing the schematic cross-section taken by vertically cutting the object portion from the side. The term "overlap" or "overlapping" means that the first object may be located above or below the second object or on the side of the second object, and vice versa. Additionally, the term "overlap" may include stacking, facing or facing, extending on ..., covering or partially covering, or any other suitable term that will be appreciated and understood by a person of ordinary skill in the art. The expression "non-overlapping" may include the meaning of any other suitable corresponding words such as "separated from ... "or "set aside ... "or "offset from ... "and any other suitable corresponding words that will be appreciated and understood by a person of ordinary skill in the art. The terms "facing" and "facing" may mean that the first object may be directly or indirectly opposite to the second object. In the case where the third object is between the first object and the second object, although still facing each other, the first object and the second object may be understood to be indirectly opposite to each other.

[0067] It should be understood that when an element, layer, region, or component is referred to as being "formed on," "located on," "connected to," or "(operably or communicatively) coupled to" another element, layer, region, or component, the element, layer, region, or component can be directly formed on, located on, connected to, or directly coupled to another element, layer, region, or component, or indirectly formed on, located on, connected to, or indirectly coupled to another element, layer, region, or component such that there may be one or more intervening elements, layers, regions, or components. Additionally, this may collectively mean direct or indirect coupling or connection, and integral or non-integral coupling or connection. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it can be directly electrically connected or electrically coupled to the other layer, region, or component, or there may be one or more intervening layers, regions, or components. The one or more intervening components may include switches, resistors, capacitors, and / or the like. When describing embodiments, unless explicitly described as being directly connected, the statement of connection indicates an electrical connection, and "directly connected / directly coupled" or "directly on..." means that one component is directly connected or coupled to another component or is located on another component without intermediate components.

[0068] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the formation direction is not limited to the upward direction, but includes forming the part on the side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the situation that the part is "directly" located "below" another part, but also includes the situation that there is another part between the part and the other part. At the same time, other expressions such as "between...", "directly between..." or "adjacent to" and "directly adjacent to" that describe the relationship between parts can be interpreted similarly. It should be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer can be the only element or layer between the two elements or layers, or one or more intermediate elements or layers may also be present.

[0069] For the purposes of this disclosure, expressions such as "at least one of..." or "any of..." or "one or more of...", when following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" may be interpreted as only X; only Y; only Z; any combination of two or more of X, Y, and Z, such as XYZ, XYY, YZ, and ZZ; or any variation thereof. Similarly, the expression "at least one of A and B" may include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the relevant listed items. For example, the expression "A and / or B" may include A, B, or A and B. Similarly, expressions such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases, when preceding or following a list of elements, modify the entire list of elements, rather than modifying the individual elements in the list.

[0070] It should be understood that although the terms "first", "second", "third", etc. can be used in this article to describe various elements, components, areas, layers and / or sections, these elements, components, areas, layers and / or sections should not be limited by these terms. These terms do not correspond to a specific order, position or priority, and are only used to distinguish an element, member, component, area, region, layer, section or part from another element, member, component, area, region, layer, section or part. Therefore, the first element, component, area, layer or section described below can be referred to as the second element, component, area, layer or section without departing from the spirit and scope of the present disclosure. The description of the element as the "first" element may not require or imply the existence of the second element or other elements. The terms "first", "second", etc. can also be used in this article to distinguish different categories or groups of elements. For the sake of brevity, the terms "first", "second", etc. can respectively represent "first category (or first group)", "second category (or second group)", etc.

[0071] In the example, the DR1 axis, the DR2 axis, and / or the DR3 axis are not limited to the three axes of the rectangular coordinate system, and may be interpreted as having a broader meaning. For example, the DR1 axis, the DR2 axis, and the DR3 axis may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. The same applies to the first, second, and / or third directions.

[0072] The terms used herein are for the purpose of describing the embodiments only and are not intended to limit the present disclosure. Unless the context clearly indicates otherwise, the singular forms "a" and "an" as used herein are also intended to include the plural forms, and the plural forms are also intended to include the singular forms. It should also be understood that the terms "comprise", "comprising", "have", "having", "include" and "including" when used in this specification specify the presence of stated features, wholes, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, parts and / or groups thereof.

[0073] When one or more embodiments can be implemented differently, the specific process order can be performed differently from the described order. For example, two processes described in succession can be performed substantially simultaneously or in the reverse order of the described order.

[0074] As used herein, the terms "substantially", "about", "approximately" and similar terms are used as terms of approximation rather than as terms of degree, and are intended to take into account the inherent deviations in measured or calculated values ​​recognized by those of ordinary skill in the art. For example, "substantially" may include a range of + / -5% of the corresponding value. Taking into account the errors associated with the measurement and the measurement of a specific amount (i.e., the limitations of the measurement system), "about" or "approximately" as used herein include the stated values ​​and mean within an acceptable deviation range for a specific value as determined by those of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. In addition, the use of "may" when describing embodiments of the present disclosure refers to "one or more embodiments of the present disclosure".

[0075] In some embodiments, known structures and devices may be described in association with one or more functional blocks (e.g., block diagrams), units and / or modules in the accompanying drawings to avoid unnecessary obscurity of various embodiments. It will be understood by those skilled in the art that such blocks, units and / or modules are physically implemented by logic circuits, separate components, microprocessors, hard-wired circuits, memory elements, line connections and other electronic circuits. This can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units and / or modules implemented by microprocessors or other similar hardware can be programmed and controlled using software to perform the various functions discussed herein, and optionally, blocks, units and / or modules implemented by microprocessors or other similar hardware can be driven by firmware and / or software. In addition, each block, unit and / or module can be implemented by a combination of dedicated hardware or dedicated hardware that performs some functions and processors (e.g., one or more programmed microprocessors and related circuits) that perform functions different from those of the dedicated hardware. In addition, in some embodiments, blocks, units and / or modules can be physically separated into two or more separate blocks, units and / or modules that interact with each other without departing from the scope of this disclosure. Additionally, in some embodiments, blocks, units and / or modules may be physically combined into more complex blocks, units and / or modules without departing from the scope of the present disclosure.

[0076] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. It should also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having the same meaning as they have in the context of the relevant technology and / or this specification, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein.

[0077] Figure 1is an exploded perspective view of a display device according to one or more embodiments.

[0078] Reference Figure 1 , the display device 10 according to one or more embodiments is a device that displays a moving image or a still image. The display device 10 according to one or more embodiments may be applied to a portable electronic device such as a mobile phone, a smart phone, a tablet personal computer, a mobile communication terminal, an electronic notepad, an electronic book, a portable multimedia player (PMP), a navigation system, an ultra mobile PC (UMPC), or the like. For example, the display device 10 may be applied as a display unit of a television, a notebook computer, a monitor, a billboard, or an Internet of Things (IoT) device. Alternatively, the display device 10 may be applied to a smart watch, a watch phone, a head mounted display device (HMD) for realizing virtual reality and augmented reality, and the like.

[0079] The display device 10 according to one or more embodiments includes a display panel 100 , a heat dissipation layer 200 , a circuit board 300 , a timing control circuit 400 , and a power supply circuit 500 .

[0080] The display panel 100 may have a planar shape similar to a quadrilateral shape. For example, the display panel 100 may have a planar shape similar to a quadrilateral shape having short sides in a first direction DR1 and long sides in a second direction DR2 intersecting the first direction DR1. In the display panel 100, a corner where the short side in the first direction DR1 and the long side in the second direction DR2 intersect may be a right angle, or rounded with a curvature (e.g., a predetermined curvature). The planar shape of the display panel 100 is not limited to a quadrilateral shape, and may be a shape similar to another polygonal shape, a circular shape, or an elliptical shape. The planar shape of the display device 10 may follow the planar shape of the display panel 100, but is not limited thereto.

[0081] The heat dissipation layer 200 may overlap the display panel 100 in the third direction DR3 which is the thickness direction of the display panel 100. The heat dissipation layer 200 may be positioned on one surface of the display panel 100, for example, on the rear surface thereof. The heat dissipation layer 200 serves to dissipate heat generated from the display panel 100. The heat dissipation layer 200 may include a metal layer such as silver (Ag), copper (Cu), or aluminum (Al) having high thermal conductivity, or graphite.

[0082] The circuit board 300 may be electrically connected to the pad portion PDA (see FIG. 1 ) of the display panel 100 by using a conductive adhesive member such as an anisotropic conductive film. Figure 4 ) of multiple pads PD (see Figure 4 ). The circuit board 300 may be a flexible printed circuit board or a flexible film having a flexible material. Figure 1100, but the circuit board 300 may be bent. In this case, one end of the circuit board 300 may be positioned on the rear surface of the display panel 100 and / or the rear surface of the heat dissipation layer 200. One end of the circuit board 300 may be a pad portion PDA (see FIG. 100 ) of the circuit board 300 connected to the display panel 100 by using a conductive adhesive member. Figure 4 ) of multiple pads PD (see Figure 4 ) at the opposite end of the other end.

[0083] The timing control circuit 400 may receive digital video data and a timing signal input from the outside. The timing control circuit 400 may generate a scanning timing control signal SCS (see FIG. 1 ) for controlling the display panel 100 in response to the timing signal. Figure 2 ), transmit timing control signal ECS (see Figure 2 ) and the data timing control signal DCS (see Figure 2 The timing control circuit 400 may output the scan timing control signal SCS to the scan driver 610 (see Figure 2 ), and the emission timing control signal ECS may be output to the emission driver 620 (see Figure 2 The timing control circuit 400 can output the digital video data and the data timing control signal DCS to the data driver 700 (see Figure 2 ).

[0084] The power supply circuit 500 may generate a plurality of panel driving voltages according to a power supply voltage from the outside. For example, the power supply circuit 500 may generate a first driving voltage VSS (see Figure 2 ), the second driving voltage VDD (see Figure 2 ) and the third driving voltage VINT (see Figure 2 ), and these voltages can be supplied to the display panel 100. Figure 3 A first driving voltage VSS, a second driving voltage VDD, and a third driving voltage VINT are described.

[0085] Each of the timing control circuit 400 and the power supply circuit 500 may be formed as an integrated circuit (IC) and may be attached to one surface of the circuit board 300. In this case, the scanning timing control signal SCS, the emission timing control signal ECS, the digital video data DATA (see Figure 2 ) and the data timing control signal DCS may be supplied to the display panel 100 through the circuit board 300. In addition, the first driving voltage VSS, the second driving voltage VDD, and the third driving voltage VINT of the power supply circuit 500 may be supplied to the display panel 100 through the circuit board 300.

[0086] Alternatively, similar to the scan driver 610, the emission driver 620, and the data driver 700, each of the timing control circuit 400 and the power supply circuit 500 may be positioned in the non-display area NDA (see FIG. 1 ) of the display panel 100. Figure 2 ). In this case, the timing control circuit 400 may include a plurality of timing transistors, and each of the power supply circuits 500 may include a plurality of power supply transistors. The plurality of timing transistors and the plurality of power supply transistors may be formed on the semiconductor substrate SSUB (see Figure 8 ). For example, the plurality of timing transistors and the plurality of power supply transistors may be formed of CMOS. Each of the timing control circuit 400 and the power supply circuit 500 may be positioned between the data driver 700 and the pad portion PDA (see Figure 4 )between.

[0087] Figure 2 is a block diagram illustrating a display device according to one or more embodiments.

[0088] Reference Figure 2 , the display panel 100 may include a display area DAA and a non-display area NDA positioned around the display area DAA. In the display area DAA, a plurality of pixels PX are positioned to emit light or display an image. In the non-display area NDA, light may not be emitted, or an image may not be displayed.

[0089] The display panel 100 may include a plurality of pixels PX positioned in the display area DAA, a plurality of scan lines, a plurality of emission control lines EL (eg, EL1 and EL2 ), and a plurality of data lines DL.

[0090] A plurality of pixels PX may be arranged in a first direction DR1 and a second direction DR2. A plurality of pixels PX may be arranged in a matrix in the display area DAA. A plurality of scan lines and a plurality of emission control lines EL may extend in the first direction DR1 and may be arranged to be spaced apart in the second direction DR2. A plurality of data lines DL may extend in the second direction DR2 and may be arranged to be spaced apart in the first direction DR1.

[0091] The plurality of scan lines may include a plurality of write scan lines GWL, a plurality of control scan lines GCL, and a plurality of bias scan lines GBL. The plurality of emission control lines EL include a plurality of first emission control lines EL1 and a plurality of second emission control lines EL2.

[0092] The plurality of pixels PX may include a plurality of sub-pixels SP1, SP2, and SP3. The plurality of sub-pixels SP1, SP2, and SP3 may include Figure 3 The plurality of pixel transistors shown in FIG. The plurality of pixel transistors can be formed by a semiconductor process to be positioned on a semiconductor substrate SSUB (see Figure 8). For example, a plurality of pixel transistors may be formed by a complementary metal oxide semiconductor (CMOS).

[0093] Each of the plurality of sub-pixels SP1, SP2, and SP3 may be connected to any one of the plurality of write scan lines GWL, any one of the plurality of control scan lines GCL, any one of the plurality of bias scan lines GBL, any one of the plurality of first emission control lines EL1, any one of the plurality of second emission control lines EL2, and / or any one of the plurality of data lines DL. Each of the plurality of sub-pixels SP1, SP2, and SP3 may receive a data voltage of the data line DL in response to a write scan signal of the write scan line GWL, and emit light from the light emitting element according to the data voltage.

[0094] The display panel 100 may include a scan driver 610 , an emission driver 620 , and a data driver 700 positioned in the non-display area NDA.

[0095] The scan driver 610 includes a plurality of scan transistors, and the emission driver 620 includes a plurality of light emitting transistors. The plurality of scan transistors and the plurality of light emitting transistors may be formed on a semiconductor substrate SSUB (see Figure 8 ). For example, a plurality of scanning transistors and a plurality of light emitting transistors may be formed by CMOS. Figure 2 , the scan driver 610 is positioned on the left side of the display area DAA and the emission driver 620 is positioned on the right side of the display area DAA, but the present disclosure is not limited thereto. For example, the scan driver 610 and the emission driver 620 may be positioned on both the left and right sides of the display area DAA.

[0096] The scan driver 610 may include a write scan signal output unit 611, a control scan signal output unit 612, and a bias scan signal output unit 613. Each of the write scan signal output unit 611, the control scan signal output unit 612, and the bias scan signal output unit 613 may receive a scan timing control signal SCS from the timing control circuit 400. The write scan signal output unit 611 may generate a write scan signal according to the scan timing control signal SCS of the timing control circuit 400, and may sequentially output them to the write scan line GWL. The control scan signal output unit 612 may generate a control scan signal in response to the scan timing control signal SCS, and may sequentially output them to the control scan line GCL. The bias scan signal output unit 613 may generate a bias scan signal according to the scan timing control signal SCS, and may sequentially output them to the bias scan line GBL.

[0097] The emission driver 620 includes a first emission control driver 621 and a second emission control driver 622. Each of the first emission control driver 621 and the second emission control driver 622 may receive an emission timing control signal ECS from the timing control circuit 400. The first emission control driver 621 may generate first emission control signals according to the emission timing control signal ECS and sequentially output them to the first emission control line EL1. The second emission control driver 622 may generate second emission control signals according to the emission timing control signal ECS and sequentially output them to the second emission control line EL2.

[0098] The data driver 700 may include a plurality of data transistors, and the plurality of data transistors may be formed on a semiconductor substrate SSUB (see Figure 8 For example, the plurality of data transistors may be formed of CMOS.

[0099] The data driver 700 may receive the digital video data DATA and the data timing control signal DCS from the timing control circuit 400. The data driver 700 converts the digital video data DATA into an analog data voltage according to the data timing control signal DCS, and outputs the analog data voltage to the data line DL. In this case, the sub-pixels SP1, SP2, and SP3 are selected by the write scan signal of the scan driver 610, and the data voltage may be supplied to the selected sub-pixels SP1, SP2, and SP3.

[0100] Figure 3 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0101] Reference Figure 3 , the sub-pixel SP can be connected to the write scan line GWL, the control scan line GCL, the bias scan line GBL, the first emission control line EL1, the second emission control line EL2 and the data line DL. In addition, the sub-pixel SP can be connected to a first driving voltage VSS (see Figure 2 ) and a first driving voltage line VSL to which a second driving voltage VDD corresponding to a high potential voltage is applied (see Figure 2 ) and a second driving voltage line VDL to which a third driving voltage VINT corresponding to the initialization voltage is applied (see Figure 2 ). That is, the first driving voltage line VSL may be a low potential voltage line, the second driving voltage line VDL may be a high potential voltage line, and the third driving voltage line VIL may be an initialization voltage line. In this case, the first driving voltage VSS may be lower than the third driving voltage VINT. The second driving voltage VDD may be higher than the third driving voltage VINT.

[0102] The sub-pixel SP includes a plurality of transistors T1 , T2 , T3 , T4 , T5 , and T6 , a light emitting element LE, a first capacitor C1 , and a second capacitor C2 .

[0103] The light emitting element LE emits light in response to a driving current flowing through the channel of the first transistor T1. The emission amount of the light emitting element LE may be proportional to the driving current. The light emitting element LE may be positioned between the fourth transistor T4 and the first driving voltage line VSL. The first electrode of the light emitting element LE may be connected to the drain electrode of the fourth transistor T4, and the second electrode thereof may be connected to the first driving voltage line VSL. The first electrode of the light emitting element LE may be an anode, and the second electrode of the light emitting element LE may be a cathode. The light emitting element LE may be an organic light emitting diode including a first electrode, a second electrode, and an organic light emitting layer positioned between the first electrode and the second electrode, but is not limited thereto. For example, the light emitting element LE may be an inorganic light emitting element including a first electrode, a second electrode, and an inorganic semiconductor positioned between the first electrode and the second electrode, in which case the light emitting element LE may be a micro light emitting diode.

[0104] The first transistor T1 may be a driving transistor that controls a source-drain current (or referred to as a "driving current") flowing between its source electrode and drain electrode according to a voltage applied to its gate electrode. The first transistor T1 includes a gate electrode connected to the first node N1, a source electrode connected to the drain electrode of the sixth transistor T6, and a drain electrode connected to the second node N2.

[0105] The second transistor T2 may be positioned between one electrode of the first capacitor C1 and the data line DL. The second transistor T2 is turned on by a write scan signal of the write scan line GWL to connect one electrode of the first capacitor C1 to the data line DL. Therefore, a data voltage of the data line DL may be applied to one electrode of the first capacitor C1. The second transistor T2 includes a gate electrode connected to the write scan line GWL, a source electrode connected to the data line DL, and a drain electrode connected to one electrode of the first capacitor C1.

[0106] The third transistor T3 may be positioned between the first node N1 and the second node N2. The third transistor T3 is turned on by a control scan signal of the control scan line GCL to connect the first node N1 to the second node N2. For this reason, since the gate electrode and the drain electrode of the first transistor T1 are connected, the first transistor T1 may operate like a diode. The third transistor T3 includes a gate electrode connected to the control scan line GCL, a source electrode connected to the second node N2, and a drain electrode connected to the first node N1.

[0107] The fourth transistor T4 may be connected between the second node N2 and the third node N3. The fourth transistor T4 is turned on by the first emission control signal of the first emission control line EL1 to connect the second node N2 to the third node N3. Therefore, the driving current of the first transistor T1 may be supplied to the light emitting element LE. The fourth transistor T4 includes a gate electrode connected to the first emission control line EL1, a source electrode connected to the second node N2, and a drain electrode connected to the third node N3.

[0108] The fifth transistor T5 may be positioned between the third node N3 and the third driving voltage line VIL. The fifth transistor T5 is turned on by the bias scan signal of the bias scan line GBL to connect the third node N3 to the third driving voltage line VIL. Therefore, the third driving voltage VINT of the third driving voltage line VIL may be applied to the first electrode of the light emitting element LE. The fifth transistor T5 includes a gate electrode connected to the bias scan line GBL, a source electrode connected to the third node N3, and a drain electrode connected to the third driving voltage line VIL.

[0109] The sixth transistor T6 may be positioned between the source electrode of the first transistor T1 and the second driving voltage line VDL. The sixth transistor T6 is turned on by the second emission control signal of the second emission control line EL2 to connect the source electrode of the first transistor T1 to the second driving voltage line VDL. Therefore, the second driving voltage VDD of the second driving voltage line VDL may be applied to the source electrode of the first transistor T1. The sixth transistor T6 includes a gate electrode connected to the second emission control line EL2, a source electrode connected to the second driving voltage line VDL, and a drain electrode connected to the source electrode of the first transistor T1.

[0110] The first capacitor C1 is formed between the first node N1 and the drain electrode of the second transistor T2. The first capacitor C1 includes one electrode connected to the drain electrode of the second transistor T2 and the other electrode connected to the first node N1.

[0111] The second capacitor C2 is formed between the gate electrode of the first transistor T1 and the second driving voltage line VDL. The second capacitor C2 includes one electrode connected to the gate electrode of the first transistor T1 and another electrode connected to the second driving voltage line VDL.

[0112] The first node N1 is a junction point between the gate electrode of the first transistor T1, the drain electrode of the third transistor T3, the other electrode of the first capacitor C1, and one electrode of the second capacitor C2. The second node N2 is a junction point between the drain electrode of the first transistor T1, the source electrode of the third transistor T3, and the source electrode of the fourth transistor T4. The third node N3 is a junction point between the drain electrode of the fourth transistor T4, the source electrode of the fifth transistor T5, and the first electrode of the light emitting element LE.

[0113] Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a metal oxide semiconductor field effect transistor (MOSFET). For example, each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, but is not limited thereto. Each of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be an N-type MOSFET. Alternatively, some of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 may be a P-type MOSFET, and each of the remaining transistors may be an N-type MOSFET.

[0114] although Figure 3 The sub-pixel SP is shown to include six transistors T1, T2, T3, T4, T5 and T6 and two capacitors C1 and C2, but it should be noted that the equivalent circuit diagram of the sub-pixel SP is not limited to Figure 3 For example, the number of transistors and the number of capacitors of the sub-pixel SP are not limited to Figure 3 The example shown in .

[0115] Figure 4 is a diagram illustrating a display panel according to one or more embodiments. Figure 5 is a view illustrating a layout of a sealing dam and a cover layer positioned in a display panel according to one or more embodiments. Figure 5 Shows Figure 4 Layout of the sealing dam DAR and the cover layer DCL in the display panel 100.

[0116] Reference Figure 4 and Figure 5 , the display panel 100 according to one or more embodiments may include a plurality of pixels PX arranged in a matrix in a display area DAA. The display panel 100 may include a scan driver 610, an emission driver 620, a data driver 700, a first distribution circuit 710, a second distribution circuit 720, a pad portion PDA, a power connection portion PCA, a dam DAM, and a sealing dam DAR positioned in a non-display area NDA. In addition, in one or more embodiments, the display panel 100 may further include an electrostatic protection portion, a moisture penetration reduction portion (e.g., a penetration prevention portion), and a crack reduction portion (e.g., a crack prevention portion) placed between the dam DAM and the sealing dam DAR.

[0117] The scan driver 610 may be positioned on a first side of the display area DAA, and the emission driver 620 may be positioned on a second side of the display area DAA. For example, the scan driver 610 may be positioned on one side of the display area DAA in the first direction DR1, and the emission driver 620 may be positioned on the other side of the display area DAA in the first direction DR1. That is, the scan driver 610 may be positioned on the left side of the display area DAA, and the emission driver 620 may be positioned on the right side of the display area DAA. However, the present specification is not limited thereto, and the scan driver 610 and the emission driver 620 may be positioned on both the first side and the second side of the display area DAA.

[0118] The pad portion PDA may include a plurality of pads PD connected to pads or bumps of the circuit board 300 through a conductive adhesive member. The pad portion PDA may be positioned on a third side of the display area DAA. For example, the pad portion PDA may be positioned on one side of the display area DAA in the second direction DR2. That is, the pad portion PDA may be positioned on the lower side of the display area DAA. The pad portion PDA may be positioned outside the data driver 700 in the second direction DR2 (as used herein, "outside" may mean "outside in a plan view"). That is, the pad portion PDA may be positioned closer to the edge of the display panel 100 than the data driver 700.

[0119] In one or more embodiments, the display panel 100 may further include an inspection pad for inspecting whether the display panel 100 operates normally. The inspection pad may be connected to a fixture or a probe pin during an inspection process, or may be connected to a circuit board for inspection. The circuit board for inspection may be a printed circuit board made of a rigid material or a flexible printed circuit board made of a flexible material.

[0120] The first distribution circuit 710 distributes the data voltage applied through the pad portion PDA to the plurality of data lines DL. For example, the first distribution circuit 710 may distribute the data voltage applied through one pad PD of the pad portion PDA to P data lines DL (P is a positive integer of 2 or more), and as a result, the number of the plurality of pads PD may be reduced. The first distribution circuit 710 may be positioned on a third side of the display area DAA of the display panel 100. For example, the first distribution circuit 710 may be positioned on one side of the display area DAA in the second direction DR2. That is, the first distribution circuit 710 may be positioned on the lower side of the display area DAA.

[0121] The second distribution circuit 720 distributes the signal applied through the pad portion PDA to the scan driver 610, the emission driver 620, and the data line DL. The second distribution circuit 720 may be configured to check the operation of each of the pixels PX in the display area DAA. The second distribution circuit 720 may be positioned on a fourth side of the display area DAA of the display panel 100. For example, the second distribution circuit 720 may be positioned on the other side of the display area DAA in the second direction DR2. That is, the second distribution circuit 720 may be positioned on the upper side of the display area DAA. However, the second distribution circuit 720 may be omitted.

[0122] The power connection part PCA refers to the light emitting element LE (see Figure 3 ) is connected to the second electrode to which the first driving voltage VSS is applied (see Figure 2 ) is connected to the power connection electrode to apply the first driving voltage VSS to the light emitting element LE (see Figure 3 ) in the area of ​​the second electrode.

[0123] The power connection part PCA may be positioned to surround the display area DAA (as used herein, "surrounding" may mean "surrounding in a plan view"). In addition, the power connection part PCA may be positioned outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the power connection part PCA may be positioned closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The power connection part PCA may be positioned to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. However, the present specification is not limited thereto, and the power connection part PCA may overlap with at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0124] The dam DAM may be used to reduce or prevent the light emitting element LE from being packaged (see Figure 3 ) of the encapsulation layer TFE of the organic encapsulation layer TFE2 (see Figure 8 ) has the possibility of overflowing to the pad portion of the PDA.

[0125] The dam DAM may be arranged to surround the display area DAA. In addition, the dam DAM may be positioned outside the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. For example, the dam DAM may be positioned closer to the edge of the display panel 100 than the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. The dam DAM may be positioned to surround the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720. However, the present specification is not limited thereto, and the dam DAM may overlap with at least one of the scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 in the third direction DR3.

[0126] In addition, the dam DAM may be positioned outside the power connection part PCA. For example, the dam DAM may be positioned closer to the edge of the display panel 100 than the power connection part PCA. The dam DAM may be positioned to surround the power connection part PCA.

[0127] According to one or more embodiments, the display device 10 may include a sealing dam DAR and a cover layer DCL positioned in the display panel 100. The sealing dam DAR may be positioned outside the dam DAM to surround the display area DAA and the dam DAM. The scan driver 610, the emission driver 620, the first distribution circuit 710, and the second distribution circuit 720 may be positioned in the area surrounded by the sealing dam DAR. In addition, the power connection part PCA and the inspection pad, the electrostatic protection part, the moisture penetration reduction part, and the crack reduction part not shown in the drawings may be further positioned in the area surrounded by the sealing dam DAR.

[0128] The cover layer DCL may be positioned in a region surrounded by the seal dam DAR. The cover layer DCL may be positioned to cover at least the pixels PX or the light emitting element layer EML of the display area DAA (see Figure 8 ). For example, the sealing dam DAR may be positioned outside the dam DAM in the non-display area NDA, and the cover layer DCL may be positioned over some portions of the display area DAA and the non-display area NDA to overlap with the plurality of pixels PX, the scan driver 610, the emission driver 620, the first distribution circuit 710, the second distribution circuit 720, the power connection part PCA, and the dam DAM. The cover layer DCL is the uppermost layer of the display panel 100 and may protect components positioned in the display panel 100.

[0129] Figure 6 It is shown that the positioning Figure 4 A plan view of first electrodes and emission regions of multiple pixels and a pixel defining layer in a display area.

[0130] Reference Figure 6 , multiple pixels PX (see Figure 2) may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may include emission areas EA1, EA2, and EA3, respectively. For example, the first sub-pixel SP1 may include a first emission area EA1, the second sub-pixel SP2 may include a second emission area EA2, and the third sub-pixel SP3 may include a third emission area EA3.

[0131] Each of the first, second, and third emission regions EA1, EA2, and EA3 may be a region defined by the pixel defining layer PDL. For example, each of the first, second, and third emission regions EA1, EA2, and EA3 may be a region defined by the first pixel defining layer PDL1.

[0132] The length of the third emission area EA3 in the first direction DR1 may be smaller than that of the first emission area EA1 in the first direction DR1, and may be smaller than that of the second emission area EA2 in the first direction DR1. The length of the first emission area EA1 in the first direction DR1 and the length of the second emission area EA2 in the first direction DR1 may be substantially the same.

[0133] In each of the plurality of pixels PX, the first emission region EA1 and the second emission region EA2 may be adjacent to each other in the second direction DR2. In addition, the first emission region EA1 and the third emission region EA3 may be adjacent to each other in the first direction DR1. In addition, the second emission region EA2 and the third emission region EA3 may be adjacent to each other in the first direction DR1. The area of ​​the first emission region EA1, the area of ​​the second emission region EA2, and the area of ​​the third emission region EA3 may be different.

[0134] The first emission area EA1 may emit light of a first color, the second emission area EA2 may emit light of a second color, and the third emission area EA3 may emit light of a third color. Here, the light of the first color may be light of a red wavelength band, the light of the second color may be light of a green wavelength band, and the light of the third color may be light of a blue wavelength band. For example, the blue wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 370nm to about 460nm, the green wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 480nm to about 560nm, and the red wavelength band may be a wavelength band of light whose main peak wavelength is in the range of about 600nm to about 750nm.

[0135] Light emitting element LE (see Figure 3 ) of the first electrode AND (see Figure 8) may have a rectangular shape in a plan view. The plan shapes of the first electrodes AND of the light emitting elements LE in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be different. For example, the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2 may have a rectangular plan shape including a long side in the first direction DR1 and a short side in the second direction DR2. The first electrode AND of the third sub-pixel SP3 may have a rectangular shape including a short side in the first direction DR1 and a long side in the second direction DR2 in a plan view. The length of the first electrode AND of the third sub-pixel SP3 in the first direction DR1 may be shorter than the length of the first electrode AND of each of the first sub-pixel SP1 and the second sub-pixel SP2 in the first direction DR1. The length of the first electrode AND of the first sub-pixel SP1 in the second direction DR2 may be longer than the length of the first electrode AND of the second sub-pixel SP2 in the second direction DR2.

[0136] The first electrode AND of the light emitting element LE can be connected through the tenth through hole VA10 (see Figure 8 ) is connected to the reflective electrode layer RL (see Figure 8 ). The tenth through hole VA10 may overlap the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 in the third direction DR3.

[0137] At least one trench TRC may be used to disconnect the light emitting stack IL between adjacent emission areas EA1, EA2, and EA3 (see Figure 8 ) structure of at least one charge generation layer. At least one trench TRC may be positioned between the first emission area EA1 and the second emission area EA2, between the first emission area EA1 and the third emission area EA3, and between the second emission area EA2 and the third emission area EA3. For example, at least one trench TRC may be positioned between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the second sub-pixel SP2, between the first electrode AND of the first sub-pixel SP1 and the first electrode AND of the third sub-pixel SP3, and between the first electrode AND of the second sub-pixel SP2 and the first electrode AND of the third sub-pixel SP3.

[0138] Figure 7 is a plan view illustrating first electrodes and emission regions of a plurality of sub-pixels and a pixel defining layer according to one or more other embodiments.

[0139] Since the plane shapes of the first emission area EA1, the second emission area EA2 and the third emission area EA3 are different from those corresponding to Figure 6 One or more embodiments of the present invention are different from those of the present invention, corresponding to Figure 7 One or more embodiments corresponding to Figure 6 One or more embodiments of the present invention are substantially the same, and thus the description corresponding to Figure 6 A description of one or more embodiments is repeated.

[0140] Reference Figure 7 , the first emission area EA1, the second emission area EA2, and the third emission area EA3 may be positioned in a hexagonal structure having a hexagonal shape in a plan view. In this case, the first emission area EA1 and the second emission area EA2 may be adjacent to each other in the first direction DR1, and the second emission area EA2 and the third emission area EA3 may be adjacent to each other in the first oblique direction DD1, and the first emission area EA1 and the third emission area EA3 may be adjacent to each other in the second oblique direction DD2. The first oblique direction DD1 may be a direction between the first direction DR1 and the second direction DR2, and may refer to a direction inclined 45 degrees relative to the first direction DR1 and relative to the second direction DR2. The second oblique direction DD2 may be a direction perpendicular to the first oblique direction DD1.

[0141] Despite Figure 6 and Figure 7 , each of the plurality of pixels PX includes three emission areas EA1, EA2, and EA3, but the present disclosure is not limited thereto. That is, each of the plurality of pixels PX may include four emission areas.

[0142] In addition, the arrangement of the emission areas EA1, EA2, and EA3 of the plurality of pixels PX is not limited to Figure 6 and Figure 7 For example, the emission regions of the plurality of pixels PX may be positioned in a stripe structure in which the emission regions are arranged in a first direction DR1, in which the emission regions are arranged in a diamond shape, or in a plurality of pixels PX. Structure, etc. and is a registered trademark of Samsung Display Co., Ltd. of South Korea).

[0143] Figure 8 is along Figure 6 Schematic cross-sectional view taken along line AA'.

[0144] Reference Figure 8 , the display panel 100 may include a semiconductor backplane SBP, a light emitting element backplane EBP, a light emitting element layer EML, an encapsulation layer TFE, an adhesive layer ADL, a color filter layer CFL, a lens array layer LNS, and a cover layer DCL. In one or more embodiments, the display panel 100 may further include a polarizing plate positioned on the cover layer DCL.

[0145] The semiconductor backplane SBP includes a semiconductor substrate SSUB including a plurality of pixel transistors PTR, a plurality of semiconductor insulating layers covering the plurality of pixel transistors PTR, and a plurality of contact terminals CTE electrically connected to the plurality of pixel transistors PTR, respectively. Figure 3 The first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are described.

[0146] The semiconductor substrate SSUB may be a silicon substrate, a germanium substrate or a silicon germanium substrate. The semiconductor substrate SSUB may be a substrate doped with a first type of impurity. A plurality of well regions WA may be positioned below the top surface of the semiconductor substrate SSUB. The plurality of well regions WA may be regions doped with a second type of impurity. The second type of impurity may be different from the first type of impurity described above. For example, when the first type of impurity is a p-type impurity, the second type of impurity may be an n-type impurity. Alternatively, when the first type of impurity is an n-type impurity, the second type of impurity may be a p-type impurity.

[0147] Each of the plurality of well regions WA includes a source region SA corresponding to a source electrode of the pixel transistor PTR, a drain region DA corresponding to a drain electrode thereof, and a channel region CH positioned between the source region SA and the drain region DA.

[0148] A lower insulating layer BINS may be positioned between the gate electrode GE and the well area WA. A side insulating layer SINS may be positioned on a side surface of the gate electrode GE. The side insulating layer SINS may be positioned on the lower insulating layer BINS.

[0149] Each of the source region SA and the drain region DA may be a region doped with first type impurities. The gate electrode GE of the pixel transistor PTR may overlap the well region WA in the third direction DR3. The channel region CH may overlap the gate electrode GE in the third direction DR3. The source region SA may be positioned on one side of the gate electrode GE, and the drain region DA may be positioned on the other side of the gate electrode GE.

[0150] Each of the plurality of well regions WA further includes a first low-concentration impurity region LDD1 positioned between the channel region CH and the source region SA and a second low-concentration impurity region LDD2 positioned between the channel region CH and the drain region DA. The first low-concentration impurity region LDD1 may be a region having an impurity concentration lower than that of the source region SA due to the lower insulating layer BINS. The second low-concentration impurity region LDD2 may be a region having an impurity concentration lower than that of the drain region DA due to the lower insulating layer BINS. The distance between the source region SA and the drain region DA may be increased due to the presence of the first low-concentration impurity region LDD1 and the second low-concentration impurity region LDD2. Therefore, the length of the channel region CH of each of the pixel transistors PTR may be increased, thereby reducing or preventing punch-through and hot carrier phenomena that may be caused by a short channel.

[0151] A first semiconductor insulating layer SINS1 may be positioned on the semiconductor substrate SSUB. The first semiconductor insulating layer SINS1 may be made of silicon carbon nitride (SiCN) or silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0152] A second semiconductor insulating layer SINS2 may be positioned on the first semiconductor insulating layer SINS1. The second semiconductor insulating layer SINS2 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0153] A plurality of contact terminals CTE may be positioned on the second semiconductor insulating layer SINS2. Each of the plurality of contact terminals CTE may be connected to any one of the gate electrode GE, the source area SA, and the drain area DA of each of the pixel transistors PTR through a hole penetrating the first semiconductor insulating layer SINS1 and the second semiconductor insulating layer SINS2. The plurality of contact terminals CTE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them.

[0154] A third semiconductor insulating layer SINS3 may be positioned on the second semiconductor insulating layer SINS2. The third semiconductor insulating layer SINS3 may also be positioned on the side surface of each of the plurality of contact terminals CTE located on the second semiconductor insulating layer SINS2. The top surface of each of the plurality of contact terminals CTE may be exposed without being covered by the third semiconductor insulating layer SINS3. The third semiconductor insulating layer SINS3 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0155] The semiconductor substrate SSUB may be replaced with a glass substrate or a polymer resin substrate such as polyimide. In this case, the thin film transistor may be positioned on the glass substrate or the polymer resin substrate. The glass substrate may be a rigid substrate that does not bend, and the polymer resin substrate may be a flexible substrate that can be bent or folded.

[0156] The light emitting element backplane EBP includes a first metal layer ML1, a second metal layer ML2, a third metal layer ML3, a fourth metal layer ML4, a fifth metal layer ML5, a sixth metal layer ML6, a seventh metal layer ML7 and an eighth metal layer ML8, a reflective electrode layer RL and a plurality of through holes VA1, VA2, VA3, VA4, VA5, VA6, VA7, VA8, VA9 and VA10. In addition, the light emitting element backplane EBP includes a plurality of interlayer insulating layers INS1, INS2, INS3, INS4, INS5, INS6, INS7, INS8, INS9, INS10 and INS11 positioned between the semiconductor backplane SBP, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8, the reflective electrode layer RL and the light emitting element layer EML.

[0157] The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 may connect a plurality of contact terminals CTE exposed from the semiconductor backplane SBP to form Figure 3 The circuit of the sub-pixel SP shown in FIG. 1 , the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 (see FIG. Figure 3 ) may be formed in the semiconductor backplane SBP, and the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5 and the sixth transistor T6 are connected to the first capacitor C1 and the second capacitor C2 (see Figure 3 ) can be realized through the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8. In addition, the connection between the drain region corresponding to the drain electrode of the fourth transistor T4, the source region corresponding to the source electrode of the fifth transistor T5 and the first electrode of the light emitting element LE can also be realized through the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8.

[0158] A first interlayer insulating layer INS1 may be positioned on the semiconductor backplane SBP. Each of the first vias VA1 may penetrate the first interlayer insulating layer INS1 to be connected to the contact terminal CTE exposed from the semiconductor backplane SBP. Each of the first metal layers ML1 may be positioned on the first interlayer insulating layer INS1 and may be connected to the first vias VA1.

[0159] A second interlayer insulating layer INS2 may be positioned on the first interlayer insulating layer INS1 and the first metal layer ML1. Each of the second vias VA2 may penetrate the second interlayer insulating layer INS2 and may be connected to the exposed first metal layer ML1. Each of the second metal layers ML2 may be positioned on the second interlayer insulating layer INS2 and may be connected to the second vias VA2.

[0160] A third interlayer insulating layer INS3 may be positioned on the second interlayer insulating layer INS2 and the second metal layer ML2. Each of the third vias VA3 may penetrate the third interlayer insulating layer INS3 and may be connected to the exposed second metal layer ML2. Each of the third metal layers ML3 may be positioned on the third interlayer insulating layer INS3 and may be connected to the third vias VA3.

[0161] A fourth interlayer insulating layer INS4 may be positioned on the third interlayer insulating layer INS3 and the third metal layer ML3. Each of the fourth vias VA4 may penetrate the fourth interlayer insulating layer INS4 and may be connected to the exposed third metal layer ML3. Each of the fourth metal layers ML4 may be positioned on the fourth interlayer insulating layer INS4 and may be connected to the fourth vias VA4.

[0162] A fifth interlayer insulating layer INS5 may be positioned on the fourth interlayer insulating layer INS4 and the fourth metal layer ML4. Each of the fifth vias VA5 may penetrate the fifth interlayer insulating layer INS5 and may be connected to the exposed fourth metal layer ML4. Each of the fifth metal layers ML5 may be positioned on the fifth interlayer insulating layer INS5 and may be connected to the fifth vias VA5.

[0163] A sixth interlayer insulating layer INS6 may be positioned on the fifth interlayer insulating layer INS5 and the fifth metal layer ML5. Each of the sixth vias VA6 may penetrate the sixth interlayer insulating layer INS6 and may be connected to the exposed fifth metal layer ML5. Each of the sixth metal layers ML6 may be positioned on the sixth interlayer insulating layer INS6 and may be connected to the sixth vias VA6.

[0164] A seventh interlayer insulating layer INS7 may be positioned on the sixth interlayer insulating layer INS6 and the sixth metal layer ML6. Each of the seventh vias VA7 may penetrate the seventh interlayer insulating layer INS7 and may be connected to the exposed sixth metal layer ML6. Each of the seventh metal layers ML7 may be positioned on the seventh interlayer insulating layer INS7 and may be connected to the seventh vias VA7.

[0165] An eighth interlayer insulating layer INS8 may be positioned on the seventh interlayer insulating layer INS7 and the seventh metal layer ML7. Each of the eighth vias VA8 may penetrate the eighth interlayer insulating layer INS8 and may be connected to the exposed seventh metal layer ML7. Each of the eighth metal layers ML8 may be positioned on the eighth interlayer insulating layer INS8 and may be connected to the eighth vias VA8.

[0166] The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 and the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7 and the eighth through hole VA8 may be formed of substantially the same material. The first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 and the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7 and the eighth through hole VA8 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd) or an alloy including any one of them. The first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7 and the eighth through hole VA8 may be made of substantially the same material. The first interlayer insulating layer INS1, the second interlayer insulating layer INS2, the third interlayer insulating layer INS3, the fourth interlayer insulating layer INS4, the fifth interlayer insulating layer INS5, the sixth interlayer insulating layer INS6, the seventh interlayer insulating layer INS7 and the eighth interlayer insulating layer INS8 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0167] The thickness of the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be respectively greater than the thickness of the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, and the sixth through hole VA6. The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be greater than the thickness of the first metal layer ML1. The thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6 may be substantially the same. For example, the thickness of the first metal layer ML1 may be about The thickness of each of the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, and the sixth metal layer ML6 may be about 1000 mm. And the thickness of each of the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, and the sixth through hole VA6 may be about

[0168] The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of the first metal layer ML1, the thickness of the second metal layer ML2, the thickness of the third metal layer ML3, the thickness of the fourth metal layer ML4, the thickness of the fifth metal layer ML5, and the thickness of the sixth metal layer ML6. The thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be greater than the thickness of the seventh through hole VA7 and the thickness of the eighth through hole VA8. The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 may be greater than the thickness of the first through hole VA1, the thickness of the second through hole VA2, the thickness of the third through hole VA3, the thickness of the fourth through hole VA4, the thickness of the fifth through hole VA5, and the thickness of the sixth through hole VA6. The thickness of the seventh metal layer ML7 and the thickness of the eighth metal layer ML8 may be substantially the same. For example, the thickness of each of the seventh metal layer ML7 and the eighth metal layer ML8 may be approximately The thickness of each of the seventh through hole VA7 and the eighth through hole VA8 may be about

[0169] A ninth interlayer insulating layer INS9 may be located on the eighth interlayer insulating layer INS8 and the eighth metal layer ML8. The ninth interlayer insulating layer INS9 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0170] Each of the ninth via holes VA9 may penetrate the ninth interlayer insulating layer INS9 and may be connected to the exposed eighth metal layer ML8. The ninth via hole VA9 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the ninth via hole VA9 may be about 100 mm.

[0171] The reflective electrode layer RL may be positioned on the ninth interlayer insulating layer INS9. The reflective electrode layer RL may include at least one reflective electrode RL1, RL2, RL3, or RL4. Figure 8 As shown in , the reflective electrode layer RL may include a first reflective electrode RL1 , a second reflective electrode RL2 , a third reflective electrode RL3 , and a fourth reflective electrode RL4 .

[0172] Each of the first reflective electrodes RL1 may be positioned on the ninth interlayer insulating layer INS9 and may be connected to the ninth through hole VA9. The first reflective electrode RL1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. For example, the first reflective electrode RL1 may include titanium nitride (TiN).

[0173] Each of the second reflective electrodes RL2 may be positioned on the first reflective electrode RL1. The second reflective electrode RL2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. For example, the second reflective electrode RL2 may include aluminum (Al).

[0174] Each of the third reflective electrodes RL3 may be positioned on the second reflective electrode RL2. The third reflective electrode RL3 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. For example, the third reflective electrode RL3 may include titanium nitride (TiN).

[0175] The fourth reflective electrode RL4 may be positioned on the third reflective electrode RL3, respectively. The fourth reflective electrode RL4 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. For example, the fourth reflective electrode RL4 may include titanium (Ti).

[0176] Since the second reflective electrode RL2 substantially reflects the light from the light emitting element LE (see Figure 3 ), so the thickness of the second reflective electrode RL2 may be greater than the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4. For example, the thickness of each of the first reflective electrode RL1, the third reflective electrode RL3, and the fourth reflective electrode RL4 may be about And the thickness of the second reflective electrode RL2 may be

[0177] A tenth interlayer insulating layer INS10 may be positioned on the ninth interlayer insulating layer INS9. The tenth interlayer insulating layer INS10 may be positioned between the reflective electrode layers RL adjacent to each other. The tenth interlayer insulating layer INS10 may be positioned on the reflective electrode layer RL in the third sub-pixel SP3. The tenth interlayer insulating layer INS10 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0178] An eleventh interlayer insulating layer INS11 may be positioned on the tenth interlayer insulating layer INS10 and the reflective electrode layer RL. The eleventh interlayer insulating layer INS11 may be made of silicon oxide (SiO x )-based inorganic layer is formed, but is not limited thereto.

[0179] In at least one of the first to third subpixels SP1 to SP3 , the tenth and eleventh interlayer insulating layers INS10 and INS11 under the first electrode AND may be omitted in consideration of a resonance distance of light emitted from the light emitting element LE.

[0180] For example, the first electrode AND of the first subpixel SP1 may be directly positioned on the fourth reflective electrode RL4, and the first electrode AND of the first subpixel SP1 may not overlap the tenth interlayer insulating layer INS10 and the eleventh interlayer insulating layer INS11. The first electrode AND of the second subpixel SP2 may be positioned on the eleventh interlayer insulating layer INS11, and the eleventh interlayer insulating layer INS11 may be directly positioned on the fourth reflective electrode RL4. That is, the first electrode AND of the second subpixel SP2 may not overlap the tenth interlayer insulating layer INS10. The first electrode AND of the third subpixel SP3 may be positioned on the eleventh interlayer insulating layer INS11, and may overlap the tenth interlayer insulating layer INS10.

[0181] In one or more embodiments, the distance between the first electrode AND and the reflective electrode layer RL may be different in the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. In order to adjust the distance from the reflective electrode layer RL to the second electrode CAT according to the main wavelength of light emitted from each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3, the presence or absence of the tenth interlayer insulating layer INS10 and the eleventh interlayer insulating layer INS11 may be determined in each of the first subpixel SP1, the second subpixel SP2, and the third subpixel SP3. For example, in Figure 8 In the embodiment of the present invention, the distance between the first electrode AND and the reflective electrode layer RL in the third sub-pixel SP3 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2, and may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. The distance between the first electrode AND and the reflective electrode layer RL in the second sub-pixel SP2 may be greater than the distance between the first electrode AND and the reflective electrode layer RL in the first sub-pixel SP1. However, the present disclosure is not limited thereto. Various modifications and designs may be made to the distance between the first electrode AND and the reflective electrode layer RL in each of the sub-pixels SP1, SP2, and SP3.

[0182] In addition, although the tenth interlayer insulating layer INS10 and the eleventh interlayer insulating layer INS11 are shown in the drawings, in the sub-pixel SP (see Figure 3 ) may further be disposed under the first electrode AND of the second sub-pixel SP2. In this case, the eleventh interlayer insulating layer INS11 and the twelfth interlayer insulating layer may be positioned under the first electrode AND of the second sub-pixel SP2, and the tenth interlayer insulating layer INS10, the eleventh interlayer insulating layer INS11, and the twelfth interlayer insulating layer may be positioned under the first electrode AND of the third sub-pixel SP3.

[0183] Each of the tenth through holes VA10 in the second sub-pixel SP2 and the third sub-pixel SP3 may penetrate the tenth interlayer insulating layer INS10 and / or the eleventh interlayer insulating layer INS11 and may be connected to the exposed fourth reflective electrode RL4. The tenth through hole VA10 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any one of them. The thickness of the tenth through hole VA10 in the second sub-pixel SP2 may be less than the thickness of the tenth through hole VA10 in the third sub-pixel SP3.

[0184] The light emitting element layer EML may be positioned on the light emitting element back plate EBP. The light emitting element layer EML may include light emitting elements LE each having a first electrode AND, a light emitting stack IL, and a second electrode CAT, a pixel defining layer PDL, and a plurality of trenches TRC.

[0185] The first electrode AND of each of the light emitting elements LE may be positioned on the tenth interlayer insulating layer INS10 or the eleventh interlayer insulating layer INS11 and may be connected to the tenth through hole VA10, or may be positioned on the fourth reflective electrode RL4. In the second subpixel SP2 and the third subpixel SP3, the first electrode AND of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the tenth through hole VA10, the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4, the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7, the eighth through hole VA8, and the ninth through hole VA9, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, and the contact terminal CTE. In the first subpixel SP1, the first electrode AND of each of the light emitting elements LE may be connected to the drain area DA or the source area SA of the pixel transistor PTR through the first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3, and the fourth reflective electrode RL4, the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7, the eighth through hole VA8, and the ninth through hole VA9, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, and the contact terminal CTE. The first electrode AND of each of the light emitting elements LE may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), and neodymium (Nd), or an alloy including any of them. For example, the first electrode AND of each of the light emitting elements LE may be titanium nitride (TiN).

[0186] The pixel defining layer PDL may be positioned on a portion of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may cover an edge of the first electrode AND of each of the light emitting elements LE. The pixel defining layer PDL may be used to separate the first emission area EA1, the second emission area EA2, and the third emission area EA3.

[0187] The first emission area EA1 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the first sub-pixel SP1 to emit light. The second emission area EA2 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the second sub-pixel SP2 to emit light. The third emission area EA3 may be defined as a region where the first electrode AND, the light emitting stack IL, and the second electrode CAT are sequentially stacked in the third sub-pixel SP3 to emit light.

[0188] The pixel defining layer PDL may include a first pixel defining layer PDL1, a second pixel defining layer PDL2, and a third pixel defining layer PDL3. The first pixel defining layer PDL1 may be positioned on the edge of the first electrode AND of each of the light emitting elements LE. The second pixel defining layer PDL2 may be positioned on the first pixel defining layer PDL1. The third pixel defining layer PDL3 may be positioned on the second pixel defining layer PDL2. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may be made of silicon oxide (SiO x )-based inorganic layer, but is not limited thereto. The first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3 may each have a thickness of about Thickness.

[0189] When the first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 are formed into one pixel defining layer, the height of the one pixel defining layer increases, so that the first inorganic encapsulation layer TFE1 may be disconnected due to the step coverage. The step coverage refers to the ratio of the degree to which the film is coated on the inclined portion to the degree to which the film is coated on the flat portion. The lower the step coverage, the greater the possibility that the film will be disconnected at the inclined portion.

[0190] In order to reduce or prevent the possibility of disconnection of the first inorganic encapsulation layer TFE1 due to the step coverage, the first pixel defining layer PDL1, the second pixel defining layer PDL2 and the third pixel defining layer PDL3 may have a cross-sectional structure including a step portion. For example, the width of the first pixel defining layer PDL1 may be greater than the width of the second pixel defining layer PDL2 and the width of the third pixel defining layer PDL3. The width of the second pixel defining layer PDL2 may be greater than the width of the third pixel defining layer PDL3. The width of the first pixel defining layer PDL1 may refer to the width in the first direction DR1 and the second direction DR2 (see Figure 6 ) is a horizontal length of the first pixel defining layer PDL1 defined on the surface.

[0191] Each of the plurality of trenches TRC may penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. In each of the plurality of trenches TRC, a portion of the tenth interlayer insulating layer INS10 may be dug out / removed, and the eleventh interlayer insulating layer INS11 may have a shape in which the eleventh interlayer insulating layer INS11 is penetrated.

[0192] At least one trench TRC may be positioned between adjacent sub-pixels SP1 , SP2 , and SP3 . Figure 7 It is shown that two trenches TRC are positioned between adjacent sub-pixels SP1 , SP2 , and SP3 , but the present disclosure is not limited thereto.

[0193] The light emitting stack IL may include a plurality of intermediate layers. Figure 8 The light emitting stack IL is shown to have a triple-series structure including the first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3, but the present disclosure is not limited thereto. For example, the light emitting stack IL may have a double-series structure including two intermediate layers.

[0194] In the three-series structure, the light emitting stack IL may have a series structure including a plurality of intermediate layers IL1, IL2, and IL3 emitting different lights. For example, the light emitting stack IL may include a first intermediate layer IL1 emitting light of a first color, a second intermediate layer IL2 emitting light of a third color, and a third intermediate layer IL3 emitting light of a second color. The first intermediate layer IL1, the second intermediate layer IL2, and the third intermediate layer IL3 may be stacked sequentially.

[0195] The first intermediate layer IL1 may have a structure in which a first hole transport layer, a first organic light emitting layer emitting light of a first color, and a first electron transport layer are sequentially stacked. The second intermediate layer IL2 may have a structure in which a second hole transport layer, a second organic light emitting layer emitting light of a third color, and a second electron transport layer are sequentially stacked. The third intermediate layer IL3 may have a structure in which a third hole transport layer, a third organic light emitting layer emitting light of a second color, and a third electron transport layer are sequentially stacked.

[0196] A first charge generation layer for supplying charges to the second intermediate layer IL2 and for supplying electrons to the first intermediate layer IL1 may be positioned between the first intermediate layer IL1 and the second intermediate layer IL2. The first charge generation layer may include an N-type charge generation layer for supplying electrons to the first intermediate layer IL1 and a P-type charge generation layer for supplying holes to the second intermediate layer IL2. The N-type charge generation layer may include a dopant of a metal material.

[0197] A second charge generation layer for supplying charges to the third intermediate layer IL3 and for supplying electrons to the second intermediate layer IL2 may be positioned between the second intermediate layer IL2 and the third intermediate layer IL3. The second charge generation layer may include an N-type charge generation layer for supplying electrons to the second intermediate layer IL2 and a P-type charge generation layer for supplying holes to the third intermediate layer IL3.

[0198] The first intermediate layer IL1 may be positioned on the first electrode AND and the pixel defining layer PDL, and may be positioned on the bottom surface of each groove TRC. Due to the groove TRC, the first intermediate layer IL1 may be disconnected between adjacent sub-pixels SP1, SP2 and SP3. The second intermediate layer IL2 may be positioned on the first intermediate layer IL1. Due to the groove TRC, the second intermediate layer IL2 may be disconnected between adjacent sub-pixels SP1, SP2 and SP3. A gap or empty space ESS may be positioned between the first intermediate layer IL1 and the second intermediate layer IL2. The third intermediate layer IL3 may be positioned on the second intermediate layer IL2. The third intermediate layer IL3 may be positioned to cover the second intermediate layer IL2 in each of the grooves TRC without being disconnected by the grooves TRC. That is, in the three-series structure, each of the grooves TRC may be a structure for disconnecting the first charge generation layer, the second charge generation layer and / or the first intermediate layer IL1 and / or the second intermediate layer IL2 of the light emitting element layer EML between adjacent sub-pixels SP1, SP2 and SP3. Furthermore, in the dual tandem structure, each of the trenches TRC may be a structure for disconnecting the charge generation layer positioned between the lower intermediate layer and the upper intermediate layer, and the lower intermediate layer.

[0199] In order to stably disconnect the first intermediate layer IL1 and / or the second intermediate layer IL2 of the light emitting element layer EML between adjacent sub-pixels SP1, SP2 and SP3, the height of each groove TRC may be greater than the height of the pixel defining layer PDL. The height / depth of each of the plurality of grooves TRC refers to the length of each of the plurality of grooves TRC in the third direction DR3. The height of the pixel defining layer PDL refers to the length of the pixel defining layer PDL in the third direction DR3. In order to disconnect the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 of the light emitting element layer EML between adjacent sub-pixels SP1, SP2 and SP3, other structures may exist instead of the groove TRC. For example, a reverse tapered partition wall may be positioned on the pixel defining layer PDL instead of the groove TRC.

[0200] The number of the intermediate layers IL1, IL2 and IL3 emitting different light is not limited to Figure 8For example, the light emitting stack IL may include two intermediate layers. In this case, one of the two intermediate layers may be substantially the same as the first intermediate layer IL1, and the other may include a second hole transport layer, a second organic light emitting layer, a third organic light emitting layer, and a second electron transport layer. In this case, a charge generation layer for supplying electrons to one intermediate layer and for supplying charges to the other intermediate layer may be positioned between the two intermediate layers.

[0201] also, Figure 8 It is shown that the first intermediate layer IL1, the second intermediate layer IL2 and the third intermediate layer IL3 are all positioned in the first emission area EA1, the second emission area EA2, and the third emission area EA3, but the present disclosure is not limited thereto. For example, the first intermediate layer IL1 may be positioned in the first emission area EA1 and may be omitted in the second emission area EA2 and the third emission area EA3. In addition, the second intermediate layer IL2 may be positioned in the second emission area EA2 and may be omitted in the first emission area EA1 and the third emission area EA3. In addition, the third intermediate layer IL3 may be positioned in the third emission area EA3 and may be omitted in the first emission area EA1 and the second emission area EA2. In this case, the first color filter CF1, the second color filter CF2 and the third color filter CF3 of the optical layer may be omitted.

[0202] The second electrode CAT may be positioned on the third intermediate layer IL3. The second electrode CAT may be positioned on the third intermediate layer IL3 in each of the plurality of trenches TRC. The second electrode CAT may be formed of a transparent conductive material (TCO) such as ITO or IZO capable of transmitting light, or a semi-transmissive conductive material such as magnesium (Mg), silver (Ag), or an alloy of Mg and Ag. When the second electrode CAT is formed of the semi-transmissive conductive material, the light emission efficiency in each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be improved due to the microcavity effect.

[0203] The encapsulation layer TFE may be positioned on the light emitting element layer EML. The encapsulation layer TFE may include at least one inorganic layer TFE1 and / or TFE3 to reduce or prevent oxygen or moisture from penetrating into the light emitting element layer EML. In addition, the encapsulation layer TFE may include at least one organic layer to protect the light emitting element layer EML from foreign matter such as dust. For example, the encapsulation layer TFE may include a first inorganic encapsulation layer TFE1, an organic encapsulation layer TFE2, and a second inorganic encapsulation layer TFE3.

[0204] The first inorganic encapsulation layer TFE1 may be positioned on the second electrode CAT, the organic encapsulation layer TFE2 may be positioned on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be positioned on the organic encapsulation layer TFE2. The first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be formed by alternately stacking silicon nitride (SiN x ) layer, silicon oxynitride (SiO x N y ) layer, silicon oxide (SiO x ) layer, titanium oxide (TiO x ) layer and aluminum oxide (AlO x ) layer. The organic encapsulation layer TFE2 may be a monomer. Alternatively, the organic encapsulation layer TFE2 may be an organic layer such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin or the like.

[0205] The adhesive layer ADL may be positioned on the encapsulation layer TFE. The adhesive layer ADL may be a layer for bonding the encapsulation layer TFE to the layer positioned thereon. The adhesive layer ADL may be a double-sided adhesive member. In addition, the adhesive layer ADL may be a transparent adhesive member such as a transparent adhesive or a transparent adhesive resin.

[0206] The color filter layer CFL, the lens array layer LNS, and the cover layer DCL may be positioned on the adhesive layer ADL. The color filter layer CFL, the lens array layer LNS, and the cover layer DCL may constitute an optical layer of the display panel 100.

[0207] The color filter layer CFL may include a plurality of color filters CF1, CF2, and CF3 and may be positioned on the adhesive layer ADL. The first color filter CF1 may overlap the first emission area EA1 of the first subpixel SP1. The first color filter CF1 may transmit light of a first color (e.g., light of a red wavelength band). The first color filter CF1 may transmit light of a first color among the light emitted from the first emission area EA1.

[0208] The second color filter CF2 may overlap the second emission area EA2 of the second subpixel SP2. The second color filter CF2 may transmit light of a second color (eg, light of a green wavelength band). Therefore, the second color filter CF2 may transmit light of a second color among the light emitted from the second emission area EA2.

[0209] The third color filter CF3 may overlap the third emission area EA3 of the third subpixel SP3. The third color filter CF3 may transmit light of a third color (e.g., light of a blue wavelength band). Therefore, the third color filter CF3 may transmit light of a third color among the light emitted from the third emission area EA3.

[0210] The lens array layer LNS may be positioned in the display area DAA (see Figure 3 ) on the color filter layer CFL in the display device 10. The lens array layer LNS may include a plurality of lenses positioned in the display area DAA. The plurality of lenses may be positioned on the first color filter CF1, the second color filter CF2, and the third color filter CF3, respectively. Each of the plurality of lenses may be a structure for increasing the ratio of light guided to the front side of the display device 10. Each of the plurality of lenses may have a cross-sectional shape that is convex in an upward direction.

[0211] The cover layer DCL may be positioned on the lens array layer LNS. The cover layer DCL may be positioned directly on the plurality of lenses of the lens array layer LNS. The cover layer DCL may have a refractive index (e.g., a predetermined refractive index) such that light travels in a third direction DR3 at an interface between the plurality of lenses and the cover layer DCL. In addition, the cover layer DCL may be a planarization layer. The cover layer DCL may be an organic layer such as an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0212] In one or more embodiments, a polarizing plate may be positioned on the cover layer DCL. The polarizing plate may be a structure for reducing or preventing visibility degradation caused by reflection of external light. The polarizing plate may include a linear polarizing plate and a phase delay film. For example, the phase delay film may be a λ / 4 plate (quarter wave plate), but is not limited thereto. However, when visibility degradation caused by reflection of external light is sufficiently overcome by the first color filter CF1, the second color filter CF2, and the third color filter CF3, the polarizing plate may be omitted.

[0213] like Figure 8 As shown in , by forming a light emitting element backplane EBP and a light emitting element layer EML on a semiconductor substrate SSUB in which a plurality of transistors are formed, the size of a plurality of pixels PX can be greatly reduced, thereby providing a display device 10 that displays a high-resolution image.

[0214] Fig. 9 It is shown Figure 4 Magnified view of region X. Fig.10 is along Fig. 9 A schematic cross-sectional view taken along line BB'.

[0215] Figure 4 The region X may be a region positioned on a lower side which is one side of the display area DAA in the second direction DR2. Fig. 9 and Fig.10 The first distribution circuit 710 , the power connection part PCA, the dam DAM, the data driver 700 , the pad PD, and the sealing dam DAR positioned on the lower side of the display area DAA are shown.

[0216] Reference Fig. 9 and Fig.10 , the first distribution circuit 710, the power connection part PCA, the dam DAM, the data driver 700, the sealing dam DAR, and the pad PD may be sequentially positioned on the lower side of the display area DAA in the second direction DR2. However, the present disclosure is not limited thereto. In some embodiments, the power connection part PCA may overlap with the first distribution circuit 710 or the data driver 700 in the thickness direction, and the dam DAM may overlap with the first distribution circuit 710 or the data driver 700 in the thickness direction.

[0217] The first distribution circuit 710 may include a plurality of first distribution transistors DBTR1. Since each of the plurality of first distribution transistors DBTR1 may be formed to be combined with Figure 8 The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of first distribution transistors DBTR1 will be omitted. In addition, since the contact terminals CTE, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 electrically connected to the plurality of first distribution transistors DBTR1 and the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7 and the eighth through hole VA8 are also connected to the plurality of first distribution transistors DBTR1. Figure 8 Those described are substantially the same, so their description will be omitted.

[0218] The power connection portion PCA includes a first power connection area PCAA1 of the semiconductor substrate SSUB, a first power connection electrode PCE1, and a second power connection electrode PCE2.

[0219] The first driving voltage VSS (see Figure 2 ) may be applied to the first power connection area PCAA1 of the semiconductor substrate SSUB.

[0220] The first power connection electrode PCE1 may be positioned on the ninth interlayer insulating layer INS9. The first power connection electrode PCE1 may be connected to the first power connection area PCAA1 of the semiconductor substrate SSUB through the contact terminal CTE, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7, and the eighth metal layer ML8, and the first via VA1, the second via VA2, the third via VA3, the fourth via VA4, the fifth via VA5, the sixth via VA6, the seventh via VA7, and the eighth via VA8.

[0221] The first power connection electrode PCE1 may include a first sub-power connection electrode SPCE1, a second sub-power connection electrode SPCE2, a third sub-power connection electrode SPCE3, and a fourth sub-power connection electrode SPCE4. The first sub-power connection electrode SPCE1, the second sub-power connection electrode SPCE2, the third sub-power connection electrode SPCE3, and the fourth sub-power connection electrode SPCE4 of the first power connection electrode PCE1 may be respectively combined with Figure 8 The first reflective electrode RL1, the second reflective electrode RL2, the third reflective electrode RL3 and the fourth reflective electrode RL4 of the reflective electrode layer RL are described to be substantially the same. That is, the first sub-power connection electrode SPCE1 may correspond to the first reflective electrode RL1, the second sub-power connection electrode SPCE2 may correspond to the second reflective electrode RL2, the third sub-power connection electrode SPCE3 may correspond to the third reflective electrode RL3, and the fourth sub-power connection electrode SPCE4 may correspond to the fourth reflective electrode RL4.

[0222] The second power connection electrode PCE2 may be positioned on the tenth interlayer insulating layer INS10. The second power connection electrode PCE2 may be connected to the first power connection electrode PCE1 through the tenth via VA10. The second power connection electrode PCE2 may include a first electrode connected to the first power connection electrode PCE1. Figure 8 The material of the first electrode AND of the light emitting element LE described above is substantially the same material. The second power connection electrode PCE2 may be separated by the pixel defining layer PDL. The second electrode CAT of the light emitting element LE may be connected to the second power connection electrode PCE2 exposed by the pixel defining layer PDL without being covered.

[0223] The dam DAM may include a first sub-dam DM1 and a second sub-dam DM2. The first sub-dam DM1 and the second sub-dam DM2 may be substantially the same as the trench TRC. Each of the first sub-dam DM1 and the second sub-dam DM2 may penetrate the first pixel defining layer PDL1, the second pixel defining layer PDL2, and the third pixel defining layer PDL3. The tenth interlayer insulating layer INS10 may be partially recessed at each of the first sub-dam DM1 and the second sub-dam DM2.

[0224] In each of the first sub-dam DM1 and the second sub-dam DM2, the first inorganic encapsulation layer TFE1 may be positioned on the bottom surface, the organic encapsulation layer TFE2 may be positioned on the first inorganic encapsulation layer TFE1, and the second inorganic encapsulation layer TFE3 may be positioned on the organic encapsulation layer TFE2. The organic encapsulation layer TFE2 may be positioned to fill a portion of each of the first sub-dam DM1 and the second sub-dam DM2. Alternatively, the organic encapsulation layer TFE2 may be omitted in each of the first sub-dam DM1 and the second sub-dam DM2. That is, the first inorganic encapsulation layer TFE1 and the second inorganic encapsulation layer TFE3 may be positioned in each of the first sub-dam DM1 and the second sub-dam DM2.

[0225] The first and second sub-dams DM1 and DM2 can reduce or prevent the possibility that the organic encapsulation layer TFE2 flows into the pad portion PDA and covers the pad PD. In the case where the organic encapsulation layer TFE2 covers the pad PD, the pad PD may not be electrically connected to the circuit board 300 (see Figure 1 ).

[0226] The data driver 700 may include a plurality of data transistors DTR. Since each of the plurality of data transistors DTR may be formed to be coupled to Figure 8 The pixel transistors PTR described are substantially the same, so a detailed description of the plurality of data transistors DTR will be omitted. In addition, since the contact terminals CTE, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 electrically connected to the plurality of data transistors DTR and the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7 and the eighth through hole VA8 are also connected to the plurality of data transistors DTR. Figure 8 Those described are substantially the same, so their description will be omitted.

[0227] The sealing dam DAR may be positioned on the tenth interlayer insulating layer INS10. The sealing dam DAR may be positioned outside the dam DAM and the data driver 700 to surround them in the non-display area NDA. The sealing dam DAR may be positioned outside the encapsulation layer TFE and formed to have a height (e.g., a predetermined height) for forming a space in which the cover layer DCL is positioned. In one or more embodiments, the height of the sealing dam DAR may be greater than the depth of the dam DAM. Similar to the way in which the dam DAM is used to reduce or prevent the possibility of overflow of the organic encapsulation layer TFE2 of the encapsulation layer TFE, the sealing dam DAR may reduce or prevent the possibility of overflow of the material of the cover layer DCL. For example, the sealing dam DAR may be positioned to be spaced apart from the outer side surface of the pixel defining layer PDL, and the cover layer DCL may be filled between them.

[0228] Each of the pads PD may include a pad metal layer PML. The pad metal layer PML may include a first sub-pad metal layer SPML1 and a second sub-pad metal layer SPML2. The first sub-pad metal layer SPML1 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd), or an alloy including any one of them. The second sub-pad metal layer SPML2 may be formed of any one of copper (Cu), aluminum (Al), tungsten (W), molybdenum (Mo), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni) and neodymium (Nd), or an alloy including any one of them. For example, the first sub-pad metal layer SPML1 may be made of aluminum (Al) and may have a thickness of about In addition, the second sub-pad metal layer SPML2 may be made of titanium nitride (TiN) and may have a thickness of about The thickness of the pad metal layer PML may be greater than the thickness of the reflective electrode layer RL.

[0229] A portion of a top surface of the pad metal layer PML of each pad PD may be exposed without being covered by the tenth interlayer insulating layer INS10. The first sub-pad metal layer SPML1 may be connected to a pad via PVA9 penetrating the ninth interlayer insulating layer INS9 to be connected to the eighth metal layer ML8.

[0230] The encapsulation layer TFE and the cover layer DCL may also be positioned in a portion of the non-display area NDA positioned on the lower side of the display area DAA. In the case where the organic encapsulation layer TFE2 of the encapsulation layer TFE is positioned up to the inner side of the dam DAM, the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE may be positioned up to the outer side of the dam DAM to form an inorganic bonding region. The cover layer DCL may be positioned up to the outer side of the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE.

[0231] The covering layer DCL may be positioned beyond the display area DAA to the non-display area NDA so that at least the display area DAA may be completely covered. The covering layer DCL may be positioned in the space surrounded by the sealing dam DAR, and its bottom surface may be in contact with the encapsulation layer TFE and the pixel defining layer PDL, and its side surface may be in contact with the sealing dam DAR. The covering layer DCL may be positioned to surround the outer surfaces of the components positioned on the backplanes SBP and EBP to protect them and fill the step portions formed by the components. In one or more embodiments, the covering layer DCL may also be partially positioned in the non-display area NDA located on the upper side of the display area DAA.

[0232] Fig.11 It is shown Figure 4 A magnified view of area Y. Fig.12 is along Fig.11 Schematic cross-sectional view taken along line CC'.

[0233] Figure 4 The region Y may be a region positioned on the left side which is one side of the display area DAA in the first direction DR1. Fig.11 and Fig.12 The scan driver 610 , the power connection part PCA, the dam DAM, and the sealing dam DAR positioned on the left side of the display area DAA are shown.

[0234] Reference Fig.11 and Fig.12 , the scan driver 610, the power connection part PCA, the dam DAM, and the sealing dam DAR may be sequentially positioned on the left side of the display area DAA in the first direction DR1. However, the present disclosure is not limited thereto, and the power connection part PCA may overlap with the scan driver 610 in the thickness direction, and the dam DAM may overlap with the scan driver 610 in the thickness direction.

[0235] The scan driver 610 may include a plurality of scan transistors STR. Since each of the plurality of scan transistors STR may be formed to be coupled to Figure 8 The pixel transistors PTR described are substantially the same, so the detailed description of the plurality of scanning transistors STR will be omitted. In addition, since the contact terminals CTE, the first metal layer ML1, the second metal layer ML2, the third metal layer ML3, the fourth metal layer ML4, the fifth metal layer ML5, the sixth metal layer ML6, the seventh metal layer ML7 and the eighth metal layer ML8 electrically connected to the plurality of scanning transistors STR and the first through hole VA1, the second through hole VA2, the third through hole VA3, the fourth through hole VA4, the fifth through hole VA5, the sixth through hole VA6, the seventh through hole VA7 and the eighth through hole VA8 are also connected to the plurality of scanning transistors STR. Figure 8 Those described are substantially the same, so their description will be omitted.

[0236] Since the power connection part PCA, the dam DAM and the sealing dam DAR are combined with Fig. 9 and Fig.10 Those described are substantially the same, so a detailed description thereof will be omitted.

[0237] In addition, since the area positioned on the second side of the display area DAA is different from the area positioned on the second side of the display area DAA in addition to the scan driver 610 being replaced with the emission driver 620. Fig.11 and Fig.12 Those shown in are substantially the same, so their description will be omitted.

[0238] The encapsulation layer TFE and the covering layer DCL may also be positioned in a portion of the non-display area NDA positioned on the left side of the display area DAA. In the case where the organic encapsulation layer TFE2 of the encapsulation layer TFE is positioned up to the inside of the dam DAM, the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE may be positioned up to the outside of the dam DAM to form an inorganic bonding area. The covering layer DCL may be positioned up to the outside of the inorganic encapsulation layers TFE1 and TFE3 of the encapsulation layer TFE. The covering layer DCL may be positioned beyond the display area DAA up to the non-display area NDA, so that the display area DAA may be completely covered. In one or more embodiments, the covering layer DCL may also be partially positioned in the non-display area NDA located on the right side of the display area DAA.

[0239] Fig.13 is a schematic cross-sectional view of a display panel along a second direction according to one or more embodiments.

[0240] Reference Fig.13 , the display device 10 may include a sealing dam DAR and a cover layer DCL positioned on the base substrate BS of the display panel 100. The light emitting element layer EML, the encapsulation layer TFE, the color filter layer CFL, and the lens array layer LNS may be positioned on the base substrate BS of the display panel 100. The base substrate BS may include the above reference Figure 8 Since the descriptions thereof are the same as those described above, the detailed descriptions thereof will be omitted.

[0241] The sealing dam DAR may be positioned in the non-display area NDA to surround components of the display panel 100 other than the pads PD. The sealing dam DAR may form a region in which a cover layer DCL for protecting components positioned in the display panel 100 is positioned. The sealing dam DAR may have a height higher than that of the lens array layer LNS from the base substrate BS. In addition, the sealing dam DAR may be formed to be partially spaced apart from the encapsulation layer TFE so that the cover layer DCL can also surround the side surface of the encapsulation layer TFE. The encapsulation layer TFE may form an inorganic bonding region at the periphery of the dam DAM, and the sealing dam DAR may be formed in a region spaced apart from the inorganic bonding region. In one or more embodiments, the sealing dam DAR may include a polymer resin.

[0242] The cover layer DCL may be positioned in the area surrounded by the sealing dam DAR to flatten the top surface of the display panel 100. The height of the cover layer DCL may be the same as the height of the sealing dam DAR, and the top surface of the cover layer DCL may be substantially on the same horizontal plane as the top surface of the sealing dam DAR. The cover layer DCL may cover at least the components positioned in the display area DAA, and may also be positioned in a portion of the non-display area NDA to surround the components. The bottom surface of the cover layer DCL may be in contact with the lens array layer LNS, the encapsulation layer TFE, and the base substrate BS, and the side surface thereof may be in contact with the sealing dam DAR. The cover layer DCL may be used to protect the components positioned in the display panel 100, and at the same time, flatten the top surface of the display panel 100 while filling the step portion formed by the components positioned on the base substrate BS. In one or more embodiments, the cover layer DCL may include a polymer resin of a transparent material.

[0243] In the display device 10, since the display panel 100 includes the sealing dam DAR and the cover layer DCL made of a polymer resin, an additional hard cover member may be omitted. As will be described later, a manufacturing process of the display device 10 may include forming a wafer substrate WF (see Fig.14 ) and the wafer substrate is divided to form the display device 10. Since the display panel 100 of the display device 10 does not include an additional covering member, damage to the covering member during the dividing process or damage to the display panel 100 caused thereby can be reduced or prevented. In addition, since the process of forming the cover layer DCL including the polymer resin involves a process of smoothing the top surface without involving a cutting or etching process that causes damage to the display panel 100, the surface quality of the display panel 100 can also be improved.

[0244] Hereinafter, a manufacturing process of the display device 10 will be described with reference to other drawings.

[0245] Figures 14 to 24 are diagrams sequentially illustrating a manufacturing process of a display device according to one or more embodiments.

[0246] The method for manufacturing the display device 10 according to one or more embodiments may include an operation of forming a light emitting element layer EML, an encapsulation layer TFE, a color filter layer CFL, and a lens array layer LNS for each unit area of ​​the wafer substrate WF and forming a sealing dam DAR around them, an operation of forming a resin layer in an area surrounded by the sealing dam DAR and flattening the top surface of the resin layer, and an operation of forming a cover layer DCL by curing the resin layer. In the operation of forming the resin layer, the resin layer may be formed to diffuse in the space formed by the sealing dam DAR, thereby filling the space formed by the sealing dam DAR. Subsequently, the top surface of the resin layer may be flattened and cured to form a cover layer DCL having a smooth top surface.

[0247] First, refer to Fig.14 and Fig.15 , a wafer substrate WF is prepared, and a preliminary display panel PAL is formed by forming a backplane SBP and EBP, a light emitting element layer EML, a packaging layer TFE, a color filter layer CFL, a lens array layer LNS, a pad PD, etc. on the wafer substrate WF. The wafer substrate WF may be a silicon substrate, a germanium substrate, or a silicon germanium substrate. The wafer substrate WF may be a substrate doped with a first type of impurities, and may be a mother substrate of the semiconductor substrate SSUB of the display panel 100.

[0248] A plurality of transistors (e.g., pixel transistors PTR) are formed on one surface of a wafer substrate WF, and then backplanes SBP and EBP, light emitting element layers EML, encapsulation layers TFE, color filter layers CFL, lens array layers LNS, etc. are formed to form a preliminary display panel PAL. The process of forming a plurality of transistors on a wafer substrate WF may be a fine semiconductor process. After the backplane SBP and EBP are formed by a fine semiconductor process, a light emitting element layer EML, an encapsulation layer TFE, a color filter layer CFL, and a lens array layer LNS are formed. The wafer substrate WF may include a plurality of unit areas, and a preliminary display panel PAL may be formed for each of the unit areas. The process of forming the light emitting element layer EML, the encapsulation layer TFE, the color filter layer CFL, and the lens array layer LNS may be implemented by a typical process. With the sealing dam DAR and the cover layer DCL formed in the process to be described later, the preliminary display panel PAL may constitute the display panel 100.

[0249] Next, refer to Fig.16 and Fig.17 , a sealing dam DAR and a cover layer DCL are formed in each of the unit areas of the wafer substrate WF. The process of forming the sealing dam DAR and the cover layer DCL may be a process of encapsulating the preliminary display panel PAL positioned on the wafer substrate WF. As described above, the cover layer DCL is formed to have a flat top surface while protecting the wafer substrate WF or the base substrate BS (see Fig.13) on the preliminary display panel PAL, thereby forming the top surface of the display panel 100. As one of the processes of forming the cover layer DCL, a process of forming a sealing dam DAR on the preliminary display panel PAL, applying a resin forming the cover layer DCL to a space formed by the sealing dam DAR, and then flattening and curing the resin may be performed. The cover layer DCL for each region in which the preliminary display panel PAL is formed may be formed on the wafer substrate WF, and the display panel 100 may form the cover layer DCL protecting the preliminary display panel PAL without forming an additional cover member that needs to be separately divided.

[0250] Reference Fig.18 and Fig.19 , a preliminary display panel PAL is formed on a wafer substrate WF (or a base substrate BS), and a sealing dam DAR is formed to surround the preliminary display panel PAL. The pad PD may be formed to be spaced apart from the preliminary display panel PAL on the wafer substrate WF. The preliminary display panel PAL formed on the wafer substrate WF may include a light emitting element layer EML, an encapsulation layer TFE, a color filter layer CFL, and a lens array layer LNS. However, the present disclosure is not limited thereto, and the preliminary display panel PAL may include all components of the display panel 100 except the base substrate BS and the pad PD. The components included in the display panel 100 are those described above with reference to Figures 8 to 12 components described herein and may be understood to be for simplicity of description Fig.18 Briefly shown in .

[0251] The sealing dam DAR may be formed on the wafer substrate WF in each unit area in which the preliminary display panel PAL and the pad PD are formed. The sealing dam DAR may be positioned to surround a portion of the unit area in which the preliminary display panel PAL is positioned except for the pad PD. In one or more embodiments, the sealing dam DAR may be formed of a polymer resin and may be formed to have a height (e.g., a predetermined height) from the wafer substrate WF. The height of the sealing dam DAR may be higher than the height of the preliminary display panel PAL.

[0252] Then, refer to Fig. 20, a resin layer DCR for forming a cover layer DCL is applied to the area surrounded by the sealing dam DAR on the preliminary display panel PAL. The resin layer DCR may include a polymer resin to cover the preliminary display panel PAL and fill the space between the preliminary display panel PAL and the sealing dam DAR. Since the resin layer DCR is a material with fluidity before curing, due to the difference in the material relative to the sealing dam DAR, the resin layer DCR may be applied to protrude higher than the top surface of the sealing dam DAR. However, the present disclosure is not limited thereto. The resin layer DCR may be recessed at the portion in contact with the sealing dam DAR. However, the overall shape or thickness of the cover layer DCL may be controlled by adjusting the amount of application of the resin layer DCR. The planar area of ​​the cover layer DCL may be equal to the planar area of ​​the area surrounded by the sealing dam DAR, and the thickness of the cover layer DCL may be substantially the same as the height of the sealing dam DAR. The amount of application of the resin layer DCR may be adjusted according to the area and the height of the sealing dam DAR, and may be adjusted to an amount sufficient to fill the space between the preliminary display panel PAL and the sealing dam DAR.

[0253] Then, refer to Fig.21 , the top surface of the resin layer DCR can be planarized by attaching a stripping film RFL to the resin layer DCR and the sealing dam DAR. Since the resin layer DCR includes a material with fluidity, it is easy to fill the space formed by the sealing dam DAR. However, when the resin layer DCR is cured as it is, the top surface of the display panel 100 may be uneven. In view of this, the resin layer DCR can be planarized by attaching a stripping film RFL to the resin layer DCR and the sealing dam DAR. The present process can be performed by bonding in a vacuum chamber so that the resin layer DCR can be planarized while filling the space formed by the sealing dam DAR, the stripping film RFL and the wafer substrate WF.

[0254] In some embodiments, one surface of the peeling film RFL in contact with the resin layer DCR may be surface treated or coated. The peeling film RFL may have a surface property that guides the resin layer DCR to diffuse well in the process of planarizing the resin layer DCR so that the resin layer DCR can fully fill the area surrounded by the sealing dam DAR. According to the physical properties of the resin layer DCR, the surface of the peeling film RFL may be treated to be hydrophilic or hydrophobic.

[0255] Then, refer to Fig. 22 and Fig.23, by irradiating ultraviolet light UV to the resin layer DCR or heat-treating the resin layer DCR, the resin layer DCR is cured to form a cover layer DCL, and the stripping film RFL is removed. The stripping film RFL can be completely removed so that the cover layer DCL and the sealing dam DAR can remain on the display panel 100. Since the resin layer DCR is cured in a state with the stripping film RFL attached, it is cured in a state where the space formed by the sealing dam DAR is completely filled, and its top surface can be flattened. In addition, since the space formed by the sealing dam DAR can be completely filled by adjusting the amount of application of the resin layer DCR, the portion where the cover layer DCL and the sealing dam DAR contact each other and the space between the preliminary display panel PAL and the sealing dam DAR can all be filled with the cover layer DCL. In the display panel 100, the cover layer DCL positioned at its uppermost layer may have a smooth top surface, and there may be no space between the sealing dam DAR and the cover layer DCL.

[0256] Then, refer to Fig.24 , the wafer substrate WF is divided to form the display panel 100, and the circuit board 300 (see Figure 1 ) is attached to the display panel 100 to manufacture the display device 10. The wafer substrate WF may be divided for each unit area in which one preliminary display panel PAL and the cover layer DCL are formed. The manufacturing process of the display device 10 may be performed to manufacture several display panels 100 on a single wafer substrate WF. Therefore, the manufacturing yield of the display device 10 may be excellent.

[0257] Furthermore, since the cover layer DCL is formed to correspond to each of the preliminary display panels PAL in the process of dividing the wafer substrate WF, there is no process of dividing an additional cover member covering the preliminary display panels PAL, which has an advantage that there is no risk of breakage and damage to the display panel 100.

[0258] In the method of manufacturing the display device 10 according to one or more embodiments, the cover layer DCL to be positioned at the uppermost layer of the display panel 100 may be formed using a polymer resin so as to have a smooth top surface while protecting components included in the display panel 100. Therefore, the display panel 100 may have very excellent surface quality, and when light emitted from the light emitting element layer EML is output in an upward direction from the display panel 100, deterioration of display quality due to scattering or refraction of light on the surface of the cover layer DCL can be reduced or prevented.

[0259] Hereinafter, various embodiments of the display device 10 will be described with reference to other drawings.

[0260] Fig.25is a schematic cross-sectional view of a display panel of a display device along a second direction according to one or more other embodiments.

[0261] Reference Fig.25 In the display device 10_1 according to one or more embodiments, the sealing dam DAR positioned in the display panel 100 may be omitted. In the display device 10_1, the cover layer DCL positioned on the lens array layer LNS of the display panel 100 is formed to completely surround the light emitting element layer EML, the encapsulation layer TFE, the color filter layer CFL, and the lens array layer LNS, and may have smooth top and side surfaces.

[0262] exist Fig.13 In the display panel 100 of FIG. 1 , the sealing dam DAR is a member for forming a space in which the cover layer DCL is to be positioned, and if the shape of the cover layer DCL can be controlled and the top surface thereof can be planarized in a process of forming the cover layer DCL, the sealing dam DAR may be omitted. Figures 18 to 23 In the manufacturing process of the cover layer DCL, the shape of the cover layer DCL is controlled and the top surface thereof is flattened by using the sealing dam DAR and the release film RFL. However, the manufacturing method of the display device 10_1 is not necessarily limited thereto. The display device 10_1 can be manufactured by a manufacturing process that enables the cover layer DCL to have a flat top surface even when the sealing dam DAR is omitted.

[0263] Figure 26 to Figure 31 is a cross-sectional view showing a portion of a manufacturing process of a display device according to one or more other embodiments.

[0264] Reference Figure 26 to Figure 31 In the manufacturing process of the display device 10_1 according to one or more embodiments, the resin layer DCR may be formed to have a controlled shape and flat top and side surfaces by using a mold MLD. Fig.26 and Fig. 27 As shown in , after forming a plurality of preliminary display panels PAL on a wafer substrate WF, a resin layer DCR is applied on the plurality of preliminary display panels PAL. The resin layer DCR is applied to correspond to each of the preliminary display panels PAL. Since there is no sealing dam DAR, it may overflow from the preliminary display panel PAL over time.

[0265] Then, if Fig.28 and Fig.29As shown in , a mold MLD whose bottom surface is partially recessed to correspond to each unit area on the wafer substrate WF in which the preliminary display panel PAL is positioned is provided, and the mold MLD is brought into contact with the wafer substrate WF so that the recessed portion of the mold MLD surrounds the resin layer DCR and the preliminary display panel PAL. The mold MLD may play a role similar to that of the sealing dam DAR. When the mold MLD and the wafer substrate WF are in contact with each other, the resin layer DCR may completely surround the preliminary display panel PAL and completely fill the recessed portion of the mold MLD. The resin layer DCR may fill the space formed by the mold MLD and the wafer substrate WF. Fig. 27 In the process, the application amount of the resin layer DCR can be adjusted in consideration of the volume of the recessed portion of the mold MLD and the shape and thickness of the cover layer DCL, and for example, can be adjusted to an amount sufficient to completely fill the recessed portion of the mold MLD when the mold MLD and the wafer substrate WF are in contact with each other.

[0266] In one or more embodiments, the recessed portion of the mold MLD may have a depth greater than the thickness of the preliminary display panel PAL, and may have an area greater than the area of ​​the preliminary display panel PAL in a plan view. The resin layer DCR filling the recessed portion of the mold MLD may naturally completely surround the top and side surfaces of the preliminary display panel PAL. The resin layer DCR may be formed to completely protect the preliminary display panel PAL as its top and side surfaces are flattened by the mold MLD.

[0267] Then, if Fig.30 and Fig.31 As shown in , by irradiating ultraviolet light UV to the resin layer DCR or heat-treating the resin layer DCR, the resin layer DCR is cured to form a cover layer DCL, and the mold MLD is removed. The mold MLD may be made of a transparent material so that it can transmit ultraviolet light UV. As an example, the mold MLD may be formed of transparent glass. A plurality of preliminary display panels PAL and a cover layer DCL positioned to correspond to each of the preliminary display panels PAL may remain on the wafer substrate WF. Even in the absence of a sealing dam DAR, the cover layer DCL may be given a smooth top surface and side surfaces, and the cover layer DCL may be formed to completely surround each of the preliminary display panels PAL.

[0268] In one or more embodiments, the display panel 100 may be formed by dividing the wafer substrate WF into a plurality of pieces, and the circuit board 300 (see Figure 1) is attached to the display panel 100 to manufacture the display device 10_1. In the display device 10_1 according to one or more embodiments, even if the sealing dam DAR is not positioned on the display panel 100, the cover layer DCL having smooth top and side surfaces can still be formed by a planarization process of the resin layer DCR using the mold MLD during the manufacturing process.

[0269] Figure 32 to Figure 36 is a cross-sectional view showing a portion of a manufacturing process of a display device according to still another embodiment or embodiments.

[0270] Reference Figure 32 to Figure 36 In the method of manufacturing the display device 10, a planarization process of the resin layer DCR may be performed by using a hard mask HM and a soft mold SMD. Fig.32 and Fig.33 As shown in , after forming a plurality of preliminary display panels PAL on a wafer substrate WF, a hard mask HM including holes respectively exposing the preliminary display panels PAL is placed on the wafer substrate WF. The hard mask HM may be directly positioned on the wafer substrate WF, but is not limited thereto. The hard mask HM may be placed on the wafer substrate WF using a fixture. However, the bottom surface of the hard mask HM may be in contact with the top surface of the wafer substrate WF so that the resin layer DCR applied on the preliminary display panel PAL does not flow.

[0271] In one or more embodiments, the hard mask HM may be made of a metal material. The hard mask HM may have a hard material for controlling the shape of the resin layer DCR applied on the preliminary display panel PAL.

[0272] Then, if Fig.33 and Fig.34 As shown in , a soft mold SMD having protrusions formed to correspond to the holes of the hard mask HM, respectively, is placed on the hard mask HM. The soft mold SMD may be positioned to be in direct contact with the hard mask HM, and the holes of the hard mask HM and the protrusions of the soft mold SMD may correspond to the unit area in which the prepared display panel PAL is positioned. The holes of the hard mask HM and the protrusions of the soft mold SMD may guide the resin layer DCR to completely fill the space between the hard mask HM, the soft mold SMD and the wafer substrate WF while completely surrounding the prepared display panel PAL. In one or more embodiments, the soft mold SMD may be made of a transparent flexible material. As an example, the soft mold SMD may be formed of a silicone elastomer such as PDMS. The hard mask HM may be made of a hard material, the soft mold SMD may be made of a flexible material, and the resin layer DCR may completely fill the space formed by the hard mask HM, the soft mold SMD and the wafer substrate WF.

[0273] In addition, the shape of the cover layer DCL can be controlled by adjusting the plane area, height, and thickness of the holes of the hard mask HM and the protrusions of the soft mold SMD. Fig.32 In the embodiment, the application amount of the resin layer DCR may be adjusted in consideration of the hole of the hard mask HM, the protrusion of the soft mold SMD, the volume of the space formed by the wafer substrate WF, the shape and thickness of the cover layer DCL, etc. For example, the application amount of the resin layer DCR may be adjusted to an amount sufficient to completely fill the space formed by the hard mask HM and the soft mold SMD when they are in contact with each other.

[0274] In one or more embodiments, the thickness of the hard mask HM may be greater than the thickness of the preliminary display panel PAL, and the thickness of the protrusion of the soft mold SMD may be less than the thickness of the hard mask HM. The resin layer DCR filling the space between the hard mask HM and the soft mold SMD may have a sufficient thickness while completely surrounding the preliminary display panel PAL. In addition, the resin layer DCR may have a smooth top surface and side surfaces that are in contact with the soft mold SMD and the hard mask HM, respectively.

[0275] Then, if Fig.35 and Fig.36 As shown in , by irradiating ultraviolet light UV to the resin layer DCR or heat-treating the resin layer DCR, the resin layer DCR is cured to form a cover layer DCL, and the soft mold SMD and the hard mask HM are removed. A plurality of prepared display panels PAL and a cover layer DCL positioned to correspond to each of them may remain on the wafer substrate WF. Even in the absence of a sealing dam DAR, the cover layer DCL may be given a smooth top surface and side surfaces, and the cover layer DCL may be formed to completely surround each of the prepared display panels PAL. Subsequently, in one or more embodiments, the display panel 100 may be formed by dividing the wafer substrate WF into a plurality of pieces, and the circuit board 300 (see Figure 1 ) is attached to the display panel 100 to manufacture the display device 10.

[0276] Fig.37 is a cross-sectional view illustrating one operation in a process of manufacturing a display device according to still one or more other embodiments.

[0277] Reference Fig.37 In the method of manufacturing the display device 10, a planarization process of the resin layer DCR may be performed by using a soft mask SM and a hard mold HMD. Fig.37 One or more corresponding embodiments and Fig.34 The corresponding one or more embodiments may differ in that the materials of the soft mask SM and the hard mold HMD are opposite. Since the other descriptions are the same as those described above, the detailed description thereof will be omitted here.

[0278] Figures 38 to 41 is a cross-sectional view showing a portion of a manufacturing process of a display device according to still another embodiment or embodiments.

[0279] Reference Figures 38 to 41 In the method of manufacturing the display device 10, the planarization process of the resin layer DCR may be performed by using the soft mask SM and the release film RFL. Figure 26 to Figure 31 One or more embodiments are different in that the height of the soft mask SM is set equal to the height or thickness of the cover layer DCL, and a release film RFL having no protruding or recessed portions is used as a top surface planarizing member for the cover layer DCL.

[0280] like Fig.38 As shown in , a soft mask SM including holes formed to correspond to unit areas in which the preliminary display panels PAL are positioned is placed on the wafer substrate WF. The soft mask SM may include a flexible silicon material such as PDMS. In one or more embodiments, the plane area and thickness of the holes of the soft mask SM may be the same as the plane area and thickness of the cover layer DCL. In the manufacturing process, the shape of the cover layer DCL can be controlled by adjusting the thickness of the soft mask SM and the area of ​​the holes.

[0281] Then, if Fig.39 and Fig.40 As shown in , a resin layer DCR is applied to the preliminary display panel PAL, and a stripping film RFL is positioned on the soft mask SM to flatten the top surface of the resin layer DCR. The resin layer DCR may completely surround the preliminary display panel PAL while filling the space formed by the soft mask SM, the stripping film RFL, and the wafer substrate WF. In addition, the top surface and the side surface of the resin layer DCR may be flattened as they contact the soft mask SM and the stripping film RFL. The stripping film RFL may be formed to have a flat bottom surface, and the thickness of the soft mask SM and the thickness of the resin layer DCR may be controlled to be the same.

[0282] Then, if Fig.41 As shown in , by irradiating ultraviolet light UV to the resin layer DCR or heat-treating the resin layer DCR, the resin layer DCR is cured to form a cover layer DCL. The stripping film RFL may be made of a transparent material so that it can transmit ultraviolet light UV. As an example, the stripping film RFL may be formed of transparent glass. Subsequently, when the soft mask SM and the stripping film RFL are removed, a plurality of preliminary display panels PAL and a cover layer DCL positioned corresponding to each of them may remain on the wafer substrate WF. Even in the absence of a sealing dam DAR, the cover layer DCL may be given a smooth top surface and side surfaces, and the cover layer DCL may be formed to completely surround each of the preliminary display panels PAL.

[0283] Fig.42 is a perspective view showing a head mounted display device according to one or more embodiments. Fig.43 It is shown Fig.42 An exploded perspective view of an example of a head-mounted display device.

[0284] Reference Fig.42 and Fig.43 According to one or more embodiments, the head-mounted display device 1000 includes a first display device 10_1, a second display device 10_2, a display device storage portion 1100, a storage portion cover 1200, a first eyepiece 1210, a second eyepiece 1220, a head-mounted strap 1300, an intermediate frame 1400, a first optical member 1510, a second optical member 1520, a control circuit board 1600 and a connector.

[0285] The first display device 10_1 provides an image to the left eye of the user, and the second display device 10_2 provides an image to the right eye of the user. Figure 1 The display devices 10 described are substantially the same, and thus descriptions of the first display device 10_1 and the second display device 10_2 will be omitted.

[0286] The first optical member 1510 may be positioned between the first display device 10_1 and the first eyepiece 1210. The second optical member 1520 may be positioned between the second display device 10_2 and the second eyepiece 1220. Each of the first optical member 1510 and the second optical member 1520 may include at least one convex lens.

[0287] The middle frame 1400 may be positioned between the first display device 10_1 and the control circuit board 1600 and between the second display device 10_2 and the control circuit board 1600. The middle frame 1400 is used to support and fix the first display device 10_1, the second display device 10_2, and the control circuit board 1600.

[0288] The control circuit board 1600 may be positioned between the middle frame 1400 and the display device receiving portion 1100. The control circuit board 1600 may be connected to the first display device 10_1 and the second display device 10_2 through a connector. The control circuit board 1600 may convert an image source input from the outside into digital video data DATA (see Figure 2 ), and the digital video data DATA may be transmitted to the first display device 10_1 and the second display device 10_2 through the connector.

[0289] The control circuit board 1600 may transmit digital video data DATA corresponding to a left-eye image optimized for the user's left eye to the first display device 10_1, and may transmit digital video data DATA corresponding to a right-eye image optimized for the user's right eye to the second display device 10_2. Alternatively, the control circuit board 1600 may transmit the same digital video data DATA to the first display device 10_1 and the second display device 10_2.

[0290] The display device storage portion 1100 is used to accommodate the first display device 10_1, the second display device 10_2, the middle frame 1400, the first optical member 1510, the second optical member 1520, the control circuit board 1600, and the connector. The storage portion cover 1200 is positioned to cover one opening surface of the display device storage portion 1100. The storage portion cover 1200 may include a first eyepiece 1210 at which the user's left eye is positioned and a second eyepiece 1220 at which the user's right eye is positioned. Fig.42 and Fig.43 It is shown that the first eyepiece 1210 and the second eyepiece 1220 are separately positioned, but the present disclosure is not limited thereto. The first eyepiece 1210 and the second eyepiece 1220 may be combined into one eyepiece.

[0291] The first eyepiece 1210 may be aligned with the first display device 10_1 and the first optical member 1510, and the second eyepiece 1220 may be aligned with the second display device 10_2 and the second optical member 1520. Therefore, the user may observe the image of the first display device 10_1 magnified into a virtual image by the first optical member 1510 through the first eyepiece 1210, and may observe the image of the second display device 10_2 magnified into a virtual image by the second optical member 1520 through the second eyepiece 1220.

[0292] The headband 1300 is used to fix the display device storage part 1100 to the user's head so that the first eyepiece 1210 and the second eyepiece 1220 of the storage part cover 1200 remain positioned on the user's left eye and right eye, respectively. When the display device storage part 1100 is implemented to be lightweight and compact, as Fig.42 As shown in , the head mounted display device 1000 may be provided with a glasses frame instead of a head mounted band 1300 .

[0293] In addition, the head mounted display device 1000 may further include a battery for supplying power, an external memory slot for accommodating an external memory, and an external connection port and a wireless communication module for receiving an image source. The external connection port may be a universal serial bus (USB) terminal, a display port, or a high-definition multimedia interface (HDMI) terminal, and the wireless communication module may be a 5G communication module, a 4G communication module, a Wi-Fi module, or a Bluetooth module.

[0294] Fig.44 is a perspective view showing a head mounted display device according to one or more embodiments.

[0295] Reference Fig.44 The head mounted display device 1000_1 according to one or more embodiments may be a glasses type display device in which the display device storage portion 1200_1 is implemented in a lightweight and compact manner. The head mounted display device 1000_1 according to one or more embodiments may include a display device 10_3, a left eye lens 1010, a right eye lens 1020, a support frame 1030, temples 1040 and 1050, an optical member 1060, an optical path changing member 1070, and a display device storage portion 1200_1.

[0296] The display device storage portion 1200_1 may include a display device 10_3, an optical member 1060, and an optical path changing member 1070. An image displayed on the display device 10_3 may be magnified by the optical member 1060, and an optical path may be changed by the optical path changing member 1070 to provide the image to the right eye of the user through the right eye lens 1020. As a result, the user may observe an augmented reality image in which a virtual image displayed on the display device 10_3 and a real image viewed through the right eye lens 1020 are combined through the right eye.

[0297] Fig.44 The display device storage portion 1200_1 is shown to be positioned at the right end of the support frame 1030, but the present disclosure is not limited thereto. For example, the display device storage portion 1200_1 may be positioned at the left end of the support frame 1030, and in this case, the image of the display device 10_3 may be provided to the left eye of the user. Alternatively, the display device storage portion 1200_1 may be positioned on both the left and right ends of the support frame 1030, and in this case, the user may observe the image displayed on the display device 10_3 through both the left eye and the right eye.

[0298] At the end of the detailed description, those skilled in the art will appreciate that many changes and modifications can be made to the embodiments without departing from the aspects of the present disclosure. Therefore, the embodiments of the present disclosure disclosed are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A display device, comprising: a semiconductor substrate including a display region including transistors and a non-display region surrounding the display region in a plan view; a light emitting element layer, the light emitting element layer being located above the semiconductor substrate and including light emitting elements located in the display area; An encapsulation layer, the encapsulation layer being located above the light-emitting element layer; a color filter layer, the color filter layer being located above the encapsulation layer and comprising color filters respectively overlapping the light emitting elements; a lens array layer located above the color filter layer and including lenses located in the display area; as well as A cover layer is located above the lens array layer, has a flat top surface and side surfaces, and surrounds the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer in a plan view.

2. The display device according to claim 1, further comprising: a pad located in the non-display area, Wherein, the covering layer does not overlap with the pad.

3. The display device according to claim 1, further comprising: a sealing dam located in the non-display area and surrounding the cover layer in a plan view, The plane area of ​​the region surrounded by the sealing dam is equal to the plane area of ​​the cover layer.

4. The display device according to claim 3, wherein: The sealing dam contacts the side surface of the cover layer, and Wherein, the height of the sealing dam is equal to the height of the covering layer.

5. The display device according to claim 3, further comprising: a gate driver and a scan driver located in the non-display area, wherein the sealing dam surrounds the gate driver and the scan driver in a plan view, and Wherein, the covering layer overlaps with the gate driver and the scan driver.

6. The display device according to claim 3, wherein: The sealing dam and the cover layer include a polymer resin.

7. The display device according to claim 1, wherein: The encapsulation layer includes a first inorganic encapsulation layer, an organic encapsulation layer located above the first inorganic encapsulation layer, and a second inorganic encapsulation layer located above the organic encapsulation layer, and The cover layer overlaps an inorganic bonding region where the first inorganic encapsulation layer and the second inorganic encapsulation layer contact each other in the non-display region.

8. The display device according to claim 1, wherein: The cover layer directly contacts the lenses of the lens array layer.

9. A method for manufacturing a display device, the method comprising: preparing a wafer substrate, the wafer substrate including transistors and having unit areas defined in the wafer substrate; forming a light emitting element layer including a light emitting element in the unit area of ​​the wafer substrate; forming a packaging layer above the light emitting element layer; forming a color filter layer above the encapsulation layer; forming a lens array layer above the color filter layer; applying a resin layer on the lens array layer; planarizing the top surface of the resin layer; curing the resin layer to form a cover layer surrounding the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer in a plan view; as well as The wafer substrate is divided into the unit areas to form display panels.

10. The method according to claim 9, further comprising: forming a sealing dam surrounding the light emitting element layer for the unit area of ​​the wafer substrate, The resin layer is applied in a region surrounded by the sealing dam.

11. The method according to claim 10, wherein: The planarizing of the top surface of the resin layer includes attaching a release film having a planar bottom surface to the sealing dam and the resin layer, and The resin layer fills a space defined by the sealing dam and the release film.

12. The method according to claim 11, wherein: In the attachment of the release film, the resin layer surrounds the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer in the unit area of ​​the wafer substrate in a plan view.

13. The method according to claim 10, wherein: The cover layer includes a flat top surface and a side surface directly contacting the sealing dam.

14. The method according to claim 9, wherein: The planarization of the top surface of the resin layer includes placing a mold including a recessed portion corresponding to the unit area where the light emitting element layer is located, and The resin layer fills the space defined by the wafer substrate and the mold.

15. The method according to claim 14, wherein: The depth of the recessed portion of the mold is equal to the thickness of the covering layer.

16. The method according to claim 14, wherein: The mold includes a transparent material.

17. The method according to claim 9, further comprising: placing a mask including holes respectively corresponding to the unit areas on the wafer substrate, wherein the planarization of the top surface of the resin layer comprises placing a mold on the mask, and The resin layer fills the space defined by the wafer substrate, the mask and the mold.

18. The method according to claim 17, wherein: The resin layer surrounds the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer.

19. The method according to claim 17, wherein: The thickness of the mask is greater than the height of the lens array layer, wherein the mold has a bottom surface having protrusions respectively corresponding to the holes of the mask, and Wherein, a thickness of the protrusion of the mold is smaller than a thickness of the mask.

20. The method according to claim 17, wherein: The mask includes a metal material, and Wherein, the mold comprises a flexible material.

21. The method according to claim 17, wherein: The mask includes a flexible material, and Wherein, the mold is a transparent hard mold.

22. The method according to claim 9, further comprising: placing a soft mask having holes respectively corresponding to the unit areas on the wafer substrate, wherein the planarization of the top surface of the resin layer comprises placing a release film having a flat bottom surface on the soft mask, and The resin layer fills a space defined by the wafer substrate, the soft mask and the release film.

23. The method according to claim 22, wherein: The thickness of the soft mask is equal to the thickness of the capping layer.

24. A head mounted display device, comprising: a frame mounted on the user's body and corresponding to the left eye and the right eye; a display device, wherein the display device is located in the frame; as well as an eyepiece, the eyepiece being located above the display device, Wherein, the display device comprises: a semiconductor substrate including a display region including transistors and a non-display region surrounding the display region in a plan view; a light emitting element layer, the light emitting element layer being located above the semiconductor substrate and including light emitting elements located in the display area; An encapsulation layer, the encapsulation layer being located above the light-emitting element layer; a color filter layer, the color filter layer being located above the encapsulation layer and comprising color filters respectively overlapping the light emitting elements; a lens array layer located above the color filter layer and including lenses located in the display area; and A cover layer is located above the lens array layer, has a flat top surface and side surfaces, and surrounds the light emitting element layer, the encapsulation layer, the color filter layer, and the lens array layer in a plan view.

25. The head mounted display device according to claim 24, wherein: The display device further includes a sealing dam located in the non-display area and surrounding the cover layer in a plan view, and Wherein, the sealing dam directly contacts the side surface of the cover layer.

Images