Display aging test device and system

Abstract

The invention discloses a display aging test device and system. The display aging test device comprises an aging bottom plate, an FPGA signal plate and / or an MCU control plate installed on the aging bottom plate, a video adapter plate, a power panel and a module adapter plate. The module adapter plate is electrically connected with the power panel, the FPGA signal panel and / or the MCU control panel and the video adapter plate; the module adapter plate is connected with a display to be subjected to aging test, and the module adapter plate transmits the received signal and the power supply to the display to be subjected to aging test; the power panel is provided with a top power interface, a bottom power interface and a voltage-adjustable power supply; the top power supply interface is electrically connected with the bottom power supply interface, and the bottom power supply interface is electrically connected with the voltage adjustable power supply; the number of the power supply boards is n, the n power supply boards can generate multiple paths of power supplies through the stacked structure to supply power to the module adapter board, and n is a positive integer. The power panels are designed to be of a stacked structure, the number of the power panels can be flexibly increased or decreased according to the needs of the display to be subjected to aging test, and the cost of the device is reduced.

Description

Technical Field

[0001] The invention belongs to the technical field of aging testing, and in particular relates to a display aging testing device and system. Background Art

[0002] With the rise of electronic devices, the demand for displays is also increasing. In order to increase the production capacity of displays, improving aging capacity has become a key step. However, in existing aging test devices, displays need to be powered separately, and different displays require different power supplies. When testing multiple displays, it is necessary to configure the corresponding power supply according to different models, which leads to redundant power supply in existing aging test devices and increases the cost of the device. In addition, the data transmission protocol standards used by displays are numerous, and sometimes even non-standard protocols, which forces the aging test device to rewrite the program frequently, increasing the time cost and affecting the product launch progress.

[0003] Although existing devices can test multiple displays at a time, the number of simultaneous tests is limited. Facing the demand for aging tests on large quantities of displays, a large number of test devices are still required, which not only increases the control difficulty, but also pushes up the aging and maintenance costs. Summary of the invention

[0004] Based on this, an embodiment of the present invention provides a display aging test device and system, aiming to solve the problems in the prior art of complex power supply configuration of the aging test device and difficulty in controlling a large number of aging test devices.

[0005] A first aspect of an embodiment of the present invention provides a display aging test device, comprising: Aging baseboard, FPGA signal board and / or MCU control board, video adapter board, power board and module adapter board installed on the aging baseboard; The module adapter board is electrically connected to the power board, the FPGA signal board and / or the MCU control board, and the video adapter board; the module adapter board is connected to the display to be tested for aging, and the module adapter board transmits the received signal and power to the display to be tested for aging; The power board is equipped with a top power interface, a bottom power interface and at least one voltage-adjustable power supply; The top power interface is a male or female socket, and the bottom power interface is a female or male socket that is buckled with the top power interface; both the top power interface and the bottom power interface have z power supply pins, where z is a positive integer; The number of the voltage-adjustable power supplies is m, and the m voltage-adjustable power supplies are electrically connected to the bottom power interface to form a power supply pin group including m power supply pins, and zm unused power supply pins of the bottom power interface are left, where m is a positive integer and m≤z; The power supply pins of zm unused bottom power interfaces are electrically connected to the zm power supply pins of the top power interface of the same power board; The number of power boards is n, and the n power boards can form an electrically connected stacked structure by buckling to generate multiple power supplies to provide power to the module adapter board. n is a positive integer and n≤z / m.

[0006] Optionally, in a stacked structure in which n power boards are electrically connected, the power supply pin group of each non-bottom-layer power board can be electrically connected to the top power interface of the power board below through snap-fitting, thereby achieving electrical connection with the bottom power interface of the power board below, and finally achieving electrical connection with the bottom power interface of the bottom-layer power board.

[0007] Optionally, the FPGA signal board is configured with a high-speed interface, and the FPGA signal board communicates with an external host computer through the high-speed interface to receive video signals and control signals; the aging baseboard is configured with an aging power supply interface, and the aging baseboard is electrically connected to an external power supply through the aging power supply interface.

[0008] Optionally, the display aging test device includes an FPGA signal board and an MCU control board. The FPGA signal board transmits the received control signal to the MCU control board, and the MCU control board converts the received control signal into a module control signal and transmits it to a module adapter board; the FPGA signal board converts the received video signal into a module video protocol signal and transmits it to a video adapter board, and the video adapter board then transmits the module video protocol signal to the module adapter board.

[0009] Optionally, the video adapter board is also configured with a switch chip and / or a bridge chip, which converts the module video protocol signal into a video protocol signal that can be received by the module adapter board and then transmits it to the module adapter board.

[0010] Optionally, the aging base plate is configured with the same top power interface as the power board, and the video adapter board is configured with the same bottom power interface as the power board.

[0011] A second aspect of an embodiment of the present invention provides a display aging test system, comprising the above-mentioned display aging test device.

[0012] Optionally, a plurality of display aging test devices are connected via high-speed cables and power cables to form a display aging test system with a chain structure.

[0013] Optionally, the FPGA signal board is configured with at least two high-speed interfaces, and each FPGA signal board is connected to the FPGA signal board of another display aging test device in the system through at least one high-speed interface to transmit video signals and control signals; one of the FPGA signal boards communicates with an external host computer through the high-speed interface to receive video signals and control signals.

[0014] Optionally, the aging baseboard is configured with at least two aging power interfaces, each aging baseboard is electrically connected to the aging baseboard of another display aging test device in the system through at least one aging power interface; at least one aging baseboard is electrically connected to an external power supply through the aging power interface.

[0015] The beneficial effects of the present invention are: 1. The power board is designed as a stacked structure, which can provide flexible and variable power supply quantity through stacking to adapt to the power supply requirements of different displays; and through the electrical connection method of the top power interface and the bottom power interface of the power board, it is not necessary to modify or redesign the power board during stacking, and the power supply quantity can be increased and decreased quickly, reused, and at low cost.

[0016] 2. In the aging test device, the MCU control board is used to convert and transmit control signals, and the FPGA signal board is used to convert and transmit video signals. The MCU control board can be used alone to control the display to be tested for aging to enter the built-in test mode for aging, which can speed up the aging process and improve production efficiency.

[0017] 3. At least two high-speed interfaces are configured in the FPGA signal board. The FPGA signal board of each aging test device in the system can be cascaded together through the high-speed interface. Only the control signal and video signal of one of the FPGA signal boards needs to be transmitted to realize the transmission of the control signal and video signal of all FPGA signal boards, thus simplifying the entire control process.

[0018] 4. At least two aging power supply interfaces are configured on the aging baseboard. The aging baseboards of each aging test device in the system can be cascaded together through the aging power supply interfaces. An external power supply can be connected to the aging power supply interface of one of the aging baseboards to realize the function of powering all aging baseboards, thereby reducing the use of external power supplies and reducing system costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The drawings described herein are used to provide further understanding of the present invention and constitute a part of the present invention. The exemplary embodiments of the present invention and their descriptions are used to explain the present invention and do not constitute improper limitations on the present invention.

[0020] Figure 1It is a schematic diagram of the three-dimensional structure of the display aging test device in Example 1 of the present invention from a first viewing angle.

[0021] Figure 2 It is a schematic diagram of the stereoscopic structure of the display aging test device in Embodiment 1 of the present invention from a second viewing angle.

[0022] Figure 3 It is an overall structural block diagram of the aging test device in Example 1 of the present invention.

[0023] Figure 4 It is a schematic diagram of the aged base plate structure in Example 1 of the present invention.

[0024] Figure 5 It is a structural schematic diagram of the FPGA signal board in Example 1 of the present invention.

[0025] Figure 6 It is a structural schematic diagram of the video adapter board in Example 1 of the present invention.

[0026] Figure 7 It is a schematic diagram of the structure of the power board in Example 1 of the present invention.

[0027] Figure 8 It is a schematic diagram of the three-dimensional structure of the distribution of the top power interface and the bottom power interface of the power board in Example 1 of the present invention.

[0028] Fig. 9 It is a schematic diagram of a stacked three-dimensional structure of a power board - a power board - a video adapter board - an FPGA signal board in Example 1 of the present invention.

[0029] Fig.10 It is a schematic diagram of the pin definition of the top power interface and the bottom power interface of the power board in Example 1 of the present invention.

[0030] Fig.11 It is a schematic diagram of the electrical connection between the power supply pins of the top power interface and the bottom power interface of the power board in Example 1 of the present invention.

[0031] Fig.12 It is a schematic diagram of the pin distribution of the top power interface and the bottom power interface of the power board in Example 1 of the present invention.

[0032] Fig.13 It is a schematic diagram of the structure of the MCU control board in Example 1 of the present invention.

[0033] Fig.14 It is a schematic diagram of the structure of the module adapter board in Example 1 of the present invention.

[0034] Fig.15 It is a schematic diagram of the overall structure of the aging test system in Example 2 of the present invention.

[0035] Fig.16 It is a connection diagram of multiple FPGA signal boards in Example 2 of the present invention.

[0036] Fig.17 It is a schematic diagram of the topological structure of multiple aged baseboards connected in Example 2 of the present invention. DETAILED DESCRIPTION

[0037] In order to more clearly illustrate the overall concept of the present invention, a detailed description is given below in an exemplary manner in conjunction with the accompanying drawings.

[0038] In the description of the present invention, it is necessary to understand that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "axial", "radial", "circumferential" and the like indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the referred device or element must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0039] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0040] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or a communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0041] In the present invention, unless otherwise clearly specified and limited, the first feature "on" or "under" the second feature may be that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. In the description of this specification, the description with reference to the terms "one scheme", "some schemes", "examples", "specific examples", or "some examples" means that the specific features, structures, materials or characteristics described in conjunction with the scheme or example are included in at least one scheme or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same scheme or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more schemes or examples in a suitable manner.

[0042] like Figure 1 to Figure 14 As shown, a first aspect of an embodiment of the present invention provides a display aging test device, comprising: Aging baseboard, FPGA signal board and / or MCU control board, video adapter board, power board and module adapter board installed on the aging baseboard; The module adapter board is electrically connected to the power board, the FPGA signal board and / or the MCU control board, and the video adapter board; the module adapter board is connected to the display to be tested for aging, and the module adapter board transmits the received signal and power to the display to be tested for aging; The power board is equipped with a top power interface, a bottom power interface and at least one voltage-adjustable power supply; The top power interface is a male or female socket, and the bottom power interface is a female or male socket that is buckled with the top power interface; both the top power interface and the bottom power interface have z power supply pins, where z is a positive integer; The number of the voltage-adjustable power supplies is m, and the m voltage-adjustable power supplies are electrically connected to the bottom power interface to form a power supply pin group including m power supply pins, and zm unused power supply pins of the bottom power interface are left, where m is a positive integer and m≤z; The power supply pins of zm unused bottom power interfaces are electrically connected to the zm power supply pins of the top power interface of the same power board; The number of power boards is n, and the n power boards can form an electrically connected stacked structure by buckling to generate multiple power supplies to provide power to the module adapter board. n is a positive integer and n≤z / m.

[0043] It should be noted that the power board can generate multiple power supplies to the module adapter board through a stacked structure, and the number of power boards can be flexibly increased or decreased according to the needs of the display to be tested for aging, and the electrical connection between the top power interface and the bottom power interface of the power board makes it possible to quickly, reusably, and cost-effectively increase or decrease the number of power supplies without modifying or redesigning the power board during stacking. The stacked structure that forms an electrical connection through a buckling method can not only flexibly configure the power supply, but also save the lateral space required by the power board.

[0044] In some embodiments of the present invention, in a stacked structure in which n power boards are electrically connected, the power supply pin group of each non-bottom-layer power board can be electrically connected to the top power interface of the power board below by buckling, and then to the bottom power interface of the power board below, and finally to the bottom power interface of the power board at the bottom layer. Specifically, except for the bottom layer, the power supply pin group of each power board can be electrically connected by buckling with the top power interface of the power board below. Since the top of the power board below is electrically connected to the bottom power interface, the electrical signal of the power supply pin group can be mapped to the power supply pin of the bottom power interface. By analogy, the signal mapped to the bottom power supply pin of the power board below can be transmitted to the top power interface of the power board at the bottom layer by buckling, and then mapped to the power supply pin of its bottom power interface through the internal connection of the power board at this layer. In this way, the transmission is carried out layer by layer until the electrical signal of the power supply pin group is mapped to the power supply pin of the bottom power interface of the power board at the bottom layer.

[0045] In some embodiments of the present invention, the power pins of the top power interface and the power pins of the bottom power interface are symmetrically distributed in the power board with the center of the power board as the origin. In this way, there is no need to determine the connection direction when stacking, simplifying the installation process.

[0046] In some embodiments of the present invention, the power board is also configured with multiple protection circuits, the voltage-adjustable power supply is electrically connected to the protection circuit, and the protection circuit is electrically connected to the bottom power interface to protect the voltage-adjustable power supply and improve the stability of the power board.

[0047] In some embodiments of the present invention, the FPGA signal board is configured with a high-speed interface, and the FPGA signal board communicates with an external host computer through the high-speed interface to receive video signals and control signals; the aging baseboard is configured with an aging power interface, and the aging baseboard is electrically connected to the external power supply through the aging power interface.

[0048] In some embodiments of the present invention, the display aging test device includes an FPGA signal board and an MCU control board. The FPGA signal board transmits the received control signal to the MCU control board, and the MCU control board converts the received control signal into a module control signal and transmits it to the module adapter board; the FPGA signal board converts the received video signal into a module video protocol signal and transmits it to the video adapter board, and the video adapter board then transmits the module video protocol signal to the module adapter board.

[0049] It should be noted that in the aging test device, the control signal is converted and transmitted by the MCU control board, and the video signal is converted and transmitted by the FPGA signal board. The program modification complexity of the FPGA is generally higher than that of the MCU. The MCU control board can be used alone to control the display to be tested by aging to enter the built-in test mode for aging, which can speed up the aging process and improve production efficiency.

[0050] In some embodiments of the present invention, the video adapter board is also configured with a switch chip and / or a bridge chip, which converts the module video protocol signal into a video protocol signal that can be received by the display and then transmits it to the module adapter board.

[0051] In some embodiments of the present invention, in some scenarios where the aging requirements are not high, the display aging test device does not include an FPGA signal board, and the MCU control board communicates with the host computer to receive the control signal and switches the display to the built-in test mode to achieve the built-in test picture switching aging of the display, which greatly saves the aging cost.

[0052] In some embodiments of the present invention, the MCU control board is also equipped with a flash chip for storing offline control instructions, so that built-in test picture switching aging can be realized for the display without a host computer.

[0053] In some embodiments of the present invention, the aging base plate is configured with the same top power interface as the power board, and the video adapter board is configured with the same bottom power interface as the power board.

[0054] It should be noted that, through the design of the power interface, the aging baseboard can form a stacked structure with the video adapter board or the power board, or the video adapter board can form a stacked structure with the power board or the aging baseboard, further saving the lateral space of the display aging test device.

[0055] like Figure 15 to Figure 17 As shown, a second aspect of an embodiment of the present invention provides a display aging test system, including the above-mentioned display aging test device.

[0056] In some embodiments of the present invention, a plurality of display aging test devices are connected via high-speed cables and power cables to form a display aging test system with a chain structure.

[0057] In some embodiments of the present invention, the FPGA signal board is configured with at least two high-speed interfaces, and each FPGA signal board is connected to the high-speed interface of another FPGA signal board of the display aging test device in the system through at least one high-speed interface to transmit video signals and control signals. One of the FPGA signal boards communicates with an external host computer through the high-speed interface to receive video signals and control signals.

[0058] It should be noted that by configuring at least two high-speed interfaces in the FPGA signal board, the FPGA signal board of each aging test device in the system can be cascaded together through the high-speed interface. Only the control signal and video signal of one of the FPGA signal boards needs to be transmitted to realize the transmission of the control signal and video signal of all FPGA signal boards, thereby simplifying the entire control process.

[0059] In some embodiments of the present invention, the burn-in baseboard is configured with at least two burn-in power interfaces, and the burn-in baseboard is electrically connected to the burn-in baseboard of another display burn-in test device in the system through at least one burn-in power interface. At least one burn-in baseboard is electrically connected to an external power supply through the burn-in power interface.

[0060] It should be noted that at least two aging power supply interfaces are configured on the aging baseboard, and the aging baseboards of each aging test device in the system can be cascaded together through the aging power supply interfaces. An external power supply can be connected to the aging power supply interface of one of the aging baseboards to realize the function of powering all aging baseboards, thereby reducing the use of external power supplies and reducing system costs. Example 1

[0061] like Figure 1-3 As shown, this embodiment provides a display aging test device, including an aging baseboard, an FPGA signal board installed on one side of the aging baseboard, a video adapter board, five power boards, ten module adapter boards and an MCU control board installed on the other side of the aging baseboard.

[0062] The FPGA signal board is connected to the MCU control board and the video adapter board, the MCU control board and the video adapter board are connected to ten module adapter boards, each module adapter board is connected to a display to be tested for aging, and each power board is connected to two module adapter boards.

[0063] like Figure 4As shown, the aging baseboard is configured with two MCU low-speed interfaces connected to the MCU control board, ten top power interfaces connected to the power board or the video adapter board, ten module low-speed interfaces connected to the module adapter board, ten module power interfaces connected to the module adapter board, and four aging power interfaces. The MCU low-speed interface of the aging baseboard is electrically connected to the ten module low-speed interfaces of the aging baseboard; the top power interface of the aging baseboard is electrically connected to the module power interface of the adjacent aging baseboard. The four aging power interfaces are electrically connected to each other, and the aging baseboard is electrically connected to the external power supply through one of the aging power interfaces to supply power to the FPGA signal board, the video adapter board, the five power boards, and the MCU control board in the device.

[0064] The structure of the FPGA signal board is as follows Figure 5 As shown, two high-speed interfaces, a universal interface, and an FPGA module are placed on the top of the FPGA signal board, and two high-speed board-to-board interfaces are placed at the bottom of the FPGA signal board. The FPGA signal board communicates with the host computer through a high-speed interface, such as an optical port, and receives the video signal and control signal of the host computer. The FPGA signal board communicates with the MCU control board through a universal interface, such as TYPE-C, and the FPGA signal board transmits the received control signal to the MCU control board. The FPGA signal board and the video adapter board establish an electrical connection through the high-speed board-to-board interface, and the FPGA signal board converts the received video signal into a module video protocol signal through the FPGA module and transmits it to the video adapter board.

[0065] The structure of the video adapter board is as follows Figure 6 As shown, two high-speed board-to-board interfaces and ten high-speed interfaces are placed on the top of the video adapter board, and two bottom power interfaces are placed on the bottom of the video adapter board.

[0066] The two high-speed board-to-board interfaces of the video adapter board are male or female ports that can be mated with the high-speed board-to-board interfaces on the FPGA signal board. The video adapter board receives the module video protocol signal sent by the FPGA signal board through the two high-speed board-to-board interfaces that are mated with the FPGA signal board.

[0067] The ten high-speed interfaces are FFC / FPC connectors and are placed on the edge of the video adapter board. They are connected to the module high-speed interfaces on the module adapter board through a flexible printed circuit board (FPC). The video adapter board receives the module video protocol signals sent from the FPGA signal board through two high-speed board-to-board interfaces that are buckled with the FPGA signal board, and distributes the received module video protocol signals to the ten high-speed interfaces of the video adapter board. The high-speed interface of the video adapter board is connected to the module high-speed interface of the module adapter board through a flexible printed circuit board, and sends the module video protocol signals to the module adapter board.

[0068] like Figure 7-12As shown, each power board is equipped with two top power interfaces, two bottom power interfaces, four voltage-adjustable power supplies and eight protection circuits. Each voltage-adjustable power supply is electrically connected to two protection circuits to generate two protected power supply circuits that are electrically connected to the two bottom power interfaces. The bottom power interface is placed at the bottom of the power board, and the top power interface is placed at the top of the power board. The top power interface and the bottom power interface of the power board each have 20 pins for power supply, that is, 20 power supply pins. The four voltage-adjustable power supplies are electrically connected to the bottom power interface through the protection circuit, and the four voltage-adjustable power supplies and the four power supply pins of the bottom power interface form a power supply pin group containing four power supply pins. The remaining 16 power supply pins of the bottom power interface are electrically connected to the power supply pins of the top power interface of the same power board.

[0069] The top power interface of the power board is a male or female socket that is buckled with the bottom power interface of the power board, and the two bottom power interfaces are male or female sockets that are buckled with the top power interface. N power boards can form a stacked structure by buckling, and in this embodiment, n≤5, that is, in this embodiment, each power board can be stacked with up to 4 power boards according to actual needs to form an electrically connected stacked structure by buckling.

[0070] In this embodiment, the power supply pins of the bottom power interface and the top power interface of the power board are defined as follows: Fig.10 As shown, the 20 power pins of the bottom power interface and the top power interface are divided into 5 power pin groups, each power pin group includes 4 power pins and are closely adjacent to each other.

[0071] Taking a power board as an example, the top power supply pin group and the bottom power supply pin group are electrically connected in a shifted manner. The specific connection method is as follows: Fig.11 As shown. The five power supply pin groups of the top power interface are top power supply pin group 1, top power supply pin group 2, top power supply pin group 3, top power supply pin group 4 and top power supply pin group 5. The 20 power supply pins of the bottom power interface are also divided into five power supply pin groups, namely bottom power supply pin group 1, bottom power supply pin group 2, bottom power supply pin group 3, bottom power supply pin group 4 and bottom power supply pin group 5. Bottom power supply pin group 1 consists of four power supply pins of the bottom power interface and four voltage adjustable power supplies. Top power supply pin group 1 is connected to bottom power supply pin group 2, top power supply pin group 2 is connected to bottom power supply pin group 3, top power supply pin group 3 is connected to bottom power supply pin group 4, and top power supply pin group 4 is connected to bottom power supply pin group 5.

[0072] When it is necessary to add another power board on top of a power board, the top power interface of this power board is mated with the bottom power interface of the added upper power board, and the top power supply pin group 1 of this power board is connected with the bottom power supply pin group 1 of the upper power board to achieve electrical connection between this power board and the upper power board. When it is necessary to add another power board below a power board, the bottom power interface of this power board is mated with the top power interface of the added lower power board, and the bottom power supply pin group 1 of this power board is connected with the top power supply pin group 1 of the lower power board to achieve electrical connection with the lower power board. In this embodiment, by repeatedly connecting in this way, the electrical connection of 5 power boards can be achieved.

[0073] The connection method described above can realize stacking of multiple identical power boards, and can generate multiple power supply pin groups in the bottom power interface of the bottom power board. This can stack different layers of power boards according to the actual power supply requirements of the display, providing a variable and flexible multi-way power supply circuit.

[0074] In this embodiment, the power supply pins of the two top power supply interfaces are distributed in the power supply board as follows: Fig.12 As shown in the figure, the power supply pins are defined to be arranged in the two top power interfaces in a centrosymmetric manner with the center of the power board as the symmetric point. The power supply pins 1-nm and the power supply pins 2-nm are centrosymmetric with the center of the power board as the symmetric point. m and n are positive integers and m≤4 and n≤5. The distribution of the power supply pins of the two bottom power interfaces in the power board is the same as that of the two top power interfaces. Fig.12 As shown, the power board center is the center of the origin, which simplifies the installation process by not needing to determine the connection direction when stacking.

[0075] In this embodiment, the two bottom power interfaces of the video adapter board are the same as the bottom power interfaces of the power board. The video adapter board is connected to the two top power interfaces of the power board through the two bottom power interfaces to form a laminated structure of the power board-video adapter board. Fig. 9 The top power interface of the aging baseboard is the same as the top power interface of the power board, and the power board can be buckled on the aging baseboard to form a stacked structure of the aging baseboard-power board-video adapter board.

[0076] The structure of the MCU control board is as follows Fig.13 As shown, the MCU module, two MCU low-speed interfaces and a general interface are all placed on the top of the MCU control board, and the two MCU low-speed interfaces and the general interface are all connected to the MCU module.

[0077] The two MCU low-speed interfaces of the MCU control board are male or female sockets that are buckled with the two MCU low-speed interfaces of the aging baseboard. The MCU control board is electrically connected to the aging baseboard through the MCU low-speed interfaces.

[0078] The universal interface of the MCU control board is connected to the universal interface of the FPGA signal board to receive the control signal transmitted by the FPGA signal board. The MCU module converts the control signal into a module control signal, which is transmitted to ten module adapter boards through the aging baseboard connected to the MCU control board.

[0079] The module adapter board is configured as follows Fig.14 As shown, it includes a module interface, a module low-speed interface, a module high-speed interface and a module power interface.

[0080] The module low-speed interface on the module adapter board is mated with the module low-speed interface on the aging baseboard, so that the module adapter board can receive the module control signal transmitted by the MCU control board and transmit it to the module interface of the module adapter board. The module power interface of the module adapter board is mated with the module power interface on the aging baseboard to receive the power supply output by the power board and transmit it to the module interface of the module adapter board. The module high-speed interface of the module adapter board is connected to the video adapter board through a flexible printed circuit board, receives the module video protocol signal from the video adapter board, and transmits it to the module interface of the module adapter board. The module interface of the module adapter board matches the module interface of the display to be tested for aging. The module adapter board is connected to the display to be tested for aging through the module interface of the module adapter board, and transmits the received module control signal, module video protocol signal and power to the display to be tested for aging. Through the module adapter board, when the module interface of the display is different or different displays are used, only the module adapter board needs to be designed without redesigning the entire aging test device, which can save a lot of costs. Example 2

[0081] like Figure 15-17 As shown, this embodiment provides a display aging test system, which includes multiple display aging test devices in Embodiment 1. Adjacent display aging test devices in the display aging test system are electrically connected to each other through high-speed cables and power cables to form a chain structure. The display aging test device at one end of the chain structure is connected to a host computer through a high-speed cable, and is connected to an external power supply through a power cable.

[0082] Specifically, the host computer communicates with the display aging test device 1 in the chain structure through the high-speed cable 1, and sends the video signal and the control signal. The display aging test device 1 transmits the received video signal and the control signal to the display aging test device 2 through the high-speed cable 2; similarly, the display aging test device 2 transmits the received video signal and the control signal to the display aging test device 3 through the high-speed cable 3, and so on and so forth until the transmission reaches the last display aging test device.

[0083] The FPGA signal board of the display aging test device in the system is equipped with two high-speed interfaces, such as Fig.16 As shown, one of the FPGA signal boards communicates with the host computer through a high-speed interface of the FPGA signal board to receive video signals and control signals, and then connects to the FPGA signal board of another display aging test device through another high-speed interface of the FPGA signal board to transmit video signals and control signals. The FPGA signal boards of adjacent display aging test devices are connected through high-speed interfaces to realize the cascade structure of multiple FPGA signal boards. The host computer can communicate with all display aging test devices by communicating with one display aging test device, which simplifies the control process of all display aging test devices and reduces the complexity of the overall system.

[0084] The aging baseboards of the display aging test device in the system are electrically connected to each other through the aging power interface. Fig.17 As shown, the aging power interfaces on multiple aging backplanes are connected through power cables to form a topology. Only one power supply needs to be connected to one of the aging backplanes to power all aging backplanes, without the need for each device to provide an additional external power supply, thereby reducing the use of external power supplies and reducing the cost of the entire system.

[0085] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

[0086] The above description is only an embodiment of the present invention and is not intended to limit the present invention. For those skilled in the art, the present invention may have various modifications and variations. Any modification, equivalent substitution, improvement, etc. made within the spirit and principle of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A display aging test device, characterized in that: include: Aging baseboard, FPGA signal board and / or MCU control board, video adapter board, power board and module adapter board installed on the aging baseboard; The module adapter board is electrically connected to the power board, the FPGA signal board and / or the MCU control board, and the video adapter board; the module adapter board is connected to the display to be tested for aging, and the module adapter board transmits the received signal and power to the display to be tested for aging; The power board is equipped with a top power interface, a bottom power interface and at least one voltage-adjustable power supply; The top power interface is a male or female socket, and the bottom power interface is a female or male socket that is buckled with the top power interface; both the top power interface and the bottom power interface have z power supply pins, where z is a positive integer; The number of the adjustable voltage power supplies is m, and the m adjustable voltage power supplies are electrically connected to the bottom power interface to form a power supply pin group including m power supply pins, and zm unused power supply pins of the bottom power interface are left, where m is a positive integer and m≤z; The power supply pins of the zm unused bottom power supply interfaces are electrically connected to the zm power supply pins of the top power supply interface of the same power board; The number of the power boards is n, and the n power boards can form an electrically connected stacked structure by snapping together to generate multiple power supplies to provide power to the module adapter board. n is a positive integer and n≤z / m.

2. The display aging test device according to claim 1, characterized in that: In the stacked structure in which the n power boards are electrically connected, the power supply pin group of each non-bottom-layer power board can be electrically connected to the top power interface of the power board below through snapping, thereby achieving electrical connection with the bottom power interface of the power board below, and finally achieving electrical connection with the bottom power interface of the bottom-layer power board.

3. The display aging test device according to claim 1, characterized in that: The FPGA signal board is configured with a high-speed interface, and the FPGA signal board communicates with an external host computer through the high-speed interface to receive video signals and control signals; the aging baseboard is configured with an aging power supply interface, and the aging baseboard is electrically connected to the external power supply through the aging power supply interface.

4. The display aging test device according to claim 3, characterized in that: The display aging test device includes an FPGA signal board and an MCU control board. The FPGA signal board transmits the received control signal to the MCU control board, and the MCU control board converts the received control signal into a module control signal and transmits it to the module adapter board; the FPGA signal board converts the received video signal into a module video protocol signal and transmits it to the video adapter board, and the video adapter board then transmits the module video protocol signal to the module adapter board.

5. The display aging test device according to claim 4, characterized in that: The video adapter board is also equipped with a switch chip and / or a bridge chip, which converts the module video protocol signal into a video protocol signal that can be received by the module adapter board and then transmits it to the module adapter board.

6. The display aging test device according to claim 1, characterized in that: The aging base plate is configured with the same top power interface as the power board, and the video adapter board is configured with the same bottom power interface as the power board.

7. A display aging test system, characterized in that , including the display aging test device described in any one of claims 1-6.

8. The display aging test system according to claim 7, characterized in that: A plurality of display aging test devices are connected via high-speed cables and power cables to form a display aging test system with a chain structure.

9. The display aging test system according to claim 8, characterized in that: The FPGA signal board is configured with at least two high-speed interfaces. Each FPGA signal board is connected to the FPGA signal board of another display aging test device in the system through at least one high-speed interface to transmit video signals and control signals; one of the FPGA signal boards communicates with an external host computer through the high-speed interface to receive video signals and control signals.

10. The display aging test system according to claim 8, characterized in that: The aging baseboard is configured with at least two aging power interfaces, each aging baseboard is electrically connected to the aging baseboard of another display aging test device in the system through at least one aging power interface; at least one aging baseboard is electrically connected to an external power supply through the aging power interface.

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