Chip testing method and chip
By setting up a built-in self-testing unit on the logic circuit module of the chip, and using test micro-instructions and functional micro-instructions for testing, the problem of inflexible testing in the existing technology is solved, and an efficient and low-power testing method is realized.
Patent Information
- Application Number
- CN202510232263.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-27
- Publication Date
- 2025-05-09
AI Technical Summary
The existing chip testing methods are inflexible and require periodic operation of test programs, which takes up time for the normal function of the chip and affects performance.
Design a chip test method, by setting up a built-in self-testing unit on the logic circuit module, testing each logic circuit module using test micro-instructions and functional micro-instructions, and testing the idle period of each module to avoid affecting the normal function operation.
Improves testing flexibility, reduces test peak power consumption, uses idle period for testing without affecting normal functions, and improves testing efficiency.
Smart Images
Figure CN119959736A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of chip design and testing, and in particular to a chip testing method and a chip. Background Art
[0002] The chip includes multiple logic circuit modules with their own functions, such as vector operation unit, floating point operation unit, decoding unit, memory access unit, etc. In order to ensure the high security and high reliability of the chip, the chip needs to be tested, including the testing of each logic circuit module inside it. Even when the chip system is in operation, it is necessary to monitor and test the relevant logic circuit modules in real time or periodically to ensure the correctness of the execution function. However, the current chip testing methods are not flexible and often require periodic running of test programs, which takes up the time for the normal function operation of the chip and has a great impact on the performance of the chip. Summary of the invention
[0003] The embodiment of the present application provides a chip testing method and a chip, wherein the chip includes a plurality of logic circuit modules, each of the logic circuit modules is provided with a corresponding built-in self-test unit, the chip further includes a test control unit for controlling each of the built-in self-test units, the chip corresponds to a test program, the test program has a test instruction, the test instruction includes a test microinstruction and a functional microinstruction correspondingly provided for each of the logic circuit modules, the test microinstruction is used to perform a functional test on the corresponding logic circuit module, and the functional microinstruction is used to control the corresponding logic circuit module to perform a specific operation and / or function implementation, the testing method includes:
[0004] Determining an idle period during which each of the logic circuit modules does not respond to the functional microinstructions;
[0005] During the idle period of the logic circuit module, the associated test microinstructions are run through the corresponding built-in self-test unit, and corresponding test data are obtained;
[0006] The test data is compared with the stored standard data to determine the target test result corresponding to the logic circuit module.
[0007] Optionally, the method further includes:
[0008] The test microinstructions are compiled into the sequence of the functional microinstructions, which includes: embedding the test microinstructions into the source code of the functional microinstructions; and compiling the source code.
[0009] Optionally, determining the idle period during which each of the logic circuit modules does not respond to the functional microinstruction includes:
[0010] An execution sequence of the functional microinstructions is determined, and based on statistical data of requirements of the functional microinstructions on each of the logic circuit modules in the execution sequence of the functional microinstructions, an idle period of the logic circuit module is determined.
[0011] Optionally, determining the execution order of the functional microinstructions and determining the idle period of the logic circuit module based on the statistical data of the demand of the functional microinstructions for each of the logic circuit modules in the execution order of the functional microinstructions includes:
[0012] Determining a program execution trace of the test program, wherein the program execution trace can characterize the execution order of the functional microinstructions;
[0013] Based on the statistical data of the requirements of the functional microinstructions on each of the logic circuit modules in the program execution trace of the test program and the corresponding requirement time of the test microinstructions, the current idle period of the logic circuit module is determined.
[0014] Optionally, determining the current idle period of the logic circuit module based on the statistical data of the requirements of the functional microinstructions for each of the logic circuit modules in the program execution trace of the test program and the requirement time of the corresponding test microinstructions includes:
[0015] According to the program execution trajectory, determining the logic circuit module that does not need to respond to the functional microinstruction;
[0016] Based on the continuous idle units of the logic circuit module that does not need to respond to the functional microinstruction, the current idle period of the logic circuit module is determined, wherein the idle unit is the idle time corresponding to the logic circuit module that does not need to respond to the functional microinstruction if the functional microinstruction is executed.
[0017] Optionally, during the idle period of the logic circuit module, the associated test microinstructions are run through the corresponding built-in self-test unit, and corresponding test data are obtained, including:
[0018] Isolating the interface signal of the corresponding logic circuit module through the built-in self-test unit;
[0019] According to the idle period of the logic circuit module and based on the request of the test control unit, determine the test vector and the test vector length of the test microinstruction;
[0020] Based on the test vector and the test vector length, the logic circuit module is tested and corresponding test data is obtained;
[0021] The isolation state of the interface signal of the logic circuit module is cancelled.
[0022] Optionally, the chip further includes a state holding unit, and the testing of the logic circuit module based on the test vector and the test vector length and obtaining corresponding test data includes:
[0023] storing the first state data of the logic circuit module before the test through the state holding unit;
[0024] Inputting the test vector into the logic circuit module to test the logic circuit module and obtain corresponding test data;
[0025] The state of the logic circuit module is restored using the first state data stored in the state holding unit.
[0026] Optionally, the testing the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data, includes:
[0027] Based on the target test module information in the test microinstruction, using the test control unit to send the corresponding test requirements to the corresponding logic circuit module;
[0028] Dispatching or forcibly dispatching a test request to the logic circuit module using the test control unit according to the fault tolerance time interval of the logic circuit module;
[0029] In a case where the logic circuit module has executed at least one test process, the test request is canceled or forcibly canceled.
[0030] Optionally, the testing the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data, includes:
[0031] In the case that the logic circuit module has not completed the complete test process, the length of the test vector is adjusted, and during the idle period of the logic circuit module, the test vector is used to continue testing the logic circuit module.
[0032] The embodiment of the present application further provides a chip capable of running a test program, wherein the test program has a test instruction, wherein the test instruction includes a test microinstruction and a functional microinstruction, and the chip includes:
[0033] A plurality of logic circuit modules, each corresponding to the test microinstruction and the functional microinstruction, wherein the test microinstruction is used to perform a functional test on the corresponding logic circuit module, and the functional microinstruction is used to control the corresponding logic circuit module to perform a specific operation and / or realize a function;
[0034] Built-in self-test units are respectively arranged on each corresponding logic circuit module;
[0035] A test control unit is used to control each of the built-in self-test units to determine an idle period during which each of the logic circuit modules does not respond to the functional microinstructions; wherein,
[0036] The built-in self-test unit is also used to run the associated test microinstructions during the idle period of the logic circuit module and obtain corresponding test data; compare the test data with the stored standard data to determine the target test result corresponding to the logic circuit module.
[0037] The chip testing method of the embodiment of the present application improves the test flexibility and reduces the test peak power consumption by setting a built-in self-test unit on the logic circuit module of the chip and using test microinstructions and functional microinstructions to test each logic circuit module respectively. In addition, during the test process, each logic circuit module is tested during its idle period, which does not affect other processing tasks of each logic circuit module, thereby improving the test efficiency. BRIEF DESCRIPTION OF THE DRAWINGS
[0038] Figure 1 A flowchart of a chip testing method according to an embodiment of the present application;
[0039] Figure 2 A schematic diagram of the test structure of the chip according to an embodiment of the present application;
[0040] Figure 3 For the embodiments of this application Figure 1 A flowchart of an embodiment of step S100;
[0041] Figure 4 For the embodiments of this application Figure 3 A flowchart of an embodiment of step S120;
[0042] Figure 5 The statistical data of the requirements of the functional microinstructions for each logic circuit module in the embodiment of the present application;
[0043] Figure 6 For the embodiments of this application Figure 1 A flowchart of an embodiment of step S200;
[0044] Figure 7For the embodiments of this application Figure 6 A flowchart of an embodiment of step S230;
[0045] Figure 8 For the embodiments of this application Figure 6 Flow chart of another embodiment of step S230 in FIG. DETAILED DESCRIPTION
[0046] Various aspects and features of the present application are described herein with reference to the accompanying drawings.
[0047] It should be understood that various modifications may be made to the embodiments of the present application. Therefore, the above description should not be considered as limiting, but only as an example of the embodiments. Other modifications within the scope and spirit of the present application will occur to those skilled in the art.
[0048] The accompanying drawings, which are incorporated in and constitute a part of the specification, illustrate embodiments of the present application and, together with the general description of the present application given above and the detailed description of the embodiments given below, serve to explain the principles of the present application.
[0049] These and other characteristics of the present application will become apparent from the following description of a preferred form of embodiment given as a non-limiting example with reference to the accompanying drawings.
[0050] It should also be understood that although the present application has been described with reference to some specific examples, those skilled in the art will be able to readily implement many other equivalent forms of the present application.
[0051] The above and other aspects, features and advantages of the present application will become more apparent in view of the following detailed description when taken in conjunction with the accompanying drawings.
[0052] Specific embodiments of the present application are described hereinafter with reference to the accompanying drawings; however, it should be understood that the embodiments applied for are merely examples of the present application, which may be implemented in a variety of ways. Well-known and / or repeated functions and structures are not described in detail to avoid unnecessary or redundant details that obscure the present application. Therefore, the specific structural and functional details applied for herein are not intended to be limiting, but merely serve as a basis and representative basis for the claims to teach those skilled in the art to use the present application in a variety of ways with substantially any suitable detailed structure.
[0053] This specification may use the phrases "in one embodiment," "in another embodiment," "in yet another embodiment," or "in other embodiments," all of which may refer to one or more of the same or different embodiments according to the present application.
[0054] A chip testing method according to an embodiment of the present application is applied to a chip, such as a SOC. Figure 2As shown, the chip includes a plurality of logic circuit modules, and each of the logic circuit modules is provided with a corresponding built-in self-test unit. The built-in self-test unit (BIST, Build In Self Test) can test the corresponding logic circuit module using a test instruction. For example, the logic circuit module includes: a multiplication and division operation unit, a floating point budget unit, a vector operation unit, an arithmetic operation unit, a jump unit atomic operation operation unit, an instruction fetch, a decoding unit, a memory access unit, a general register write-back unit, a general register, an L1 core bus, an L1 instruction cache, a core timer, a core interrupt controller, an L1 data cache, an L1 tightly coupled cache, an L2 core bus, etc.
[0055] The chip also includes a test control unit for controlling each of the built-in self-test units. The test control unit is connected to each of the built-in self-test units respectively and can control each of the built-in self-test units so that the built-in self-test units test the corresponding logic circuit modules.
[0056] The chip has a test program corresponding to it, and the test program can be pre-built based on the chip to adapt it to the chip. The test program has test instructions, and the test instructions include test microinstructions and functional microinstructions corresponding to each logic circuit module.
[0057] In one embodiment, each logic circuit module has a corresponding test microinstruction, so that the test microinstruction can be used to perform functional testing on the corresponding logic circuit module. After the logic circuit module executes the test microinstruction, it can feedback corresponding test data, and through the test data, it can be determined whether the logic circuit module meets the preset requirements. The functional microinstruction is used to control the corresponding logic circuit module to perform specific operations and / or function realization. In this embodiment, since the test of the entire chip is divided into the test of multiple independent small logic circuit modules, the test time of each logic circuit module is greatly shortened. At the same time, the peak power consumption during the test of a single logic circuit module is greatly reduced relative to the overall power consumption of the entire test chip.
[0058] For example, when the functional microinstruction is a MUL multiplication instruction and the logic circuit module is a multiplication and division operation unit, the MUL multiplication instruction can be used to implement the multiplication and division functions of the multiplication and division operation unit; when the functional microinstruction is a single-precision addition instruction and the logic circuit module is a floating-point budget unit, the single-precision addition instruction can be used to implement the single-precision addition function of the floating-point budget unit; when the functional microinstruction is a VL vector load instruction and the logic circuit module is a vector operation unit, the VL vector load instruction can be used to implement the vector operation function of the vector operation unit; when the functional microinstruction is an SRL logical right shift instruction and the logic circuit module is an arithmetic operation unit, the SRL logical right shift instruction can be used to implement the logical and arithmetic operation function of the logical and arithmetic operation unit; when the functional microinstruction is a BEQ equal condition jump instruction and the logic circuit module is a jump unit, it can be used to implement the jump function of the jump unit; when the functional microinstruction is an AMOSWAP atomic exchange instruction and the logic circuit module is an atomic operation operation unit, the AMOSWAP atomic exchange instruction can be used to implement the atomic exchange function of the atomic operation operation unit, etc.
[0059] Based on the above structure of the chip, Figure 1 Shown and combined Figure 2 The chip testing method of the embodiment of the present application comprises the following steps:
[0060] S100, determining an idle period during which each of the logic circuit modules does not respond to the functional microinstructions.
[0061] Exemplarily, after the chip runs the test program, it can run the test instructions therein, including running multiple consecutive functional microinstructions. Each functional instruction has a corresponding functional microinstruction. After a functional microinstruction is run, the corresponding logic circuit module will respond, while other logic circuit modules will not respond to it, so that the unresponsive logic circuit module will have an idle period, and the idle period is the time limit during which the corresponding logic circuit module does not make a functional response. After multiple consecutive functional microinstructions are run, each logic circuit module may have its idle period.
[0062] In one embodiment, determining the idle period of the logic circuit module includes: determining the execution order of the functional microinstructions, and determining the idle period of the logic circuit module based on the statistical data of the demand of the functional microinstructions for each of the logic circuit modules in the execution order of the functional microinstructions.
[0063] For example, multiple test instructions in the test program have corresponding test sequences. Correspondingly, after running the test program, multiple functional microinstructions will be continuously run, and the multiple functional microinstructions have an execution sequence. If the functional microinstructions are executed in this execution sequence, in this process, for each functional microinstruction, the corresponding logic circuit module will respond, while other logic circuit modules will not respond, which indicates that the functional microinstruction needs to cooperate with the corresponding logic circuit module, but does not require the cooperation of other logic circuit modules. In this embodiment, based on the request of each functional microinstruction to each logic circuit module, the corresponding demand statistical data can be obtained, and the demand statistical data indicates the demand of the functional microinstruction for each logic circuit module. Based on the demand statistical data, the idle period of each logic circuit module is determined.
[0064] In another embodiment, the test program can be pre-tested to pre-test multiple functional microinstructions. During the test run, all logic circuit modules will generate corresponding response identifiers, including identifiers of successful responses and failed responses. After all response identifiers are obtained, the idle period of the logic circuit module can be determined based on the statistical information of the response identifiers.
[0065] In another embodiment, each functional microinstruction has identification information of its corresponding logic circuit module. After the test program is determined, the identification information can be sorted. Based on the sorting of the identification information, the idle period during which each logic circuit module will not respond to the functional microinstruction can be determined.
[0066] S200, during the idle period of the logic circuit module, the associated test microinstructions are run through the corresponding built-in self-test unit, and corresponding test data are obtained.
[0067] Exemplarily, the logic circuit module does not make a functional response during its idle period. Each logic circuit module may have multiple idle periods. The logic circuit module may be tested during its idle period. The specific testing method may be to run a test microinstruction associated with the logic circuit module through a built-in self-test unit attached to the logic circuit module. After executing the test microinstruction, the logic circuit module returns corresponding test data.
[0068] For example, when the logic circuit module is a multiplication and division unit, the MUL multiplication instruction is run through the built-in self-test unit attached to the multiplication and division unit to test the multiplication and division functions of the multiplication and division unit. After the multiplication and division unit executes the MUL multiplication instruction, it returns corresponding test data, and the built-in self-test unit obtains the test data. Similarly, when the logic circuit module is a floating-point budget unit, the single-precision addition instruction is run through the built-in self-test unit attached to the multiplication and division unit to test the single-precision addition function of the floating-point budget unit. After the floating-point budget unit executes the single-precision addition instruction, it returns corresponding test data, and the built-in self-test unit obtains the test data.
[0069] In one embodiment, during the initial stage of the idle period of the logic circuit module, the corresponding built-in self-test unit can run the associated test microinstructions and obtain the corresponding test data, thereby extending the test time of the logic circuit module as much as possible.
[0070] S300, comparing the test data with the stored standard data to determine a target test result corresponding to the logic circuit module.
[0071] Exemplarily, the standard data is data obtained by executing corresponding instructions on the corresponding logic circuit module that meets the quality requirements. In one embodiment, each logic circuit module in the chip that meets the production quality requirements has its corresponding standard data, which can be pre-stored in the chip, for example, in a test microinstruction, or in a built-in self-test unit.
[0072] When testing the logic circuit module, the acquired test data can be compared with the stored standard data. If the difference between the test data and the standard data is within the first range, such as the test data and the standard data are the same, it can be determined that the target test result corresponding to the logic circuit module is that the logic circuit module meets the test requirements. If the difference between the test data and the standard data exceeds the first range, such as the content between the test data and the standard data is significantly different, it can be determined that the target test result corresponding to the logic circuit module is that the logic circuit module does not meet the test requirements.
[0073] The chip testing method of the embodiment of the present application improves the test flexibility and reduces the test peak power consumption by setting a built-in self-test unit on the logic circuit module of the chip and using test microinstructions and functional microinstructions to test each logic circuit module respectively. In addition, during the test process, each logic circuit module is tested during its idle period, which does not affect other processing tasks of each logic circuit module, thereby improving the test efficiency.
[0074] In one embodiment of the present application, the method further includes determining a corresponding test program based on a test structure (test architecture) of the chip, including constructing a test microinstruction corresponding to the test program based on the logic circuit module. Different chips have different corresponding test structures, and the test program is adapted to the chip and its test structure.
[0075] Constructing a test program includes constructing the test microinstructions therein. For example, construct a BIST test microinstruction (BIST_INST). The BIST_INST needs to contain the following information: the execution code (Operation Code) corresponding to BISTI, and the target test unit (Target Test Unit). Among them, the target test unit has a test target number, and the minimum value can be represented as not testing any sub-module, and the maximum value can be represented as testing all sub-modules, in order to expand the flexibility of the test. Excluding the minimum value and the maximum value, each remaining number corresponds to a sub-module inside the CPU that can be independently tested by BIST.
[0076] The test microinstruction also includes a test initial vector pointer (Initial Vector), a test vector number (Vector Length), and a test result return value (Test Result). The test initial vector pointer (Initial Vector) is used to store the test initial vector, and the test vector number (Vector Length) refers to how many test vectors are run in one test. The more vectors there are, the longer the test time will be. The test result return value (Test Result) contains the test result information.
[0077] In one embodiment of the present application, the method further includes the following steps: compiling the test microinstructions into a sequence of the functional microinstructions, including: embedding the test microinstructions into source code of the functional microinstructions; and compiling the source code.
[0078] Exemplarily, the test microinstructions are compiled into the sequence of the functional microinstructions to form corresponding test instructions. Based on the test instructions, the responses of the various logic circuit modules can be counted, and then the idle period of the logic circuit module can be determined. The test microinstructions are embedded into the source code of the functional microinstructions and the source code is compiled to form an assembly language that can be executed by hardware. The test microinstructions in the test instructions can be run during the idle period of the logic circuit module.
[0079] In one embodiment of the present application, the step of determining the idle period during which each of the logic circuit modules does not respond to the functional microinstructions includes: determining the execution order of the functional microinstructions, and determining the idle period of the logic circuit module based on the statistical data of the demand of the functional microinstructions for each of the logic circuit modules in the execution order of the functional microinstructions. The step of determining the idle period is further as follows: Figure 3 As shown, the following steps are included:
[0080] S110, determining a program execution trace of the test program, wherein the program execution trace can characterize an execution order of the functional microinstructions.
[0081] Exemplarily, after the test program is constructed, it has a corresponding program execution track, which marks the running process of the test program. Since the test program is provided with test instructions, the program execution track can characterize the execution order of the functional microinstructions. During the execution of the functional microinstructions in their execution order, each logic circuit module will judge each functional microinstruction executed in sequence to determine whether to respond.
[0082] S120, determining the idle period of the logic circuit module based on the statistical data of the demand of the functional microinstructions for each of the logic circuit modules in the program execution trace of the test program and the demand time of the corresponding test microinstructions.
[0083] Exemplarily, in the program execution trace of the test program, each functional microinstruction is executed in a corresponding order, and during the execution, the requirements for each logic circuit module are different. For example, if the functional microinstruction of the MUL multiplication instruction is executed, the logic circuit module of the multiplication and division operation unit needs to respond to it, and no other logic circuit modules need to respond. If the functional microinstruction of the single-precision addition instruction is executed, the logic circuit module of the floating-point operation unit needs to respond to it, and no other logic circuit modules need to respond.
[0084] In one embodiment, based on the execution order of the functional microinstructions, the demand information of each functional microinstruction on each logic circuit module can be counted to form demand statistical data, so as to determine the idle period of the logic circuit module based on the demand statistical data.
[0085] In another embodiment, based on the execution order of the functional microinstructions, the demand information of each functional microinstruction for each logic circuit module can be counted to form demand statistics, so as to determine the current idle period of the logic circuit module based on the demand statistics and the demand time of the corresponding test microinstructions. Specifically, there may be multiple time periods when the logic circuit module does not respond to the functional microinstructions, and each time period can be used as an idle period. The demand time of the test microinstruction is the time required to run the complete test microinstruction. If the demand time of the test microinstruction is less than a pre-used time period of the corresponding logic circuit module, in this case the test microinstruction can be completely run, and the time period can be determined as the current idle period. If the demand time of the test microinstruction is greater than a pre-used time period of the corresponding logic circuit module, another larger pre-used time period can be selected as the current idle period, so that the larger idle period can be effectively utilized to run the test microinstruction.
[0086] In one embodiment of the present application, the current idle period of the logic circuit module is determined based on the statistical data of the demand of the functional microinstructions for each of the logic circuit modules in the program execution trace of the test program and the demand time of the corresponding test microinstructions, such as Figure 4 Shown and combined Figure 5 ,include:
[0087] S121, determining the logic circuit module that does not need to respond to the functional microinstruction based on the program execution trajectory.
[0088] Exemplarily, after the test program is constructed, the test program may have multiple program execution traces for the test architecture of the corresponding chip. In this embodiment, based on each program execution trace, the logic circuit module to which it is associated can be determined.
[0089] For example, through analysis, we can conclude that there are three possible program execution trajectories:
[0090] Path1: A1->A2->A3->A4->B1->B2->B3->B4->F1->F2->R1
[0091] Path2: A1->A2->A3->A4->C1->C2->D1->D2->G1->G2->R1
[0092] Path3: A1->A2->A3->A4->C1->C2->E1->E2->G1->G2->R1
[0093] Each program execution track is associated with multiple functional microinstructions. For example, the functional microinstructions associated with Path1 are as follows: A1, A2, A3, A4, B1, B2, B3, B4, F1, F2, R1. The functional microinstructions associated with Path2 are as follows: A1, A2, A3, A4, C 1, C 2, D1, D2, G 1, G 2, R1. The functional microinstructions associated with Path3 are as follows: A1, A2, A3, A4, C 1, C 2, E 1, E 2, G 1, G 2, R1.
[0094] According to the program execution trajectory, the corresponding functional microinstruction execution order is analyzed to obtain the logic circuit module that does not need to respond to each functional microinstruction. For example, for A1 in Path1, only the first logic circuit module corresponding to it needs to respond, while other logic circuit modules do not need to respond. For A2 in Path1, only the second logic circuit module corresponding to it needs to respond, while other logic circuit modules do not need to respond, and so on.
[0095] S122, determining the current idle period of the logic circuit module based on the continuous idle units of the logic circuit module that does not need to respond to the functional microinstruction, wherein the idle unit is the idle time corresponding to the logic circuit module that does not need to respond to the functional microinstruction if the functional microinstruction is run.
[0096] Exemplarily, for a functional microinstruction, multiple logic circuit modules may not need to respond to it. The running time period of the functional microinstruction can be used as an idle unit of the logic circuit module that does not need to respond to the functional microinstruction.
[0097] Combination Figure 5 For example, for a MUL multiplication instruction, except for the multiplication and division operation unit, other floating point budget units, vector operation units, arithmetic operation units, jump units, and atomic operation operation units do not need to respond to it. The time when the multiplication and division operation unit responds to the MUL multiplication instruction is used as the first time period. The first time period is the idle time of the logic circuit module that does not need to respond to the MUL multiplication instruction, and then the first time period can be used as an idle unit of the logic circuit module that will not respond to the MUL multiplication instruction.
[0098] For the single-precision addition instruction, except for the floating-point budget unit, other multiplication and division operation units, vector operation units, arithmetic operation units, jump units, and atomic operation operation units will not respond to it. The time when the floating-point budget unit responds to the single-precision addition instruction is used as the second time period, and the second time period is the idle time of the logic circuit module that will not respond to the single-precision addition instruction, and then the second time period can be used as another idle unit of the logic circuit module that will not respond to the single-precision addition instruction.
[0099] For a plurality of continuous microinstructions with different functions, each logic circuit module has continuous idle cells. The continuous idle cells can be used as an idle period. In one embodiment, a relationship table indicating the association between each functional microinstruction and each logic circuit module can be constructed, and the idle cells of each logic circuit module are determined based on the content in the relationship table, thereby determining the idle period of each logic circuit module.
[0100] In one embodiment of the present application, during the idle period of the logic circuit module, the associated test microinstructions are run through the corresponding built-in self-test unit, and corresponding test data are obtained, such as Figure 6 As shown, including:
[0101] S210, isolating the interface signal of the corresponding logic circuit module through the built-in self-test unit.
[0102] Exemplarily, the interface signal of the logic circuit module is used for data exchange between the logic circuit module and other modules in the chip. The built-in self-test unit can use the control instruction to close the interface of the corresponding logic circuit module, thereby isolating the interface signal of the logic circuit module from other parts of the chip. This will prevent the logic circuit module from being affected by external factors during the test.
[0103] S220, determining a test vector and a test vector length of the test microinstruction according to an idle period of the logic circuit module and based on a request of the test control unit.
[0104] Exemplarily, the test control unit will issue a request to the built-in self-test unit, and the built-in self-test unit will start the test operation according to the request, and determine the test vector and test vector length of the test microinstruction according to the idle period of the logic circuit module. Among them, the test vector is a set of preset input signal combinations, which can be presented in the form of binary code. The test vector is applied to the logic circuit module under test, and the logic circuit module will generate corresponding test data according to its own circuit logic. By comparing the test data with the stored standard data, it can be determined whether the logic circuit module has functional failures or performance problems. The test vector length refers to the number of binary bits contained in a test vector. When testing the chip, each binary bit represents the state of an input signal (0 or 1), and the test vector length reflects the number of input signal combinations applied to the logic circuit under test at the same time in a test.
[0105] In this embodiment, the test vector and the test vector length of the test microinstruction can be determined according to the size of the idle period, so that the test vector and the test vector length are compatible with the size of the idle period of the logic circuit module.
[0106] S230, testing the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data.
[0107] Exemplarily, based on the test vector and the test vector length, the test microinstruction can be run at the start time of the idle period to test the corresponding logic circuit module and obtain the corresponding test data. Running the test microinstruction at the start time of the idle period can effectively utilize the idle period of the logic circuit module and increase the test time as much as possible.
[0108] The built-in self-test unit selects the corresponding initial test vector and test vector length to test the logic circuit module under test according to the request of the test control unit. The test process can use boundary scan (SCAN) technology to input the test vector into the logic circuit module under test and check the response of the logic circuit module to the test vector, obtain the test data and compare it with the stored standard data, determine the correctness of the logic circuit module according to the comparison result, and then obtain the target test result. The built-in self-test unit returns the target test result to the test control unit.
[0109] Preferably, when the logic circuit module has not completed a complete test process, the length of the test vector is adjusted, and the logic circuit module is continuously tested using the test vector during an idle period of the logic circuit module.
[0110] For example, if the length of the test vector is relatively long, it may not be fully tested during the idle period, so that the logic circuit module can only perform a partial test process during the idle period, and cannot perform a complete test. This requires that the test be continued during another idle period of the logic circuit module, and the length of the test vector can be adjusted to make it suitable for another idle period, so as to continue testing the logic circuit module.
[0111] S240, canceling the isolation state of the interface signal of the logic circuit module.
[0112] For example, after the roadbed circuit module is tested, the built-in self-test unit can use a control instruction to open the interface of the corresponding logic circuit module, thereby canceling the isolation of the interface signal of the logic circuit module from other parts of the chip, so that the logic circuit module can resume its function.
[0113] In one embodiment of the present application, the chip further includes a state holding unit, which tests the logic circuit module based on the test vector and the test vector length, and obtains corresponding test data, such as Figure 7 As shown, including:
[0114] S231, storing the first state data of the logic circuit module before the test through the state holding unit.
[0115] Exemplarily, the state holding unit is used to hold the original state of the logic circuit module before the test. The state holding unit can be connected to the built-in self-test units of all the logic circuit modules in the chip, and the first state data of the logic circuit module before the test can be obtained through the built-in self-test unit, and the first state data is stored.
[0116] S232, input the test vector into the logic circuit module to test the logic circuit module and obtain corresponding test data.
[0117] Exemplarily, during the process of the test control unit controlling the built-in self-test unit to test the logic circuit module, the built-in self-test unit selects the corresponding initial test vector and the test vector length to test the tested logic circuit module according to the request of the test control unit. The built-in self-test unit obtains the corresponding test data and compares it with the stored standard data to obtain the target test result.
[0118] S233: Restore the state of the logic circuit module by using the first state data stored in the state holding unit.
[0119] Exemplarily, after completing the test of the logic circuit module, the state of the logic circuit module is restored using the first state data stored in the state holding unit, so that the logic circuit module enters the state before the test, preventing errors in the logic circuit module and maintaining the stability of the logic circuit module.
[0120] In one embodiment of the present application, the logic circuit module is tested based on the test vector and the test vector length, and corresponding test data is obtained, such as Figure 8 As shown, including:
[0121] S234, based on the target test module information in the test microinstruction, using the test control unit to send the corresponding test requirements to the corresponding logic circuit module;
[0122] S235, dispatching or forcibly dispatching a test request to the logic circuit module using the test control unit according to the fault tolerance time interval of the logic circuit module;
[0123] S236: When the logic circuit module has executed at least one test process, cancel or forcibly cancel the test request.
[0124] Exemplarily, the target test module information in the test microinstruction includes relevant information of the test target, and also includes relevant information of the test vector and test length of the test instruction. Based on the target test module information, the test control unit sends the corresponding test requirements to the corresponding logic circuit module.
[0125] For example, the test control unit parses the test microinstruction (BIST_INST instruction) and dispatches the test requirement (Vector, Length) to the corresponding logic circuit module (Target Test Unit). The test vector Vector is the vector address (Last Vector) completed in the last test. After this test is completed, Last Vector = Last Vector + Length. If (Laster Vector-Initial Vector) is greater than the total length of the test vector Total Vector Length, the Last Vector is reset to the initial vector (Initial Vector) address. Length is calculated based on the Vector Length in BIST_INST. If Vector Length + (Last Vector-Initial Vector) is less than Total Vector Length, Length = Vector Length, otherwise Length = Total Vector Length-(Last Vector-Initial Vector).
[0126] The test control unit can choose to forcibly dispatch a test request according to the requirements of the fault tolerance time interval (FTTI) of the logic circuit module. In a high-security application scenario, at least one test of the tested logic circuit module needs to be completed within a FTTI time period. Due to the uncertainty of instruction execution, in a specific scenario, within a FTTI time interval, the test microinstruction (BSIT_INST instruction) of the logic circuit module may not be fully executed, resulting in insufficient testing of the tested logic circuit module. In order to meet the requirements of FTTI, the test control unit can enable the function of forcibly dispatching test requests in a high-security scenario. Specifically, the test control unit allocates a timer to each tested logic circuit module. The timing interval of the timer is set to be no greater than the interval of FTTI. If the FTTI is 5 milliseconds, the timing interval of the timer can be set to 4 milliseconds. The timer starts counting from the execution of the first test microinstruction (BSIT_INST instruction) of the corresponding tested logic circuit module. If a complete test of the unit under test is not completed within a 4 millisecond interval, a test request is forcibly dispatched to the unit under test. Of course, the tested logic circuit module can choose to forcibly cancel the test request according to the requirement of the fault tolerance time interval (FTTI). In one embodiment, according to the requirement of FTTI, only one test of the tested unit needs to be completed within one FTTI time period.
[0127] In addition, similar to the process of forcibly dispatching test requests, the test control unit can enable forced cancellation of test requests. Within a timer counting cycle, if a complete test has been completed, the subsequent test microinstructions (BSIT_INST instructions) within the cycle will be forcibly canceled to improve CPU performance while reducing power consumption wasted due to unnecessary testing. During the execution of the test microinstruction (BSIT_INST instruction), the subsequent functional microinstructions can be executed in parallel.
[0128] The embodiment of the present application provides a chip capable of executing the above method. The chip can run a test program, wherein the test program has a test instruction, and the test instruction includes a test microinstruction and a functional microinstruction, such as Figure 2 As shown, the chip includes:
[0129] A plurality of logic circuit modules, each corresponding to the test microinstruction and the functional microinstruction, wherein the test microinstruction is used to perform a functional test on the corresponding logic circuit module, and the functional microinstruction is used to control the corresponding logic circuit module to perform a specific operation and / or realize a function;
[0130] Built-in self-test units are respectively arranged on each corresponding logic circuit module;
[0131] A test control unit is used to control each of the built-in self-test units to determine an idle period during which each of the logic circuit modules does not respond to the functional microinstructions; wherein,
[0132] The built-in self-test unit is also used to run the associated test microinstructions during the idle period of the logic circuit module and obtain corresponding test data; compare the test data with the stored standard data to determine the target test result corresponding to the logic circuit module.
[0133] An embodiment of the present application further provides an electronic device, including a processor and a memory, wherein the memory stores an executable program, and the memory executes the executable program to perform the steps of the method described above.
[0134] An embodiment of the present application further provides a storage medium, wherein the storage medium carries one or more computer programs, and when the one or more computer programs are executed by a processor, the steps of the method described above are implemented.
[0135] An embodiment of the present application also provides a computer program product, including a computer program / instruction, characterized in that the steps of the above method are implemented when the computer program / instruction is executed by a processor.
[0136] It should be understood that in the embodiments of the present application, the processor may be a central processing unit (CPU), and the processor may also be other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field-programmable gate arrays (FPGA), or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, etc.
[0137] It should also be understood that the memory mentioned in the embodiments of the present application may be a volatile memory or a non-volatile memory, or may include both volatile and non-volatile memories. Among them, the non-volatile memory may be a read-only memory (ROM), a programmable read-only memory (PROM), an erasable programmable read-only memory (EPROM), an electrically erasable programmable read-only memory (EEPROM), or a flash memory. The volatile memory may be a random access memory (RAM), which is used as an external cache. By way of example but not limitation, many forms of RAM are available, such as static random access memory (SRAM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), enhanced synchronous dynamic random access memory (ESDRAM), synchronous link dynamic random access memory (SLDRAM) and direct memory bus random access memory (Direct Rambus RAM, DR RAM).
[0138] It should be noted that when the processor is a general-purpose processor, DSP, ASIC, FPGA or other programmable logic device, discrete gate or transistor logic device, discrete hardware component, the memory (storage module) is integrated in the processor.
[0139] It should be noted that the memory described herein is intended to include, but is not limited to, these and any other suitable types of memory.
[0140] It should also be understood that the first, second, third, fourth and various numerical numbers involved in this document are only distinctions made for the convenience of description and are not intended to limit the scope of the present application.
[0141] It should be understood that the term "and / or" in this article is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / " in this article generally indicates that the associated objects before and after are in an "or" relationship.
[0142] In the implementation process, each step of the above method can be completed by an integrated logic circuit of hardware in a processor or an instruction in the form of software. The steps of the method disclosed in conjunction with the embodiment of the present application can be directly embodied as a hardware processor for execution, or a combination of hardware and software modules in a processor for execution. The software module can be located in a storage medium mature in the art such as a random access memory, a flash memory, a read-only memory, a programmable read-only memory or an electrically erasable programmable memory, a register, etc. The storage medium is located in a memory, and the processor reads the information in the memory and completes the steps of the above method in conjunction with its hardware. To avoid repetition, it is not described in detail here.
[0143] In various embodiments of the present application, the size of the serial numbers of the above-mentioned processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present application.
[0144] Those skilled in the art will appreciate that the various illustrative logical blocks (ILBs) and steps described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, or in a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.
[0145] In the several embodiments provided in the present application, it should be understood that the disclosed methods, chips, electronic devices, etc. can be implemented in other ways. For example, the chip embodiments described above are only schematic. For example, the division of the units is only a logical function division. There may be other division methods in actual implementation, such as multiple units or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be an indirect coupling or communication connection through some interfaces, devices or units, which can be electrical, mechanical or other forms.
[0146] The units described as separate components may or may not be physically separated, and the components shown as units may or may not be physical units, that is, they may be located in one place or distributed on multiple network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
[0147] In addition, each functional unit in each embodiment of the present application may be integrated into one processing unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.
[0148] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integration. The available medium can be a magnetic medium, (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state hard disk), etc.
[0149] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art who is familiar with the present technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.
Claims
1. A chip testing method, characterized in that: The chip includes a plurality of logic circuit modules, each of which is provided with a corresponding built-in self-test unit, and the chip also includes a test control unit for controlling each of the built-in self-test units. The chip corresponds to a test program, and the test program has test instructions. The test instructions include test microinstructions and functional microinstructions correspondingly provided for each of the logic circuit modules. The test microinstructions are used to perform functional tests on the corresponding logic circuit modules, and the functional microinstructions are used to control the corresponding logic circuit modules to perform specific operations and / or function implementations. The test method includes: Determining an idle period during which each of the logic circuit modules does not respond to the functional microinstructions; During the idle period of the logic circuit module, the associated test microinstructions are run through the corresponding built-in self-test unit, and corresponding test data are obtained; The test data is compared with the stored standard data to determine the target test result corresponding to the logic circuit module.
2. The chip testing method according to claim 1, characterized in that: The method further comprises: The test microinstructions are compiled into the sequence of the functional microinstructions, which includes: embedding the test microinstructions into the source code of the functional microinstructions; and compiling the source code.
3. The chip testing method according to claim 1, characterized in that: The step of determining an idle period during which each of the logic circuit modules does not respond to the functional microinstruction comprises: An execution sequence of the functional microinstructions is determined, and based on statistical data of requirements of the functional microinstructions on each of the logic circuit modules in the execution sequence of the functional microinstructions, an idle period of the logic circuit module is determined.
4. The chip testing method according to claim 3, characterized in that: The step of determining the execution order of the functional microinstructions and determining the idle period of the logic circuit module based on the statistical data of the demand of the functional microinstructions for each logic circuit module in the execution order of the functional microinstructions comprises: Determining a program execution trace of the test program, wherein the program execution trace can characterize the execution order of the functional microinstructions; Based on the statistical data of the requirements of the functional microinstructions on each of the logic circuit modules in the program execution trace of the test program and the corresponding requirement time of the test microinstructions, the current idle period of the logic circuit module is determined.
5. The chip testing method according to claim 4, characterized in that: The determining of the current idle period of the logic circuit module based on the statistical data of the demand of the functional microinstructions for each logic circuit module in the program execution trace of the test program and the demand time of the corresponding test microinstructions includes: According to the program execution trajectory, determining the logic circuit module that does not need to respond to the functional microinstruction; Based on the continuous idle units of the logic circuit module that does not need to respond to the functional microinstruction, the current idle period of the logic circuit module is determined, wherein the idle unit is the idle time corresponding to the logic circuit module that does not need to respond to the functional microinstruction if the functional microinstruction is executed.
6. The chip testing method according to claim 1, characterized in that: During the idle period of the logic circuit module, the associated test microinstructions are run through the corresponding built-in self-test unit, and corresponding test data are obtained, including: Isolating the interface signal of the corresponding logic circuit module through the built-in self-test unit; According to the idle period of the logic circuit module and based on the request of the test control unit, determine the test vector and the test vector length of the test microinstruction; Based on the test vector and the test vector length, the logic circuit module is tested and corresponding test data is obtained; The isolation state of the interface signal of the logic circuit module is cancelled.
7. The chip testing method according to claim 6, characterized in that: The chip further includes a state holding unit, which tests the logic circuit module based on the test vector and the test vector length and obtains corresponding test data, including: storing the first state data of the logic circuit module before the test through the state holding unit; Inputting the test vector into the logic circuit module to test the logic circuit module and obtain corresponding test data; The state of the logic circuit module is restored using the first state data stored in the state holding unit.
8. The chip testing method according to claim 6, characterized in that: The testing of the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data, includes: Based on the target test module information in the test microinstruction, using the test control unit to send the corresponding test requirements to the corresponding logic circuit module; Dispatching or forcibly dispatching a test request to the logic circuit module using the test control unit according to the fault tolerance time interval of the logic circuit module; In a case where the logic circuit module has executed at least one test process, the test request is canceled or forcibly canceled.
9. The chip testing method according to claim 6, characterized in that: The testing of the logic circuit module based on the test vector and the test vector length, and obtaining corresponding test data, includes: In the case that the logic circuit module has not completed the complete test process, the length of the test vector is adjusted, and during the idle period of the logic circuit module, the test vector is used to continue testing the logic circuit module.
10. A chip, characterized in that: A test program can be run, wherein the test program has test instructions, wherein the test instructions include test microinstructions and functional microinstructions, and the chip includes: A plurality of logic circuit modules, each corresponding to the test microinstruction and the functional microinstruction, wherein the test microinstruction is used to perform a functional test on the corresponding logic circuit module, and the functional microinstruction is used to control the corresponding logic circuit module to perform a specific operation and / or realize a function; Built-in self-test units are respectively arranged on each corresponding logic circuit module; A test control unit is used to control each of the built-in self-test units to determine an idle period during which each of the logic circuit modules does not respond to the functional microinstructions; wherein, The built-in self-test unit is also used to run the associated test microinstructions during the idle period of the logic circuit module and obtain corresponding test data; compare the test data with the stored standard data to determine the target test result corresponding to the logic circuit module.