Power supply time sequence control chip and method, and computer readable storage medium

Abstract

The invention provides a power supply time sequence control chip and method, a chip and a computer readable storage medium, and the power supply time sequence control chip comprises a level conversion circuit which is used for outputting a first voltage signal; the power failure control circuit is connected with the level conversion circuit and used for outputting a power-on control signal to the level conversion circuit according to the first voltage signal when the level conversion circuit receives the first forbidden signal and controlling the level conversion circuit to be powered on according to the power-on control signal. The problem that the controller enters an unknown operation state due to inaccurate power-on or power-off logic is avoided, and the correctness of the sequential logic of the chip is ensured, so that the starting efficiency of the controller is optimized, the effective reset of the controller is realized, and the whole power supply sequential control chip can be normally started.

Description

Technical Field

[0001] The present invention relates to the field of power supply control technology, and in particular to a power supply timing control chip and method, and a computer-readable storage medium. Background Art

[0002] In the prior art, when a controller in a conventional vehicle-mounted system fails, for example, due to some strong electromagnetic interference pulses, causing the program to run away, the controller usually needs to be powered off and then powered on and reset before it can enter a normal working state. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art.

[0004] To this end, one purpose of the present invention is to propose a power timing control chip, which can accurately control the power-off timing and power-on timing of the controller, avoid the problem of inaccurate power-on or power-off logic causing the controller to enter an unknown operating state, ensure the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller, and effectively resetting the controller, so that the entire power timing control chip can start normally.

[0005] Therefore, a second objective of the present invention is to provide a power sequence control method.

[0006] To this end, a third object of the present invention is to provide a chip.

[0007] To this end, a fourth object of the present invention is to provide a non-transitory computer-readable storage medium.

[0008] In order to achieve the above-mentioned purpose, an embodiment of the first aspect of the present invention proposes a power timing control chip, which includes: a level conversion circuit, which is used to output a first voltage signal; a power-off control circuit, which is connected to the level conversion circuit, and is used to output a power-on control signal to the level conversion circuit according to the first voltage signal when the level conversion circuit receives a first disable signal, and control the level conversion circuit to power on according to the power-on control signal.

[0009] According to the power timing control chip of the embodiment of the present invention, a power-off control circuit is set to monitor the first voltage signal of the level conversion circuit. When the level conversion circuit receives the first disable signal, the first voltage signal begins to decrease. The power-off control circuit continuously monitors the first voltage signal, and after determining that the controller is successfully powered off according to the first voltage signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit, so that the level conversion circuit is powered on again to supply power to the controller, thereby achieving accurate control of the power-off timing and power-on timing of the controller, avoiding the problem of the controller entering an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller, achieving effective resetting of the controller, and allowing the entire power timing control chip to start normally.

[0010] In some embodiments, the power-off control circuit includes: a comparison subcircuit connected to the level conversion circuit, used to compare the first voltage signal with a preset voltage threshold; an output subcircuit connected to the output end of the comparison subcircuit, used to output the power-on control signal to the level conversion circuit according to the comparison result of the comparison subcircuit.

[0011] In some embodiments, the method further includes: an interface conversion circuit connected to the level conversion circuit, and configured to send the second control signal to the level conversion circuit upon receiving a wake-up signal.

[0012] In some embodiments, the output subcircuit is specifically configured to: output the power-on control signal to the level conversion circuit when the first voltage signal is less than the preset voltage threshold and the second control signal is received.

[0013] In some embodiments, the method further includes: a controller connected to the level conversion circuit, wherein the level conversion circuit outputs the first voltage signal for powering the controller.

[0014] In some embodiments, it also includes: a counter circuit, which is respectively connected to the level conversion circuit and the controller, and is used to send a third control signal to the level conversion circuit when it is determined that the controller is not faulty, and the third control signal is used to enable the level conversion circuit to output a power supply voltage signal, wherein the power supply voltage signal at least includes a first voltage signal.

[0015] In some embodiments, the counter circuit is further configured to: send the first disable signal to the level conversion circuit when it is determined that the controller fails.

[0016] In some embodiments, the counter circuit includes: a storage sub-circuit connected to the level conversion circuit and used to store the cycle time of the counter circuit.

[0017] In some embodiments, the counter circuit is further used to: determine that the controller is not faulty when a control signal from the controller is received within the cycle time; and determine that the controller is faulty when no control signal from the controller is received within the cycle time.

[0018] In some embodiments, the counter circuit further includes: a clock subcircuit connected to the storage subcircuit and configured to provide a periodic frequency for the counter circuit.

[0019] In some embodiments, the level conversion circuit includes: a fault detection subcircuit connected to the level conversion circuit, and configured to control the level conversion circuit to power off when the level conversion circuit fails.

[0020] In some embodiments, the fault detection subcircuit includes: a power supply detection subcircuit, which is connected to the level conversion circuit, and is used to detect the power supply signal at the input or output end of the level conversion circuit, and control the level conversion circuit to power off when the power supply signal does not meet the preset power supply condition.

[0021] In some embodiments, the fault detection subcircuit also includes: a temperature detection subcircuit, connected to the level conversion circuit, for detecting a temperature signal of the level conversion circuit, and controlling the level conversion circuit to power off when the temperature signal is higher than a preset temperature threshold.

[0022] In some embodiments, the power supply detection subcircuit includes: a current detection subcircuit connected to the level conversion circuit, used to detect the current signals at the input and output ends of the level conversion circuit, and when the current signal exceeds a preset current threshold, determine that the current signal does not meet the preset power supply condition.

[0023] In some embodiments, the power supply detection subcircuit includes: a voltage detection subcircuit connected to the level conversion circuit, used to detect the voltage signals at the input and output ends of the level conversion circuit, and when the voltage signal is lower than a preset voltage threshold, determine that the voltage signal does not meet the preset power supply condition.

[0024] In some embodiments, the interface conversion circuit includes: a CAN transceiver sub-circuit connected to the level conversion circuit, and configured to send the second control signal to the level conversion circuit when receiving a wake-up signal.

[0025] In some embodiments, the interface conversion circuit includes: a LIN transceiver sub-circuit connected to the level conversion circuit, and configured to send the second control signal to the level conversion circuit when receiving a wake-up signal.

[0026] In some embodiments, the level conversion circuit is integrated with the interface conversion circuit.

[0027] In some embodiments, the counter circuit is integrated with the interface conversion circuit.

[0028] In order to achieve the above-mentioned purpose, an embodiment of the second aspect of the present invention proposes a power timing control method, which is used for the power timing control chip as described in the above-mentioned embodiment, and the power timing control chip includes a level conversion circuit and a power-off control circuit. The power timing control method includes: the level conversion circuit outputs a first voltage signal; when the level conversion circuit receives a first disable signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit according to the first voltage signal, and controls the level conversion circuit to power on according to the power-on control signal.

[0029] According to the power timing control method of the embodiment of the present invention, by monitoring the first voltage signal of the level conversion circuit, when the level conversion circuit receives the first disable signal, the first voltage signal begins to decrease, the power-off control circuit continuously monitors the first voltage signal, and after determining that the controller is successfully powered off according to the first voltage signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit, so that the level conversion circuit is powered on again to supply power to the controller, thereby achieving accurate control of the power-off timing and power-on timing of the controller, avoiding the problem of the controller entering an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller, achieving effective reset of the controller, and allowing the entire power timing control chip to start normally.

[0030] In order to achieve the above object, an embodiment of the third aspect of the present invention provides a chip, which includes: a power timing control chip as described in the above embodiment.

[0031] According to the chip of the embodiment of the present invention, by monitoring the first voltage signal of the level conversion circuit, when the level conversion circuit receives the first disable signal, the first voltage signal begins to decrease, the power-off control circuit continuously monitors the first voltage signal, and after determining that the controller is successfully powered off according to the first voltage signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit, so that the level conversion circuit is powered on again to supply power to the controller, thereby achieving accurate control of the power-off timing and power-on timing of the controller, avoiding the problem of the controller entering an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller, achieving effective reset of the controller, and allowing the entire power timing control chip to start normally.

[0032] In order to achieve the above-mentioned purpose, an embodiment of the fourth aspect of the present invention proposes a non-temporary computer-readable storage medium, on which a power timing control program is stored. When the power timing control program is executed by a processor, the power timing control method described in the above-mentioned embodiment is implemented.

[0033] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0035] Figure 1 It is a schematic diagram of abnormal power-on timing of a controller according to the related art;

[0036] Figure 2 is a structural block diagram of a power timing control chip according to an embodiment of the present invention;

[0037] Figure 3 is a structural block diagram of a power timing control chip according to a specific embodiment of the present invention;

[0038] Figure 4 is a schematic diagram of the internal structure of a power-off control circuit according to an embodiment of the present invention;

[0039] Figure 5 is a schematic diagram of a controller power-on timing sequence according to an embodiment of the present invention;

[0040] Figure 6 is a schematic diagram of an application scenario of a power timing control chip according to an embodiment of the present invention;

[0041] Figure 7 is a flow chart of a power sequence control method according to an embodiment of the present invention;

[0042] Figure 8 is a structural block diagram of a chip according to an embodiment of the present invention.

[0043] Reference numerals: power timing control chip 1;

[0044] Level conversion circuit 11; power-off control circuit 12; counter circuit 13; controller 14; interface conversion circuit 15;

[0045] Fault detection subcircuit 111;

[0046] Comparison subcircuit 121; output subcircuit 122;

[0047] Storage subcircuit 131;

[0048] Chip 2. DETAILED DESCRIPTION

[0049] Embodiments of the present invention are described in detail below. The embodiments described with reference to the accompanying drawings are exemplary. Embodiments of the present invention are described in detail below.

[0050] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the abnormal power-on timing of the controller in the related art. The working state of the controller is abnormal, the level conversion circuit receives the power-off signal at time t1, and the output voltage begins to drop. If the output voltage does not drop below the predetermined voltage threshold of the controller, the controller fails to power off successfully. Some redundant circuits in the vehicle system may send an enable signal to the level conversion circuit at time t2, and the output voltage signal begins to rise on this basis, causing the controller to work in a "dead" state.

[0051] Therefore, the power timing control chip of the embodiment of the present invention adds a power-off control circuit to provide a power-off control signal. When the power-off signal and the enable signal appear at the same time, the level conversion circuit preferentially powers off according to the power-off signal. After the power-off is successful, the enable signal is valid, thereby preventing the controller from entering an unknown operating state, optimizing the startup efficiency of the controller, and realizing effective reset of the vehicle-mounted system, so that the entire system program can start normally.

[0052] Combine the following Figure 2-Figure 7 A power timing control chip 1 according to an embodiment of the present invention is described.

[0053] like Figure 2 As shown, the power timing control chip 1 of the embodiment of the present invention includes: a level conversion circuit 11 and a power-off control circuit 12, wherein:

[0054] The level conversion circuit 11 is used to output a first voltage signal; the power-off control circuit 12 is connected to the level conversion circuit 11, and is used to output a power-on control signal to the level conversion circuit 11 according to the first voltage signal when the level conversion circuit 11 receives a first disable signal, and control the level conversion circuit 11 to power on according to the power-on control signal.

[0055] In an embodiment, Figure 3 , which is a block diagram of a power timing control chip according to a specific embodiment of the present invention. The level conversion circuit 11 is electrically connected to the power supply, and the power-off control circuit 12 is electrically connected to the controller 14. When the level conversion circuit 11 receives a power signal, it converts the power signal into a first voltage signal, and outputs the first voltage signal to the power input terminal of the controller 14 through the power output terminal, thereby supplying power to the controller 14.

[0056] When a fault occurs in the controller 14, the level conversion circuit 11 receives a first disable signal, and the first voltage signal output to the controller 14 begins to decrease. At this time, the power-off control circuit 12 continuously monitors the first voltage signal, and determines whether the controller 14 is successfully powered off based on the relationship between the first voltage signal and the preset value.

[0057] After the controller 14 is powered off successfully, the power-off control circuit 12 outputs a power-on control signal to the level conversion circuit 11 to control the level conversion circuit 11 to power on according to the power-on control signal. After receiving the power-on control signal, the level conversion circuit 11 starts to work normally, and the first voltage signal starts to rise, so that the controller 14 is powered on again. By setting the power-off control circuit 12, the power-off timing and power-on timing of the controller 14 can be accurately controlled, thereby avoiding the problem of the controller 14 entering an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the timing logic of the chip.

[0058] According to the power timing control chip 1 of the embodiment of the present invention, a power-off control circuit 12 is set to monitor the first voltage signal of the level conversion circuit 11. When the level conversion circuit 11 receives the first disable signal, the first voltage signal begins to decrease. The power-off control circuit 12 continuously monitors the first voltage signal, and after determining that the controller 14 is successfully powered off according to the first voltage signal, the power-off control circuit 12 outputs a power-on control signal to the level conversion circuit 11, so that the level conversion circuit 11 is powered on again to supply power to the controller 14, thereby achieving accurate control of the power-off timing and power-on timing of the controller 14, avoiding the problem that the controller 14 enters an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller 14, achieving effective reset of the controller 14, and allowing the entire power timing control chip 1 to start normally.

[0059] In some embodiments, Figure 4 FIG. 1 is a schematic diagram of the internal structure of a power-off control circuit according to an embodiment of the present invention. The power-off control circuit 12 comprises: a comparison subcircuit 121 and an output subcircuit 122, wherein the output subcircuit 122 is a logic "AND" unit including two channels.

[0060] The comparison subcircuit 121 is connected to the level conversion circuit 11, and is used to compare the first voltage signal with the preset voltage threshold; the output subcircuit 122 is connected to the output end of the comparison subcircuit 121, and is used to output a power-on control signal to the level conversion circuit 11 according to the comparison result of the comparison subcircuit 121.

[0061] In the embodiment, when the level conversion circuit 11 receives the first disable signal, the comparison subcircuit 121 collects the first voltage signal of the level conversion circuit 11 in real time, and compares the magnitude relationship between the first voltage signal and the preset voltage threshold. When the first voltage signal is less than the preset voltage threshold, it is considered that the controller 14 is powered off successfully, and when the first voltage signal is not lower than the preset voltage threshold, it is considered that the controller 14 is not powered off successfully. When the controller 14 is powered off successfully, the comparison subcircuit 121 outputs the comparison result to one of the channels of the output subcircuit 122 through the output terminal. After the output subcircuit 122 obtains the comparison result, it outputs a power-on control signal to the level conversion circuit 11 according to the comparison result of the comparison subcircuit 121. After the level conversion circuit 11 receives the power-on control signal, it starts to work normally, and the first voltage signal starts to rise, so that the controller 14 is powered on again. By setting the comparison subcircuit 121, it is possible to accurately determine whether the controller 14 is powered off successfully, and after the controller 14 is powered off successfully, the output subcircuit 122 outputs the power-on control signal to the level conversion circuit 11, so as to achieve accurate control of the power-off and power-on timing of the level conversion circuit 11.

[0062] In some embodiments, Figure 3 The power timing control chip 1 further includes: an interface conversion circuit 15, which is connected to the level conversion circuit 11 and is used to send a second control signal to the level conversion circuit 11 when receiving a wake-up signal.

[0063] In the embodiment, the data information interaction end of the interface conversion circuit 15 is electrically connected to the data information interaction end of the controller 14; the interface conversion circuit 15 is bidirectionally connected to the level conversion circuit 11, and the power output end of the level conversion circuit 11 sends a second voltage signal to the power input end of the interface conversion circuit 15 to power the interface conversion circuit 15. The interface conversion circuit 15 is used for communication and information exchange of the entire system, and monitors the wake-up signal at the same time. When the wake-up signal is received, the output end of the interface conversion circuit 15 sends a second control signal to the input end of the level conversion circuit 11, and the level conversion circuit 11 continues to send the first voltage signal to the controller 14 according to the second control signal to power the controller 14, thereby realizing accurate control of the power-off and power-on timing of the level conversion circuit 11.

[0064] In some embodiments, the output subcircuit 122 is specifically configured to output a power-on control signal to the level conversion circuit 11 when the first voltage signal is less than a preset voltage threshold and the second control signal is received.

[0065] In the embodiment, after waking up, the interface conversion circuit 15 sends a second control signal to the input end of the level conversion circuit 11. When the first voltage signal is less than the preset voltage threshold and the second control signal is received, the output subcircuit 122 considers that the controller 14 has been powered off successfully, and then outputs a power-on control signal to the level conversion circuit 11. After receiving the power-on control signal, the level conversion circuit 11 starts to work normally, and the first voltage signal starts to rise, so that the controller 14 is powered on again. In other words, once the level conversion circuit 11 receives the first disable signal, no matter when the second control signal appears, the power-off control circuit 12 can ensure that the first voltage signal is lower than the preset voltage threshold, that is, after the power-off is successful, and then output the power-on control signal according to the second control signal, so as to realize accurate control of the power-off and power-on timing of the level conversion circuit 11, so that the controller 14 can achieve effective power-off and power-on reset.

[0066] like Figure 5 As shown, it is a schematic diagram of the controller power-on timing of an embodiment of the present invention. When the level conversion circuit 11 receives the first disable signal at time t3, the first voltage signal output to the controller 14 begins to decrease, and the first voltage signal is equal to the preset voltage threshold at time t4. After time t4, the first voltage signal is less than the preset voltage threshold, and it is considered that the controller 14 is powered off successfully, and when the output sub-circuit 122 receives the second control signal, it outputs a power-on control signal to the level conversion circuit 11, so as to realize accurate control of the power-off and power-on timing of the level conversion circuit 11.

[0067] In some embodiments, Figure 3 As shown, the power timing control chip 1 also includes: a counter circuit 13, the counter circuit 13 is respectively connected to the level conversion circuit 11 and the controller 14, and is used to determine that when the controller 14 is not faulty, send a third control signal to the level conversion circuit 11, and the third control signal is used to enable the level conversion circuit 11 to output a power supply voltage signal, wherein the power supply voltage signal at least includes a first voltage signal, wherein when the third control signal is an enable signal, it is used to ensure the normal operation of the entire power timing control chip 1, so that the controller 14 can output the control signal normally, and the counter circuit 13 outputs the enable signal of the third control signal to the level conversion circuit 11, which can ensure that the level conversion circuit 11 normally outputs the power supply voltage signal, such as the first voltage signal or the second voltage signal.

[0068] In the embodiment, the input end of the counter circuit 13 is connected to the output end of the controller 14, and is used to receive a control signal of the controller 14, and judge the fault state of the controller 14 according to the control signal, so as to output a corresponding trigger source signal, that is, an enable signal or a disable signal; the counter circuit 13 is bidirectionally connected to the level conversion circuit 11, and the power output end of the level conversion circuit 11 sends a third voltage signal to the power input end of the counter circuit 13 to power the counter circuit 13; when it is determined that the controller 14 is not faulty, the output end of the counter circuit 13 continuously sends a third control signal to the input end of the level conversion circuit 11, wherein the third control signal is an enable signal, which ensures that the level conversion circuit 11 normally outputs a power supply voltage signal, such as a first voltage signal or a second voltage signal, so that the controller 14 can normally output a control signal, thereby ensuring the normal operation of the entire power timing control chip 1.

[0069] In some embodiments, the counter circuit 13 is further configured to send a first disable signal to the level conversion circuit 11 when determining that the controller 14 fails.

[0070] In the embodiment, when it is determined that the controller 14 fails, the output end of the counter circuit 13 sends a first disable signal to the input end of the level conversion circuit 11. After the level conversion circuit 11 receives the first disable signal, the first voltage signal sent to the controller 14 begins to decrease. When it gradually decreases to below the preset voltage threshold, the controller 14 is powered off successfully. By setting the counter circuit 13, real-time monitoring of the working state of the controller 14 is achieved, and the fault state of the controller 14 can be responded to in time. According to the fault state of the controller 14, it is determined whether the level conversion circuit 11 supplies power to the controller 14, thereby achieving accurate control of the power-off and power-on timing of the controller 14.

[0071] In some embodiments, Figure 3 As shown, the counter circuit 13 includes: a storage subcircuit 131, connected to the level conversion circuit 11, and used to store the cycle time of the counter circuit.

[0072] In the embodiment, the counter circuit 13 includes an independent storage subcircuit 131 , and the storage subcircuit 131 internally stores the adjustable cycle time of the counter circuit 13 , and the cycle time of the counter circuit 13 can be adjusted according to actual requirements.

[0073] In some embodiments, the counter circuit 13 is further used to: determine that the controller 14 is not faulty if a control signal from the controller 14 is received within a cycle time; and determine that the controller 14 is faulty if no control signal from the controller 14 is received within a cycle time.

[0074] In the embodiment, if the counter circuit 13 receives a control signal from the controller 14 during the cycle time, it is determined that the controller 14 is faulty; if the counter circuit 13 does not receive a control signal from the controller 14 during the cycle time, it is determined that the controller 14 is not faulty. At this time, the power timing control chip 1 may be affected by some strong electromagnetic interference pulses, causing the program to "run away".

[0075] In some embodiments, the counter circuit 13 further includes: a clock subcircuit connected to the storage subcircuit and configured to provide a periodic frequency for the counter circuit 13 .

[0076] In an embodiment, the counter circuit 13 has an independent clock subcircuit, which is different from the clock of the controller 14 and provides a periodic frequency for the counter circuit 13 , thereby providing a reliable timing period for accurate counting of the counter circuit 13 .

[0077] In some embodiments, Figure 3 The level conversion circuit 11 further includes a fault detection subcircuit 111 connected to the level conversion circuit 11 and used to control the level conversion circuit 11 to power off when the level conversion circuit 11 fails.

[0078] In the embodiment, in addition to configuring power output for other circuits, the level conversion circuit 11 is also provided with a fault detection subcircuit 111 responsible for monitoring the state of the power supply of the entire vehicle system. When the fault detection subcircuit 111 detects a fault in the level conversion circuit 11, the fault detection subcircuit 111 controls the level conversion circuit 11 to enter a power supply disconnection mode to control the power-off of the level conversion circuit 11. By providing the fault detection subcircuit 111 in the level conversion circuit 11 to monitor the operation state of the communication system in real time, the protection function of the communication system can be realized.

[0079] In some embodiments, the fault detection subcircuit 111 includes: a power supply detection subcircuit, connected to the level conversion circuit 11, for detecting the power supply signal at the input or output end of the level conversion circuit 11, and controlling the level conversion circuit 11 to power off when the power supply signal does not meet the preset power supply condition; a temperature detection subcircuit, connected to the level conversion circuit 11, for detecting the working temperature signal of the level conversion circuit, and controlling the level conversion circuit to power off when the working temperature signal is higher than the preset temperature threshold.

[0080] In an embodiment, the power supply detection subcircuit detects a power supply signal, such as a current signal or a voltage signal, at a communication input terminal or a power signal output terminal of the level conversion circuit 11, and when the power supply signal does not meet a preset power supply condition, controls the level conversion circuit 11 to enter a power supply disconnection mode to control the level conversion circuit 11 to power off.

[0081] The temperature detection subcircuit detects the temperature signal of the level conversion circuit 11 in real time, and when the temperature signal exceeds a preset temperature threshold, controls the level conversion circuit 11 to enter a power-off mode to control the level conversion circuit 11 to power off. By setting the power supply detection subcircuit and the temperature detection subcircuit to monitor the operating status of the communication system in real time, the protection function of the communication system can be realized.

[0082] In some embodiments, the power supply detection subcircuit includes: a current detection subcircuit, connected to the level conversion circuit 11, for detecting the current signal at the input and output ends of the level conversion circuit 11, and when the current signal exceeds a preset current threshold, determining that the current signal does not meet the preset power supply condition.

[0083] In an embodiment, the current detection subcircuit detects the current signal at the communication input terminal or the power signal output terminal of the level conversion circuit 11 in real time, and when the current signal exceeds a preset current threshold, it is considered that an overcurrent phenomenon occurs in the circuit, and it is determined that the current signal does not meet the preset power supply conditions. By setting the current detection subcircuit to monitor the operating status of the communication system in real time, the protection function of the communication system can be realized.

[0084] In some embodiments, the power supply detection subcircuit includes: a voltage detection subcircuit, connected to the level conversion circuit 11, used to detect the voltage signals at the input and output ends of the level conversion circuit, and when the voltage signal is lower than a preset voltage threshold, determine that the voltage signal does not meet the preset power supply condition.

[0085] In an embodiment, the voltage detection subcircuit detects the voltage signal at the communication input terminal or the power signal output terminal of the level conversion circuit 11 in real time, and when the voltage signal is lower than a preset voltage threshold, it is considered that the circuit has an overvoltage phenomenon, and it is determined that the voltage signal does not meet the preset power supply conditions. By setting the voltage detection subcircuit to monitor the operating status of the communication system in real time, the protection function of the communication system can be realized.

[0086] In some embodiments, the interface conversion circuit 15 includes: a CAN transceiver sub-circuit, which is connected to the level conversion circuit 11 and is used to send a second control signal to the level conversion circuit when receiving a wake-up signal.

[0087] In an embodiment, Figure 6 The power timing control chip 1 can be applied to an SBC (System Basis Chip) integrated chip, and the interface conversion circuit 15 includes a CAN transceiver subcircuit, which sends a second control signal to the level conversion circuit when receiving a wake-up signal.

[0088] In some embodiments, the interface conversion circuit 15 includes: a LIN transceiver sub-circuit, which is connected to the level conversion circuit 11 and is used to send a second control signal to the level conversion circuit when receiving the wake-up signal.

[0089] In an embodiment, Figure 6 The power timing control chip 1 can be applied to an SBC (System Basis Chip) integrated chip, and the interface conversion circuit 15 includes a LIN transceiver subcircuit, which sends a second control signal to the level conversion circuit when receiving a wake-up signal.

[0090] In some embodiments, Figure 6 As shown, the level conversion circuit 11, the power-off control circuit 12, the counter circuit 13 and the interface conversion circuit 15 are integrated.

[0091] In the embodiment, the level conversion circuit 11, the power-off control circuit 12, the counter circuit 13 and the interface conversion circuit 15, such as the CAN / LIN transceiver sub-circuit chip, are integrated at a relatively low cost, so that the power supply of the controller 14 can be cut off in time when the controller 14 fails, thereby achieving the same safety effect as the double protection architecture. The interface conversion circuit 15 of the integrated counter circuit 13, such as the SBC chip dedicated to the CAN / LIN transceiver sub-circuit, achieves multiple monitoring effects on the working status of the controller 14 without increasing the number of components, thereby saving design costs, improving system reliability, and being beneficial to subsequent circuit integration.

[0092] According to the power timing control chip 1 of the embodiment of the present invention, a power-off control circuit 12 is set to monitor the first voltage signal of the level conversion circuit 11. When the level conversion circuit 11 receives the first disable signal, the first voltage signal begins to decrease. The power-off control circuit 12 continuously monitors the first voltage signal, and after determining that the controller 14 is successfully powered off according to the first voltage signal, the power-off control circuit 12 outputs a power-on control signal to the level conversion circuit 11, so that the level conversion circuit 11 is powered on again to supply power to the controller 14, thereby achieving accurate control of the power-off timing and power-on timing of the controller 14, avoiding the problem that the controller 14 enters an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller 14, achieving effective reset of the controller 14, and allowing the entire power timing control chip 1 to start normally.

[0093] Reference below Figure 7 The power sequence control method according to an embodiment of the present invention is described. The power sequence control method is used for the power sequence control chip 1 according to the above embodiment.

[0094] like Figure 7 As shown, the power sequence control method of the embodiment of the present invention at least includes step S1-step S2.

[0095] Step S1, outputting a first voltage signal.

[0096] In an embodiment, the level conversion circuit is electrically connected to the power supply, and the power-off control circuit is electrically connected to the controller. When the level conversion circuit receives a power signal, it converts the power signal into a first voltage signal, and outputs the first voltage signal to the power input terminal of the controller through the power output terminal to power the controller.

[0097] Step S2: when the level conversion circuit receives the first disable signal, output a power-on control signal to the level conversion circuit according to the first voltage signal, and control the level conversion circuit to power on according to the power-on control signal.

[0098] In an embodiment, when a controller fails, the level conversion circuit receives a first disable signal, and the first voltage signal output to the controller begins to decrease. At this time, the power-off control circuit continuously monitors the first voltage signal and determines whether the controller is successfully powered off based on the size relationship between the first voltage signal and a preset value.

[0099] After the controller is powered off successfully, the power-off control circuit outputs a power-on control signal to the level conversion circuit to control the level conversion circuit to power on according to the power-on control signal. After receiving the power-on control signal, the level conversion circuit starts to work normally, and the first voltage signal starts to rise, so that the controller is powered on again. By setting the power-off control circuit, the correctness of the power-off timing of the first voltage signal of the level conversion circuit and the effectiveness of the reset timing are guaranteed.

[0100] According to the power timing control method of the embodiment of the present invention, a power-off control circuit is set to monitor the first voltage signal of the level conversion circuit. When the level conversion circuit receives the first disable signal, the first voltage signal begins to decrease. The power-off control circuit continuously monitors the first voltage signal, and after determining that the controller is successfully powered off based on the first voltage signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit, so that the level conversion circuit is powered on again to supply power to the controller, thereby achieving accurate control of the power-off timing and power-on timing of the controller, avoiding the problem of the controller entering an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller, achieving effective reset of the controller, and allowing the entire power timing control chip to start normally.

[0101] In some embodiments, the power timing control chip further includes: a controller, and the method further includes: the level conversion circuit outputs a first voltage signal for powering the controller.

[0102] In some embodiments, the power timing control chip also includes: a counter circuit, and the method also includes: when it is determined that the controller is not faulty, sending a third control signal to the level conversion circuit, the third control signal is used to enable the level conversion circuit to output a power supply voltage signal, wherein the power supply voltage signal includes at least a first voltage signal.

[0103] In some embodiments, the method further includes: when it is determined that the controller fails, sending a first disable signal to the level conversion circuit.

[0104] In some embodiments, the counter circuit includes: a storage subcircuit, and the method further includes: the storage subcircuit is used to store the cycle time of the counter circuit.

[0105] In some embodiments, the method further includes: determining that the controller is not faulty when a control signal from the controller is received within a cycle time; and determining that the controller is faulty when a control signal from the controller is not received within a cycle time.

[0106] In some embodiments, the counter circuit further includes: a clock subcircuit, and the method further includes: the clock subcircuit is used to provide a periodic frequency for the counter circuit.

[0107] In some embodiments, the level conversion circuit includes: a fault detection subcircuit, and the method includes: when the level conversion circuit fails, the fault detection subcircuit controls the level conversion circuit to power off.

[0108] In some embodiments, the fault detection subcircuit includes: a power supply detection subcircuit, which controls the level conversion circuit to power off when the level conversion circuit fails, including: detecting the power supply signal at the input or output end of the level conversion circuit, and controlling the level conversion circuit to power off when the power supply signal does not meet the preset power supply condition.

[0109] In some embodiments, the fault detection subcircuit also includes: a temperature detection subcircuit, which controls the level conversion circuit to power off when the level conversion circuit fails, and also includes: detecting a temperature signal of the level conversion circuit, and controlling the level conversion circuit to power off when the temperature signal is higher than a preset temperature threshold.

[0110] In some embodiments, the power supply detection subcircuit includes: a current detection subcircuit, which detects the power supply signal at the input or output end of the level conversion circuit, and controls the level conversion circuit to power off when the power supply signal does not meet the preset power supply condition, including: detecting the current signal at the input and output ends of the level conversion circuit, and determining that the current signal does not meet the preset power supply condition when the current signal exceeds a preset current threshold.

[0111] In some embodiments, the power supply detection subcircuit includes: a voltage detection subcircuit, which detects the power supply signal at the input or output end of the level conversion circuit, and controls the level conversion circuit to power off when the power supply signal does not meet the preset power supply condition, including: detecting the voltage signal at the input and output ends of the level conversion circuit, and determining that the voltage signal does not meet the preset power supply condition when the voltage signal is lower than a preset voltage threshold.

[0112] According to the power timing control method of the embodiment of the present invention, a power-off control circuit is set to monitor the first voltage signal of the level conversion circuit. When the level conversion circuit receives the first disable signal, the first voltage signal begins to decrease. The power-off control circuit continuously monitors the first voltage signal, and after determining that the controller is successfully powered off based on the first voltage signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit, so that the level conversion circuit is powered on again to supply power to the controller, thereby achieving accurate control of the power-off timing and power-on timing of the controller, avoiding the problem of the controller entering an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller, achieving effective reset of the controller, and allowing the entire power timing control chip to start normally.

[0113] Reference below Figure 8 The chip 2 according to the embodiment of the present invention is described.

[0114] like Figure 8 As shown, the chip 2 of the embodiment of the present invention includes: the power timing control chip 1 as described in the above embodiment.

[0115] According to the chip 2 of the embodiment of the present invention, a power-off control circuit 12 is set to monitor the first voltage signal of the level conversion circuit 11. When the level conversion circuit 11 receives the first disable signal, the first voltage signal begins to decrease. The power-off control circuit 12 continues to monitor the first voltage signal, and after determining that the controller 14 is successfully powered off according to the first voltage signal, the power-off control circuit 12 outputs a power-on control signal to the level conversion circuit 11, so that the level conversion circuit 11 is powered on again to supply power to the controller 14, thereby achieving accurate control of the power-off timing and power-on timing of the controller 14, avoiding the problem that the controller 14 enters an unknown operating state due to inaccurate power-on or power-off logic, and ensuring the correctness of the chip timing logic, thereby optimizing the startup efficiency of the controller 14, achieving effective reset of the controller 14, and allowing the entire power timing control chip 1 to start normally.

[0116] The following describes a non-transitory computer-readable storage medium according to an embodiment of the present invention.

[0117] A power sequence control program is stored on a computer-readable storage medium in an embodiment of the present invention. When the power sequence control program is executed by a processor, the power sequence control method of the above embodiment is implemented.

[0118] In the description of this specification, the description with reference to the terms "one embodiment", "some embodiments", "illustrative embodiments", "examples", "specific examples", or "some examples" means that the specific features, structures, materials, or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example.

[0119] Although the embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

Claims

1. A power timing control chip, characterized in that: include: A level conversion circuit, used for outputting a first voltage signal; A power-off control circuit is connected to the level conversion circuit, and is used to output a power-on control signal to the level conversion circuit according to the first voltage signal when the level conversion circuit receives a first disable signal, and control the level conversion circuit to power on according to the power-on control signal.

2. The power timing control chip according to claim 1, characterized in that: The power-off control circuit comprises: A comparison sub-circuit, connected to the level conversion circuit, and used to compare the first voltage signal with a preset voltage threshold; The output sub-circuit is connected to the output end of the comparison sub-circuit, and is used to output the power-on control signal to the level conversion circuit according to the comparison result of the comparison sub-circuit.

3. The power timing control chip according to claim 2, characterized in that: Also includes: The interface conversion circuit is connected to the level conversion circuit and is used to send the second control signal to the level conversion circuit when receiving the wake-up signal.

4. The power timing control chip according to claim 3, characterized in that: The output subcircuit is specifically used for: When the first voltage signal is less than the preset voltage threshold and the second control signal is received, the power-on control signal is output to the level conversion circuit.

5. The power timing control chip according to claim 3, characterized in that: Also includes: A controller is connected to the level conversion circuit, and the level conversion circuit outputs the first voltage signal for powering the controller.

6. The power timing control chip according to claim 5, characterized in that: Also includes: A counter circuit is connected to the level conversion circuit and the controller respectively, and is used to send a third control signal to the level conversion circuit when determining that the controller is not faulty, wherein the third control signal is used to enable the level conversion circuit to output a power supply voltage signal, wherein the power supply voltage signal at least includes a first voltage signal.

7. The power timing control chip according to claim 6, characterized in that: The counter circuit is further used for: When it is determined that the controller fails, the first disable signal is sent to the level conversion circuit.

8. The power timing control chip according to claim 6, characterized in that: The counter circuit comprises: The storage sub-circuit is connected to the level conversion circuit and is used to store the cycle time of the counter circuit.

9. The power timing control chip according to claim 8, characterized in that: The counter circuit is further used for: When receiving a control signal from the controller within the cycle time, determining that the controller is not faulty; When no control signal from the controller is received within the cycle time, it is determined that the controller is faulty.

10. The power timing control chip according to claim 8, characterized in that: The counter circuit further comprises: The clock subcircuit is connected to the storage subcircuit and is used to provide a periodic frequency for the counter circuit.

11. The power timing control chip according to claim 1, characterized in that: The level conversion circuit comprises: The fault detection sub-circuit is connected to the level conversion circuit and is used to control the level conversion circuit to power off when the level conversion circuit fails.

12. The power timing control chip according to claim 11, characterized in that: The fault detection subcircuit comprises: The power supply detection subcircuit is connected to the level conversion circuit and is used to detect the power supply signal at the input end or the output end of the level conversion circuit, and control the level conversion circuit to power off when the power supply signal does not meet the preset power supply condition.

13. The power timing control chip according to claim 12, characterized in that: The fault detection subcircuit also includes: The temperature detection subcircuit is connected to the level conversion circuit and is used to detect a temperature signal of the level conversion circuit when the level conversion circuit is working, and control the level conversion circuit to power off when the temperature signal is higher than a preset temperature threshold.

14. The power timing control chip according to claim 12, characterized in that: The power supply detection subcircuit includes: The current detection subcircuit is connected to the level conversion circuit and is used to detect the current signals at the input and output ends of the level conversion circuit, and when the current signal exceeds a preset current threshold, determine that the current signal does not meet the preset power supply condition.

15. The power timing control chip according to claim 12 or 14, characterized in that: The power supply detection subcircuit includes: The voltage detection subcircuit is connected to the level conversion circuit and is used to detect the voltage signals at the input and output ends of the level conversion circuit, and when the voltage signal is lower than a preset voltage threshold, determine that the voltage signal does not meet the preset power supply condition.

16. The power timing control chip according to claim 3, characterized in that: The interface conversion circuit comprises: The CAN transceiver sub-circuit is connected to the level conversion circuit, and is used to send the second control signal to the level conversion circuit when receiving the wake-up signal.

17. The power timing control chip according to claim 3 or 16, characterized in that: The interface conversion circuit comprises: The LIN transceiver sub-circuit is connected to the level conversion circuit and is used to send the second control signal to the level conversion circuit when receiving the wake-up signal.

18. The power timing control chip according to claim 3, characterized in that: The level conversion circuit is integrated with the interface conversion circuit.

19. The power timing control chip according to claim 6, characterized in that: The counter circuit is integrated with the interface conversion circuit.

20. A power timing control method, characterized in that: Used for a power sequence control chip according to any one of claims 1 to 18, the power sequence control chip comprising a level conversion circuit and a power-off control circuit, and the power sequence control method comprising: The level conversion circuit outputs a first voltage signal; When the level conversion circuit receives the first disable signal, the power-off control circuit outputs a power-on control signal to the level conversion circuit according to the first voltage signal, and controls the level conversion circuit to power on according to the power-on control signal.

21. The power sequence control method according to claim 20, characterized in that: Outputting a power-on control signal to the level conversion circuit according to the first voltage signal includes: Comparing the first voltage signal with a preset voltage threshold; The power-on control signal is output to the level conversion circuit according to the comparison result of the comparison subcircuit.

22. The power sequence control method according to claim 21, characterized in that: The power timing control chip further includes: an interface conversion circuit, and the method further includes: When the interface conversion circuit receives the wake-up signal, the interface conversion circuit sends the second control signal to the level conversion circuit.

23. The power sequence control method according to claim 22, characterized in that: Outputting the power-on control signal to the level conversion circuit includes: When the first voltage signal is less than the preset voltage threshold and the second control signal is received, the power-on control signal is output to the level conversion circuit.

24. A chip, characterized in that: include: A power timing control chip as described in any one of claims 1 to 19.

25. A non-transitory computer-readable storage medium, characterized in that: The computer-readable storage medium stores a power sequence control program, and when the power sequence control program is executed by the processor, the power sequence control method according to any one of claims 20 to 23 is implemented.

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