Control device, sleep controller, control method, chip and electronic equipment

Abstract

The invention discloses a control device, a sleep controller, a control method, a chip and electronic equipment, the control device comprises a digital logic module, the sleep controller and at least one resource module, and the digital logic module comprises a control unit; wherein the control unit is configured to generate a first sleep signal according to a sleep instruction after receiving the sleep instruction, and send the first sleep signal to the sleep controller; and the sleep controller is configured to generate a second sleep signal according to the first sleep signal, and control the at least one resource module to be closed and reset the digital logic module when the second sleep signal is in a first level state, so that the control device enters a deep sleep state. Therefore, the power consumption of the chip in the deep sleep state can be reduced, and the cruising ability of the electronic equipment is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a control device, a sleep controller, a control method, a chip and an electronic device. Background Art

[0002] With the development of power electronics technology, electronic products have higher and higher requirements for low power consumption. Today's chip systems generally include multiple working modes, such as normal mode, high-speed mode, sleep mode, low power mode and ultra-low power mode. Considering the long battery life requirements of the device, when the chip is not working, it is usually required to quickly enter the ultra-low power mode to ensure that the device can standby for a long time.

[0003] However, as the scale of digital logic in chips becomes larger and larger, digital logic units manufactured with advanced processes have large leakage currents, which limits the ultra-low power operation of chips in deep sleep. In addition, how to achieve reliable sleep and reliable wake-up of chips in deep sleep has become an urgent problem to be solved. Summary of the invention

[0004] The present application proposes a control device, a sleep controller, a control method, a chip and an electronic device, which can reduce the power consumption of the chip in a deep sleep state and improve the endurance of the electronic device.

[0005] To achieve the above purpose, the technical solution of this application is implemented as follows:

[0006] In a first aspect, an embodiment of the present application provides a control device, the control device comprising a digital logic module, a sleep controller and at least one resource module, and the digital logic module comprises a control unit; wherein:

[0007] a control unit configured to, after receiving a sleep instruction, generate a first sleep signal according to the sleep instruction, and send the first sleep signal to the sleep controller;

[0008] The sleep controller is configured to generate a second sleep signal according to the first sleep signal, and when the second sleep signal is in a first level state, control at least one resource module to shut down and reset the digital logic module to make the control device enter a deep sleep state.

[0009] In a second aspect, an embodiment of the present application provides a sleep controller, which is applied to the control device of the first aspect; wherein:

[0010] A sleep controller is configured to receive a first sleep signal and an external reset signal, and generate a second sleep signal according to the first sleep signal and the external reset signal; wherein, when the second sleep signal is in a first level state, the control device is in a deep sleep state; and when the second sleep signal is in a second level state, the control device is in a normal working state.

[0011] In a third aspect, an embodiment of the present application provides a control method, which is applied to the control device as described in the first aspect, and the method includes:

[0012] After receiving the sleep instruction, the control unit generates a first sleep signal according to the sleep instruction, and sends the first sleep signal to the sleep controller;

[0013] The sleep controller generates a second sleep signal according to the first sleep signal, and when the second sleep signal is at a first level, controls at least one resource module in the control device to shut down and reset the digital logic module, so that the control device enters a deep sleep state.

[0014] In a fourth aspect, an embodiment of the present application provides a chip, which includes the control device as described in the first aspect.

[0015] In a fifth aspect, an embodiment of the present application provides an electronic device, which includes a display driver chip, and the display driver chip includes the control device as described in the first aspect.

[0016] A control device, a sleep controller, a control method, a chip and an electronic device provided in an embodiment of the present application, the control device includes a digital logic module, a sleep controller and at least one resource module, and the digital logic module includes a control unit. The control unit is configured to generate a first sleep signal according to the sleep instruction after receiving the sleep instruction, and send the first sleep signal to the sleep controller; the sleep controller is configured to generate a second sleep signal according to the first sleep signal, and when the second sleep signal is in a first level state, control at least one resource module to close and reset the digital logic module, so that the control device enters a deep sleep state. That is, after receiving the sleep instruction, the control unit can send the generated first sleep signal to the sleep controller, and the sleep controller generates a second sleep signal in a high level state according to the first sleep signal, which can reliably close at least one resource module (for example, close the reset module, the power module and the oscillator module, etc.), so that not only the digital logic module can be reset, but also the power supply and clock of the digital logic module can be turned off by turning off the power module and the oscillator module, so that the chip can enter an ultra-low power deep sleep mode; in addition, when the chip needs to wake up, the sleep controller can also control the second sleep signal to be in a low level state according to the received external reset signal, so that the chip can be reliably woken up in the deep sleep mode. This not only reduces the power consumption of the chip in deep sleep mode and improves the battery life of electronic devices, but also enables reliable sleep and reliable wake-up of the chip in deep sleep mode, improving the reliability of electronic devices. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 It is a schematic diagram of the circuit structure of a chip in deep sleep mode;

[0018] Figure 2 A schematic diagram of the structure of a control device provided in an embodiment of the present application Figure 1 ;

[0019] Figure 3 A schematic diagram of the structure of a control device provided in an embodiment of the present application Figure 2 ;

[0020] Figure 4 A schematic diagram of the structure of a control device provided in an embodiment of the present application Figure 3 ;

[0021] Figure 5 A schematic diagram of the structure of a sleep controller provided in an embodiment of the present application;

[0022] Figure 6 A schematic diagram of the composition structure of the first logic unit provided in an embodiment of the present application;

[0023] Figure 7 A schematic diagram of the composition structure of the first processing unit provided in an embodiment of the present application;

[0024] Figure 8 A schematic diagram of the structure of a logic operation unit provided in an embodiment of the present application;

[0025] Fig. 9 A schematic diagram of the composition structure of the second processing unit provided in an embodiment of the present application;

[0026] Fig.10 A schematic diagram of the composition structure of a chip provided in an embodiment of the present application;

[0027] Fig.11 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application;

[0028] Fig.12 A schematic diagram of the circuit structure of a chip provided in an embodiment of the present application;

[0029] Fig.13 A detailed structural diagram of a sleep controller provided in an embodiment of the present application;

[0030] Fig.14 A schematic diagram of a 1.8V power-on process operation analysis provided in an embodiment of the present application;

[0031] Fig.15 A schematic diagram of a simulation waveform of a sleep controller provided in an embodiment of the present application;

[0032] Fig.16 A flow chart of a control method provided in an embodiment of the present application. DETAILED DESCRIPTION

[0033] In order to enable a more detailed understanding of the features and technical contents of the embodiments of the present application, the implementation of the embodiments of the present application is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present application.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application.

[0035] It should also be noted that the terms "first\second\third" involved in the embodiments of the present application are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present application described here can be implemented in an order other than that illustrated or described here.

[0036] It should also be noted that in the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it can be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments, and may be combined with each other without conflict.

[0037] To facilitate understanding of the technical solutions of the embodiments of the present application, the relevant technologies of the embodiments of the present application are described below. The following related technologies can be arbitrarily combined with the technical solutions of the embodiments of the present application as optional solutions, and they all belong to the protection scope of the embodiments of the present application.

[0038] Figure 1 This is a schematic diagram of the circuit structure of a chip in deep sleep mode. Figure 1 As shown, the chip 100 may include a low dropout regulator (LDO) module 101, an oscillator (OSC) module 102, a power on reset (POR) module 103, a general purpose input / output port (GPIO) detection module 104 and a digital logic module 105. Among them, the chip 100 may include two power domains: a first power domain U1 and a second power domain U2. Here, the first power domain U1 represents the 1.8V power domain where the LDO module 101, the OSC module 102, the POR module 103 and the GPIO detection module 104 are located, and the second power domain U2 represents the 1.2V power domain where the digital logic module 105 is located.

[0039] It should be noted that in Figure 1 In the figure, the LDO module 101 can also be called a low-difference linear regulator or a low-dropout regulator. It is a type of linear DC regulator and is used to provide a stable DC voltage power supply, such as a 1.2V power supply, to the digital logic module 105. The OSC module 102 can also be called a "crystal oscillator", which can generate a stable high-frequency electrical signal and is used to provide a clock signal CLK to the digital logic module 105. The POR module 103 means that when the power supply voltage gradually rises from low to high, if the power supply voltage reaches the threshold voltage, the POR module 103 will release an internal reset signal and the state machine will start to initialize the device. Before the initialization is completed, the device will ignore external signals to ensure stable operation of the system. That is, the POR module 103 can provide an internal reset signal RESET_IN to the digital logic module 105.

[0040] In addition, Figure 1In the embodiment, the digital logic module 105 includes a microcontroller unit (MCU) module 106. The MCU module 106 can also be referred to as MCU or single-chip microcomputer, which appropriately reduces the main frequency and specifications of the central processing unit (CPU), and integrates multiple functional modules and interfaces such as memory, timer, analog to digital (AD) conversion, clock, input / output (I / O) port and serial communication on a single chip to realize the terminal control function, and has the advantages of high performance, low power consumption, programmability, high flexibility, etc.

[0041] It should also be noted that after receiving the sleep instruction, the MCU module 106 will shut down most of the modules inside the digital logic module 105, and switch the OSC module 102 to the low-frequency mode, and then switch the LDO module 101 to the low-power mode, and the entire chip enters deep sleep. The wake-up process can be awakened by the external reset signal RESET received by the POR module 103 or the level signal detected by the GPIO detection module 104, and then the OSC module 102 switches to the normal power supply mode, the LDO module 101 switches to the high-frequency mode, and then other power-consuming modules are turned on one after another, and the chip works normally.

[0042] That is to say, in the traditional chip architecture, the way for the chip to enter the deep sleep state can be: after the MCU controls the digital logic module to shut down most of the power-consuming modules, the MCU uses a low-frequency clock to run at low power consumption, and then selects the digital logic power supply as a low-power LDO. In order to wake up the chip, the MCU can monitor the changes in external signals through the GPIO detection module and wait for the chip to be woken up. However, as the digital logic scale of the chip becomes larger and larger, for metal-oxide-semiconductor field-effect transistors (MOSFET or MOS for short), such as low-voltage NMOS and PMOS, there is a large leakage current under advanced processes, which limits the ultra-low power consumption of the chip in deep sleep. For portable devices such as mobile phones and notebooks, long battery life is generally required, so it is important to achieve a deep sleep mode with ultra-low power consumption of the chip.

[0043] In the traditional chip architecture, since the digital logic power supply and clock are always present, it is relatively simple for the MCU to control the chip to enter deep sleep and wake up from deep sleep. However, there are still some defects here, such as the following two problems: The first problem is that the digital logic module manufactured by advanced technology has a large leakage current. In particular, the leakage current is high under the fast-fast (Fast N Fast P, FF) process corner. If the digital logic module does not perform power and ground switch control (power gating), the static leakage current of the larger chip itself is very high. For example, in a 55nm high-voltage process, a 1.2V inverter has a leakage current of nanoamperes, and the leakage current is at the milliampere level for a scale of millions of gates. The second problem is how to achieve reliable sleep and reliable wake-up in the deep sleep mode of the chip. When the MCU of the chip sends a sleep signal to the analog controller, the analog controller needs to recognize the sleep signal before the digital logic power of the chip is powered off. After that, before resetting the digital logic module, it is also necessary to lock the sleep signal to turn off the digital logic power, and the sleep signal is stable until the digital logic power is turned off. Simply put, the display driver chip in a portable device consumes high power in deep sleep state, resulting in short battery life of the device.

[0044] Based on this, the embodiment of the present application provides a control device, a sleep controller, a chip and an electronic device, wherein the control device includes a digital logic module, a sleep controller and at least one resource module, and the digital logic module includes a control unit. After receiving the sleep instruction, the control unit can send the generated first sleep signal to the sleep controller, and the sleep controller generates a second sleep signal in a high level state according to the first sleep signal, and can reliably shut down at least one resource module (for example, shut down a reset module, a power module and an oscillator module, etc.), so that not only can the digital logic module be reset, but also the power supply and clock of the digital logic module can be shut down by shutting down the power module and the oscillator module, so that the chip can enter an ultra-low power deep sleep mode; in addition, when the chip needs to wake up, the sleep controller can also control the second sleep signal to be in a low level state according to the received external reset signal, so that the chip can be reliably awakened in the deep sleep mode. In this way, not only can the power consumption of the chip in the deep sleep state be reduced, and the endurance of the electronic device be improved; but also the reliable sleep and reliable wake-up of the chip in the deep sleep mode can be realized, and the reliability of the electronic device is improved.

[0045] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0046] In one embodiment of the present application, Figure 2 A schematic diagram of the structure of a control device provided in an embodiment of the present application Figure 1 .like Figure 2As shown, the control device 200 may include a digital logic module 201, a sleep controller 202 and at least one resource module 203, and the digital logic module 201 may include a control unit 204; wherein:

[0047] The control unit 204 is configured to generate a first sleep signal according to the sleep instruction after receiving the sleep instruction, and send the first sleep signal to the sleep controller 202;

[0048] The sleep controller 202 is configured to generate a second sleep signal according to the first sleep signal, and when the second sleep signal is at a first level, control at least one resource module 203 to shut down and reset the digital logic module 201, so that the control device 200 enters a deep sleep state.

[0049] It should be noted that in the embodiment of the present application, the control unit 204 may be an MCU, which can receive a sleep instruction sent by an external host, and generate a first sleep signal (represented by DSTB_IN) according to the sleep instruction, and then send the first sleep signal DSTB_IN to the sleep controller 202 through the digital logic module 201. In addition, after the control unit 204 receives the sleep instruction, it can also control at least some modules in the digital logic module 201 to shut down, so as not only to reduce power consumption, but also to shut down at least some modules in sequence according to the working sequence, and to avoid abnormal detection, such as display abnormality caused by sudden power failure. Among them, at least some modules here may refer to most modules in the digital logic module 201, such as the clock inside the digital logic module 201, other control modules, etc.

[0050] It should also be noted that in the embodiment of the present application, after receiving the first sleep signal DSTB_IN, the sleep controller 202 can generate a second sleep signal DSTB_OUT and send it to at least one resource module 203, so as to control the at least one resource module 203 to shut down and reset the digital logic module 201, so that the control device 200 enters an ultra-low power consumption deep sleep state.

[0051] In an embodiment of the present application, for the first sleep signal DSTB_IN, after the control unit 204 receives the sleep instruction, the first sleep signal DSTB_IN generated at this time is in a first level state; after the digital logic module 201 is reset, the first sleep signal DSTB_IN is switched from the first level state to the second level state. Among them, the first level state can be a high level state, and the second level state can be a low level state. That is to say, in an embodiment of the present application, the first sleep signal DSTB_IN can be a positive pulse signal with a preset pulse width. Here, "positive" is used to characterize that the pulse is in a high level state.

[0052] In addition, in the embodiment of the present application, the first level state can be a high level state, and the second level state can be a low level state. In this way, for the sleep controller 202, after receiving the first sleep signal DSTB_IN, the generated second sleep signal DSTB_OUT is in a high level state; and before resetting the digital logic module 201, the sleep controller 202 will lock the second sleep signal DSTB_OUT in a high level state and turn off at least one resource module 203, so that the power supply and clock of the digital logic module 201 are turned off, and the second sleep signal DSTB_OUT remains in a high level state during the process, so that reliable sleep in a deep sleep state can be achieved.

[0053] In some embodiments, Figure 2 Based on the control device 200 shown, see Figure 3 , at least one resource module 203 may include a reset module 301, and the reset module 301 is connected to the reset terminal of the digital logic module 201; wherein:

[0054] The reset module 301 is configured to receive the second sleep signal DSTB_OUT sent by the sleep controller 202, and turn off when the second sleep signal DSTB_OUT is in the first level state, and send an internal reset signal RESET_IN to the digital logic module 201 to reset the digital logic module 201 and enter a low power consumption state.

[0055] It should be noted that, in the embodiment of the present application, the reset module 301 may refer to a module with a power-on reset function, or may refer to a module with a power-off reset function. If the reset module has a power-on reset function, when the power supply voltage gradually increases from low to high, if the power supply voltage reaches the threshold voltage, the reset module 301 will release the internal reset signal RESET_IN to reset the digital logic module 201; if the reset module has a power-off reset function, when the power supply voltage gradually decreases from high to low, if the power supply voltage drops to the threshold voltage, the reset module 301 will release the internal reset signal RESET_IN to reset the digital logic module 201.

[0056] It should be noted that, in the embodiment of the present application, the reset module 301 here may refer to the aforementioned POR module. After the sleep controller 202 receives the first sleep signal DSTB_IN, the sleep controller 202 may control the reset module 301 to be forced to shut down according to the second sleep signal DSTB_OUT, and then provide the internal reset signal RESET_IN to the digital logic module 201, so that the digital logic module 201 is reset and enters a low power consumption state, that is, the control device 200 enters a sleep state.

[0057] In some embodiments, see Figure 3 , at least one resource module 203 may also include an oscillator module 302 and a power supply module 303, and the oscillator module 302 is connected to the clock end of the digital logic module 201, and the power supply module 303 is connected to the power supply end of the digital logic module 201;

[0058] The oscillator module 302 is configured to receive the second sleep signal DSTB_OUT sent by the sleep controller 202, and to be turned off when the second sleep signal DSTB_OUT is in a first level state, so as to turn off the clock of the digital logic module 201;

[0059] The power module 303 is configured to receive the second sleep signal DSTB_OUT sent by the sleep controller 202 and to be turned off when the second sleep signal DSTB_OUT is in a first level state, so as to turn off the power supply of the digital logic module 201 .

[0060] It should also be noted that, in the embodiment of the present application, the oscillator module 302 may refer to the aforementioned OSC module, which is capable of generating a stable high-frequency electrical signal for providing a clock signal CLK to the digital logic module 201; the power supply module 303 may refer to the aforementioned LDO module, which is used to provide a stable DC voltage power supply, such as a 1.2V power supply, to the digital logic module 105.

[0061] In this way, after the sleep controller 202 receives the first sleep signal DSTB_IN, the sleep controller 202 can output the second sleep signal DSTB_OUT in a high level state, which can control the reset module 301, the oscillator module 302 and the power supply module 303 to be completely turned off, thereby turning off the power supply and clock of the digital logic module 201, so that the control device 200 enters a deep sleep state.

[0062] That is to say, in the embodiment of the present application, for the control device 200, after the control unit 204 receives the sleep instruction, at least part of the modules in the digital logic module 201 can be turned off first, and then the low power consumption control of the sleep controller 202 can be divided into two stages: sleep state and deep sleep state. Among them, after the sleep controller 202 receives the first sleep signal DSTB_IN, the second sleep signal DSTB_OUT output by the sleep controller 202 is sent to the reset module 301, and the internal reset signal RESET_IN output by the reset module 301 can reset the digital logic module 201 and enter the low power consumption state, that is, the control device 200 enters the sleep state; further, the second sleep signal DSTB_OUT output by the sleep controller 202 continues to maintain a high level state, and can also control the reset module 301, the oscillator module 302 and the power module 303 to be all turned off, so that the control device 200 enters the deep sleep state.

[0063] In addition, in the embodiments of the present application, Figure 3 As shown, the control device 200 may also include two power domains: a first power domain U1 and a second power domain U2. Here, the first power domain U1 represents the 1.8V power domain where at least one resource module such as the reset module 301, the oscillator module 302, the power module 303, and the sleep controller 202 are located, and the second power domain U2 represents the 1.2V power domain where the digital logic module 201 is located. The power supply of the 1.2V power domain may be provided by the 1.8V power domain.

[0064] That is to say, in the embodiment of the present application, for the power supply of the digital logic module 201, the required 1.2V power supply can be obtained by voltage conversion by the power module 303 in the 1.8V power domain. In this way, after the control unit 204 (such as MCU) receives the sleep instruction, by turning off the reset module 301, the oscillator module 302 and the power module 303, the control device 200 can enter an ultra-low power deep sleep state.

[0065] In some embodiments, the control unit 204 is also configured to, after receiving a sleep instruction, shut down at least part of the modules in the digital logic module 201, and generate a first sleep signal in a first level state according to the sleep instruction; and after the digital logic module 201 is reset, control the first sleep signal to be in a second level state, so that the first sleep signal received by the sleep controller 202 is a positive pulse signal whose pulse width meets a preset condition.

[0066] It should be noted that, in an embodiment of the present application, the first sleep signal DSTB_IN can be equivalent to a forward pulse signal. Among them, the pulse width satisfies the preset condition, which can also mean that the first sleep signal DSTB_IN is a forward pulse signal with a preset pulse width. Exemplarily, the preset pulse width can be at the microsecond (microsecond, us) level, for example, it can be set to a pulse width of more than 4us. That is to say, in an embodiment of the present application, the first sleep signal DSTB_IN can be a forward pulse signal with a pulse width of more than 4us.

[0067] In a specific implementation, after receiving the sleep instruction, the control unit 204 will shut down at least part of the modules in the digital logic module 201, and output a first sleep signal DSTB_IN in a high level state to the sleep controller 202. After the sleep controller 202 controls the reset module 301 to shut down and reset the digital logic module 201, the digital logic module 201 enters a low power consumption mode, and also forces the first sleep signal DSTB_IN to output a low level state, so that the first sleep signal DSTB_IN received by the sleep controller 202 is a positive pulse signal.

[0068] It can be understood that in the embodiment of the present application, in order to ensure reliable sleep in the deep sleep state, the state of the second sleep signal DSTB_OUT needs to be stable, so the sleep controller 202 needs to lock the high level state of the first sleep signal DSTB_IN, so that the output second sleep signal DSTB_OUT is always in a high level state. Figure 3 Based on the control device 200 shown, see Figure 4 , the sleep controller 202 may include a latch unit 205, wherein:

[0069] The sleep controller 202 is further configured to keep the second sleep signal at the first level through the latch unit 205 when the first sleep signal switches from the first level state to the second level state, so as to put the control device 200 into the deep sleep state.

[0070] In the embodiment of the present application, the latch unit 205 may also be referred to as a latch. Among them, the latch is a level-triggered storage unit that can change state under the action of a specific input level. Latching, as the name implies, is to temporarily store a signal to maintain a certain level state. Its working principle is that when the latch no longer latches data, the signal at the output end changes with the input signal; once the latch signal takes effect, the data is locked and the input signal has no effect. In other words, the latch can use the level to control the input of data. Once the latch signal takes effect, the data is locked and the input signal no longer affects the output.

[0071] It should also be noted that the difference between a latch and a trigger and a buffer is that when a latch latches data, the signal at the output end does not change with the input signal, just like the signal passing through a buffer. A trigger triggers a storage action under specific conditions, which is different from a latch. That is to say, in an embodiment of the present application, after resetting the digital logic module 201, the digital logic module 201 will force the first sleep signal DSTB_IN to output a low level state. At this time, the sleep controller 202 needs to lock the high level state of the first sleep signal DSTB_IN through the latch unit 205, so that the output second sleep signal DSTB_OUT is always in a high level state, that is, the state of the second sleep signal DSTB_OUT is stable, so that the control device 200 can achieve reliable sleep in a deep sleep state.

[0072] It can also be understood that in the embodiment of the present application, when the control device 200 needs to be awakened, it can be reliably awakened by an external reset signal RESET sent by an external host. In some embodiments, the sleep controller 202 is further configured to control the second sleep signal DSTB_OUT to be in a second level state according to the external reset signal when receiving the external reset signal RESET in a second level state, so as to wake up at least one resource module 203 and control the digital logic module 201 to start working.

[0073] In a possible implementation, the sleep controller 202 is further configured to keep the second sleep signal DSTB_OUT in the second level state through the latch unit 205 after waking up at least one resource module 203 and releasing the external reset signal RESET, so that the control device is in a normal working state.

[0074] It should be noted that, in the embodiment of the present application, the awakening of the deep sleep state can only be achieved by external reset RESET. Here, the first level state is a high level state, and the second level state is a low level state. Then when the external reset signal RESET is in a low level state, the output of the latch unit 205 can be in a low level state, and the other end input of the latch unit 205 is locked in a low level state, so that the second sleep signal DSTB_OUT output by the sleep controller 202 is in a low level state.

[0075] It should also be noted that, in the embodiment of the present application, for awakening the at least one resource module 203, first, the output of the power module 303 begins to be established, and the oscillator module 302 also begins to be established. After the output of the power module 303 is stable, the reset module 301 resets the digital logic module 201, so that the first sleep signal DSTB_IN is in a low level state, and the second sleep signal DSTB_OUT is in a low level state; thereafter, when the external reset signal RESET is released to a high level state, at this time, both inputs of the latch unit 205 are invalid, and the output of the latch unit 205 is locked to a low level state, so that the second sleep signal DSTB_OUT maintains a low level state. At this time, the state of the second sleep signal DSTB_OUT is also stable, thereby enabling the control device 200 to be reliably awakened in a deep sleep state, so that the control device 200 can work normally.

[0076] That is to say, in the embodiment of the present application, reliable sleep and reliable wake-up in the deep sleep state can be achieved according to the level state of the second sleep signal DSTB_OUT. Specifically, if the second sleep signal DSTB_OUT is in the first level state, then at least one resource module 203 can be controlled to be turned off so that the control device 200 enters the sleep state and the deep sleep state; if the second sleep signal DSTB_OUT is in the second level state, then the at least one resource module 203 can be awakened so that the control device 200 works normally. Moreover, in this process, the state of the second sleep signal DSTB_OUT is stable and unchanged through the effective locking of the latch unit 205, thereby achieving reliable sleep and reliable wake-up of the control device 200 in the deep sleep state.

[0077] The embodiment of the present application provides a control device, after the control unit receives the sleep instruction, the generated first sleep signal can be sent to the sleep controller, and the sleep controller generates a second sleep signal in a high level state according to the first sleep signal, which can reliably shut down at least one resource module (for example, shut down the reset module, the power module and the oscillator module, etc.), so that not only the digital logic module can be reset, but also the power supply and clock of the digital logic module can be shut down by shutting down the power module and the oscillator module, so that the control device can enter an ultra-low power deep sleep mode; in addition, when the wake-up work is required, the sleep controller can also control the second sleep signal to be in a low level state according to the received external reset signal, so that the control device can be reliably awakened in the deep sleep mode. In this way, not only can the reliable sleep and reliable awakening of the control device in the deep sleep mode be achieved, but also the power consumption of the control device in the deep sleep state can be reduced, and the endurance of the electronic device can be improved.

[0078] In another embodiment of the present application, the embodiment of the present application may further provide a sleep controller, which may be applied to the control device 200 as described in any one of the aforementioned embodiments.

[0079] In an embodiment of the present application, the sleep controller 202 can be configured to receive a first sleep signal DSTB_IN and an external reset signal RESET, and generate a second sleep signal DSTB_OUT according to the first sleep signal DSTB_IN and the external reset signal RESET; wherein, when the second sleep signal DSTB_OUT is in a first level state, the control device 200 is in a deep sleep state; when the second sleep signal DSTB_OUT is in a second level state, the control device 200 is in a normal working state.

[0080] The following is a description of the internal circuit structure of the sleep controller 202 in conjunction with the accompanying drawings.

[0081] Figure 5 The following is a schematic diagram of the structure of a sleep controller provided in an embodiment of the present application. Figure 5 As shown, the sleep controller 202 may include a first logic unit 501, a first processing unit 502, a second processing unit 503 and a logic operation unit 504, the output end of the first logic unit 501 is connected to the first processing unit 502 and the second processing unit 503 respectively, and the output end of the first processing unit 502 and the output end of the second processing unit 503 are connected to two input ends of the logic operation unit 504 correspondingly; wherein:

[0082] The first logic unit 501 is configured to receive the first sleep signal DSTB_IN, and perform a logic operation on the first sleep signal DSTB_IN to generate a first input signal IN1 and a second input signal IN1N;

[0083] The first processing unit 502 is configured to receive an external reset signal RESET and a first input signal IN1, and generate a first output signal P1OUT according to the external reset signal RESET and the first input signal IN1;

[0084] The second processing unit 503 is configured to receive the first input signal IN1, the second input signal IN1N, and the sleep feedback signal DSTB_FB, and generate a second output signal P2OUT according to the first input signal IN1, the second input signal IN1N, and the sleep feedback signal DSTB_FB;

[0085] The logic operation unit 504 is configured to receive the first output signal P1OUT and the second output signal P2OUT, perform a logic operation on the first output signal P1OUT and the second output signal P2OUT, and generate a second sleep signal DSTB_OUT.

[0086] Here, the sleep feedback signal DSTB_FB may be an intermediate process signal of the logic operation unit 504 , and the sleep feedback signal DSTB_FB and the second sleep signal DSTB_OUT are in an anti-phase relationship.

[0087] It should be noted that, in the embodiment of the present application, the sleep controller 202 may also include two power domains: a first power domain U1 and a second power domain U2. Here, the first power domain U1 represents the 1.8V power domain where the first processing unit 502, the second processing unit 503, and the logic operation unit 504 are located, and the second power domain U2 represents the 1.2V power domain where the first logic unit 501 is located.

[0088] It should also be noted that, in the embodiment of the present application, the first sleep signal DSTB_IN is obtained in the 1.2V power domain; therefore, the logic operation of the first sleep signal DSTB_IN is also performed in the 1.2V power domain.

[0089] In the embodiment of the present application, the first input signal IN1 and the second input signal IN1N are mutually inverted level signals. In a possible implementation, see Figure 6 , the first logic unit 501 may include a first inverter M1 and a second inverter M2, wherein:

[0090] The first inverter M1 is configured to receive the first sleep signal DSTB_IN and perform an inversion operation on the first sleep signal DSTB_IN to generate a second input signal IN1N;

[0091] The second inverter M2 is configured to receive the second input signal IN1N and perform an inversion operation on the second input signal IN1N to generate the first input signal IN1.

[0092] Here, the power supply of the first inverter M1 and the second inverter M2 both belong to the 1.2V power domain. Among them, whether it is the first inverter M1 or the second inverter M2, the inverter here can also be called a "non-gate", and its main function is to change the phase of the input signal (for example, invert or invert the input signal) and enhance the amplitude of the input signal. Exemplarily, the level of the input signal can be converted from a high level to a low level, or from a low level to a high level, and can be used as a buffer link in the signal processing circuit.

[0093] That is to say, in the embodiment of the present application, if the first sleep signal DSTB_IN is a positive pulse signal, then the first input signal IN1 is a positive pulse signal with enhanced amplitude, and the second input signal IN1N is an inverted pulse signal with enhanced amplitude; that is, the first sleep signal DSTB_IN has the same phase as the first input signal IN1, and the first sleep signal DSTB_IN has an opposite phase to the second input signal IN1N.

[0094] In some embodiments, see Figure 7 , the first processing unit 502 may include a second logic unit 521, a pulse processing unit 522, a first AND gate 523 and a latch unit 205, the first output end of the second logic unit 521 and the output end of the pulse processing unit 522 are connected to the two input ends of the first AND gate 523 correspondingly, the second output end of the second logic unit 521 and the output end of the first AND gate 523 are connected to the two input ends of the latch unit 205 correspondingly, wherein:

[0095] The second logic unit 521 is configured to receive an external reset signal RESET and perform a logic operation on the external reset signal to generate a first reset signal RST1 and a second reset signal RST2;

[0096] The pulse processing unit 522 is configured to receive the first input signal IN1, perform level conversion and pulse filtering on the first input signal IN1, and generate a third input signal IN2;

[0097] The first AND gate 523 is configured to receive the first reset signal RST1 and the third input signal IN2, and perform an AND operation on the first reset signal RST1 and the third input signal IN2 to generate a fourth input signal IN3;

[0098] The latch unit 205 is configured to receive the second reset signal RST2 and the fourth input signal IN3 , and generate a first output signal P1OUT according to the second reset signal RST2 and the fourth input signal IN3 .

[0099] In the embodiment of the present application, the second logic unit 521 may also be composed of two inverters. Figure 7 , the second logic unit 521 may include a third inverter M3 and a fourth inverter M4, wherein:

[0100] The third inverter M3 is configured to receive the external reset signal RESET and perform an inversion operation on the external reset signal RESET to generate a second reset signal RST2;

[0101] The fourth inverter M4 is configured to receive the second reset signal RST2 and perform an inversion operation on the second reset signal RST2 to generate the first reset signal RST1.

[0102] The external reset signal RESET has the same phase as the first reset signal RST1 and is opposite in phase to the second reset signal RST2. The external reset signal RESET is provided by an external host and is used to trigger a reset operation to wake up the control device 200 to start working.

[0103] Here, the power supply of the third inverter M3 and the fourth inverter M4 both belong to the 1.8V power domain. Whether it is the third inverter M3 or the fourth inverter M4, the inverter here can also be called a "non-gate", and its main function is to change the phase of the external reset signal RESET (for example, invert or invert the external reset signal RESET) and enhance the amplitude of the external reset signal RESET.

[0104] In the embodiment of the present application, the pulse processing unit 522 may be composed of a first level shift (LevelShift 1) unit and a pulse filtering unit. Figure 7 , the pulse processing unit 522 includes a first level conversion unit 5221 and a pulse filtering unit 5222, the output end of the first level conversion unit 5221 is connected to the input end of the pulse filtering unit 5222, wherein:

[0105] The first level conversion unit 5221 is configured to receive the first input signal IN1 and perform level conversion on the first input signal IN1 to obtain an intermediate input signal;

[0106] The pulse filtering unit 5222 is configured to receive the intermediate input signal and perform pulse filtering processing on the intermediate input signal whose pulse width does not meet the preset condition to obtain a third input signal IN2, and the pulse width of the third input signal IN2 meets the preset condition.

[0107] It should be noted that, in an embodiment of the present application, the first level conversion unit 5221 may be a circuit that implements a level conversion function, and its main function is to convert a signal of one level standard into a signal of another level standard to meet the communication requirements between different circuits or devices. Exemplarily, the first level conversion unit 5221 may convert a high level (such as 5V) into a low level (such as 3.3V), or convert a low level (such as 3.3V) into a high level (such as 5V). It may generally be composed of a level conversion chip that can convert the level of an input signal into an output signal that meets the requirements. In an embodiment of the present application, the first level conversion unit 5221 may be a circuit that converts 1.2V into 1.8V, so as to meet the requirements of a 1.8V power domain.

[0108] It should also be noted that, in the embodiment of the present application, the pulse filtering unit 5222 may be a narrow pulse filtering unit, which is used to identify pulses whose pulse widths meet preset conditions, for example, it may identify positive pulses greater than 4us. In one possible implementation, the pulse filtering unit 5222 may be a filtering circuit composed of a resistor R-capacitor C. In other words, the pulse filtering unit 5222 may filter out pulses whose pulse widths are less than 4us, and allow positive pulses whose pulse widths are greater than 4us to pass through, thereby filtering out narrower useless clutter and avoiding clutter interference. In the embodiment of the present application, the third input signal IN2 is still a positive pulse signal, and the pulse width is usually greater than 4us.

[0109] It should also be noted that, in the embodiment of the present application, for the first AND gate 523, if the first reset signal RST1 and the third input signal IN2 are both in the first level state, then the fourth input signal IN3 output by the first AND gate 523 is in the first level state; if at least one of the first reset signal RST1 and the third input signal IN2 is in the second level state, then the fourth input signal IN3 output by the first AND gate 523 is in the second level state. Here, the first level state can be a high level state (or referred to as "logic 1"), and the second level state can be a low level state (or referred to as "logic 0").

[0110] It should also be noted that, in the embodiment of the present application, for the latch unit 205, Figure 7As shown, the latch unit 205 may include a first transistor N1, a second transistor N2, a fifth inverter M5, a sixth inverter M6, and a seventh inverter M7. Among them, the control end of the first transistor N1 is used as the first input end of the latch unit 205 for receiving the second reset signal RST2, the control end of the second transistor N2 is used as the second input end of the latch unit 205 for receiving the fourth input signal IN3, the first end of the first transistor N1 is respectively connected to the input end of the fifth inverter M5 and the output end of the seventh inverter M7, the second end of the first transistor N1 is connected to the ground, the first end of the second transistor N2 is respectively connected to the input end of the seventh inverter M7 and the output end of the fifth inverter M5, the second end of the second transistor N2 is connected to the ground, the output end of the fifth inverter M5 is also connected to the input end of the sixth inverter M6, and the output end of the sixth inverter M6 is used as the output end of the latch unit 205 for outputting the first output signal P1OUT.

[0111] In the embodiment of the present application, for the latch unit 205, its working principle can be based on the input of the level control data. When there is no latch signal, the output of the latch unit 205 changes with the input signal, just like the signal passing through a buffer. Once the latch signal takes effect and the data is locked, the input signal no longer affects the output. This means that when there is a latch signal, the state of the input is saved to the output and does not change until the next latch signal arrives.

[0112] In a possible embodiment, the latch unit 205 is configured to lock the first output signal P1OUT to the first level state when the second reset signal RST2 is in the second level state and the fourth input signal IN3 is in the first level state; and to lock the first output signal P1OUT to the second level state when the second reset signal RST2 is in the first level state and the fourth input signal IN3 is in the second level state.

[0113] It should be noted that when the control device 200 enters the sleep state, the external reset signal RESET is in a high level state and the first sleep signal DSTB_IN is in a high level state. Then, after the external reset signal RESET is inverted by the third inverter M3, the obtained second reset signal RST2 is in a low level state; after the first sleep signal DSTB_IN is inverted by the first inverter M1 and the second inverter M2 connected in series, the obtained fourth input signal IN3 is still in a high level state. In this case, for the latch unit 205, if the first input end of the latch unit 205 receives a low level signal and the second input end of the latch unit 205 receives a high level signal, then the output end of the latch unit 205 outputs a high level signal, that is, the first output signal P1OUT is in a high level state, and the first output signal P1OUT is also locked to a high level state. At this time, both inputs of the latch unit 205 are invalid, and the first output signal P1OUT maintains a high level state, so as to reliably enter the ultra-low power deep sleep state.

[0114] It should also be noted that when the control device 200 enters the awake state, the external reset signal RESET is in a low level state and the first sleep signal DSTB_IN is in a low level state. Then, after the external reset signal RESET is inverted by the third inverter M3, the obtained second reset signal RST2 is in a high level state; after the first sleep signal DSTB_IN is inverted by the first inverter M1 and the second inverter M2 connected in series, the obtained fourth input signal IN3 is still in a low level state. In this case, for the latch unit 205, if the first input end of the latch unit 205 receives a high level signal and the second input end of the latch unit 205 receives a low level signal, then the output end of the latch unit 205 outputs a low level signal, that is, the first output signal P1OUT is in a low level state, and the first output signal P1OUT is also locked to a low level state. At this time, both inputs of the latch unit 205 are invalid, and the first output signal P1OUT maintains a low level state, so as to achieve reliable awakening of the control device 200.

[0115] In some embodiments, see Figure 8 , the logic operation unit 504 may include a first NAND gate 541 and a first NOT gate 542, the output end of the first processing unit 502 and the output end of the second processing unit 503 are connected to the two input ends of the first NAND gate 541 correspondingly, and the output end of the first NAND gate 541 is connected to the input end of the first NOT gate 542, wherein:

[0116] The first NAND gate 541 is configured to receive the first output signal P1OUT and the second output signal P2OUT, and perform a NAND operation on the first output signal P1OUT and the second output signal P2OUT to obtain a sleep feedback signal DSTB_FB;

[0117] The first NOT gate 542 is configured to receive the sleep feedback signal DSTB_FB and perform an inversion operation on the sleep feedback signal DSTB_FB to obtain a second sleep signal DSTB_OUT.

[0118] In the embodiment of the present application, the first output signal P1OUT is output by the first processing unit 502, and the second output signal P2OUT is output by the second processing unit 503. In this way, if the first output signal P1OUT is in a high level state and the second output signal P2OUT is in a high level state, then the sleep feedback signal DSTB_FB is in a low level state and the second sleep signal DSTB_OUT is in a high level state; if at least one of the first output signal P1OUT and the second output signal P2OUT is in a low level state, then the sleep feedback signal DSTB_FB is in a high level state and the second sleep signal DSTB_OUT is in a low level state; in this way, a stable second sleep signal DSTB_OUT can be obtained to achieve reliable sleep and reliable wake-up.

[0119] In some embodiments, see Fig. 9 , the second processing unit 503 may include a second level shift (LevelShift 2) unit 531, wherein:

[0120] The second level conversion unit 531 is configured to receive the first input signal IN1, the second input signal IN1N and the sleep feedback signal DSTB_FB, and perform level conversion according to the first input signal IN1, the second input signal IN1N and the sleep feedback signal DSTB_FB to obtain a second output signal P2OUT.

[0121] It should be noted that, in the embodiment of the present application, the working principle of the second level conversion unit 531 is similar to that of the first level conversion unit 5221, and they are basically circuits that implement the level conversion function, and their main function is to convert a signal of one level standard into a signal of another level standard to meet the communication requirements between different circuits or devices. Here, the second level conversion unit 5221 can also convert 1.2V to 1.8V, so as to meet the requirements of the 1.8V power domain.

[0122] In one possible implementation, see Fig. 9, the second level conversion unit 531 may include a level conversion subunit 5311, a pull-down unit 5312, a pull-up unit 5313 and a first buffer unit 5314; wherein:

[0123] The first end of the level conversion subunit 5311 is used to receive the first input signal IN1, the second end of the level conversion subunit 5311 is used to receive the second input signal IN1N, the third end of the level conversion subunit 5311 and the control end of the pull-up unit 5313 are used to receive the sleep feedback signal DSTB_FB, the first end of the pull-up unit 5313 is connected to the first power supply, the fourth end of the level conversion subunit 5311, the second end of the pull-up unit 5313 and the first end of the pull-down unit 5312 are respectively connected to the first end of the first buffer unit 5314, the fifth end of the level conversion subunit 5311 and the second end of the pull-down unit 5312 are respectively connected to the ground, and the second end of the first buffer unit 5314 is used to output the second output signal P2OUT.

[0124] In the embodiment of the present application, the level conversion subunit 5311 may be composed of five transistors, such as Fig. 9 As shown, the level conversion subunit 5311 includes a third transistor N3, a fourth transistor N4, a fifth transistor N5, a sixth transistor P1 and a seventh transistor P2. Among them, the first end of the sixth transistor P1 is connected to the second power supply, the first end of the seventh transistor P2 is connected to the third power supply, the second end of the sixth transistor P1 is respectively connected to the first end of the fourth transistor N4 and the control end of the seventh transistor P2, the second end of the seventh transistor P2 is respectively connected to the first end of the fifth transistor N5, the control end of the sixth transistor P1 and the first end of the first buffer unit 5314 as the fourth end of the level conversion sub-unit 5311, the control end of the fourth transistor N4 is used as the first end of the level conversion sub-unit 5311 for receiving the first input signal IN1, the control end of the fifth transistor N5 is used as the second end of the level conversion sub-unit 5311 for receiving the second input signal IN1N, the first end of the third transistor N3 is respectively connected to the second end of the fourth transistor N4 and the second end of the fifth transistor N5, the control end of the third transistor N3 is used as the third end of the level conversion sub-unit 5311 for receiving the sleep feedback signal DSTB_FB, and the second end of the third transistor N3 is connected to the ground as the fifth end of the level conversion sub-unit 5311.

[0125] In the embodiment of the present application, the pull-down unit 5312 may be composed of a pull-down resistor, and the pull-up unit 5313 may be composed of an eighth transistor P3. Fig. 9As shown, the pull-down unit 5312 includes a pull-down resistor R1, and the pull-up unit 5313 includes an eighth transistor P3. The first end of the eighth transistor P3 is connected to the first power supply, the control end of the eighth transistor P3 is used to receive the sleep feedback signal DSTB_FB, the second end of the eighth transistor P3 is respectively connected to the first end of the pull-down resistor R1 and the first end of the first buffer unit 5314, the second end of the pull-down resistor R1 is respectively connected to the second end of the third transistor N3 and the ground, and the second end of the first buffer unit 5314 is used to output the second output signal P2OUT.

[0126] It should be noted that in the embodiment of the present application, the first power supply, the second power supply and the third power supply can be set to the same power supply, or can also be set to different power supplies, without any limitation here.

[0127] It should also be noted that, in the embodiment of the present application, the first transistor N1, the second transistor N2, the third transistor N3, the fourth transistor N4 and the fifth transistor N5 may be N-type transistors, and the sixth transistor P1, the seventh transistor P2 and the eighth transistor P3 may be P-type transistors. The transistors here may be MOSFETs, switch tubes, triodes, etc., and no limitation is made here.

[0128] For example, in Fig. 9 In the embodiment, the first transistor N1, the second transistor N2, the third transistor N3, the fourth transistor N4 and the fifth transistor N5 may be NMOS transistors, and the sixth transistor P1, the seventh transistor P2 and the eighth transistor P3 may be PMOS transistors.

[0129] It should also be noted that the first buffer unit 5314 can also be called a buffer, which is an intermediate medium for temporarily storing data, and the buffer can also enhance the driving ability of the signal. In addition, in the embodiment of the present application, the pull-down resistor R1 can select a large resistance, for example, a 1 megohm (MΩ) resistor can be selected, which is used during the power-on process. If the first input signal IN1 and the second input signal IN1N are both in a low level state, the second output signal P2OUT can be pulled down to a low level state through the pull-down resistor R1, ensuring that the final output second sleep signal DSTB_OUT is a low level, so that the sleep controller 202 is reliable during the power-on process.

[0130] An embodiment of the present application provides a sleep controller, which can generate a second sleep signal DSTB_OUT based on a first sleep signal DSTB_IN and an external reset signal RESET; and based on the internal structure of the sleep controller, when the control device enters the sleep state, the sleep controller can keep the second sleep signal DSTB_OUT in a high level state and the level state is stable and unchanged, so that it can reliably enter the deep sleep mode; when the control device needs to work normally, the sleep controller can keep the second sleep signal DSTB_OUT in a low level state and the level state is also stable and unchanged, so that it can be reliably awakened; this can not only reduce the power consumption of the control device in the deep sleep state, but also achieve reliable sleep and reliable wake-up of the control device in the deep sleep mode.

[0131] In another embodiment of the present application, Fig.10 The schematic diagram of the structure of a chip provided in the embodiment of the present application is shown in FIG. Fig.10 As shown, the chip 1000 may include the control device 200 as described in the above embodiments.

[0132] In an embodiment of the present application, the sleep controller 202 in the control device 200 can be a deep sleep simulation control circuit, specifically a controller that can achieve high stability in deep sleep of the chip and can achieve ultra-low power consumption of the chip 1000 in the deep sleep state.

[0133] In addition, for chip 1000, after receiving the sleep instruction, the control unit 204 (such as MCU) in chip 1000 will send a first sleep signal DSTB_IN to the sleep controller, which can reliably shut down the clock, power supply and other power-consuming modules of the digital logic module, so that chip 1000 enters an ultra-low power deep sleep mode; when chip 1000 needs to be awakened, it can also be reliably awakened by an external reset signal RESET sent by an external host.

[0134] That is to say, after the MCU in chip 1000 sends the first sleep signal DSTB_IN to the sleep controller, the sleep controller needs to recognize the first sleep signal DSTB_IN before the power supply of the digital logic module of chip 1000 is powered off, and before resetting the digital logic module, it needs to lock the second sleep signal DSTB_OUT to turn off the clock and power supply of the digital logic module, and the second sleep signal DSTB_OUT is stable until the clock and power supply of the digital logic module are turned off, so as to achieve reliable sleep and reliable wake-up of chip 1000 in deep sleep state.

[0135] In a possible implementation, the aforementioned control device 200, or the internal sleep controller, can be applied to a touch and display driver integration (TDDI) chip. That is, the chip 1000 here can be a display driver chip or other MCU chip that requires a deep sleep function, without any limitation.

[0136] In yet another embodiment of the present application, Fig.11 The following is a schematic diagram of the structure of an electronic device provided in an embodiment of the present application. Fig.11 As shown, the electronic device 1100 may include a display driver chip 1101 , and the display driver chip 1101 includes the control device 200 as described in the above embodiment.

[0137] In the embodiment of the present application, the electronic device 1100 may be a portable device such as a mobile phone, a notebook, a PDA, a personal digital assistant, etc. Moreover, the electronic device 1100 includes a display driver chip 1101 for realizing the display function of the electronic device.

[0138] Here, in order to improve the problem of high power consumption of the display driver chip in a deep sleep state, the embodiment of the present application provides a low-power solution for the deep sleep state of the chip, which can be to apply the control device 200 to the display driver chip 1101, and also provide a reliable sleep controller architecture, so that after the control unit (such as MCU) receives the sleep instruction, the generated first sleep signal can be sent to the sleep controller, and the sleep controller generates a second sleep signal in a high level state according to the first sleep signal, and can reliably shut down at least one resource module (such as shutting down the reset module, the power module and the oscillator module, etc.), so that not only can the digital logic module be reset, but also the power supply and clock of the digital logic module can be shut down by shutting down the power module and the oscillator module, so that the chip can enter an ultra-low power deep sleep mode; in addition, when the chip needs to wake up, the sleep controller can also control the second sleep signal to be in a low level state according to the received external reset signal, so that the chip can be reliably awakened in the deep sleep mode. In this way, not only can the power consumption of the chip in the deep sleep state be reduced, and the endurance of the electronic device be improved; but also the reliable sleep and reliable wake-up of the chip in the deep sleep mode can be achieved, and the reliability of the electronic device is improved.

[0139] In another possible implementation, Fig.12 A schematic diagram of the circuit structure of a chip provided in an embodiment of the present application. Fig.12As shown, the chip 1000 may include: an LDO module 101, an OSC module 102, a POR module 103, a sleep controller 202 and a digital logic module 201, wherein the digital logic module 201 internally includes an MCU module 106. The first power domain U1 indicates that the module is in the 1.8V power domain, and the second power domain U2 indicates that the module is in the 1.2V power domain.

[0140] In the embodiment of the present application, after the MCU module 106 receives the sleep instruction sent by the external host, it will shut down most of the modules inside the digital logic module 201, and output a high-level first sleep signal DSTB_IN to the sleep controller 202. After the sleep controller 202 receives the first sleep signal with a suitable positive pulse width (for example, more than 4us), the second sleep signal DSTB_OUT output by the sleep controller 202 first forces the POR module 103 to shut down and reset the digital logic module 201, and the digital logic module 201 enters the low power consumption mode, and at the same time, the first sleep signal DSTB_IN is forced to output a low level. At this time, the sleep controller 202 needs to lock the high-level pulse signal of the first sleep signal DSTB_IN, and the output second sleep signal DSTB_OUT continues to be high, thereby keeping the chip 1000 in the sleep state. When the second sleep signal DSTB_OUT output by the sleep controller 202 is high, the LDO module 101, the OSC module 102, the POR module 103 and other power-consuming modules will be shut down to ensure that only part of the logic in the 1.8V power domain of the entire chip is working to maintain the entire sleep state. In addition, the deep sleep wake-up of chip 1000 can only be achieved through the external reset signal RESET. After the external reset signal RESET is reset, the sleep controller 202 will jump out of the previously locked sleep state, making the second sleep signal DSTB_OUT a low level. After that, the LDO module 101 is gradually established, the OSC module 102 is established, and the first sleep signal DSTB_IN is reset to a low level. After the external reset signal RESET is released, the second sleep signal DSTB_OUT locked by the sleep controller 202 is always a low level, and the digital logic module 201 begins to be established according to the normal timing to enable the chip 1000 to work normally.

[0141] In another possible implementation, based on the above Figures 5 to 9 The sleep controller shown, Fig.13 Detailed structural diagram of a sleep controller provided in an embodiment of the present application. Fig.13As shown, in the sleep controller 202, the first sleep signal DSTB_IN is equivalent to a positive pulse in the deep sleep process. After passing through the first level conversion unit 5221 from the first path PATH1, it enters the pulse filtering unit 5222 (for example, narrow pulse filtering), and can identify positive pulses greater than 4us. At this time, the output is also a positive pulse. The positive pulse locks the output P1OUT of the subsequent latch unit 205 to a high level. After the latch unit 205 enters the locked state, both inputs are invalid, and the output P1OUT of the latch unit 205 maintains a high level. At the same time, when the first sleep signal DSTB_IN is in the locked state, the output P1OUT of the latch unit 205 is in the locked state. When the signal DSTB_IN is at a high level, the eighth transistor P3 is controlled to be turned on, thereby pulling the signal level up to a high level, that is, the output P2OUT of the second level conversion unit 531 is at a high level. At this time, the sleep feedback signal DSTB_FB is at a low level and will feedback the state of locking the second path PATH2, so that the output P2OUT of the second level conversion unit 531 is at a high level. After that, the P2OUT output is maintained at a high level during the process of the LDO module 101 decreasing to 0V, and the second sleep signal DSTB_OUT is maintained at a high level, and the entire chip enters an ultra-low power deep sleep mode. Here, the awakening of the deep sleep state can only be achieved through the external reset signal RESET. When the external reset signal RESET is at a low level, the external reset signal RESET is inverted by the third inverter M3, and the obtained second reset signal RST2 is at a high level, which can turn on the first transistor N1 in the latch unit 205, thereby pulling the signal level down to a low level. After the low-level signal is inverted by the fifth inverter M5 and the sixth inverter M6 connected in series, the final output P1OUT is still at a low level. At the same time, the other end input of the locking latch unit 205 is also at a low level, and the input of the sleep controller 202 is The output DSTB_OUT is low, the output of the LDO module 101 starts to build, and the OSC module 102 also starts to build. After the output of the LDO module 101 is stable, the POR module 103 resets the digital logic module 201, so that the first sleep signal DSTB_IN is low, and P2OUT can be low through the second path PATH2. After that, when the external reset signal RESET is released to a high level, the two inputs of the latch unit 205 are invalid, and the output P1OUT of the latch unit 205 is low. The second sleep signal DSTB_OUT finally outputted maintains a low level, so that the chip can work normally.

[0142] It should also be noted that, in the embodiments of the present application, Fig.13It can be seen that for the second sleep signal DSTB_OUT that is finally output, the level state of the second sleep signal DSTB_OUT can be controlled by the first path PATH1 and the second path PATH2. Among them, when P1OUT output through the first path PATH1 is at a high level and P2OUT output through the second path PATH2 is at a high level, after the logic operation of the first NAND gate 541 and the first NOT gate 542, the second sleep signal DSTB_OUT that is finally output will be at a high level; otherwise, if only one of the signals P1OUT output through the first path PATH1 and P2OUT output through the second path PATH2 is at a low level, then after the logic operation of the first NAND gate 541 and the first NOT gate 542, the second sleep signal DSTB_OUT that is finally output is at a low level. In this way, according to the second path PATH2 and the first path PATH1, the level state of the second sleep signal DSTB_OUT can be guaranteed to be correct, thereby achieving reliable sleep and reliable wake-up in a deep sleep state.

[0143] For example, Fig.14 This is a schematic diagram of the working analysis of a 1.8V power-on process provided in an embodiment of the present application. Fig.14 As shown, when the 1.8V power supply is powered on, the sleep controller 202 normally outputs a low level, that is, the second sleep signal DSTB_OUT is always at a low level, thereby ensuring its reliability. Through analysis, it can be seen that during the 1.8V power supply power-on process, the external reset signal RESET always follows the power-on, and at this time the first path PATH1 will not work. Fig.12 and Fig.13 It can be seen that during the power-on process of the 1.8V power supply, the output of the LDO module 101 is 0V, so the 1.2V power supply is also 0V. At this time, the first input signal IN1 and the second input signal IN1N are both low levels. At this time, the second output signal P2OUT can be forced to be a low level output through the pull-down resistor R1 (resistance is about 1MΩ), ensuring that the final output second sleep signal DSTB_OUT is a low level, so the sleep controller 202 is reliable during the power-on process.

[0144] In one possible implementation, Fig.15 The following is a schematic diagram of a simulation waveform of a sleep controller provided in an embodiment of the present application. The 1.8V waveform indicates the power-on condition of the 1.8V power supply, and the LDO_OUT waveform indicates the power output condition of the LDO module 101. Fig.15 The simulation waveforms of the three processes of 1.8V power-on, entering deep sleep and waking up from deep sleep are given in the figure.

[0145] During the 1.8V power supply power-on process, the output of LDO_OUT is low level, the first sleep signal DSTB_IN, the external reset signal RESET and the internal reset signal RESET_IN are all low level, in this case, the first output signal P1OUT and the second output signal P2OUT are also low level output, so that the second sleep signal DSTB_OUT outputted finally is also low level. After the 1.8V power supply is powered on, the LDO module 101 starts to work, so that LDO_OUT gradually rises from low level to high level; and the external reset signal RESET and the internal reset signal RESET_IN are also released to high level.

[0146] In the process of entering deep sleep, first, the MCU receives a sleep instruction. At this time, the first sleep signal DSTB_IN is high, the external reset signal RESET is high, and the first output signal P1OUT and the second output signal P2OUT are both high, so that the second sleep signal DSTB_OUT output by the sleep controller 202 is also high. By forcibly closing the POR module 103 to change the internal reset signal RESET_IN from high to low, the digital logic module 201 is reset, so that the first sleep signal DSTB_IN becomes low, so the first sleep signal received by the sleep controller 202 is a positive pulse signal; at the same time, because the second sleep signal DSTB_OUT is high, the LDO module 101 and the OSC module 102 are also forced to be closed, so that LDO_OUT gradually drops from high to low, so as to turn off the power supply and clock of the digital logic module 201; and when the first sleep signal DSTB_IN is low, the sleep controller 202 will lock the high-level pulse signal of DSTB_IN, so that the output second sleep signal DSTB_OUT is always high, which can keep the chip in a deep sleep state.

[0147] During the wake-up process from deep sleep, first the external reset signal RESET is switched to a low level for reset, so that the sleep controller 202 jumps out of the previously locked sleep state. At this time, the first sleep signal DSTB_IN is a low level. At this time, the first output signal P1OUT and the second output signal P2OUT are both low levels, so that the second sleep signal DSTB_OUT output by the sleep controller 202 is also a low level. Then the LDO module 101 is gradually established, and LDO_OUT gradually rises from a low level to a high level; and the OSC module 102 and the POR module 103 are established. Subsequently, after the external reset signal RESET is released, the second sleep signal DSTB_OUT locked by the sleep controller 202 is always a low level, so that the digital logic module 201 begins to be established according to the normal timing, and the chip works normally.

[0148] In the embodiments of the present application, the specific implementation of the aforementioned embodiments is elaborated in detail through the above embodiments. It can be seen that through the technical scheme of the aforementioned embodiments, a control device capable of deep sleep is provided here, which may specifically include a low-power solution for the chip deep sleep mode and a reliable sleep controller architecture implementation, which can not only reduce the power consumption of the chip in the deep sleep state and improve the endurance of the electronic device; but also can realize reliable sleep and reliable wake-up of the chip in the deep sleep mode, thereby improving the reliability of the electronic device.

[0149] In yet another embodiment of the present application, based on the control device 200 described in the above embodiment, Fig.16 A flow chart of a control method provided in an embodiment of the present application. Fig.16 As shown, the process includes:

[0150] S1601: After receiving a sleep instruction, the control unit generates a first sleep signal according to the sleep instruction, and sends the first sleep signal to a sleep controller.

[0151] S1602: The sleep controller generates a second sleep signal according to the first sleep signal, and when the second sleep signal is at a first level, controls at least one resource module in the control device to shut down and reset the digital logic module, so that the control device enters a deep sleep state.

[0152] In the embodiment of the present application, the control method can be applied to the control device 200 described in the above embodiment, or the chip 1000 integrated with the control device. Based on the control method, the sleep controller can realize reliable sleep and reliable wake-up of the chip in the deep sleep mode, and can also reduce the power consumption of the chip in the deep sleep state, thereby solving the problem of short battery life.

[0153] In some embodiments, when the second sleep signal is in a first level state, the sleep controller controls at least one resource module in the control device to shut down and reset the digital logic module, which may include: when the second sleep signal is in a first level state, the sleep controller controls the reset module to shut down and sends an internal reset signal to the digital logic module to reset the digital logic module and enter a low power consumption state.

[0154] In an embodiment of the present application, after the sleep controller receives the first sleep signal DSTB_IN, the sleep controller can control the reset module to force shutdown according to the second sleep signal DSTB_OUT, and then provide an internal reset signal RESET_IN to the digital logic module, so that the digital logic module is reset and enters a low power consumption state, that is, the chip enters a sleep state.

[0155] In some embodiments, when the second sleep signal is in a first level state, the method may further include: when the second sleep signal is in the first level state, the sleep controller controls the oscillator module to turn off so that the clock of the digital logic module is turned off; and the sleep controller controls the power supply module to turn off so that the power supply of the digital logic module is turned off.

[0156] In an embodiment of the present application, after the sleep controller receives the first sleep signal DSTB_IN, the sleep controller can output a second sleep signal DSTB_OUT in a high level state, which can control the reset module, the oscillator module and the power module to all be turned off, thereby turning off the power supply and clock of the digital logic module, so that the chip enters a deep sleep state.

[0157] That is to say, for the chip, after the control unit receives the sleep instruction, at least part of the modules in the digital logic module can be turned off first, and then the low power consumption control of the sleep controller can be divided into two stages: sleep state and deep sleep state. Among them, after the sleep controller receives the first sleep signal DSTB_IN, according to the second sleep signal DSTB_OUT output by the sleep controller, the digital logic module is reset and enters the low power consumption state through the internal reset signal RESET_IN output by the reset module, that is, the chip enters the sleep state; further, the second sleep signal DSTB_OUT output by the sleep controller continues to maintain a high level state, so that the reset module, oscillator module and power module can be controlled to be all turned off, so that the chip enters the deep sleep state.

[0158] In some embodiments, the method may also include: after receiving a sleep instruction, the control unit shuts down at least part of the modules in the digital logic module, and generates a first sleep signal in a first level state according to the sleep instruction; and after the digital logic module is reset, controls the first sleep signal to be in a second level state, so that the first sleep signal received by the sleep controller is a positive pulse signal whose pulse width meets a preset condition.

[0159] In an embodiment of the present application, after receiving the sleep instruction, the control unit will shut down at least part of the modules in the digital logic module, and at the same time output a first sleep signal DSTB_IN in a high level state to the sleep controller. After the sleep controller controls the reset module to shut down and reset the digital logic module, the digital logic module enters a low power consumption mode, and at the same time, the first sleep signal is forced to output a low level state, so that the first sleep signal DSTB_IN received by the sleep controller is a positive pulse signal. Here, "positive" is used to characterize that the pulse is in a high level state.

[0160] In some embodiments, in order to ensure reliable sleep in the deep sleep state, the state of the second sleep signal needs to be stable. Accordingly, the method may also include: when the first sleep signal switches from the first level state to the second level state, the sleep controller keeps the second sleep signal in the first level state through an internal latch unit, so that the control device is in the deep sleep state.

[0161] In an embodiment of the present application, after resetting the digital logic module, the digital logic module will force the first sleep signal DSTB_IN to output a low level state. At this time, the sleep controller needs to lock the high level state of the first sleep signal DSTB_IN through an internal latch unit, so that the output second sleep signal DSTB_OUT is always in a high level state, that is, the state of the second sleep signal DSTB_OUT is stable, thereby enabling the chip to achieve reliable sleep in a deep sleep state.

[0162] In some embodiments, when the chip needs to be awakened, it can be reliably awakened by an external reset signal sent by an external host. Accordingly, the method may also include: when the sleep controller receives an external reset signal in a second level state, controlling the second sleep signal to be in a second level state according to the external reset signal to wake up at least one resource module and control the digital logic module to start working.

[0163] In a possible implementation, the method may further include: a sleep controller, further configured to keep the second sleep signal in a second level state through a latch unit after waking up at least one resource module and the external reset signal is released, so that the control device is in a normal working state.

[0164] In an embodiment of the present application, for awakening the at least one resource module, first the output of the power module begins to be established, and the oscillator module also begins to be established. After the output of the power module is stable, the reset module resets the digital logic module, so that the first sleep signal DSTB_IN is in a low level state, and the second sleep signal DSTB_OUT is in a low level state; thereafter, when the external reset signal RESET is released to a high level state, at this time both inputs of the latch unit are invalid, and the output of the latch unit is locked to a low level state, so that the second sleep signal DSTB_OUT maintains a low level state, and at this time the state of the second sleep signal DSTB_OUT is also stable, thereby enabling the chip to be reliably awakened in a deep sleep state to enable the chip to work normally.

[0165] The embodiment of the present application provides a control method, after the control unit receives the sleep instruction, the sleep controller generates a second sleep signal in a high level state according to the first sleep signal, which can reliably shut down at least one resource module (for example, shut down the reset module, the power module and the oscillator module, etc.), so that not only the digital logic module can be reset, but also the power supply and clock of the digital logic module can be shut down by shutting down the power module and the oscillator module, so that the chip can enter an ultra-low power deep sleep mode; in addition, when the chip needs to be awakened, the second sleep signal can also be controlled to be in a low level state according to the received external reset signal, so that the chip can be reliably awakened in the deep sleep mode. In this way, not only can the power consumption of the chip in the deep sleep state be reduced, and the endurance of the electronic device be improved; but also the reliable sleep and reliable awakening of the chip in the deep sleep mode can be achieved, and the reliability of the electronic device can be improved.

[0166] In the embodiment of the present application, a computer-readable storage medium is also provided for storing a computer program. The computer-readable storage medium can be applied to the chip or electronic device in the embodiment of the present application, and when the computer program is executed by at least one processor, the corresponding process implemented by the chip or electronic device in each method of the embodiment of the present application is implemented, which will not be described in detail for the sake of brevity.

[0167] In the embodiments of the present application, a computer program product is also provided, including computer program instructions. The computer program product can be applied to the chip or electronic device in the embodiments of the present application, and the computer program instructions enable the computer to execute the corresponding processes implemented by the chip or electronic device in each method of the embodiments of the present application, which will not be described in detail for the sake of brevity.

[0168] Those of ordinary skill in the art will appreciate that the devices, systems, and algorithm steps of each example described in conjunction with the embodiments disclosed in this application can be implemented in electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of this application.

[0169] Those skilled in the art should also understand that the devices, chips, equipment and methods disclosed in the present application can be implemented in other ways. For example, the device embodiments described above are only schematic. For example, the division of the modules is only a logical function division. There may be other division methods in actual implementation, such as multiple modules or components can be combined or integrated into another system, or some features can be ignored or not executed. Another point is that the mutual coupling or direct coupling or communication connection shown or discussed can be through some interfaces, indirect coupling or communication connection of devices or modules, which can be electrical, mechanical or other forms.

[0170] It should also be noted that in this application, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0171] The serial numbers of the above-mentioned embodiments of the present application are for description only and do not represent the advantages or disadvantages of the embodiments.

[0172] The features disclosed in several product embodiments provided in this application can be arbitrarily combined without conflict to obtain new product embodiments.

[0173] The features disclosed in several system or method embodiments provided in this application can be arbitrarily combined without conflict to obtain new system embodiments or method embodiments.

[0174] The above description is only a specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present application, which should be included in the protection scope of the present application.

Claims

1. A control device, characterized in that: The control device comprises a digital logic module, a sleep controller and at least one resource module, and the digital logic module comprises a control unit; wherein: The control unit is configured to, after receiving a sleep instruction, generate a first sleep signal according to the sleep instruction, and send the first sleep signal to the sleep controller; The sleep controller is configured to generate a second sleep signal according to the first sleep signal, and when the second sleep signal is in a first level state, control the at least one resource module to shut down and reset the digital logic module, so that the control device enters a deep sleep state.

2. The control device according to claim 1, characterized in that: The at least one resource module includes a reset module, and the reset module is connected to a reset terminal of the digital logic module; The reset module is configured to receive the second sleep signal sent by the sleep controller, and to be turned off when the second sleep signal is in a first level state, and to send an internal reset signal to the digital logic module to reset the digital logic module and enter a low power consumption state.

3. The control device according to claim 2, characterized in that: The at least one resource module further includes an oscillator module and a power supply module, wherein the oscillator module is connected to a clock terminal of the digital logic module, and the power supply module is connected to a power supply terminal of the digital logic module; The oscillator module is configured to receive the second sleep signal sent by the sleep controller, and to be turned off when the second sleep signal is in a first level state, so as to turn off the clock of the digital logic module; The power supply module is configured to receive the second sleep signal sent by the sleep controller, and to be turned off when the second sleep signal is in a first level state, so as to turn off the power supply of the digital logic module.

4. The control device according to claim 1, characterized in that: The control unit is also configured to, after receiving a sleep instruction, shut down at least part of the modules in the digital logic module, and generate a first sleep signal in a first level state according to the sleep instruction; and after the digital logic module is reset, control the first sleep signal to be in a second level state, so that the first sleep signal received by the sleep controller is a positive pulse signal whose pulse width meets a preset condition.

5. The control device according to any one of claims 1 to 4, characterized in that: The sleep controller comprises a latch unit, wherein: The sleep controller is further configured to keep the second sleep signal in the first level state through the latch unit when the first sleep signal switches from the first level state to the second level state, so as to put the control device in a deep sleep state.

6. The control device according to claim 5, characterized in that: The sleep controller is further configured to control the second sleep signal to be in the second level state according to the external reset signal when receiving the external reset signal in the second level state, so as to wake up the at least one resource module and control the digital logic module to start working.

7. The control device according to claim 6, characterized in that: The sleep controller is further configured to keep the second sleep signal in a second level state through the latch unit after waking up the at least one resource module and the external reset signal is released, so as to keep the control device in a normal working state.

8. A sleep controller, characterized in that: The sleep controller is applied to a control device as claimed in any one of claims 1 to 7; wherein: The sleep controller is configured to receive a first sleep signal and an external reset signal, and generate a second sleep signal according to the first sleep signal and the external reset signal; wherein, when the second sleep signal is in a first level state, the control device is in a deep sleep state; and when the second sleep signal is in a second level state, the control device is in a normal working state.

9. The sleep controller according to claim 8, characterized in that: The sleep controller comprises a first logic unit, a first processing unit, a second processing unit and a logic operation unit, wherein the output end of the first logic unit is connected to the first processing unit and the second processing unit respectively, and the output end of the first processing unit and the output end of the second processing unit are connected to two input ends of the logic operation unit correspondingly; wherein: The first logic unit is configured to receive a first sleep signal and perform a logic operation on the first sleep signal to generate a first input signal and a second input signal; The first processing unit is configured to receive an external reset signal and the first input signal, and generate a first output signal according to the external reset signal and the first input signal; The second processing unit is configured to receive the first input signal, the second input signal and the sleep feedback signal, and generate a second output signal according to the first input signal, the second input signal and the sleep feedback signal; The logic operation unit is configured to receive the first output signal and the second output signal, perform a logic operation on the first output signal and the second output signal, and generate a second sleep signal.

10. The sleep controller according to claim 9, characterized in that: The first processing unit includes a second logic unit, a pulse processing unit, a first AND gate and a latch unit, wherein the first output end of the second logic unit and the output end of the pulse processing unit are connected to the two input ends of the first AND gate correspondingly, and the second output end of the second logic unit and the output end of the first AND gate are connected to the two input ends of the latch unit correspondingly, wherein: The second logic unit is configured to receive the external reset signal and perform a logic operation on the external reset signal to generate a first reset signal and a second reset signal; The pulse processing unit is configured to receive the first input signal, perform level conversion and pulse filtering on the first input signal, and generate a third input signal; The first AND gate is configured to receive the first reset signal and the third input signal, and perform an AND operation on the first reset signal and the third input signal to generate a fourth input signal; The latch unit is configured to receive the second reset signal and the fourth input signal, and generate the first output signal according to the second reset signal and the fourth input signal.

11. The sleep controller according to claim 10, characterized in that: The pulse processing unit includes a first level conversion unit and a pulse filtering unit, wherein the output end of the first level conversion unit is connected to the input end of the pulse filtering unit, wherein: The first level conversion unit is configured to receive the first input signal and perform level conversion on the first input signal to obtain an intermediate input signal; The pulse filtering unit is configured to receive the intermediate input signal and perform pulse filtering processing on the intermediate input signal whose pulse width does not meet the preset condition to obtain the third input signal, and the pulse width of the third input signal meets the preset condition.

12. The sleep controller according to claim 10, characterized in that: The latch unit is configured to lock the first output signal to a first level state when the second reset signal is in a second level state and the fourth input signal is in a first level state; And when the second reset signal is in the first level state and the fourth input signal is in the second level state, the first output signal is locked to the second level state.

13. The sleep controller according to claim 9, characterized in that: The logic operation unit includes a first NAND gate and a first NOT gate, the output end of the first processing unit and the output end of the second processing unit are connected to two input ends of the first NAND gate correspondingly, and the output end of the first NAND gate is connected to the input end of the first NOT gate, wherein: The first NAND gate is configured to receive the first output signal and the second output signal, and perform a NAND operation on the first output signal and the second output signal to obtain a sleep feedback signal; The first NOT gate is configured to receive the sleep feedback signal and perform an inversion operation on the sleep feedback signal to obtain the second sleep signal.

14. The sleep controller according to claim 13, characterized in that: The second processing unit comprises a second level conversion unit, wherein: The second level conversion unit is configured to receive the first input signal, the second input signal and the sleep feedback signal, and perform level conversion according to the first input signal, the second input signal and the sleep feedback signal to obtain the second output signal.

15. The sleep controller according to claim 14, characterized in that: The second level conversion unit includes a level conversion sub-unit, a pull-down unit, a pull-up unit and a first buffer unit; wherein: The first end of the level conversion subunit is used to receive the first input signal, the second end of the level conversion subunit is used to receive the second input signal, the third end of the level conversion subunit and the control end of the pull-up unit are used to receive the sleep feedback signal, the first end of the pull-up unit is connected to a power supply, the fourth end of the level conversion subunit, the second end of the pull-up unit and the first end of the pull-down unit are respectively connected to the first end of the first buffer unit, the fifth end of the level conversion subunit and the second end of the pull-down unit are respectively connected to the ground, and the second end of the first buffer unit is used to output the second output signal.

16. A control method, characterized in that: Applied to the control device according to any one of claims 1 to 7, the method comprises: After receiving the sleep instruction, the control unit generates a first sleep signal according to the sleep instruction, and sends the first sleep signal to the sleep controller; The sleep controller generates a second sleep signal according to the first sleep signal, and when the second sleep signal is in a first level state, controls at least one resource module in the control device to shut down and reset a digital logic module, so that the control device enters a deep sleep state.

17. A chip, characterized in that: The chip includes the control device according to any one of claims 1 to 7.

18. An electronic device, characterized in that: The electronic device comprises a display driver chip, and the display driver chip comprises the control device according to any one of claims 1 to 7.

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