Controller, phase adjustment method of controller, equipment and storage medium

Abstract

The embodiment of the invention provides a controller, a phase adjustment method of the controller, electronic equipment and a storage medium, and the circuit comprises an interface design module which is used for transmitting an output data signal and a clock signal to external equipment, receiving an input data signal sent by the external device in response to the output data signal and the clock signal; the delay module is used for adjusting a time sequence and / or a phase between the output data signal and the clock signal according to delay information; the interface data monitoring module is used for judging whether the input data signal meets a preset condition or not; and the delay control module is used for adjusting the delay information if the input data signal does not meet the preset condition. Whether the input data signal is met or not can be judged based on the preset condition, the time sequence and phase of the output data and the output clock are automatically adjusted according to the delay information, time consumption of manual phase adjustment is reduced, and debugging and testing efficiency can be improved.

Description

Technical Field

[0001] The present invention relates to the field of clock phase, and in particular to a controller, a phase adjustment method of a controller, an electronic device and a computer-readable storage medium. Background Art

[0002] In controller applications, bus devices of various protocols are often processed and implemented. How to handle the synchronization of data signals and clock signals on the bus protocol is the focus and key issue of controller implementation. Constraints are usually used to constrain the establishment and hold time of data signals and clock signals. This approach is usually used when the external device is determined and the clock signal speed is not too fast. If the external device is uncertain or the clock signal is fast, the external device has a certain degree of unknowns. Affected by external hardware and connections, it is difficult to ensure that the external device accurately receives the data signal when the clock signal is synchronized.

[0003] When the existing controller realizes data interaction with external devices with clocks, it needs to manually adjust the phase, which consumes manpower and a lot of time. For large-scale projects, it takes more time and cannot guarantee timeliness. Especially when replacing external devices, related parameters need to be readjusted and debugged. Summary of the invention

[0004] In view of the above problems, embodiments of the present invention are proposed to provide a controller, a phase adjustment method of a controller, an electronic device and a computer-readable storage medium that overcome the above problems or at least partially solve the above problems.

[0005] In a first aspect, an embodiment of the present invention discloses a controller, the controller comprising:

[0006] An interface design module, used for sending an output data signal and a clock signal to an external device, and receiving an input data signal sent by the external device in response to the output data signal and the clock signal;

[0007] A delay module, connected to the interface design module, for adjusting the timing and / or phase between the output data signal and the clock signal according to the delay information;

[0008] An interface data monitoring module, connected to the interface design module, for determining whether the input data signal meets a preset condition; if the input data signal meets the preset condition, recording the delay information corresponding to the preset condition;

[0009] A delay control module is connected to the interface data monitoring module and the delay module, and is used to adjust the delay information if the input data signal does not meet the preset condition.

[0010] Optionally, the interface data monitoring module is used to obtain an expected data signal corresponding to the output data signal; determine whether the input data signal matches the expected data signal; if the input data signal matches the expected data signal, determine that a preset condition is met.

[0011] Optionally, the interface data monitoring module includes: a non-volatile storage unit; the delay information includes a delay step;

[0012] The interface data monitoring module is used to read an expected data signal matching the output data signal from the non-volatile storage unit;

[0013] The delay module is used to read the delay step and the mapping relationship between the delay step and the phase delay value from the non-volatile storage unit, determine the phase delay value according to the delay step and the mapping relationship between the delay step and the phase delay value; and adjust the timing and / or phase between the output data signal and the clock signal according to the phase delay value;

[0014] The delay control module is used to read the step control mode and the delay step from the non-volatile storage unit; adjust the delay step according to the step control mode, and write the adjusted delay step into the non-volatile storage unit; wherein the adjusted delay step is greater than the delay step before adjustment.

[0015] Optionally, the interface data monitoring module is used to record the delay information corresponding to the preset condition being met in the non-volatile storage unit if the input data signal meets the preset condition.

[0016] Optionally, the delay module is used to read the delay information corresponding to the situation when the preset condition is met from the non-volatile storage unit when the controller is started next time, and adjust the timing and / or phase between the output data signal and the clock signal according to the delay information corresponding to the situation when the preset condition is met.

[0017] In a second aspect, an embodiment of the present invention discloses a phase adjustment method of a controller, the method comprising:

[0018] Sending an output data signal and a clock signal to an external device, and adjusting the timing and / or phase between the output data signal and the clock signal according to the delay information;

[0019] Receiving an input data signal sent by the external device;

[0020] Determining whether the input data signal meets a preset condition;

[0021] If the input data signal does not meet the preset condition, adjusting the delay information;

[0022] If the input data signal satisfies a preset condition, the delay information corresponding to when the preset condition is met is recorded.

[0023] Optionally, the determining whether the input data signal satisfies a preset condition includes:

[0024] Acquire an expected data signal corresponding to the output data signal;

[0025] Determining whether the input data signal matches the expected data signal;

[0026] If the input data signal matches the expected data signal, it is determined that a preset condition is met.

[0027] Optionally, the delay information includes a delay step; and determining to adjust the timing and / or phase between the output data signal and the clock signal according to the delay information includes:

[0028] Acquire the delay step and a mapping relationship between the delay step and the phase delay value;

[0029] Determine the phase delay value according to the delay step and the mapping relationship between the delay step and the phase delay value;

[0030] According to the phase delay value, adjusting the timing and / or phase between the output data signal and the clock signal;

[0031] The adjusting the delay information includes:

[0032] Get the step control mode;

[0033] The delay step length is adjusted according to the step length control mode; wherein the delay step length after adjustment is greater than the delay step length before adjustment.

[0034] Optionally, it also includes:

[0035] When the controller is started next time, the delay information corresponding to when the preset condition is met is read, and the timing and / or phase between the output data signal and the clock signal is adjusted according to the delay information corresponding to when the preset condition is met.

[0036] In a third aspect, the present invention shows an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor implements the steps of the above-mentioned controller phase adjustment method when executing the computer program.

[0037] In a fourth aspect, the present invention shows a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a processor, the steps of the phase adjustment method of the controller are implemented.

[0038] The embodiments of the present invention include the following advantages:

[0039] The present invention proposes a phase adjustment method of a controller, in which an output data signal and a clock signal are sent to an external device, and the timing and / or phase between the output data signal and the clock signal are adjusted according to the delay information; an input data signal sent by the external device is received; it is determined whether the input data signal meets the preset conditions; if the input data signal does not meet the preset conditions, the delay information is adjusted; if the input data signal meets the preset conditions, the delay information corresponding to the preset conditions is recorded. It is possible to determine whether the input data signal meets the preset conditions based on the preset conditions, thereby recording the delay information corresponding to the preset conditions, and automatically adjusting the timing and phase of the output data and the output clock according to the delay information, reducing the time consumption of manually adjusting the phase, and helping to improve the debugging and testing efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 is a structural block diagram of a controller provided by an embodiment of the present invention;

[0041] Figure 2 is a schematic diagram of an interface data monitoring module monitoring input data provided by an embodiment of the present invention;

[0042] Figure 3 is a schematic diagram of a delay control module adjusting delay information provided by an embodiment of the present invention;

[0043] Figure 4 It is a flowchart of a phase adjustment method of a controller provided by an embodiment of the present invention;

[0044] Figure 5 is a structural block diagram of an electronic device provided by an embodiment of the present invention;

[0045] Figure 6 It is a structural block diagram of a computer-readable storage medium provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0046] In order to make the above-mentioned objects, features and advantages of the present invention more obvious and easy to understand, the present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0047] One of the core concepts of the embodiment of the present invention is that, on the basis of the manual timing phase adjustment logic, the present invention adds an interface data monitoring module to monitor the interface data, and adds the control logic of the delay control module to control the adjustable delay circuit. The present invention uses a feedback mechanism to determine whether the phase adjustment is reasonable with the help of the returned data, and completes the adjustment and fixation of the phase with the help of this mechanism. The timing and phase of the output data and the output clock can be automatically adjusted based on whether the expected return data is correct, reducing the time consumption of manually adjusting the phase.

[0048] Figure 1 : is a block diagram of a controller structure provided by an embodiment of the present invention, the structure comprising:

[0049] The interface design module 10 is used to send an output data signal and a clock signal to an external device, and receive an input data signal sent by the external device in response to the output data signal and the clock signal;

[0050] The embodiments of the present invention may be applied to various bus and protocol controllers that require timing or phase adjustment to reduce manual adjustment time, which is not limited by the embodiments of the present invention.

[0051] In this embodiment, the external device interacts with the clock phase control circuit of the present invention. In the controller-based clock phase control circuit, the interface design module can send data signals and clock signals to the external device for transmission.

[0052] The data signal is the data that needs to be transmitted by various buses and protocols, and is transmitted in the form of a signal through the IO port on the interface design module. The clock signal is a periodic square wave signal. During the data transmission process, when the clock signal reaches the rising edge or the falling edge, it means that the data is transferred to the next stage, which controls the rhythm and synchronization of the data transmission process. The external device will respond to the data signal and clock signal sent by the interface design module, and return the response data signal to the interface design module after the response is completed.

[0053] A delay module 20, connected to the interface design module, for adjusting the timing and / or phase between the output data signal and the clock signal according to the delay information;

[0054] In this embodiment, the delay module can perform corresponding delay according to the number of the control logic. The delay information includes the delay step, which indicates the delay time of the signal from low level to high level or from high level to low level. The delay module is connected to the interface design module in the clock signal control circuit. The delay module can obtain the delay information, and dynamically adjust the phase between the data signal and the clock signal according to the obtained information. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, so as to make corresponding adjustments to the timing between the data signal and the clock signal.

[0055] In some embodiments, the delay module 20 is used to read the delay step and the mapping relationship between the delay step and the phase delay value from the non-volatile storage unit, and determine the phase delay value according to the delay step and the mapping relationship between the delay step and the phase delay value; adjust the timing and / or phase between the output data signal and the clock signal according to the phase delay value;

[0056] In this embodiment, the non-volatile storage unit is connected and controlled by the interface data monitoring module. It is a storage device that can still store data after power failure. It is suitable for various application scenarios that require data persistence. There is a corresponding mapping relationship between the delay step and the phase delay value. The corresponding delay step time can be obtained through the phase delay value. For example, when the phase delay value is 1, the delay can be 1us, or when the phase delay value is 1, the delay can be 1ms.

[0057] There is a clear corresponding relationship between the phase delay value and the delay. According to the mapping relationship between the delay step and the delay step and the phase delay value, the phase delay value during the transmission of the data signal and the clock signal can be determined. The delay module can dynamically adjust the phase between the output data signal and the clock signal according to the determined phase delay value. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, thereby making corresponding adjustments to the timing between the data signal and the clock signal to ensure the correct transmission and processing of the data.

[0058] In some embodiments, the delay module is used to read the delay information corresponding to when the preset condition is met from the non-volatile storage unit when the controller is started next time, and adjust the timing and / or phase between the output data signal and the clock signal according to the delay information corresponding to when the preset condition is met.

[0059] In this embodiment, the preset conditions are determined by the interface data monitoring module and stored in the non-volatile storage unit. When the controller is started next time and the timing and / or phase between the output data signal and the clock signal need to be adjusted, the delay module can access the non-volatile storage unit, read the delay information corresponding to the data signal when it meets the preset conditions from the non-volatile storage unit, and make corresponding adjustments to the phase between the data signal and the clock signal according to the acquired delay information. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, thereby making corresponding adjustments to the timing between the data signal and the clock signal. The timing and phase settings of the system can be quickly restored to reduce the startup time. By reading the pre-stored delay information, the timing and phase settings of the system can be quickly restored to ensure that the system enters a normal working state immediately after startup.

[0060] An interface data monitoring module 30, connected to the interface design module, is used to determine whether the input data signal meets a preset condition; if the input data signal meets the preset condition, then record the delay information corresponding to the preset condition;

[0061] In this embodiment, the preset conditions are pre-set by the interface data monitoring module and stored in the non-volatile storage unit. The preset conditions include the synchronization time of the clock signal during the data signal transmission process, which can ensure that each data transmission period remains stable during this time period.

[0062] Figure 2 is a schematic diagram of an interface data monitoring module monitoring input data provided by an embodiment of the present invention, referring to Figure 2 The interface data monitoring module is connected to the interface design module. When the external device transmits a data signal to the interface design module, the interface data monitoring module will monitor the data returned by the interface design module at any time, and judge whether the input data signal can meet the preset conditions according to the set preset conditions. If the input data signal meets the preset conditions, the delay information corresponding to the data signal when the preset conditions are met will be recorded.

[0063] By determining whether the input data signal meets the preset conditions, the integrity and correctness of the data can be verified, the performance of the system can be optimized, and unnecessary processing and resource consumption can be reduced.

[0064] In some embodiments, the interface data monitoring module 30 is used to obtain an expected data signal corresponding to the output data signal; determine whether the input data signal matches the expected data signal; if the input data signal matches the expected data signal, determine that a preset condition is met.

[0065] In this embodiment, the expected data signal can be written through the bus, or can be pre-set and pre-stored in the memory unit of the interface data monitoring. There is a one-to-one correspondence between the pre-stored data signal and the output data signal. By determining the output data signal, the return data signal can be expected, that is, the expected data signal corresponding to the output data signal can be determined.

[0066] When the external device transmits a data signal to the interface design module, the interface data monitoring module will monitor the data returned by the interface design module at any time to compare whether the input data signal matches the expected data signal. If the input data signal matches the expected data signal, the transmission of the input data signal can be determined to meet the preset conditions.

[0067] In some embodiments, the interface data monitoring module 30 is used to read an expected data signal matching the output data signal from the non-volatile storage unit;

[0068] In this embodiment, when it is necessary to obtain the expected data signal, the interface data monitoring module accesses the data in the non-volatile storage unit according to the characteristics of the output data signal, and the expected data signal read from the non-volatile storage unit needs to be checked whether the data matches the output data signal. If the data matches the output data signal, the corresponding expected data signal is read.

[0069] In some embodiments, the interface data monitoring module 30 is used to record the delay information corresponding to the preset condition in the non-volatile storage unit if the input data signal meets the preset condition.

[0070] In this embodiment, the interface data monitoring module compares whether the input data signal matches the expected data signal. If the input data signal matches the expected data signal, the input data signal satisfies the preset condition.

[0071] The interface data monitoring module will record the corresponding delay information when the preset conditions are met. The recorded delay information will be saved in the non-volatile storage unit and connected and controlled by the interface data monitoring module. The non-volatile storage unit can still maintain the stored data after power failure, ensuring that the delay information will not be lost due to system restart or power failure. In the event of system failure or abnormality, the system status can be quickly restored by reading the delay information in the non-volatile storage unit.

[0072] The delay control module 40 is connected to the interface data monitoring module and the delay module, and is used to adjust the delay information if the input data signal does not meet the preset condition.

[0073] Figure 3 is a schematic diagram of the delay control module adjusting the delay information provided by the embodiment of the present invention, referring to Figure 3In the clock phase control circuit, the delay control module is connected to the interface data monitoring module and the delay module respectively. The interface data monitoring module will monitor the data returned by the interface design module at any time, and judge whether the input data signal can meet the preset conditions according to the set preset conditions. If the input data signal does not meet the preset conditions, the delay control module will dynamically adjust the delay information until the input data signal meets the preset conditions, then fix the delay information.

[0074] The present invention sends an output data signal and a clock signal to an external device, and determines to adjust the timing and / or phase between the output data signal and the clock signal according to the delay information; receives an input data signal sent by the external device; determines whether the input data signal meets a preset condition; if the input data signal does not meet the preset condition, adjusts the delay information; if the input data signal meets the preset condition, records the delay information corresponding to when the preset condition is met. It can determine whether the input data signal meets the preset condition based on the preset condition, thereby recording the delay information corresponding to when the preset condition is met, and automatically adjusts the timing and phase of the output data and the output clock according to the delay information, reducing the time consumption of manually adjusting the phase, and helping to improve the debugging and testing efficiency.

[0075] In some embodiments, the delay control module 40 is used to read the step control mode and the delay step from the non-volatile storage unit; adjust the delay step according to the step control mode, and write the adjusted delay step into the non-volatile storage unit; wherein the adjusted delay step is greater than the delay step before adjustment.

[0076] In this embodiment, the step control mode is a control method for outputting digital data. Linear control is a control method in which the digital data of the control logic increases according to an arithmetic progression, in which the difference can be 1 or N, etc. Nonlinear control is a control method in which the digital data of the control logic can be 1, 4, 8, 16, etc., which are powers of 2, and other digital change curves output different numbers. Different digital outputs to the delay module will produce different delay effects. The step control mode is a control method in which the digital data is dynamically adjusted according to the system state or external input to improve the adaptability of the system, and can provide a fault-tolerant mechanism to ensure that the system can still operate stably under different conditions.

[0077] The delay control module is connected to the interface data monitoring module, and the step control mode and the delay step can be read from the non-volatile storage unit of the interface data monitoring module. The delay control module adjusts the delay step accordingly according to the acquired step control mode, and dynamically sets the delay step. The adjusted delay step is greater than the delay step before adjustment. After the delay control module completes the adjustment of the delay step, it will write the adjusted delay step into the non-volatile storage unit of the interface data monitoring module. By dynamically adjusting the delay step, the overall performance of the system can be optimized according to the current needs of the system. Under high load conditions, reducing the delay step can speed up data processing and make more efficient use of system resources.

[0078] Figure 4 : is a flow chart of the steps of a phase adjustment method of a controller provided by an embodiment of the present invention, the method comprising:

[0079] Step 201, sending an output data signal and a clock signal to an external device, and adjusting the timing and / or phase between the output data signal and the clock signal according to delay information;

[0080] In this embodiment, the external device interacts with the clock phase control circuit of the present invention. In the controller-based clock phase control circuit, the interface design module can send data signals and clock signals to the external device for transmission.

[0081] Data signals are data that need to be transmitted by various buses and protocols, and are transmitted in the form of signals through the IO ports on the interface design module. The clock signal is a periodic square wave signal. During the data transmission process, when the clock signal reaches the rising edge or falling edge, it means that the data is transferred to the next stage, controlling the rhythm and synchronization of the data transmission process.

[0082] The delay information includes the delay step, which represents the delay time of the signal from low level to high level or from high level to low level. In the clock signal control circuit, the delay module is connected to the interface design module. The delay module can obtain the delay information and dynamically adjust the phase between the data signal and the clock signal according to the obtained information. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, thereby making corresponding adjustments to the timing between the data signal and the clock signal.

[0083] In some embodiments, step 201 may include the following sub-steps:

[0084] Sub-step S11, obtaining the delay step and the mapping relationship between the delay step and the phase delay value;

[0085] The delay step indicates the delay time of the signal from low level to high level or from high level to low level. The phase delay value and the delay step have a clear corresponding relationship. For example, a phase delay value of 1 means a delay of 1us, and a phase delay value of 2 means a delay of 2us; or a phase delay value of 1 means a delay of 1ms, and a phase delay value of 2 means a delay of 2ms, and so on.

[0086] Sub-step S12, determining a phase delay value according to the delay step and a mapping relationship between the delay step and the phase delay value;

[0087] According to the mapping relationship between the delay step and the delay step and the phase delay value, the specific phase delay value during the transmission of the data signal and the clock signal can be determined.

[0088] Sub-step S13, adjusting the timing and / or phase between the output data signal and the clock signal according to the phase delay value;

[0089] According to the determined phase delay value, the phase between the output data signal and the clock signal can be dynamically adjusted, and the specific delay time of the clock phase can be adjusted. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, so as to make corresponding adjustments to the timing between the data signal and the clock signal to ensure the correct transmission and processing of data.

[0090] In this embodiment, the phase delay value and the delay have a clear corresponding relationship. According to the delay step and the mapping relationship between the delay step and the phase delay value, the phase delay value during the transmission of the data signal and the clock signal can be determined. The delay module can dynamically adjust the phase between the output data signal and the clock signal according to the determined phase delay value. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, thereby making corresponding adjustments to the timing between the data signal and the clock signal to ensure the correct transmission and processing of the data.

[0091] Step 202, receiving an input data signal sent by the external device;

[0092] In this embodiment, the external device interacts with the clock phase control circuit. The external device sends an input data signal, and the clock phase control circuit delays the input data signal accordingly.

[0093] Step 203, determining whether the input data signal meets a preset condition;

[0094] In this embodiment, the preset conditions include the synchronization time of the clock signal during the data signal transmission process, and each data transmission period can be guaranteed to remain stable during this time period. When the external device inputs the data signal to the clock phase control circuit, the clock phase control circuit will monitor the data input by the external device at any time, and determine whether the input data signal can meet the preset conditions according to the preset preset conditions.

[0095] In some embodiments, step 203 may include the following sub-steps:

[0096] Sub-step S21, acquiring an expected data signal corresponding to the output data signal;

[0097] The expected data signal can be written through the bus, or can be pre-set and pre-stored in the memory unit. By accessing the memory unit, the corresponding expected data signal can be read.

[0098] Sub-step S22, determining whether the input data signal matches the expected data signal;

[0099] There is a one-to-one correspondence between the pre-stored data signal and the output data signal. By determining the output data signal, the return data signal can be anticipated, that is, the expected data signal corresponding to the output data signal can be determined.

[0100] Sub-step S23: If the input data signal matches the expected data signal, it is determined that a preset condition is satisfied.

[0101] The returned data is monitored to compare whether the input data signal matches the expected data signal. If the input data signal matches the expected data signal, the transmission of the input data signal can be determined to meet the preset condition.

[0102] In this embodiment, the expected data signal is pre-stored in the memory unit of the interface data monitoring. There is a one-to-one correspondence between the pre-stored data signal and the output data signal. By determining the output data signal, the return data signal can be expected, that is, the expected data signal corresponding to the output data signal can be determined. When the external device transmits a data signal to the interface design module, the interface data monitoring module will monitor the data returned by the interface design module at any time to compare whether the input data signal matches the expected data signal. If the input data signal matches the expected data signal, the transmission of the input data signal can be determined to meet the preset conditions.

[0103] Step 204, if the input data signal does not meet the preset condition, adjust the delay information;

[0104] In this embodiment, the returned data is monitored to determine whether the input data signal meets the preset conditions based on the set preset conditions. If the input data signal does not meet the preset conditions, the delay information is dynamically adjusted until the input data signal meets the preset conditions, then the delay information is fixed.

[0105] In some embodiments, step 204 may include the following sub-steps:

[0106] Sub-step S31, obtaining a step length control mode;

[0107] Step control mode is a control method for outputting numbers. For example, linear control means that the numbers of the control logic increase according to an arithmetic progression, where the difference can be 1 or N, etc.; nonlinear control means that the numbers of the control logic can be 1, 4, 8, 16, etc., which are powers of 2, and other digital change curves output different numbers. Different numbers output to the delay module will produce different delay effects.

[0108] Sub-step S32, adjusting the delay step length according to the step length control mode; wherein the delay step length after adjustment is greater than the delay step length before adjustment.

[0109] The delay step is adjusted accordingly according to the acquired step control mode, and the delay step is set dynamically. The adjusted delay step is larger than the delay step before adjustment. After the delay control module completes the delay step adjustment, it will write the adjusted delay step into the non-volatile storage unit of the interface data monitoring module.

[0110] Sub-step S33, when the controller is started next time, read the delay information corresponding to when the preset condition is met, and adjust the timing and / or phase between the output data signal and the clock signal according to the delay information corresponding to when the preset condition is met.

[0111] The preset condition is preset and stored in the non-volatile storage unit. When the controller is started next time and the timing and / or phase between the output data signal and the clock signal need to be adjusted, the non-volatile storage unit is accessed to read the delay information corresponding to the data signal when the preset condition is met from the non-volatile storage unit, and the phase between the data signal and the clock signal is adjusted accordingly based on the acquired delay information. By adjusting the phase between the data signal and the clock signal, the timing adjustment amount corresponding to the phase is obtained, thereby making a corresponding adjustment to the timing between the data signal and the clock signal.

[0112] Step 205: If the input data signal meets a preset condition, the delay information corresponding to the preset condition is recorded.

[0113] The preset conditions include the synchronization time of the clock signal during the data signal transmission process, which can ensure that each data transmission period remains stable during this time period. When the external device transmits the data signal, the returned data will be monitored at any time, and the input data signal will be judged according to the preset conditions to determine whether it meets the preset conditions. If the input data signal meets the preset conditions, the delay information corresponding to the data signal when the preset conditions are met will be recorded.

[0114] It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

[0115] like Figure 5 , showing a structural block diagram of an electronic device provided in an embodiment of the present invention, including:

[0116] It includes a processor, a memory, and a computer program stored in the memory and capable of running on the processor. When the computer program is executed by the processor, the various processes of the phase adjustment method embodiment of the above-mentioned controller are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0117] like Figure 6 , showing that an embodiment of the present invention also provides a structural block diagram of a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the various processes of the phase adjustment method embodiment of the above-mentioned controller are implemented, and the same technical effect can be achieved. To avoid repetition, it will not be repeated here.

[0118] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0119] It will be appreciated by those skilled in the art that the embodiments of the present invention may be provided as methods, devices, or computer program products. Therefore, the embodiments of the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the embodiments of the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program codes.

[0120] The embodiments of the present invention are described with reference to the flowcharts and / or block diagrams of the methods, terminal devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of the processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing terminal device to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing terminal device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0121] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing terminal device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0122] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal device so that a series of operating steps are executed on the computer or other programmable terminal device to produce a computer-implemented process, thereby providing instructions for executing on the computer or other programmable terminal device to implement the process. Figure 1 A process or multiple processes and / or boxes Figure 1 The steps for the functions specified in one or more boxes.

[0123] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the embodiments of the present invention.

[0124] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or terminal device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or terminal device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or terminal device including the elements.

[0125] The controller, the phase adjustment method of the controller, the electronic device and the computer-readable storage medium provided by the present invention are introduced in detail above. The principles and implementation methods of the present invention are explained in this article using specific examples. The description of the above embodiments is only used to help understand the method of the present invention and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present invention, there will be changes in the specific implementation method and application scope. In summary, the content of this specification should not be understood as a limitation on the present invention.

Claims

1. A controller, characterized in that: include: An interface design module, used for sending an output data signal and a clock signal to an external device, and receiving an input data signal sent by the external device in response to the output data signal and the clock signal; A delay module, connected to the interface design module, for adjusting the timing and / or phase between the output data signal and the clock signal according to the delay information; An interface data monitoring module, connected to the interface design module, for determining whether the input data signal meets a preset condition; If the input data signal satisfies the preset condition, then the delay information corresponding to the preset condition is recorded; A delay control module is connected to the interface data monitoring module and the delay module, and is used to adjust the delay information if the input data signal does not meet the preset condition.

2. The controller according to claim 1, characterized in that: The interface data monitoring module is used to obtain an expected data signal corresponding to the output data signal; determine whether the input data signal matches the expected data signal; if the input data signal matches the expected data signal, determine that a preset condition is met.

3. The controller according to claim 1, characterized in that: The interface data monitoring module includes: a non-volatile storage unit; the delay information includes a delay step; The interface data monitoring module is used to read an expected data signal matching the output data signal from the non-volatile storage unit; The delay module is used to read the delay step and the mapping relationship between the delay step and the phase delay value from the non-volatile storage unit, determine the phase delay value according to the delay step and the mapping relationship between the delay step and the phase delay value; and adjust the timing and / or phase between the output data signal and the clock signal according to the phase delay value; The delay control module is used to read the step control mode and the delay step from the non-volatile storage unit; adjust the delay step according to the step control mode, and write the adjusted delay step into the non-volatile storage unit; wherein the adjusted delay step is greater than the delay step before adjustment.

4. The controller according to claim 3, characterized in that: The interface data monitoring module is used to record the delay information corresponding to the preset condition being met in the non-volatile storage unit if the input data signal meets the preset condition.

5. The controller according to claim 4, characterized in that: Also includes: The delay module is used to read the delay information corresponding to the situation where the preset condition is met from the non-volatile storage unit when the controller is started next time, and adjust the timing and / or phase between the output data signal and the clock signal according to the delay information corresponding to the situation where the preset condition is met.

6. A controller phase adjustment method, characterized in that: include: Sending an output data signal and a clock signal to an external device, and adjusting the timing and / or phase between the output data signal and the clock signal according to the delay information; Receiving an input data signal sent by the external device; Determining whether the input data signal meets a preset condition; If the input data signal does not meet the preset condition, adjusting the delay information; If the input data signal satisfies a preset condition, the delay information corresponding to when the preset condition is met is recorded.

7. The method according to claim 6, characterized in that The determining whether the input data signal satisfies a preset condition comprises: Acquire an expected data signal corresponding to the output data signal; Determining whether the input data signal matches the expected data signal; If the input data signal matches the expected data signal, it is determined that a preset condition is met.

8. The method according to claim 6, characterized in that The delay information includes a delay step length; The step of determining and adjusting the timing and / or phase between the output data signal and the clock signal according to the delay information includes: Acquire the delay step and a mapping relationship between the delay step and the phase delay value; Determine the phase delay value according to the delay step and the mapping relationship between the delay step and the phase delay value; According to the phase delay value, adjusting the timing and / or phase between the output data signal and the clock signal; The adjusting the delay information includes: Get the step control mode; The delay step length is adjusted according to the step length control mode; wherein the delay step length after adjustment is greater than the delay step length before adjustment.

9. The method according to claim 6, characterized in that Also includes: When the controller is started next time, the delay information corresponding to when the preset condition is met is read, and the timing and / or phase between the output data signal and the clock signal is adjusted according to the delay information corresponding to when the preset condition is met.

10. An electronic device, characterized in that: include: A processor, a memory, and a computer program stored in the memory and capable of running on the processor, wherein when the computer program is executed by the processor, the steps of the phase adjustment method of the controller as described in any one of claims 6 to 9 are implemented.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps of the phase adjustment method of the controller as described in any one of claims 6 to 9 are implemented.

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