Gate drive circuit and display device

Abstract

The embodiment of the invention relates to a gate driving circuit and a display device. Specifically, in each of at least one compensation period other than a scanning period in which a scanning signal is applied to a plurality of gate lines in a display driving period, a compensation signal corresponding to a change in a gate low voltage in the scanning period is applied to at least one of the plurality of gate lines. Accordingly, it is possible to provide a gate driving circuit and a display device capable of achieving low-power operation and improved image quality by reducing flicker due to a decrease in luminance during low-speed driving.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Korean Patent Application No. 10-2023-0154718, filed on November 9, 2023, and Korean Patent Application No. 10-2024-0101062, filed on July 30, 2024, which are incorporated herein by reference for all purposes as if fully set forth herein. Background Art Technical Field

[0003] Embodiments of the present disclosure relate to a gate driving circuit and a display device.

[0004] Related fields

[0005] As the information society develops, the demand for display devices for displaying images is increasing, and various types of display devices are utilized, such as liquid crystal display devices and organic light emitting display devices.

[0006] Among these display devices, an organic light emitting display device may have advantages in response speed, contrast, light emitting efficiency, brightness, and viewing angle by using an organic light emitting diode having a self-luminous characteristic.

[0007] The organic light emitting display device can control current flowing to an organic light emitting diode (OLED) arranged in each sub-pixel of a display panel to emit light, and controls the brightness displayed by each sub-pixel, thereby being able to display an image.

[0008] Here, current flowing to the organic light emitting diode during a period in which the organic light emitting diode emits light may be weakened due to an off current in a sub-pixel, and brightness displayed by the organic light emitting diode may be reduced due to a reduction in the amount of current driving the organic light emitting diode.

[0009] In particular, if the display device is driven at a low display driving frequency in order to reduce power consumption, the degree of decrease in luminance during the light emission period may increase, and thus there may be a problem that the decrease in luminance may be recognized as flicker. Summary of the invention

[0010] Embodiments of the present disclosure may provide a gate driving circuit and a display device capable of achieving low-power operation and improved image quality by, among other things, reducing flicker due to reduced brightness during low-speed driving.

[0011] Embodiments of the present disclosure may provide a gate driving circuit and a display device capable of high-frequency compensation for a gate low voltage VGL that slightly increases by a predetermined length before and after a turn-on timing of a scan signal during low-speed driving.

[0012] Embodiments of the present disclosure provide a gate driving circuit and a display device capable of improving a phenomenon in which flicker is perceived differently between areas of a display panel through high frequency compensation.

[0013] An embodiment of the present disclosure provides a display device, including: a display panel, on which a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels are arranged; a gate driving circuit, the gate driving circuit is used to provide scanning signals to the plurality of gate lines during a display driving period; and a data driving circuit, the data driving circuit is used to provide data voltages to the plurality of data lines.

[0014] The gate driving circuit can apply a compensation signal corresponding to a change in the gate low voltage within the scanning period to at least one of the multiple gate lines in each compensation period of at least one compensation period other than the scanning period in which the scanning signal is applied to the multiple gate lines during the display driving period.

[0015] According to an embodiment of the present disclosure, a gate drive circuit may include: a buffer circuit, the buffer circuit including a pull-up transistor connected between a first node and a second node and a pull-down transistor connected between a third node and the second node; and a control circuit, the control circuit being configured to control a voltage of a first control node serving as a gate node of the pull-up transistor and a voltage of a second control node serving as a gate node of the pull-down transistor.

[0016] The buffer circuit can output a gate signal to a gate line electrically connected to the second node. One of the first power supply voltage applied to the first node and the second power supply voltage applied to the third node can be a gate low voltage, and the other can be a gate high voltage higher than the gate low voltage.

[0017] The gate low voltage may vary over time between a first voltage level and a second voltage level higher than the first voltage level, and may have the second voltage level during a period in which the gate signal has an on-level voltage.

[0018] The gate signal may include a first signal section having a variable gate high voltage higher than the gate high voltage, a second signal section having a gate low voltage at a second voltage level, and a third signal section having the gate low voltage at the first voltage level.

[0019] A display device according to an embodiment of the present disclosure may include: a display panel on which a plurality of gate lines, a plurality of data lines, and a plurality of sub-pixels are disposed; and a gate driving circuit configured to supply gate signals to the plurality of gate lines.

[0020] The gate driving circuit may provide a gate signal including a first signal segment having a variable gate high voltage higher than the gate high voltage, a second signal segment having a gate low voltage at a second voltage level, and a third signal segment having a gate low voltage at a first voltage level lower than the second voltage level.

[0021] According to the embodiments of the present disclosure, it is possible to provide a gate driving circuit and a display device capable of achieving low-power operation and improved image quality by reducing flickering due to reduced brightness during low-speed driving.

[0022] According to the embodiments of the present disclosure, a gate driving circuit and a display device capable of high-frequency compensation for a gate low voltage VGL slightly increased by a predetermined length before and after a turn-on timing of a scan signal during low-speed driving can be provided.

[0023] According to an embodiment of the present disclosure, a gate driving circuit and a display device capable of improving a phenomenon in which flicker is perceived differently between areas of a display panel through high-frequency compensation may be provided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] Figure 1 is a diagram for explaining a display device according to an embodiment of the present disclosure.

[0025] Figure 2 An example of a sub-pixel SP circuit provided in a display panel according to an embodiment of the present disclosure is shown.

[0026] Figure 3A and Figure 3B 1 is a diagram for explaining operation timings of sub-pixel circuits during a refresh frame period and an anode reset frame period in a display device according to an embodiment of the present disclosure.

[0027] Figure 4A and Figure 4B is a diagram for explaining a phenomenon in which flicker occurs in a display panel according to an embodiment of the present disclosure.

[0028] Figure 5 is a diagram for explaining an example of performing high frequency compensation in the display device according to the embodiment of the present disclosure.

[0029] Figure 6 is a diagram for explaining a high frequency compensation process performed in a display device according to an embodiment of the present disclosure.

[0030] Figure 7 is a diagram for further explaining a high frequency compensation process performed in a display device according to an embodiment of the present disclosure.

[0031] FIG. 8A to FIG. 8Cis a diagram for explaining a result of performing high frequency compensation in the display device according to the embodiment of the present disclosure.

[0032] Fig. 9 2 is a diagram for explaining an implementation example of a display device according to an embodiment of the present disclosure.

[0033] Fig.10 2 is a diagram for explaining an implementation example of a gate driving circuit according to an embodiment of the present disclosure.

[0034] FIG. 11A to FIG. 11D is a diagram for further illustrating a gate driving circuit of a display device according to an embodiment of the present disclosure.

[0035] Fig.12 FIG. 1 is a diagram for explaining an implementation example of a display panel according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0036] In the following description of examples or embodiments of the present disclosure, reference will be made to the accompanying drawings, in which specific examples or embodiments that can be implemented are shown by way of example, and the same reference numerals and symbols may be used in the accompanying drawings to represent the same or similar parts, even if they are shown in different drawings from each other. In addition, in the following description of examples or embodiments of the present disclosure, when it is determined that the detailed description of the well-known functions and components incorporated herein may make the subject matter in certain embodiments of the present disclosure less clear, its detailed description will be omitted. Terms such as "including", "having", "comprising", "consisting of", "composed of", and "formed of" used herein are generally intended to allow the addition of other components unless these terms are used with the term "only". As used herein, the singular form is intended to include the plural form unless the context clearly indicates otherwise.

[0037] Terms such as "first", "second", "A", "B", "(A)" or "(B)" may be used herein to describe elements of the present disclosure. Each of these terms is not used to define the nature, order, sequence or quantity of an element, etc., but is only used to distinguish the corresponding element from other elements.

[0038] When it is mentioned that a first element is “connected or combined”, “contacted or overlapped”, etc. with a second element, it should be understood that the first element and the second element may not only be “directly connected or combined” or “directly contacted or overlapped”, but also a third element may be “interposed” between the first element and the second element, or the first and second elements may be “connected or combined”, “contacted or overlapped”, etc. with each other through a fourth element. Here, the second element may be included in at least one of the two or more elements of “connected or combined”, “contacted or overlapped”, etc.

[0039] When time relative terms (such as "after", "subsequently", "next", "before", etc.) are used to describe a process or operation of an element or configuration, or a flow or step in an operation, process, or manufacturing method, these terms can be used to describe non-sequential or non-sequential processes or operations unless used with the terms "directly" or "immediately".

[0040] In addition, when referring to any dimension, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0041] Hereinafter, various embodiments of the present disclosure will be described in detail with reference to the accompanying drawings.

[0042] Figure 1 is a diagram for explaining a display device according to an embodiment of the present disclosure.

[0043] Reference Figure 1 According to an embodiment of the present disclosure, a display device 100 may include: a display panel 110 including a plurality of sub-pixels SP; and a driving circuit for driving the plurality of sub-pixels SP included in the display panel 110.

[0044] The driving circuit may include a data driving circuit 120 and a gate driving circuit 130 , and may further include a controller 140 for controlling the data driving circuit 120 and the gate driving circuit 130 .

[0045] The display panel 110 may include a substrate SUB and signal lines (eg, a plurality of data lines DL and a plurality of gate lines GL) disposed on the substrate SUB. The plurality of data lines DL and the plurality of gate lines GL may be connected to the plurality of sub-pixels SP.

[0046] The display panel 110 may include a display area DA for displaying an image and a non-display area NDA for not displaying an image. In the display area DA of the display panel 110, a plurality of sub-pixels SP for displaying an image are provided, and in the non-display area NDA, the driving circuits 120, 130, and 140 may be electrically connected or may be installed, and a pad portion connected to an integrated circuit or a printed circuit may be provided.

[0047] The data driving circuit 120 may be a circuit for driving the plurality of data lines DL, and may provide data signals to the plurality of data lines DL.

[0048] The gate driving circuit 130 may be a circuit for driving the plurality of gate lines GL, and may provide gate signals to the plurality of gate lines GL.

[0049] The controller 140 may provide a data control signal DCS to the data driving circuit 120 to control an operation timing of the data driving circuit 120 , and may provide a gate control signal GCS to the gate driving circuit 130 to control an operation timing of the gate driving circuit 130 .

[0050] The controller 140 can start scanning according to the timing of each frame implementation, convert the input image data input from the outside into the data signal format used by the data driving circuit 120, provide the converted image data Data to the data driving circuit 120, and control the data driving at an appropriate time according to the scanning.

[0051] The controller 140 may receive various timing signals including a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK, as well as input image data from the outside (eg, the host system 150 ).

[0052] The controller 140 can receive timing signals such as a vertical synchronization signal VSYNC, a horizontal synchronization signal HSYNC, an input data enable signal DE, and a clock signal CLK to control the data driving circuit 120 and the gate driving circuit 130, generate various control signals DCS and GCS, and output control signals to the data driving circuit 120 and the gate driving circuit 130.

[0053] For example, the controller 140 may output various gate control signals GCS including a gate start pulse GSP, a gate shift clock GSC, and a gate output enable signal GOE to control the gate driving circuit 130 .

[0054] In addition, the controller 140 may output various data control signals DCS including a source start pulse SSP, a source sampling clock SSC, and a source output enable signal SOE to control the data driving circuit 120 .

[0055] The controller 140 may be implemented as a separate component from the data driving circuit 120 , or may be implemented as an integrated circuit by being integrated with the data driving circuit 120 .

[0056] The controller 140 may be a timing controller used in conventional display technology, or may be a control device capable of performing other control functions including a timing controller, may be a control device other than a timing controller, or may be a circuit inside a control device. The controller 140 may be implemented as various circuits or electronic components, such as an integrated circuit (IC), a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), or a processor.

[0057] The display device 100 according to an embodiment of the present disclosure may further include a power management integrated circuit PMIC. For convenience of explanation, the controller 140 and / or the power management integrated circuit PMIC may be described as a driver integrated circuit D-IC hereinafter.

[0058] The data driving circuit 120 may receive the image data Data from the controller 140 and provide data voltages to the plurality of data lines DL, thereby driving the plurality of data lines DL. Here, the data driving circuit 120 may also be referred to as a source driving circuit.

[0059] The data driving circuit 120 may include at least one source driver integrated circuit SDIC.

[0060] Each source driver integrated circuit may include a shift register, a latch circuit, a digital-to-analog converter DAC, and an output buffer. Depending on circumstances, each source driver integrated circuit may further include an analog-to-digital converter ADC.

[0061] For example, each source driver integrated circuit can be connected to the display panel 110 in a tape automated bonding (TAB) manner, can be connected to a bonding pad of the display panel 110 in a chip on glass (COG) or chip on panel (COP) manner, or can be implemented and connected to the display panel 110 in a chip on film (COF) manner.

[0062] The gate driving circuit 130 may output a gate signal of an on voltage level or a gate signal of an off voltage level according to the control of the controller 140. The gate driving circuit 130 may sequentially drive the plurality of gate lines GL by sequentially providing the gate signal of the on voltage level to the plurality of gate lines GL.

[0063] The gate driving circuit 130 according to an embodiment of the present disclosure may provide scan signals (eg, first to third scan signals, etc.) to the plurality of gate lines GL for each preset display driving period D / P.

[0064] For example, the display driving period D / P may be a period corresponding to the driving mode of the display device 100. In addition, if it is assumed that the display device 100 is driven at a low speed of 10 Hz, the display driving period D / P may be set to 10 Hz (ie, 0.1 s).

[0065] The display driving period D / P may include: a scanning period S / P, in which a first scanning signal is applied to the plurality of gate lines GL; and at least one compensation period C / P, in which a compensation signal corresponding to a change in the gate low voltage VGL in the scanning period S / P is applied to at least one gate line among the plurality of gate lines GL.

[0066] The gate driving circuit 130 may be connected to the display panel 110 in a tape automated bonding (TAB) manner, may be connected to a bonding pad of the display panel 110 in a chip on glass (COG) or chip on panel (COP) manner, or may be connected to the display panel 110 in a chip on film (COF) manner. Alternatively, the gate driving circuit 130 may be formed in a non-display area NDA of the display panel 110 in a gate in panel (GIP) type. The gate driving circuit 130 may be disposed on or connected to the substrate SUB. That is, if the gate driving circuit 130 is a GIP type, it may be disposed in the non-display area NDA of the substrate SUB. If the gate driving circuit 130 is a chip on glass (COG) type or a chip on film (COF) type, it may be connected to the substrate SUB.

[0067] The gate driving circuit 130 according to an embodiment of the present disclosure, when implemented as at least one GIP circuit disposed within the display panel 100, can receive a gate voltage and a compensation signal from a driver integrated circuit D-IC disposed outside the display panel 100, and can generate a scan signal based on the gate voltage.

[0068] For example, the gate voltage may include at least one of a gate high voltage VGH and a gate low voltage VGL.

[0069] In addition, the gate voltage may further include at least one of a light emitting high voltage VEH and a light emitting low voltage VEH.

[0070] Here, the driver integrated circuit D-IC may generate a compensation signal based on the gate low voltage VGL and provide the compensation signal to the gate driving circuit 130 .

[0071] On the other hand, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed in the display area DA. For example, at least one of the data driving circuit 120 and the gate driving circuit 130 may be disposed not to overlap with the subpixel SP, or may be disposed to partially or completely overlap with the subpixel SP.

[0072] If the gate line GL selected by the gate driving circuit 130 is driven, the data driving circuit 120 may convert the image data Data received from the controller 140 into an analog data voltage and provide the converted image data to the plurality of data lines DL.

[0073] The data driving circuit 120 may be connected to one side (e.g., the upper side or the lower side) of the display panel 110. The data driving circuit 120 may be connected to both sides (e.g., the upper side and the lower side) of the display panel 110, or may be connected to two or more of the four sides of the display panel 110, depending on a driving method and a panel design method.

[0074] The gate driving circuit 130 may be connected to one side (e.g., the left side or the right side) of the display panel 110. The gate driving circuit 130 may be connected to both sides (e.g., the left side and the right side) of the display panel 110, or may be connected to more than two of the four sides of the display panel 110, depending on the gate driving method and the panel design method.

[0075] The controller 140 may be mounted on a printed circuit board, a flexible printed circuit, or the like, and may be electrically connected to the data driving circuit 120 and the gate driving circuit 130 through the printed circuit board, the flexible printed circuit, or the like.

[0076] The controller 140 can send and receive signals with the data driving circuit 120 according to one or more predefined interfaces. Here, for example, the interface may include a low voltage differential signal (LVDS: Low Voltage Differential Signaling) interface, an embedded clock point-to-point interface (EPI: Embedded Clock Point to Point Interface), a serial peripheral interface (SPI: Serial Peripheral Interface), etc.

[0077] The controller 140 may include one or more storage media, such as registers.

[0078] The display device 100 according to an embodiment of the present disclosure may be a display including a backlight unit, such as a liquid crystal display, or may be a self-luminous display, such as an organic light emitting display, a quantum dot display, an inorganic light emitting display, or the like.

[0079] If the display device 100 is an organic light emitting display device, each sub-pixel SP may include an organic light emitting diode (OLED) that emits light by itself as a light emitting device.

[0080] If the display device 100 is a quantum dot display device, each sub-pixel SP may include a light emitting device made of a quantum dot, which is a semiconductor crystal that emits light by itself.

[0081] If the display device 100 is an inorganic light emitting display device, each sub-pixel SP may include an inorganic light emitting device that emits light by itself and is made of inorganic materials as a light emitting device. For example, an inorganic light emitting device may also be called a micro light emitting diode, and the inorganic light emitting display device may also be called a micro LED display device.

[0082] Figure 2 An example of a sub-pixel SP circuit provided in the display panel 110 according to an embodiment of the present disclosure is shown.

[0083] Reference Figure 2 The sub-pixel SP may include a light emitting device ED and a driving transistor DT configured to drive the light emitting device ED. For example, the light emitting device ED may be an organic light emitting device.

[0084] The sub-pixel SP may further include one or more transistors in addition to the driving transistor DT, and the sub-pixel SP may include one or more oxide semiconductor transistors.

[0085] The sub-pixel SP may include a driving transistor DT and first to sixth transistors T1 to T6 . Each transistor may be a P-type transistor or an N-type transistor.

[0086] The N-type transistor may be an oxide transistor formed using a semiconductor oxide (e.g., a transistor having a channel formed of a semiconductor oxide (e.g., an oxide of indium, gallium, zinc, or IGZO)). The P-type transistor may be a silicon transistor formed of a semiconductor (e.g., silicon) (e.g., a transistor having a polysilicon channel formed using a low temperature process, which is called LTPS or low temperature polysilicon).

[0087] Oxide transistors have a relatively small leakage current compared to silicon transistors, so they are relatively advantageous in achieving low refresh frame rates.

[0088] The subpixel SP may further include a storage capacitor Cstg configured to apply the high potential driving voltage VDD applied from the high potential driving voltage line VDDL to the gate node of the driving transistor DT for one frame period.

[0089] like Figure 2As shown, the structure of the sub-pixel SP including seven transistors and one capacitor may be referred to as a 7T1C structure.

[0090] In the following, for ease of explanation, the structure of the sub-pixel SP is taken as a 7T1C structure as an example, but the embodiments of the present disclosure are not limited thereto and can be easily applied to sub-pixel circuits of various structures such as a 3T1C structure and an 8TO2 structure (e.g., LTPS TFT+oxide TFT).

[0091] That is, even if the structure of the sub-pixel SP is a 7T1C structure, the structure of the sub-pixel SP may be designed in various ways according to the arrangement of transistors and capacitors.

[0092] One end of the storage capacitor Cstg may be electrically connected to the second node N2 of the driving transistor DT, and the other end may be electrically connected to the high potential driving voltage line VDDL. The other end of the storage capacitor Cstg may be electrically connected to the source node or the drain node of the third transistor T3. The second node N2 of the driving transistor DT may be the gate node of the driving transistor DT.

[0093] The first transistor T1 may be electrically connected between the second node N2 and the third node N3 of the driving transistor DT. The operation timing of the third transistor T3 may be controlled by the first scan signal Scan1[n] applied from the first scan signal line SCL1 (where n is a positive integer). The third node N3 of the driving transistor DT may be a source node or a drain node of the driving transistor DT.

[0094] The first transistor T1 may be an oxide transistor. Due to the low leakage current characteristic of the oxide transistor, the voltage level of the second node N2 of the driving transistor DT may be kept constant. Therefore, even if the data voltage Vdata for image display is not applied for each frame, the sub-pixel SP may display an image according to the data voltage Vdata inputted in the previous frame.

[0095] The second transistor T2 may be configured to switch the electrical connection between the first node N1 of the driving transistor DT and the data line DL. The first node N1 of the driving transistor DT may be the other of the source node or the drain node of the driving transistor DT. The operation timing of the second transistor T2 may be controlled by the second scan signal Scan2[n] applied from the second scan signal line SCL2. When the second scan signal Scan2[n] of the turn-on voltage level is applied to the second transistor T2, the data voltage Vdata may be applied from the data line DL to the first node N1 of the driving transistor DT.

[0096] The third transistor T3 may be configured to switch the electrical connection between the first node N1 of the driving transistor DT and the high potential driving voltage line VDDL. The operation timing of the third transistor T3 may be controlled by the third light emitting control signal EM[n+2] applied from the third light emitting control signal line EML3. When the third light emitting control signal EM[n+2] of the turn-on voltage level is applied to the third transistor T3, the high potential driving voltage VDD may be applied to the first node N1 of the driving transistor DT.

[0097] The fourth transistor T4 may be configured to switch electrical connection between the third node N3 of the driving transistor DT and the first electrode of the light emitting device ED. Operation timing of the fourth transistor T4 may be controlled by the first light emitting control signal EM[n] applied from the first light emitting control signal line EML1.

[0098] The fourth transistor T4 may include a fourth node N4 , and the fourth node N4 of the fourth transistor T4 may be electrically connected to the first electrode of the light emitting device ED.

[0099] The fourth node N4 of the fourth transistor T4 may be a source node of the fourth transistor T4 or a drain node of the fourth transistor T4. The first electrode of the light emitting device ED may be an anode or a cathode. Hereinafter, it will be described assuming that the first electrode of the light emitting device ED is an anode.

[0100] The fifth transistor T5 can be configured to switch the electrical connection between the third node N3 of the driving transistor DT and the initialization voltage line VINIL. The driving timing of the fifth transistor T5 can be controlled by the third scan signal Scan3[n]. When the third scan signal Scan3[n] of the on voltage level is applied, the initialization voltage Vini[n] can be applied from the initialization voltage line VINIL to the third node N3 of the driving transistor DT.

[0101] The sixth transistor T6 may be configured to switch the electrical connection between the first electrode of the light emitting device ED and the reset voltage line VARL. If the first electrode of the light emitting device ED is an anode, the reset voltage VAR applied from the reset voltage line VARL may be an anode reset voltage.

[0102] The operation timing of the sixth transistor T6 may be controlled by the second light emitting control signal EM[n+1] applied from the second light emitting control signal line EML2.

[0103] According to an embodiment of the present disclosure, the gate driving circuit 130 can generate a plurality of scan signals including a first scan signal Scan1[n], a second scan signal Scan2[n] and a third scan signal Scan3[n] and a plurality of light-emitting control signals including a first light-emitting control signal EM[n], a second light-emitting control signal EM[n+1] and a third light-emitting control signal EM[n+2], and can provide each of the plurality of scan signals and the plurality of light-emitting control signals to at least one corresponding sub-pixel among a plurality of sub-pixels SP.

[0104] The first electrode of the light emitting device ED may be electrically connected to the fourth node N4 of the fourth transistor T4, and the second electrode may be electrically connected to a low potential driving voltage line VSSL to which a low potential driving voltage VSS is applied. The first electrode of the light emitting device ED may be an anode AND or a cathode CAT, and the second electrode may be the other of the anode AND or the cathode CAT. The light emitting device ED may further include a light emitting layer EL disposed between the anode AND and the cathode CAT.

[0105] The high potential driving voltage line VDDL and the low potential driving voltage line VSSL may be common voltage lines commonly connected to a plurality of sub-pixels SP arranged on the display panel 110 .

[0106] Reference Figure 2 , the first transistor T1 and the sixth transistor T6 may be N-type transistors, and the driving transistor DT, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be P-type transistors.

[0107] However, the embodiments of the present disclosure are not limited thereto, and at least one of the first transistor T1 and the sixth transistor T6 may be configured as a P-type transistor, or at least one of the driving transistor DT, the second transistor T2, the third transistor T3, the fourth transistor T4, and the fifth transistor T5 may be configured as an N-type transistor.

[0108] Figure 3A and Figure 3B 1 is a diagram for explaining operation timings of a sub-pixel SP circuit during a refresh frame R / F period and an anode reset frame AR period in the display device 100 according to an embodiment of the present disclosure.

[0109] Specifically, Figure 3A 1 shows an operation timing diagram of the sub-pixel SP circuit during the refresh frame R / F period, Figure 3B FIG. 1 shows an operation timing diagram of the sub-pixel SP circuit during the anode reset frame AR period. Figure 2 The operation timing of the sub-pixel SP according to the refresh frame R / F period and the anode reset frame AR period is described below.

[0110] Reference Figure 3A , the refresh frame R / F period may include: a first on bias period OBS1 and a second on bias period OBS2 configured to apply an initialization voltage DVINI of a high voltage level to a third node N3 of the driving transistor DT; and a sampling period configured to apply a voltage corresponding to the data voltage Vdata to a second node N2 of the driving transistor DT. Here, the initialization voltage DVINI may be a DC voltage.

[0111] The on-bias periods OBS1 and OBS2 may be periods set to alleviate a hysteresis effect that may occur in the driving transistor DT and improve response characteristics.

[0112] During the sampling period, the third light emitting control signal EM[n+2] of the cut-off voltage level may be applied to the third transistor T3, the first light emitting control signal EM[n] of the cut-off voltage level may be applied to the fourth transistor T4, the third scan signal SCAN3[n] of the cut-off voltage level may be applied to the fifth transistor T5, and the second light emitting control signal EM[n+1] of the cut-off voltage level may be applied to the sixth transistor T6.

[0113] During the sampling period, a first scan signal SCAN1 [n] of a turn-on voltage level may be applied to the first transistor T1 , and a second scan signal SCAN2 [n] of a turn-on voltage level may be applied to the second transistor T2 .

[0114] According to one embodiment of the present disclosure, during the process of applying the first scan signal SCAN1[n] of the on-voltage level to the first scan node (i.e., the gate node of the first transistor T1) during the sampling period, a phenomenon in which the gate low voltage VGL slightly increases or rises may occur. In response to this, the gate drive circuit 130 can provide a compensation signal corresponding to the increased gate low voltage level (e.g., the VGL rising level) that has been raised at the first scan node during multiple compensation periods C / P after the sampling period.

[0115] That is, the gate driving circuit 130 may apply the first scan signal SCAN1[n] and the compensation signal to the gate node of the first transistor at different times.

[0116] For example, when the level of the first scan signal SCAN1[n] (ie, the gate high voltage VGH) is 10V, the increased gate low voltage level (eg, the VGL rising level) may be 150mV or less.

[0117] Reference Figure 3A, when the first transistor T1 is turned on during the sampling period, the third node N3 and the second node N2 of the driving transistor DT may be electrically connected, and a voltage of an on level may be applied to the second node N2 of the driving transistor DT.

[0118] During the sampling period, if the driving transistor DT, the first transistor T1 and the second transistor T2 are turned on, a voltage corresponding to the data voltage Vdata may be applied to the second node N2 of the driving transistor DT and thus may be applied to one end of the storage capacitor Cstg.

[0119] Reference Figure 3B During the anode reset frame AR period, the third light emitting control signal EM[n+2] of the turn-off voltage level may be applied to the third transistor T3, and the first light emitting control signal EM[n] of the turn-off voltage level may be applied to the fourth transistor T4.

[0120] A first scan signal Scan1[n] of a turn-off voltage level may be applied to the first transistor T1. A second scan signal Scan2[n] of a turn-off voltage level may be applied to the second transistor T2. A second light emission control signal EM[n+1] of a turn-on voltage level may be applied to the sixth transistor T6.

[0121] On the other hand, the third scan signal Scan3[n] may be applied to the fifth transistor T5 and may have at least one on-level voltage and at least one off-level voltage during the anode reset frame AR period.

[0122] When the third scan signal Scan3[n] is at the on voltage level, the fifth transistor T5 is turned on, and the initialization voltage DVINI of a high level voltage may be applied to the third node N3 of the driving transistor DT.

[0123] During the anode reset frame AR period, a period in which the initialization voltage DVINI of a high level voltage is applied to the third node N3 of the driving transistor DT may be a third on-bias period OBS3 and a fourth on-bias period OBS4 .

[0124] When the second light emitting control signal EM[n+1] is a turn-on level voltage, the sixth transistor T6 may be turned on, and the anode reset voltage VAR may be applied to the first electrode of the light emitting device ED.

[0125] Figure 4A and Figure 4B is a diagram for explaining a phenomenon in which flicker occurs in the display panel 110 according to an embodiment of the present disclosure.

[0126] Hereinafter, a case where the gate driving circuit 130 is a GIP circuit GIPC is exemplified, but the embodiments of the present disclosure are not limited thereto.

[0127] In addition, for the convenience of description, a case where the display panel 110 is divided into an upper area Top, a middle area Middle, and a lower area Bottom according to positions is illustrated.

[0128] For example, if it is assumed that a plurality of gate lines GL are connected by Figure 1 In the plan view, the upper area Top may refer to an area in which the first gate line to the kth gate line (wherein k is a positive integer greater than 2) are arranged in sequence in the -y-axis direction.

[0129] In addition, the middle area Middle may refer to the area in which the k+1th gate line to the lth gate line (where l is a positive integer satisfying the condition l>k+1) are set, and the bottom area Bottom may refer to the area in which the l+1th gate line to the mth gate line (where m is a positive integer satisfying the condition m>l+1) are set.

[0130] Reference Figure 4A According to an embodiment of the present disclosure, the gate driving circuit 130 (eg, GIPC) may provide a first scan signal Scan1[n] to a gate node (ie, a first scan node) of a first transistor T1 of a sub-pixel SP through a gate line GL.

[0131] In this case, if the display device 100 is driven at a low speed (for example, driven at 10 Hz), due to a parasitic capacitor (for example, Para. Cap) formed between the second node N2 and the gate node of the first transistor, a period (hereinafter referred to as a low voltage rising period) in which the gate low voltage VGL slightly rises or increases at the gate node of the first transistor T1 may occur before and after the turn-on moment of the first scan signal SCAN1[N], and the period lasts for a predetermined length, for example, a length of 120 Hz.

[0132] Reference Figure 4B , a low voltage rising period (e.g., VGL Rising) may occur during a scanning period S / P in which the first scanning signal SCAN1[N] is sequentially applied to each of the plurality of gate lines GL. In this case, the scanning period S / P may include a refresh frame R / F period corresponding to the moment when the first scanning signal SCAN1[N] is applied, and at least one anode reset frame AR period.

[0133] Reference Figure 4BThe low voltage rising period (ie, VGL Rising) may affect the gate node (ie, the second node N2) of the driving transistor DT, so that a phenomenon in which brightness or luminance slightly decreases during the low voltage rising period (ie, VGL Rising) may occur.

[0134] Specifically, in the display panel 110, since the first scan signal SCAN1[N] is applied to each of the multiple gate lines GL at different times, a phenomenon of slight decrease in brightness at different positions in the upper area Top, middle area Middle and lower area Bottom of the panel may occur, which may cause the flicker to be dispersed by position.

[0135] Therefore, the gate driving circuit 130 according to an embodiment of the present disclosure can provide a compensation signal corresponding to an increased gate low voltage level in a low voltage rising period (i.e., VGL Rising) during multiple compensation periods different from the low voltage rising period (i.e., VGL Rising), thereby minimizing the occurrence of flicker.

[0136] Figure 5 is a diagram for explaining an example of performing high frequency compensation in the display device 100 according to an embodiment of the present disclosure.

[0137] Reference Figure 5 The gate driving circuit 130 may be composed of at least one GIP circuit GIPC, and may apply a compensation signal corresponding to the scanning period to at least one gate line among the multiple gate lines GL in each compensation period C / P of at least one compensation period C / P except for a scanning period S / P in which the first scanning signal Scan1[n] is applied to the multiple gate lines GL during the display driving period D / P.

[0138] For example, the gate driving circuit 130 may generate a first scan signal Scan1[n] using a gate voltage and a gate control signal received from a driver integrated circuit D-IC located outside the display panel 110, and may sequentially apply the first scan signal Scan1[n] to a plurality of gate lines GL during a scan period S / P.

[0139] In addition, the gate driving circuit 130 can receive a compensation signal corresponding to the gate low voltage VGL that is slightly increased due to the influence of the parasitic capacitor during the low voltage rising period (i.e., VGL Rising) from a driver integrated circuit D-IC located outside the display panel 110, and can apply the compensation signal in each remaining period except the scanning period S / P in the display driving period D / P (i.e., in each compensation period of at least one compensation period C / P).

[0140] For example, the driver integrated circuit D-IC may determine an intermediate value of the increased gate low voltage levels within the scan period S / P of the plurality of gate lines GL as the voltage level of the compensation signal, and may generate the compensation signal by adjusting the first gate low voltage VGL whose voltage level is not increased according to the intermediate value.

[0141] For example, the increased gate low voltage level within the scanning period S / P may be slightly different for each of the multiple gate lines GL (i.e., each position), and the driver integrated circuit D-IC can pre-calculate the increased gate low voltage level within the scanning period S / P for each of the multiple gate lines GL or each preset area of ​​the display panel 110, and determine the middle value (or average value) of the calculated voltage levels as the voltage level of the compensation signal.

[0142] For a more specific example, assuming that the increased gate low voltage level in the upper area Top of the display panel 110 is 110mV, the gate low voltage level in the middle area Middle is 100mV and the gate low voltage level in the lower area Bottom is 90mV, the voltage level of the compensation signal can be determined to be 100mV.

[0143] That is, the display device 100 according to an embodiment of the present disclosure can compensate for the increased gate low voltage within the scanning period S / P by applying a compensation signal within the compensation period C / P which is different from the scanning period S / P, thereby reducing the flicker and minimizing the flicker deviation between the upper area Top, the middle area Middle and the lower area Bottom of the display panel 110.

[0144] Figure 6 is a diagram for explaining a high frequency compensation process performed in a display device according to an embodiment of the present disclosure.

[0145] Reference Figure 6 The gate driving circuit 130 may generate and output a first scanning signal Scan1[n] (eg, a first scanning signal Scan1[n]) to be applied to at least one gate line among the plurality of gate lines GL during a scanning period S / P in a preset display driving period D / P. Figure 6 'Scan1' in the command output).

[0146] The scanning period S / P may include: a low voltage rising period (VGL Rising), in which the gate low voltage VGL applied to the gate node (i.e., the first scanning node) of the first transistor T1 slightly rises before and after the moment when the scanning signal is applied to the plurality of gate lines due to the influence of a parasitic capacitor formed between the second node (N2) of the sub-pixel SP and the gate node of the first transistor T1; and a blank period (Blank) having a predetermined length after the low voltage rising period.

[0147] The gate driving circuit 130 may receive a compensation signal corresponding to the gate low voltage increased during the low voltage rising period (VGL Rising) (ie, Figure 6 Here, the compensation signal may refer to a gate low voltage increased by a predetermined voltage from an initial gate low voltage, and more specifically, may refer to a toggle having a voltage level corresponding to the level of the gate low voltage VGL increased in the low voltage rising period (VGL Rising).

[0148] The gate driving circuit 130 may apply a compensation signal to the gate node of the first transistor T1 in each preset compensation period C / P during the display driving period D / P.

[0149] The first transistor T1 may be a transistor capable of controlling the connection between the second node N2 and the third node N3 of the driving transistor DT by being turned on or off according to the first scan signal Scan1[n]. The second node N2 of the driving transistor DT may be a gate node, and the third node N3 of the driving transistor DT may be a drain node or a source node.

[0150] For example, the gate driving circuit 130 may include a plurality of sub gate driving circuits that generate various types of gate signals provided to the sub-pixels SP provided in the display panel 110 .

[0151] For example, if the sub-pixel SP has Figure 2 According to the circuit structure shown, the multiple sub-gate driving circuits included in the gate driving circuit 130 may include a first scanning driver SCD1 providing a first scanning signal, a second scanning driver SCD2 providing a second scanning signal, a third scanning driver SCD3 providing a third scanning signal, and a light-emitting control driver EMD providing a light-emitting control signal.

[0152] In addition, the gate driving circuit 130 may be configured in multiple stages, and the first scan driver SCD1 , the second scan driver SCD2 , the third scan driver SCD3 , and the light emission control driver EMD may be respectively provided in at least one of the multiple stages.

[0153] The first scan driver SCD1 provided in the nth stage may output a compensation signal to the first scan line SCL1 during the compensation period C / P of the display driving period D / P. Here, the compensation signal may be a first scan signal Scan1[n], and may be a signal having a gate low voltage increased by a predetermined voltage compared to an initial gate low voltage.

[0154] The second scan driver SCD2 provided in the nth stage may generate a second scan signal Scan2[n] output to the second scan line SCL2, and the third scan driver SCD3 provided in the nth stage may generate a third scan signal Scan3[n] output to the third scan line SCL3.

[0155] The light-emitting control driver EMD equipped in the nth stage can generate a first light-emitting control signal EM[n] output to the first light-emitting control signal line EML1, the light-emitting control driver EMD equipped in the (n+1)th stage can generate a second light-emitting control signal EM[n+1] output to the second light-emitting control signal line EML2, and the light-emitting control driver EMD equipped in the (n+2)th stage can generate a third light-emitting control signal EM[n+2] output to the third light-emitting control signal line EML3.

[0156] The compensation period C / P may include a compensation signal application period for applying a compensation signal and a blank period (Blank) having a predetermined length after the compensation signal application period, and the blank period included in the scanning period S / P and the blank period included in each compensation period C / P may be set to have the same length.

[0157] That is, the gate driving circuit 130 may apply the first scanning signal Scan1[n] of the gate high voltage VGH level to the gate node of the first transistor T1 during the scanning period S / P of the display driving period D / P, and may apply the compensation signal to the gate node of the first transistor T1 during each compensation period C / P except the scanning period S / P, thereby compensating for the increased gate low voltage VGL (i.e., Figure 6 'CompensationScan1' in the

[0158] Hereinafter, a low voltage rising period (VGL Rising) may be described as a first signal section S1 , a blank period may be described as a second signal section S2 , and a period for applying a compensation signal may be described as a third signal section S3 .

[0159] In addition, the initial gate low voltage may be described as a gate low voltage VGL1 of a first voltage level, and the increased gate low voltage (or compensation signal) may be described as a gate low voltage VGL2 of a second voltage level. In this case, the gate low voltage VGL1 of the first voltage level may refer to a voltage of a level lower than the gate low voltage VGL2 of the second voltage level.

[0160] Reference Figure 6 , the first signal segment S1 may be a signal segment having a variable gate high voltage VGH_R higher than an initial gate high voltage, the second signal segment S2 may be a signal segment having a gate low voltage VGL2 of a second voltage level, and the third signal segment S3 may be a signal segment having a gate low voltage VGL1 of a first voltage level.

[0161] A voltage difference between the variable gate high voltage VGH_R and the initial gate high voltage may correspond to a difference between the second voltage level and the first voltage level (ie, VGL2 − VGL1 ).

[0162] Figure 7 is a diagram for further explaining a high frequency compensation process performed in a display device according to an embodiment of the present disclosure.

[0163] Reference Figure 7 The length of the display driving period D / P can be set to L1, and the length of the scanning period S / P can be set to L2. For example, L1 can be 10 Hz (0.1 s), and L2 can be 120 Hz (about 0.00833 s).

[0164] Specifically, the display device 100 can perform low-speed driving of 10 Hz to achieve low power. In this case, within the display drive period D / P, a total of 11 (i.e., 12-1 (scanning period)) compensation toggles (i.e., compensation signals) can be applied based on the value obtained by dividing the length of the display drive period D / P by the length of the scanning period S / P.

[0165] Similarly, if the display device 100 is driven at a low speed of 24 Hz, the length of the display drive period D / P can be set to 24 Hz (approximately 0.0417 s), and the length of the scanning period S / P can be set to 120 Hz (i.e., approximately 0.00833 s), so a total of 4 (i.e., 5-1 (scanning period)) compensation switches (i.e., compensation signals) can be applied within the display drive period D / P.

[0166] That is, the length of the scanning period S / P and the length of the compensation period C / P in the display driving period D / P can be set to be the same. For example, the length of the scanning period S / P and the length of the compensation period C / P can be set to be the same as 120 Hz, including the blank period.

[0167] FIG. 8A to FIG. 8C is a diagram for explaining a result of performing high frequency compensation in the display device according to the embodiment of the present disclosure.

[0168] Specifically, Fig. 8A is a diagram illustrating flicker perception characteristics of a user, and shows a flicker perception value of a user according to a change in frequency.

[0169] Figure 8B It is related to the verification result through the unit driving test, and the flicker test results by the position (eg, Top, Middle, Bottom) of the display panel 110 are shown.

[0170] Figure 8B and Figure 8C The "flicker" shown is related to the flicker value, and more specifically, may refer to a value obtained according to the difference in brightness waveform between the refresh period and the hold period when the display device 100 is driven at a specific frequency (e.g., 10 Hz). In addition, here, factors according to the flicker position deviation may be design factors such as the difference in Vobs voltage and the rise of the gate low voltage (i.e., VGL Rising), as well as driving factors such as voltage / time optimization and gate low voltage compensation (i.e., VGL compensation).

[0171] Figure 8C The flicker simulation results are shown according to the positions (eg, Top, Middle, Bottom) of the display panel 110. Here, "Vobs" may refer to an on-bias-stress (OBS) voltage.

[0172] Reference Fig. 8A It has been confirmed that when the display device 100 is driven at a low speed, the user is likely to feel the flicker within the screen, and specifically, it has been confirmed that when driven at a low speed of 10 Hz, the user is likely to feel the flicker.

[0173] Reference Figure 8B and Figure 8C, since the voltage level of the gate low voltage VGL rises at the gate node (i.e., the first scanning node) of the first transistor T1 in the sub-pixel SP when the display device 100 is driven at a low speed (e.g., driven at 10 Hz), a flicker value dB that the user can perceive at various positions (e.g., Top, Middle, Bottom) of the display panel 110 is presented. However, if high-frequency compensation is applied, it has been confirmed that the flicker value dB at various positions (e.g., Top, Middle, Bottom) may be reduced.

[0174] That is, the display device 100 according to an embodiment of the present disclosure can compensate for the voltage level rising phenomenon (i.e., VGL Rising) of the gate low voltage VGL by applying a high-frequency input signal (i.e., compensation signal), thereby minimizing the flicker deviation according to the position (e.g., Top, Middle, Bottom) of the display panel 110.

[0175] Specifically, assuming that the gate driving circuit 130 performs low-speed driving at 10 Hz, the first scan signal Scan1[n] including the increased gate low voltage VGL and the 120 Hz high-frequency compensation signal (including the blank period) provided from the driver integrated circuit D-IC can be applied to the display panel 110. Through the high-frequency compensation process, the 10 Hz flicker component can be moved to the 120 Hz frequency band, and the flicker component moved to 120 Hz may be attenuated due to the user's perception of the flicker.

[0176] Reference Figure 8B and 8C , although the flicker and the VOBS voltage are different from each other according to the position (eg, Top, Middle, Bottom) of the display panel 110, it has been confirmed that the flicker phenomenon and uniformity are improved after the high frequency compensation.

[0177] Fig. 9 1 is a diagram for explaining an implementation example of the display device 100 according to an embodiment of the present disclosure.

[0178] Reference Fig. 9 , the display panel 110 may include a display area DA where an image is displayed and a non-display area NDA where no image is displayed.

[0179] The display area DA may be a region capable of displaying an image, and may also be referred to as an active region. A plurality of sub-pixels SP for displaying an image may be disposed in the display area DA.

[0180] The non-display area NDA may be an area where no image is displayed, and may be an outer area of ​​the display area DA. The non-display area NDA may also be referred to as a frame (or frame area). The non-display area NDA may include a pad area.

[0181] For example, the non-display area NDA may include a first non-display area, a second non-display area, a third non-display area, and a fourth non-display area. The first non-display area may be located outside the display area DA in the row direction. The second non-display area may be located outside the display area DA in the row direction and may be located on the opposite side of the first non-display area. The third non-display area may be located outside the display area DA in the column direction. The fourth non-display area may be located outside the display area DA in the column direction and may be located on the opposite side of the third non-display area.

[0182] In the first non-display area to the fourth non-display area, the fourth non-display area may include a pad area connected or bonded (or combined) to the driving circuit, and the first non-display area to the third non-display area may have a very small size, but the embodiments of the present disclosure are not limited thereto.

[0183] For another example, a boundary area between the display area DA and the non-display area NDA may be bent so that the non-display area NDA may be located below the display area DA.

[0184] When the user views the display device 100 from the front, the user may hardly see the non-display area NDA or may not see the non-display area NDA, but embodiments of the present disclosure are not limited thereto.

[0185] according to Fig. 9 For example, the data driving circuit 120 may receive image data DATA in digital form from the controller 140, convert the received image data DATA into analog data signals (or also referred to as data voltages), and output the converted image data to a plurality of data lines DL.

[0186] The data driving circuit 120 can be connected to the display panel 110 in a tape-automated-bonding (TAB) manner, can be connected to the bonding pads of the display panel 110 in a chip-on-glass (COG) or chip-on-panel (COP) manner, or can be implemented and connected to the display panel 110 in a chip-on-film (COF) manner, but is not limited thereto.

[0187] The gate driving circuit 130 may be implemented as a gate-in-panel (GIP) type, and may be formed in the non-display area NDA of the display panel 110. The gate driving panel circuit 130 may be disposed in both the non-display area NDA located at one outer side of the display area DA and the non-display area NDA located at the other outer side of the display area DA, but the embodiments of the present disclosure are not limited thereto, and the gate driving circuit 130 may be disposed in only one of the non-display area NDA located at one outer side of the display area DA and the non-display area NDA located at the other outer side of the display area DA.

[0188] As another example, the gate drive circuit 130 may be disposed in the display area DA of the display panel 110. As an example, the gate drive circuit 130 may be disposed in a first partial area within the display area DA (e.g., a left area or a right area within the display area DA). As another example, the gate drive circuit 130 may be disposed in a first partial area within the display area DA (e.g., a left area or a right area within the display area DA) and a second partial area (e.g., a right area or a left area within the display area DA). As another example, the gate drive circuit 130 may be disposed over the entire area of ​​the display area DA.

[0189] If the gate driving circuit 130 is disposed in the display area DA of the display panel 110 , the gate driving circuit 130 may overlap the sub-pixels SP disposed in the display area DA in a vertical direction.

[0190] For example, the gate drive circuit 130 may overlap the light emitting devices and transistors included in the sub-pixels SP provided in the display area DA in the vertical direction. The gate drive circuit 130 may overlap the light emitting devices and transistors included in the multiple sub-pixels SP provided in the display area DA in the vertical direction. The gate drive circuit 130 may include multiple transistors. Each of the multiple transistors included in the gate drive circuit 130 may include an active layer including a first semiconductor material, and each of the multiple transistors included in the sub-pixels SP may include an active layer including a second semiconductor material. As an example, the first semiconductor material and the second semiconductor material may be substantially the same. As another example, the first semiconductor material and the second semiconductor material may be different from each other. For example, the first semiconductor material may be a silicon-based semiconductor material (e.g., low temperature polycrystalline silicon (LTPS)), and the second semiconductor material may be an oxide semiconductor material. For example, the active layer may be a semiconductor layer, but is not limited thereto.

[0191] The controller 140 may be connected to the host system 150 , may perform an overall control function related to driving the display panel 110 , and may control operations of the data driving circuit 120 and the gate driving circuit 130 .

[0192] The display device 100 may further include a power management integrated circuit, and the power management integrated circuit may provide various voltages or currents to the data driving circuit 120 and the gate driving circuit 130 or control the various voltages or currents to be provided.

[0193] Hereinafter, for convenience of explanation, the controller 140 and / or the power management integrated circuit PMIC may be described as a driver integrated circuit D-IC.

[0194] The controller 140 of the display device 100 according to an embodiment of the present disclosure may output a gate control signal GCS for gate driving to the gate driving circuit 130 (eg, a plurality of GIP circuits GIPC).

[0195] For example, the gate driving circuit 130 can generate multiple gate signals (e.g., scan signals, light emitting control signals, etc.) based on the gate control signal GCS received from the controller 140 and the gate voltage received from the power management integrated circuit, and output the generated gate signals to multiple gate lines GL respectively.

[0196] On the other hand, the gate driving circuit 130 according to an embodiment of the present disclosure may receive a gate control signal, a gate voltage, and a compensation signal from a driver integrated circuit D-IC disposed outside the display panel 110 .

[0197] The gate voltage may include at least one of a gate high voltage VGH and a gate low voltage VGL, and the gate voltage may further include at least one of a light emitting high voltage VEH and a light emitting low voltage VEL.

[0198] For example, the gate driving circuit 130 may receive the gate high voltage VGH and the light emission high voltage VEH through a high level gate voltage line, and may receive the gate low voltage VGL and the light emission low voltage VEL through a low level gate voltage line.

[0199] The compensation signal may be a signal generated in response to a change in the gate low voltage VGL within the scan period S / P during the display driving period D / P.

[0200] The gate driving circuit 130 may generate a scan signal based on at least one of the gate high voltage VGH and the gate low voltage VGL and the gate control signal. For example, the scan signal Scan may include at least one of the first scan signal Scan1[n], the second scan signal Scan2[n], and the third scan signal Scan3[n].

[0201] The gate driving circuit 130 may generate a light emitting control signal EM based on at least one of the light emitting high voltage VEH and the light emitting low voltage VEL and a gate control signal.

[0202] The gate driving circuit 130 may output a scan signal and a light emitting control signal to at least one gate line GL among the plurality of gate lines GL at corresponding timings based on the gate control signal.

[0203] The gate driving circuit 130 can output a first scanning signal Scan1[n] to at least one gate line GL among the plurality of gate lines GL in a scanning period S / P in a display driving period D / P based on a gate control signal, and can output a compensation signal in at least one compensation period C / P other than the scanning period S / P in the display driving period D / P.

[0204] The gate driving circuit 130 may include at least one of a first scan driver SCD1, a second scan driver SCD2, a third scan driver SCD3, and a light emission control driver EMD, which will be referred to later. FIG. 11A to FIG. 11D The first scan driver SCD1, the second scan driver SCD2, the third scan driver SCD3, and the light emission control driver EMD are described in more detail.

[0205] Fig.10 1 is a diagram for explaining an implementation example of the gate driving circuit 130 according to an embodiment of the present disclosure.

[0206] Reference Fig.10 The gate driving circuit 130 may include a plurality of GIP circuits GIPC. The plurality of GIP circuits GIPC may be disposed in the non-display area NDA corresponding to each of the plurality of stages STG.

[0207] For example, the plurality of GIP circuits GIPC may include a GIP circuit GIPC disposed in a left non-display area NDA and a GIP circuit GIPC disposed in a right non-display area NDA based on a display area DA corresponding to each of the plurality of stages STG, but is not limited thereto. In addition, the GIP circuit GIPC may be disposed only in the non-display area NDA corresponding to the left or right side of the display area DA.

[0208] Each of the plurality of GIP circuits GIPC may include at least one of a first scan driver SCD1 , a second scan driver SCD2 , a third scan driver SCD3 , and a light emission control driver EMD.

[0209] according to Fig.10For example, the GIP circuit GIPC disposed in the left non-display area NDA may have a first scan driver SCD1 and a second scan driver SCD2 disposed in an area close to the display area DA, and a light emission control driver EMD disposed in an area far from the display area DA.

[0210] The GIP circuit GIPC disposed in the right non-display area NDA may have second and third scan drivers SCD2 and SCD3 disposed in an area close to the display area DA, and a light emission control driver EMD disposed in an area far from the display area DA.

[0211] That is, the second scan driver SCD2 may be provided in both the GIP circuit GIPC located in the left non-display area NDA and the GIP circuit GIPC located in the right non-display area NDA.

[0212] An area of ​​the light emission control driver EMD in each of the plurality of GIP circuits GIPC may be wider than that of the first, second, and third scan drivers SCD1, SCD2, and SCD3, and an area of ​​each of the first, second, and third scan drivers SCD1, SCD2, and SCD3 may be the same.

[0213] However, the driver arrangement and area of ​​each driver in the GIP circuit GIPC are not limited thereto, and the drivers arranged in each of the plurality of GIP circuits GIPC and the area of ​​each driver may be designed and changed by a user.

[0214] Reference Figure 2 and Fig.10 , the first scan driver SCD1 disposed in the nth stage STGn may generate a first scan signal Scan1[n] output to the first scan line SCL1.

[0215] In addition, the first scan driver SCD1 provided in the nth stage STGn can output a compensation signal to the first scan line SCL1 during the compensation period C / P of the display driving period D / P. Here, the compensation signal can be a first scan signal Scan1[n], and can be a signal having a gate low voltage increased by a predetermined voltage compared to an initial gate low voltage.

[0216] The second scan driver SCD2 in the nth stage STGn may generate a second scan signal Scan2[n] output to the second scan line SCL2, and the third scan driver SCD3 in the nth stage may generate a third scan signal Scan3[n] output to the third scan line SCL3.

[0217] On the other hand, the light-emitting control driver EMD equipped in the nth level STGn can generate a first light-emitting control signal EM[n] output to the first light-emitting control signal line EML1, the light-emitting control driver EMD equipped in the (n+1)th level STGn+1 can generate a second light-emitting control signal EM[n+1] output to the second light-emitting control signal line EML2, and the light-emitting control driver EMD equipped in the (n+2)th level STGn+2 can generate a third light-emitting control signal EM[n+2] output to the third light-emitting control signal line EML3.

[0218] FIG. 11A to FIG. 11D 1 is a diagram for further illustrating the gate driving circuit 130 of the display device 100 according to an embodiment of the present disclosure.

[0219] Specifically, Fig.11A 1 shows a first scan driver SCD1 included in the gate driving circuit 130, Fig. 11B 1 shows a second scan driver SCD2 included in the gate driving circuit 130, Fig. 11C 1 shows a third scan driver SCD3 included in the gate driving circuit 130, Fig.11D A light emission control driver EMD included in the gate driving circuit 130 is shown.

[0220] Reference FIG. 11A to FIG. 11D , each of the first scan driver SCD1 , the second scan driver SCD2 , the third scan driver SCD3 , and the light emission control driver EMD may include buffer circuits 1110 , 1130 , 1150 , and 1170 and control circuits 1120 , 1140 , 1160 , and 1180 , respectively.

[0221] Each of the buffer circuits 1110 , 1130 , 1150 , and 1170 may include a pull-up transistor Tu connected between the first node ND1 and the second node ND2 , and a pull-down transistor Td connected between the third node ND3 and the second node ND2 .

[0222] Each of the control circuits 1120, 1140, 1160, 1180 can control the voltage of the first control node (i.e., the Q node, which is the gate node of the pull-up transistor Tu) and the voltage of the second control node (i.e., the QB node, which is the gate node of the pull-down transistor Td).

[0223] Each of the buffer circuits 1110 , 1130 , 1150 , and 1170 may output a gate driving signal to a gate line electrically connected to the second node.

[0224] Specifically, the buffer circuit 1110 of the first scan driver SCD1 can output the first scan signal Scan1, the buffer circuit 1130 of the second scan driver SCD2 can output the second scan signal Scan2, the buffer circuit 1150 of the third scan driver SCD3 can output the third scan signal Scan3, and the buffer circuit 1170 of the light emitting control driver EMD can output the light emitting control signal EM.

[0225] One of the first power supply voltage applied to the first node ND1 of the buffer circuits 1110, 1130, 1150 of the first scan driver SCD1, the second scan driver SCD2, and the third scan driver SCD3 and the second power supply voltage applied to the third node ND3 can be a gate low voltage VGL, and the other can be a gate high voltage VGH higher than the gate low voltage VGL.

[0226] For example, if the pull-up transistor Tu and the pull-down transistor Td of each of the first, second, and third scan drivers SCD1, SCD2, and SCD3 are N-type transistors, the first power supply voltage may be the gate high voltage VGH, and the second power supply voltage may be the gate low voltage VGL.

[0227] In addition, if the pull-up transistor Tu and the pull-down transistor Td of each of the first, second, and third scan drivers SCD1, SCD2, and SCD3 are P-type transistors, the first power supply voltage may be the gate low voltage VGL, and the second power supply voltage may be the gate high voltage VGH.

[0228] One of the third power supply voltage applied to the first node ND1 of the light emission control driver EMD and the fourth power supply voltage applied to the third node ND3 may be the light emission low voltage VEL, and the other may be the light emission high voltage VEH higher than the light emission low voltage VEL.

[0229] For example, if the pull-up transistor Tu and the pull-down transistor Td of the light emission control driver EMD are N-type transistors, the third power supply voltage may be the light emission high voltage VEH, and the fourth power supply voltage may be the light emission low voltage VEL.

[0230] In addition, if the pull-up transistor Tu and the pull-down transistor Td of the light emission control driver EMD are P-type transistors, the third power supply voltage may be the light emission low voltage VEL, and the fourth power supply voltage may be the light emission high voltage VEH.

[0231] Reference Figure 6 and Fig.11A, the gate low voltage VGL applied to the third node ND3 of the first scan driver SCD1 may change or vary over time between a first voltage level VGL1 and a second voltage level VGL2 higher than the first voltage level VGL1. In this case, during a period in which the first scan signal Scan1 has an on-level voltage, the gate low voltage VGL may have a second voltage level VGL2.

[0232] Specifically, the first scan signal Scan1 may include: a first signal segment S1, the first signal segment S1 having a variable gate high voltage VGH_R higher than the gate high voltage VGH; a second signal segment S2, the second signal segment S2 having a gate low voltage VGL2 of a second voltage level; and a third signal segment S3, the third signal segment S3 having a gate low voltage VGL1 of a first voltage level.

[0233] A voltage difference between the variable gate high voltage VGH_R and the gate high voltage VGH may correspond to a difference between the second voltage level and the first voltage level (ie, VGL2 - VGL1 ).

[0234] according to FIG. 11A to FIG. 11C In the example of, each of the first scan driver SCD1, the second scan driver SCD2 and the third scan driver SCD3 can be provided with a start signal VST and a first clock signal CLK1, a second clock signal CLK2 and a third clock signal CLK3 corresponding to each driver, and a gate high voltage VGH can be provided to a pull-up transistor Tu which is turned on or off according to the voltage of the Q node, and a gate low voltage VGL can be provided to a pull-down transistor Td which is turned on or off according to the voltage of the QB node, thereby outputting a first scan signal Scan1, a second scan signal Scan2 and a third scan signal Scan3, respectively.

[0235] according to Fig.11D For example, the light emission control driver EMD may generate the light emission control signal EM based on the fourth clock signal CLK4 received from the controller 140 and the light emission high voltage VEH and the light emission low voltage VEL received from the power management integrated circuit.

[0236] For example, the light emitting control driver EMD can generate a light emitting control signal EM by providing a start signal VST and a fourth clock signal CLK4, provide a light emitting high voltage VEH to the pull-up transistor Tu that is turned on or off according to the voltage of the Q node, and provide a light emitting low voltage VEL to the pull-down transistor Td that is turned on or off according to the voltage of the QB node.

[0237] The first scan driver SCD1, the second scan driver SCD2, the third scan driver SCD3 and the light emitting control driver EMD can change the voltage of the output signal in synchronization with the edge of the clocks CLK1 to CKL4 corresponding to each driver according to the voltage of the start signal VST, so that the output signal can be generated with the same waveform as the phase of the start signal VST. If the waveform of the start signal VST changes, the waveform of the output signal may also change accordingly, and the input signal may overlap with the output signal.

[0238] Fig.12 1 is a diagram for explaining an implementation example of the display panel 110 according to an embodiment of the present disclosure.

[0239] Reference Fig.12 , the display panel 110 according to the embodiment of the present disclosure may include a transistor part, a light emitting device part, and a packaging part, but the embodiment of the present disclosure is not limited thereto.

[0240] The substrate 111 may be a single layer or multiple layers. If the substrate 111 is a multilayer, the substrate 111 may include a first substrate 301, an intermediate substrate layer (or intermediate layer) 302, and a second substrate 303. The intermediate substrate layer 302 may be located between the first substrate 301 and the second substrate 303. For example, each of the first substrate 301 and the second substrate 303 may be a polyimide (PI) layer, but the embodiments of the present disclosure are not limited thereto. The intermediate substrate layer 302 may be an inorganic insulating layer, but the embodiments of the present disclosure are not limited thereto. When charges are charged into the first substrate 301 as a polyimide layer, the intermediate substrate layer 302 may block the charges from passing through the second substrate 303 (which is a polyimide layer) to affect the transistors placed on the second substrate 303.

[0241] In addition, the intermediate substrate layer 302 can block the moisture component from penetrating upward through the first substrate 301. For example, the intermediate substrate layer 302 can be formed of a single layer or a multilayer of silicon nitride (SiNx) or silicon oxide (SiOx), or a double layer of silicon dioxide (SiO2) and silicon nitride (SiNx), but is not limited thereto.

[0242] The transistor part may include a substrate 111 , insulating layers 311 , 312 , 313 , 321 , 322 , and 323 on the substrate 111 , thin film transistors TFT1 and TFT2 , a storage capacitor Cst, and various electrodes or signal lines.

[0243] The thin film transistor included in the transistor part may include a first thin film transistor TFT1 and a second thin film transistor TFT2.

[0244] The first thin film transistor TFT1 may include a first active layer ACT1, a first electrode E1a, a second electrode E1b, and a third electrode E1c.

[0245] The first electrode E1a may be a gate electrode, the second electrode E1b may be a source electrode or a drain electrode, and the third electrode E1c may be a drain electrode or a source electrode. Hereinafter, for the sake of convenience, the first electrode E1a is referred to as a first gate electrode E1a, the second electrode E1b is referred to as a first source electrode E1b, and the third electrode E1c is referred to as a first drain electrode E1c. However, the embodiments of the present disclosure are not limited thereto.

[0246] The first active layer ACT1 may include a first semiconductor material, but the embodiments of the present disclosure are not limited thereto. For example, the first semiconductor material may include an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low temperature polycrystalline silicon (LTPS), but the embodiments of the present disclosure are not limited thereto. The first thin film transistor TFT1 may be implemented as a p-channel transistor or an n-channel transistor, but the embodiments of the present disclosure are not limited thereto.

[0247] The second thin film transistor TFT2 may include a second active layer ACT2, a fourth electrode E2a, a fifth electrode E2b, and a sixth electrode E2c.

[0248] The fourth electrode E2a may be a gate electrode, the fifth electrode E2b may be a source electrode or a drain electrode, and the sixth electrode E2c may be a drain electrode or a source electrode. In the following, for the sake of convenience, the fourth electrode E2a is referred to as a second gate electrode E2a, the fifth electrode E2b is referred to as a second source electrode E2b, and the sixth electrode E2c is referred to as a second drain electrode E2c. However, the embodiments of the present disclosure are not limited thereto.

[0249] The second active layer ACT2 may include a second semiconductor material, but the embodiments of the present disclosure are not limited thereto. For example, the second semiconductor material may include an oxide semiconductor, amorphous silicon, polycrystalline silicon, or low temperature polycrystalline silicon (LTPS), but the embodiments of the present disclosure are not limited thereto. The second thin film transistor TFT2 may be implemented as a p-channel transistor or an n-channel transistor, but the embodiments of the present disclosure are not limited thereto.

[0250] For example, one of the first active layer ACT1 of the first thin film transistor TFT1 and the second active layer ACT2 of the second thin film transistor TFT2 may include an oxide semiconductor material. For another example, one of the first active layer ACT1 of the first thin film transistor TFT1 and the second active layer ACT2 of the second thin film transistor TFT2 may include a low-temperature polysilicon semiconductor material. For another example, the first active layer ACT1 of the first thin film transistor TFT1 and the second active layer ACT2 of the second thin film transistor TFT2 may include an oxide semiconductor material. For another example, the first active layer ACT1 of the first thin film transistor TFT1 and the second active layer ACT2 of the second thin film transistor TFT2 may include a low-temperature polysilicon semiconductor material. For another example, in the first thin film transistor TFT1 and the second thin film transistor TFT2, the driving transistor DT may be configured with an oxide semiconductor as an active layer, and the scanning transistor ST may be configured with a low-temperature polysilicon as an active layer. For another example, in the first thin film transistor TFT1 and the second thin film transistor TFT2, the driving transistor DT may be configured with a low-temperature polysilicon as an active layer, and the scanning transistor ST may be configured with an oxide semiconductor as an active layer. For another example, the transistors included in the gate-in-panel (GIP) type gate driver circuit 130 may be configured with an oxide semiconductor or low-temperature polysilicon as an active layer. For another example, all transistors configured on the substrate 111 and the transistors included in the gate-in-panel (GIP) type gate driver circuit 130 may be configured with an oxide semiconductor as an active layer.

[0251] The second active layer ACT2 of the second thin film transistor TFT2 is located at a higher position from the substrate 111 than the first active layer ACT1 of the first thin film transistor TFT1 .

[0252] A first buffer layer 311 may be disposed under the first active layer ACT1 of the first thin film transistor TFT1, and a second buffer layer 321 may be disposed under the second active layer ACT2 of the second thin film transistor TFT2. For example, the first active layer ACT1 of the first thin film transistor TFT1 may be located on the first buffer layer 311, and the second active layer ACT2 of the second thin film transistor TFT2 may be located on the second buffer layer 321. The second buffer layer 321 may be located at a higher position than the first buffer layer 311.

[0253] The storage capacitor Cst may be disposed in various metal layers within the display panel 110. For example, the storage capacitor Cst may include a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2.

[0254] The light emitting device part may include a plurality of light emitting devices ED disposed on the planarization layer 330. Each of the plurality of light emitting devices ED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE.

[0255] For example, the pixel electrode PE may be an anode AND, and the common electrode CE may be a cathode CAT.

[0256] The encapsulation part may include an encapsulation layer 200 located on the plurality of light emitting devices ED. The encapsulation layer 200 may be a single layer or multiple layers, but the embodiments of the present disclosure are not limited thereto. The encapsulation part may further include a dam DAM in addition to the encapsulation layer 200.

[0257] Reference Fig.12 , a first buffer layer 311 may be disposed on the substrate 111. The first buffer layer 311 may be a single layer or a multi-layer, but the embodiments of the present disclosure are not limited thereto. If the first buffer layer 311 is a multi-layer, the first buffer layer 311 may include a lower buffer layer 311a and an upper buffer layer 311b.

[0258] The first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the first buffer layer 311. The first active layer ACT1 may include a channel region where a channel is formed, a source connection region at one side of the channel region, and a drain connection region at the other side of the channel region.

[0259] A first insulating layer 312 may be disposed on the first active layer ACT1 of the first thin film transistor TFT1. A first gate E1a of the first thin film transistor TFT1 may be disposed on the first insulating layer 312. A second insulating layer 313 may be disposed on the first gate E1a of the first thin film transistor TFT1. The first insulating layer 312 may be a gate insulating layer, but the embodiments of the present disclosure are not limited thereto. The second insulating layer 313 may be an interlayer insulating layer, but the embodiments of the present disclosure are not limited thereto.

[0260] The second buffer layer 321 may be disposed on the second insulating layer 313 .

[0261] The second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the second buffer layer 321. The second active layer ACT2 may include a channel region where a channel is formed, a source connection region at one side of the channel region, and a drain connection region at the other side of the channel region.

[0262] A third insulating layer 322 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2. A second gate E2a of the second thin film transistor TFT2 may be disposed on the third insulating layer 322. A fourth insulating layer 323 may be disposed on the second gate E2a of the second thin film transistor TFT2. The third insulating layer 322 may be a gate insulating layer, but the embodiments of the present disclosure are not limited thereto. The fourth insulating layer 323 may be an interlayer insulating layer, but the embodiments of the present disclosure are not limited thereto.

[0263] The first source electrode E1 b and the first drain electrode E1 c of the first thin film transistor TFT1 and the second source electrode E2 b and the second drain electrode E2 c of the second thin film transistor TFT2 may be disposed on the fourth insulating layer 323 .

[0264] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 may be connected to the source connection region and the drain connection region of the first active layer ACT1 through the holes of the fourth insulating layer 323 , the third insulating layer 322 , the second buffer layer 321 , the second insulating layer 313 , and the first insulating layer 312 , respectively.

[0265] The second source electrode E2 b and the second drain electrode E2 c of the second thin film transistor TFT2 may be connected to the source connection region and the drain connection region of the second active layer ACT2 through the hole of the fourth insulating layer 323 and the hole of the third insulating layer 322 , respectively.

[0266] The first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2 may include a first metal and may be disposed in a first metal layer. Here, the first metal and the first metal layer may be referred to as a first source-drain metal and a first source-drain metal layer.

[0267] Reference Fig.12 As an example, the storage capacitor Cst may be formed of a first capacitor electrode CAPE1 and a second capacitor electrode CAPE2. In some cases, the storage capacitor Cst may be formed of three or more capacitor electrodes, and may be in the form of two or more capacitors connected in parallel.

[0268] Each of the first capacitor electrode CAPE1 and the second capacitor electrode CAPE2 may be disposed on various metal layers disposed within the display panel 110 .

[0269] For example, the first capacitor electrode CAPE1 may include the same first gate metal as the first gate E1a of the first thin film transistor TFT1 on the first insulating layer 312 and may be disposed in the first gate metal layer, but the embodiments of the present disclosure are not limited thereto. For example, the second capacitor electrode CAPE2 may be disposed on the second insulating layer 313.

[0270] The second source electrode E2 b of the second thin film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 through the hole of the fourth insulating layer 323 , the hole of the third insulating layer 322 , and the hole of the second buffer layer 321 .

[0271] For example, if the sub-pixel SP is Figure 2 The configuration shown in FIG. 1 , the first thin film transistor TFT1 can be Figure 2 The first transistor T1 and the second thin film transistor TFT2 can be Figure 2 The driving transistor DT.

[0272] The transistor portion may further include metal layers MP1 and MP2. For example, the first metal layer MP1 may be disposed between the lower buffer layer 311a and the upper buffer layer 311b included in the first buffer layer 311, but the embodiments of the present disclosure are not limited thereto. The second metal layer MP2 may include the same first gate metal as the first gate E1a of the first thin film transistor TFT1, and may be disposed in the first gate metal layer, but the embodiments of the present disclosure are not limited thereto. The first metal layer MP1 may be a first metal pattern, and the second metal layer MP2 may be a second metal pattern, but the embodiments of the present disclosure are not limited thereto.

[0273] Each of the first metal layer MP1 and the second metal layer MP2 may be disposed in the display area DA or the non-display area NDA.

[0274] Reference Fig.12 , the transistor part may further include a first shielding pattern BSM1 disposed on the substrate 111. The first shielding pattern BSM1 may overlap the first active layer ACT1 of the first thin film transistor TFT1. The first shielding pattern BSM1 may be disposed under the first active layer ACT1 of the first thin film transistor TFT1. For example, the first shielding pattern BSM1 may be disposed between the substrate 111 and the first buffer layer 311, or may be disposed between the lower buffer layer 311a and the upper buffer layer 311b.

[0275] The transistor portion may further include a second shielding pattern BSM2 disposed on the substrate 111. The second shielding pattern BSM2 may overlap with the second active layer ACT2 of the second thin film transistor TFT2. The second shielding pattern BSM2 may be disposed below the second active layer ACT2 of the second thin film transistor TFT2. For example, the second shielding pattern BSM2 may be disposed in a metal layer between the second insulating layer 313 and the second buffer layer 321. The second shielding pattern BSM2 may be disposed in the same metal layer as the second capacitor electrode CAPE2, but the embodiments of the present disclosure are not limited thereto. For another example, the second shielding pattern BSM2 may be disposed in the same first gate metal layer as the first gate E1a of the first thin film transistor TFT1.

[0276] Reference Fig.12 The transistor part may further include a common driving signal layer CVP to which a common driving signal is applied. The common driving signal layer CVP may be disposed in the display area DA or the non-display area NDA.

[0277] For example, the common drive signal applied to the common drive signal layer CVP may be referred to as a power signal, and may include at least one of a drive voltage VDD and a base voltage VSS. The drive voltage VDD may also be referred to as a high potential drive voltage (e.g., a high potential power supply voltage or a high potential voltage), and the base voltage VSS may also be referred to as a low potential drive voltage (e.g., a low potential power supply voltage or a low potential voltage).

[0278] The planarization layer 330 may be disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2 and may be disposed under the light emitting device ED. The planarization layer 330 may be an organic insulating layer including an organic insulating material.

[0279] For example, the planarization layer 330 may be composed of one layer. As another example, the planarization layer 330 may include two layers. The planarization layer 330 may include a first planarization layer 331 and a second planarization layer 332. As another example, the planarization layer 330 may include three or more layers. The embodiments of the present disclosure are not limited thereto.

[0280] Reference Fig.12 , the first planarization layer 331 may be disposed on the first source electrode E1b and the first drain electrode E1c of the first thin film transistor TFT1 and the second source electrode E2b and the second drain electrode E2c of the second thin film transistor TFT2. For example, the first planarization layer 331 may be disposed on the first thin film transistor TFT1 and the second thin film transistor TFT2. For example, the first planarization layer 331 may be disposed to cover both the first thin film transistor TFT1 and the second thin film transistor TFT2.

[0281] Reference Fig.12 , a relay electrode RE may be disposed on the first planarization layer 331. The relay electrode RE may electrically connect the second source electrode E2b of the second thin film transistor TFT2 and the pixel electrode PE.

[0282] The relay electrode RE may be electrically connected to the second source electrode E2b of the second thin film transistor TFT2 through the hole of the first planarization layer 331. The second source electrode E2b of the second thin film transistor TFT2 may be electrically connected to the second capacitor electrode CAPE2 of the storage capacitor Cst.

[0283] The relay electrode RE may be disposed in a second metal layer on the first planarization layer 331 and may include a second metal. The second metal and the second metal layer may be referred to as a second source-drain metal and a second source-drain metal layer.

[0284] The second planarization layer 332 may be disposed on the relay electrode RE.

[0285] Reference Fig.12 , the light emitting device portion may be disposed on the second planarization layer 332. The light emitting device ED may be formed on the second planarization layer 332. The light emitting device ED may include a pixel electrode PE, a light emitting layer EL, and a common electrode CE. The light emitting area of ​​the light emitting device ED may be formed in a region where the pixel electrode PE, the light emitting layer EL, and the common electrode CE overlap and contact each other.

[0286] The pixel electrode PE may be disposed on the second planarization layer 332. The pixel electrode PE may be electrically connected to the relay electrode RE through the hole of the second planarization layer 332.

[0287] A bank 340 may be disposed on the pixel electrode PE. An opening of the bank 340 may expose a portion of the pixel electrode PE to form a light emitting region. The opening of the bank 340 may overlap a portion of the pixel electrode PE.

[0288] For example, the bank 340 may be made of a material containing a black pigment or an organic material such as a benzocyclobutene resin, a polyimide resin, an acrylic resin, or a photopolymer, but the embodiments of the present disclosure are not limited thereto. If the bank 340 is made of a material containing a black pigment or a black dye, the bank may be a black bank. If the bank 340 is made of a material containing a black pigment or a black dye, the bank may block light from the outside or light reflected from the outside, thereby further improving the brightness or luminance of the display device 100.

[0289] The light emitting layer EL of the light emitting device ED may be disposed on the pixel electrode PE and a portion of the bank 340. The common electrode CE may be disposed on the light emitting layer EL.

[0290] Reference Fig.12 The encapsulation part may be disposed on the light emitting device part and may be located on the common electrode CE. The encapsulation part may include an encapsulation layer 200 formed on the common electrode CE.

[0291] The encapsulation layer 200 may prevent moisture or oxygen from penetrating into the light emitting device ED. For example, the encapsulation layer 200 may prevent moisture or oxygen from penetrating into an organic material included in the light emitting layer EL of the light emitting device ED. The encapsulation layer 200 may be composed of a single layer or multiple layers, but the embodiments of the present disclosure are not limited thereto.

[0292] For example, the encapsulation layer 200 may include a first encapsulation layer 341, a second encapsulation layer 342, and a third encapsulation layer 343, but the embodiments of the present disclosure are not limited thereto. For example, the first encapsulation layer 341 and the third encapsulation layer 343 may include an inorganic encapsulation layer, and the second encapsulation layer 342 may include an organic encapsulation layer, but the embodiments of the present disclosure are not limited thereto.

[0293] The above-mentioned embodiments of the present disclosure are briefly described below.

[0294] A display device according to an embodiment of the present disclosure may include: a display panel on which a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels are arranged; a gate driving circuit for providing a scanning signal to the plurality of gate lines during a display driving period; and a data driving circuit for providing a data voltage to the plurality of data lines.

[0295] The gate driving circuit can apply a compensation signal corresponding to a change in the gate low voltage within the scanning period to at least one of the multiple gate lines in each compensation period within at least one compensation period during the display driving period except for the scanning period in which the scanning signal is applied to the multiple gate lines.

[0296] The voltage level of the compensation signal may be a middle value of the increased gate low voltage levels within the scan period corresponding to each of the plurality of gate lines.

[0297] The length of the compensation period may be equal to the length of the scanning period.

[0298] The scan period may include a low voltage rising period in which a gate low voltage slightly increases at a node to which the scan signal is applied due to the influence of a parasitic capacitor before and after a moment when the scan signal is applied to the plurality of gate lines, and a blank period.

[0299] The scanning period and the compensation period may include a blank period, and the length of the blank period included in the scanning period may be equal to the length of the blank period included in the compensation period.

[0300] The scan period may include a refresh frame period corresponding to a time when the scan signal is applied, and at least one anode reset frame period.

[0301] Each of the plurality of sub-pixels may include a driving transistor and a first transistor connecting a second node corresponding to a gate electrode of the driving transistor and a third node corresponding to a second electrode of the driving transistor.

[0302] The gate driving circuit may provide a scan signal and a compensation signal to a gate node of the first transistor.

[0303] The gate driving circuit may include at least one gate in panel (GIP) circuit disposed in the display panel.

[0304] The gate driving circuit may receive a gate voltage and a compensation signal from a driver integrated circuit disposed outside the display panel, and generate a scan signal based on the gate voltage.

[0305] The driver integrated circuit may generate a compensation signal based on a gate low voltage among the gate voltages.

[0306] According to an embodiment of the present disclosure, a gate drive circuit may include: a buffer circuit, the buffer circuit including a pull-up transistor connected between a first node and a second node and a pull-down transistor connected between a third node and the second node; and a control circuit, the control circuit being configured to control a voltage of a first control node serving as a gate node of the pull-up transistor and a voltage of a second control node serving as a gate node of the pull-down transistor.

[0307] The buffer circuit may output a gate signal to a gate line electrically connected to the second node.

[0308] One of the first power supply voltage applied to the first node and the second power supply voltage applied to the third node may be a gate low voltage, and the other may be a gate high voltage higher than the gate low voltage.

[0309] The gate low voltage may vary over time between a first voltage level and a second voltage level higher than the first voltage level, and may have the second voltage level during a period in which the gate signal has an on-level voltage.

[0310] The gate signal may include a first signal section having a variable gate high voltage higher than the gate high voltage, a second signal section having a gate low voltage at a second voltage level, and a third signal section having the gate low voltage at the first voltage level.

[0311] A voltage difference between the variable gate high voltage and the gate high voltage may correspond to a difference between the second voltage level and the first voltage level.

[0312] The buffer circuit may output a first scan signal having a first signal section, a second signal section, and a third signal section to the gate line as a gate signal.

[0313] The buffer circuit may output at least one of the second scan signal, the third scan signal, and the light emitting control signal to the gate line as a gate signal.

[0314] A display device according to an embodiment of the present disclosure may include: a display panel on which a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels are arranged; and a gate driving circuit configured to provide gate signals to the plurality of gate lines based on a gate high voltage and a gate low voltage.

[0315] The gate driving circuit may provide a gate signal including a first signal segment having a variable gate high voltage higher than the gate high voltage, a second signal segment having a gate low voltage at a second voltage level, and a third signal segment having a gate low voltage at a first voltage level lower than the second voltage level.

[0316] The above description is provided to enable those skilled in the art to make and use the technical concepts of the present disclosure, and is provided in the context of specific applications and their requirements. It will be apparent to those skilled in the art that various modifications, additions, and substitutions to the described embodiments will be apparent without departing from the spirit and scope of the present disclosure, and the general principles defined herein may be applied to other embodiments and applications. The above description and accompanying drawings provide examples of the technical concepts of the present disclosure for illustrative purposes only. That is, the disclosed embodiments are intended to illustrate the scope of the technical concepts of the present disclosure.

[0317] The various embodiments described above can be combined to provide further embodiments. Aspects of the embodiments can be modified, if necessary, to employ concepts of the various embodiments to provide still further embodiments.

[0318] These and other changes can be made to the embodiments in light of the above detailed description. Generally, in the appended claims, the terms used should not be interpreted as limiting the claims to the specific embodiments disclosed in the specification and claims, but should be understood to include all possible embodiments and the full range of equivalents to which these claims are entitled. Therefore, the claims are not limited by this disclosure.

Claims

1. A display device, comprising: A display panel, wherein a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels are arranged on the display panel; a gate driving circuit for supplying a scanning signal to the plurality of gate lines during a display driving period; as well as a data driving circuit, the data driving circuit being configured to supply data voltages to the plurality of data lines, In which, the gate driving circuit is configured to apply a compensation signal corresponding to a change in the gate low voltage within the scanning period to at least one of the multiple gate lines during the display driving period, except for the scanning period in which the scanning signal is applied to the multiple gate lines.

2. The display device according to claim 1, wherein: A voltage level of the compensation signal is a middle value of the increased gate low voltage levels within the scan period corresponding to each of the plurality of gate lines.

3. The display device according to claim 1, wherein: The length of the compensation period is equal to the length of the scanning period.

4. The display device according to claim 1, wherein: The scan period includes a blank period and a low voltage rising period. In the low voltage rising period, before and after the moment when the scan signal is applied to the plurality of gate lines, a gate low voltage increases at a node to which the scan signal is applied due to an influence of a parasitic capacitor.

5. The display device according to claim 1, wherein: The scanning period and the compensation period include a blank period, and a length of the blank period included in the scanning period is equal to a length of the blank period included in the compensation period.

6. The display device according to claim 1, wherein: The scan period includes a refresh frame period corresponding to a time when the scan signal is applied, and at least one anode reset frame period.

7. The display device according to claim 1, wherein: Each of the plurality of sub-pixels includes a driving transistor and a first transistor, the first transistor connecting a second node corresponding to a gate electrode of the driving transistor and a third node corresponding to a second electrode of the driving transistor, The gate driving circuit is configured to supply the scan signal and the compensation signal to a gate node of the first transistor.

8. The display device according to claim 1, wherein: The gate driving circuit includes at least one in-panel gate circuit disposed in the display panel.

9. The display device according to claim 1, wherein: The gate driving circuit is configured to receive a gate voltage and the compensation signal from a driver integrated circuit disposed outside the display panel and generate the scan signal based on the gate voltage.

10. The display device according to claim 9, wherein: The driver integrated circuit is configured to generate the compensation signal based on the gate low voltage among the gate voltages.

11. A gate drive circuit, comprising: a buffer circuit comprising a pull-up transistor connected between a first node and a second node and a pull-down transistor connected between a third node and the second node; as well as a control circuit configured to control a voltage of a first control node and a voltage of a second control node, the first control node being a gate node of the pull-up transistor and the second control node being a gate node of the pull-down transistor, wherein the buffer circuit is configured to output a gate signal to a gate line electrically connected to the second node, wherein one of a first power supply voltage applied to the first node and a second power supply voltage applied to the third node is a gate low voltage, and the other of the first power supply voltage and the second power supply voltage is a gate high voltage higher than the gate low voltage, wherein the gate low voltage is configured to vary over time between a first voltage level and a second voltage level higher than the first voltage level, and has the second voltage level during a period in which the gate signal has an on-level voltage, The gate signal includes a first signal section having a variable gate high voltage higher than the gate high voltage, a second signal section having the gate low voltage at the second voltage level, and a third signal section having the gate low voltage at the first voltage level.

12. The gate driving circuit according to claim 11, wherein: A voltage difference between the variable gate high voltage and the gate high voltage corresponds to a difference between the second voltage level and the first voltage level.

13. The gate driving circuit according to claim 11, wherein: The buffer circuit is configured to output a first scan signal having the first signal section, the second signal section, and the third signal section to the gate line as the gate signal.

14. The gate driving circuit according to claim 11, wherein: The buffer circuit is configured to output at least one of a second scan signal, a third scan signal, or a light emission control signal to the gate line as the gate signal.

15. A display device, comprising: A display panel, wherein a plurality of gate lines, a plurality of data lines and a plurality of sub-pixels are arranged on the display panel; as well as a gate driving circuit configured to supply gate signals to the plurality of gate lines based on a gate high voltage and a gate low voltage, Wherein, the gate drive circuit is configured to supply the gate signal, and the gate signal includes a first signal segment having a variable gate high voltage higher than the gate high voltage, a second signal segment having the gate low voltage at a second voltage level, and a third signal segment having the gate low voltage at a first voltage level lower than the second voltage level.

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