Distributed phase alignment method and alignment device

Abstract

The invention relates to the field of microwaves, in particular to a distributed phase alignment method and alignment device which can be applied to radar and microwave communication products. The device is composed of a comparison and control circuit, a distributed channel and a synthesizer. Through the comparison and control circuit, communication with each channel is kept while channel phase comparison is completed, 0-360-degree successive adjustment of output signal phases of the corresponding channels is completed in real time, and finally automatic phase alignment among all the channels is achieved.

Description

Technical Field

[0001] The present invention relates to the field of microwaves, and in particular to a distributed phase alignment method and an alignment device, which can be applied to radar and microwave communication products. Background Art

[0002] With the rapid development of radar, microwave communication, mobile communication, satellite communication, electronic countermeasure and other technologies, the demand for array and distributed microwave products is also increasing. For phased array radars with hundreds or even thousands of transceiver channels, especially distributed array phased array radars, their performance is better than that of centralized radars. It overcomes the shortcomings of centralized radars that the transmission signal is unified and cannot be changed flexibly. With the help of independent waveform generation units for each channel, distributed radars have obvious advantages such as convenient waveform control, flexible phase control, and convenient array combination. In particular, the convenient array combination is extremely obvious compared to centralized radars. However, distribution also brings a distinct disadvantage due to its own characteristics, that is, the difference between channels, especially the phase difference. This disadvantage has also become one of the main difficulties restricting the application of distributed systems.

[0003] The common way to implement distributed radar is to place a DDS circuit (direct digital synthesizer) in each independent transmission channel. DDS has extremely short frequency agility time, high frequency resolution and excellent phase noise performance, and can easily implement various modulations. However, the phase of the RF signal output by the DDS in each channel cannot be exactly the same at the same time. In addition, there are inevitable differences in the RF circuits between channels, resulting in consistency differences in the phase of the output signals between the channels.

[0004] In phased array radars, correction networks are usually used to compensate for phase differences between channels. However, the correction network is susceptible to external interference and requires the coordination of correction plug-ins and signal processing subsystems to work. In addition, the phase difference between channels will gradually increase with the increase of working time, which will eventually affect the overall performance of the radar. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a distributed phase alignment method and an alignment device. The device of the present invention is composed of a comparison and control circuit, a distributed channel and a synthesizer. The present invention uses a comparison and control circuit to complete channel phase comparison while maintaining communication with each channel, and completes the 0° to 360° phase adjustment and comparison of the corresponding channel output signal in real time, and finally realizes automatic phase alignment between all channels.

[0006] The technical method of the present invention is: a distributed phase alignment method, characterized in that: it specifically includes the following steps:

[0007] Step 1: Store all corresponding phase control words from 0° to 360° into the ROM IP core of the FPGA;

[0008] Step 2: Select one channel from the N distributed channels as the reference channel, turn on the reference channel output through the comparison and control circuit, write the phase control word into the DDS chip of the reference channel, use the phase state of its output signal as the reference phase, and turn off the output of the channel to be aligned;

[0009] Step 3: The comparison and control circuit turns on one output of the channel to be aligned while the outputs of the other channels to be aligned remain turned off;

[0010] a) Write the phase control word into the DDS chip of the channel to be aligned with the output turned on, digitally sample the synthesizer output signal and record the amplitude value a1 and store it in the FPGA;

[0011] b) Write the phase control word with the minimum offset (i.e., the minimum phase step) relative to a) into the DDS chip of the channel to be aligned with the output turned on, digitally sample the synthesizer output signal and record the amplitude value a2 and store it in the FPGA.

[0012] c) According to b), continue to perform the minimum phase stepping operation. Each time the synthesizer output signal is digitally sampled and the amplitude value is recorded and stored in the FPGA until a 360° phase shift is completed relative to the state of a). At this point, the amplitude value recorded reaches a16384;

[0013] d) FPGA compares the amplitude values ​​a1 to a16384 and takes out the maximum value a max , write the corresponding phase control word into the DDS chip of the channel to be aligned with the output turned on and save it to complete the phase alignment between the channel and the reference channel.

[0014] Step 4: Repeat step 3 to complete the phase alignment of all remaining channels to be aligned.

[0015] According to the distributed phase alignment method as described above, it is characterized in that: by formula Calculate all the values ​​of the phase control word. Each phase control word corresponds to a phase state. When POW is 1, △θ = 0.02197265625°. This value is the minimum phase shift accuracy of this method, which is also the minimum phase step value in step three.

[0016] According to a distributed phase alignment method as described above, it is characterized in that: during the phase alignment process, the phase step value is not limited to the minimum phase step value, and can be adjusted according to the actual accuracy requirement. The lower the accuracy requirement, the higher the step value, the fewer the amplitude values ​​recorded and compared, and the faster the phase alignment speed, and vice versa.

[0017] The present invention also discloses a distributed phase alignment device, comprising a distributed channel, a comparison and control circuit and a synthesizer, wherein the distributed channel is N; N is greater than or equal to 2, and the device is characterized in that:

[0018] The comparison and control circuit is connected to the N-channel distributed channel circuits through a communication bus. The comparison and control circuit can control any distributed channel to generate a low phase noise, high-resolution RF signal, and can accurately adjust the phase of the RF signal; each distributed channel includes a transmitting output port and a detecting output port, and the transmitting output port and the detecting output port signals are generated by power division after being amplified by the previous stage circuit;

[0019] The synthesizer includes N input RF interfaces and one output RF interface. The N input RF interfaces are connected to N detection output ports of the distributed channel. The phase difference from each input port to the output port is the same. The output RF interface of the synthesizer is connected to the comparison and control circuit.

[0020] According to the distributed phase alignment device as described above, it is characterized in that each distributed channel includes a DDS circuit.

[0021] According to the distributed phase alignment device as described above, it is characterized in that the comparison and control circuit includes an FPGA, a high-speed analog-to-digital converter ADC, a clock synthesizer and an FPGA configuration circuit.

[0022] According to the distributed phase alignment device as described above, it is characterized in that the comparison and control circuit uses the above-mentioned distributed phase alignment method to control the distributed channels.

[0023] The beneficial effects of the present invention are:

[0024] 1) Intelligent and automated, the entire phase alignment process can be completed automatically with one button, and the operation is simple and convenient.

[0025] 2) Convenience: This system does not require the coordination of a calibration network, calibration plug-in, or signal processing system; the system itself can complete phase alignment.

[0026] 3) High precision. The minimum phase alignment accuracy of the entire system is 0.02197265625°. However, the operation of controlling the phase using traditional phase shifter chips is limited by device performance and the minimum accuracy is usually 5.625°.

[0027] 4) The circuit of the present invention can be mass-produced and no debugging is required after mass production.

[0028] 5) The present invention has a wide range of applications and can be applied to various fields such as radar, microwave communication and measurement that require multi-path phase alignment. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 Principle block diagram of the distributed fully automatic phase alignment system. DETAILED DESCRIPTION

[0030] The present invention is further described below with reference to the accompanying drawings and examples.

[0031] like Figure 1 As shown, a distributed phase alignment device of the present invention includes a distributed channel, a comparison and control circuit and a synthesizer. There are N distributed channels; the comparison and control circuit is connected to the N distributed channel circuits through a communication bus, and the comparison and control circuit can control any distributed channel to generate a low phase noise, high-resolution radio frequency signal, and can accurately adjust the phase of the radio frequency signal.

[0032] like Figure 1 As shown, each distributed channel includes a DDS circuit. The DDS circuit chip of the present invention takes the AD9914 chip of ADI Company as an example. The circuit is characterized in that the phase of the output signal can be adjusted online in real time, and the phase adjustment accuracy is as high as 0.02197265625°.

[0033] like Figure 1 As shown, each distributed channel includes a transmitting output port and a detecting output port. The transmitting output port and the detecting output port signals are both amplified by the previous stage circuit and then divided, so the transmitting output port and the detecting output port have the same phase. The characteristic of this circuit is that the phase value of the transmitting output port signal can be obtained by measuring the phase value of the detecting output port signal.

[0034] like Figure 1 As shown, the synthesizer includes N input RF interfaces and one output RF interface. The N input RF interfaces are directly connected to the N detection output ports of the distributed channels. The phase difference from each input port to the output port is the same. The characteristic of the synthesizer is that N detection signals are synthesized into one output.

[0035] like Figure 1As shown, the output RF interface of the synthesizer is connected to the comparison and control circuit. The comparison and control circuit includes FPGA, high-speed analog-to-digital converter ADC, clock synthesizer and FPGA configuration circuit. The FPGA chip of the present invention adopts Xilinx's 7 series FPGA chip xc7k325tffg900-2, which is used to complete data calculation and analysis and configuration and control functions of other chips; the analog-to-digital converter ADC chip adopts ADI's AD9680, with a bit width of 14bit and a sampling rate of 1GSPS, and adopts 204B communication protocol, which is used to sample the RF signal output by the synthesizer; the clock synthesis chip adopts ADI's integrated JESD204B SYSREF generator to provide high-quality clock signals for FPGA and ADC circuits; the FPGA configuration circuit includes a FLASH chip for storing code curing files, a 50Mhz crystal oscillator for providing a basic clock signal, a power supply chip, and a circuit protection device self-reset fuse and a transient voltage suppressor. The power chip LTM4644 converts the input voltage into multiple voltage outputs of different voltages to meet the various voltage specifications required by FPGA; the self-resetting fuse uses a domestic polymer self-resetting fuse, which is an overcurrent protection device with self-recovery function; the transient voltage suppressor uses a domestic TVS diode to protect the precision components in the circuit from the impact of transient high-voltage spike pulses. The characteristic of the comparison and control circuit is that after adjusting the phase of the distributed channel one by one, the peak-to-peak value of the synthesized signal can be obtained in real time through the high-speed analog-to-digital converter ADC and recorded, compared and judged, thereby completing the phase alignment of the distributed channel.

[0036] like Figure 1 As shown, the comparison and control circuit is connected to N distributed channels, and the connection method is a communication bus. The output phase of the distributed channel is controlled by writing a phase control word into the DDS chip in the distributed channel. Taking the AD9914 chip as an example, its phase control word is a 14-bit phase offset word (POW), and its phase offset formula is:

[0037]

[0038] Among them, Δθ is the phase degree value that needs to be moved. Taking 1° as an example, after substituting it into the above formula, it is calculated that POW=45.51. After converting this value into hexadecimal and writing it into the phase control register of AD9914, a 1° phase shift of the output signal can be achieved.

[0039] According to formula (1), when the value of POW is 1, △θ=0.02197265625°, that is, the phase alignment accuracy of the present invention can reach a minimum of 0.02197265625°. For example, the phase control word "00000000000001" is phase-shifted by 0.02197265625° compared to "00000000000000".

[0040] The present invention also discloses a distributed phase alignment method, which specifically comprises the following steps:

[0041] Step 1: According to formula (1), the range of all phase control words is 0 to 16383. Each phase control word corresponds to a phase state. All phase control words are stored in the ROM IP core of the FPGA.

[0042] Step 2: Select any channel from the N distributed channels as the reference channel. Now, take channel 1 as the reference channel as an example.

[0043] The comparison and control circuit turns on the output of channel 1, writes the phase control word (00000000000000) into the DDS chip of channel 1, uses the phase state of its output signal as the reference phase, and turns off the outputs of channels 2 to channel N (channels 2 to channel N are collectively referred to as channels to be aligned).

[0044] Step 3: The comparison and control circuit turns on the output of channel 2, and the outputs of channels 3 to N remain off. Then perform the following operations:

[0045] a) Write the phase control word (000000000000000) into the DDS chip of channel 2, and then digitally sample the synthesizer output signal through the ADC analog-to-digital conversion chip AD9680 and record the amplitude value a1 and store it in the FPGA.

[0046] b) Write a 0.02197265625° offset phase control word (00000000000001) into the DDS chip of channel 2, and then digitally sample the synthesizer output signal through the ADC analog-to-digital conversion chip AD9680 and record the amplitude value a2 and store it in the FPGA.

[0047] c) Refer to the operation in b) and write "00000000000010~11111111111111" to the DDS chip of channel 2 one by one

[0048] Phase control word, FPGA records the amplitude value a3~a16384 corresponding to each control word respectively. At this point, channel 2 has completed a 360° phase shift relative to state a).

[0049] d) FPGA compares the amplitude values ​​a1 to a16384 and takes out the maximum value a max , write the corresponding phase control word into the DDS chip of channel 2 and save it to complete the phase alignment between channel 2 and the reference channel.

[0050] Step 4: Repeat step 3 (the output of the channels that have completed the alignment can be turned off during the repetition process) to complete the phase alignment of channels 3 to N in sequence.

[0051] The present invention is not limited to the above-mentioned implementation modes and steps. A person skilled in the art can implement the present invention in various other specific implementation modes based on the contents disclosed in the present invention. Therefore, any design that adopts the implementation principles and ideas of the present invention and makes some simple changes or modifications shall fall within the scope of protection of the present invention.

Claims

1. A distributed phase alignment method, Features: The specific steps include: Step 1: Store all corresponding phase control words from 0° to 360° into the ROM IP core of the FPGA; Step 2: Select one channel from the N distributed channels as the reference channel, turn on the reference channel output through the comparison and control circuit, write the phase control word into the DDS chip of the reference channel, use the phase state of its output signal as the reference phase, and turn off the output of the channel to be aligned; Step 3: The comparison and control circuit turns on one output of the channel to be aligned while the outputs of the other channels to be aligned remain turned off; a) Write the phase control word into the DDS chip of the channel to be aligned with the output turned on, digitally sample the synthesizer output signal and record the amplitude value a1 and store it in the FPGA; b) writing the minimum offset phase control word relative to a) into the DDS chip of the channel to be aligned whose output is turned on, digitally sampling the synthesizer output signal and recording the amplitude value a2 and storing it in the FPGA; c) According to b), continue the minimum phase stepping operation. Each time the synthesizer output signal is digitally sampled and the amplitude value is recorded and stored in the FPGA until the state relative to a) is completed. 360° phase shift, so far, the amplitude value recorded is a16384; d) FPGA compares the amplitude values ​​a1 to a16384 and takes out the maximum value a max , write the corresponding phase control word into the DDS chip of the channel to be aligned with the output turned on and save it to complete the phase alignment between the channel and the reference channel. Step 4: Repeat step 3 to complete the phase alignment of all remaining channels to be aligned.

2. A distributed phase alignment method according to claim 1, Features: By formula Calculate all the values ​​of the phase control word. Each phase control word corresponds to a phase state. When POW is 1, △θ=0.02197265625°. This value is the minimum phase shift accuracy of this method, which is also the minimum phase step value in step three.

3. A distributed phase alignment method according to claim 1, Features: During the phase alignment process, adjustments are made according to the actual accuracy requirements; the lower the accuracy requirements, the higher the step value, the fewer amplitude values ​​recorded and compared, and the faster the phase alignment speed, and vice versa.

4. A distributed phase alignment device, comprising distributed channels, comparison and control circuits and synthesizers, wherein the distributed channels are N; N is greater than or equal to 2, Features: The comparison and control circuit is connected to the N-channel distributed channel circuits through a communication bus. The comparison and control circuit can control any distributed channel to generate a low phase noise, high-resolution radio frequency signal, and adjust the phase of the radio frequency signal; each distributed channel includes a transmitting output port and a detecting output port, and the transmitting output port and the detecting output port signals are generated by power division after amplification by the previous stage circuit; The synthesizer includes N input RF interfaces and one output RF interface. The N input RF interfaces are connected to N detection output ports of the distributed channel. The phase difference from each input port to the output port is the same. The output RF interface of the synthesizer is connected to the comparison and control circuit.

5. A distributed phase alignment device according to claim 4, Features: Each distributed channel contains a DDS circuit.

6. A distributed phase alignment device according to claim 4, Features: The comparison and control circuit includes FPGA, a high-speed analog-to-digital converter ADC, a clock synthesizer and an FPGA configuration circuit.

7. A distributed phase alignment device according to claim 4, Features: The comparison and control circuit uses any distributed phase alignment method of claim 1 to claim 3 to control the distributed channel.

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