Pin monitoring method and system based on domestic FPGA chip
By configuring the pins of the domestic FPGA chip to a three-state gate and collecting status information, the problem that the domestic FPGA chip cannot monitor the pin status is solved, real-time monitoring and control of the pin status is achieved, and the reliability and security of the system are improved.
Patent Information
- Application Number
- CN202510208380.6
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-02-25
- Publication Date
- 2025-05-23
AI Technical Summary
Domestic FPGA chips cannot effectively monitor and control their pin state during operation, resulting in the inability to obtain the operation status of external devices connected to them in time.
By configuring several pins of the domestic FPGA chip as a three-state gate and configuring the corresponding working mode of each pin in the three-state gate state, the status information of the pin is collected and sent to the upper computer at a preset time interval.
It realizes monitoring and control of the pin status of domestic FPGA chips, improves the integration and reliability of the system, ensures the real-time and accuracy of information, and improves the security of the system through the encrypted communication mechanism.
Smart Images
Figure CN120029152A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of chip technology, and in particular to a pin monitoring method and system based on a domestically produced FPGA chip. Background Art
[0002] FPGA (Field Programmable Gate Array) chips are developed based on programmable devices (PAL (Programmable Array Logic), GAL (General Array Logic), CPLD (Complex Programmable Logic Device)). They are semi-customized, programmable integrated chips. FPGA chips are widely used in communications, national defense, aerospace and other fields.
[0003] Currently, there is no effective technical means to monitor the pin status of domestic FPGA chips during their operation. Summary of the invention
[0004] In view of this, the present invention proposes a pin monitoring method and system based on a domestic FPGA chip, which solves the problem that the pin status of the domestic FPGA chip cannot be monitored and controlled during operation.
[0005] On the one hand, an embodiment of the present invention provides a pin monitoring method based on a domestic FPGA chip, the method comprising: Configure several first pins of the domestic FPGA chip as tri-state gates, and configure the corresponding working mode of each first pin in the tri-state gate state; In response to the domestic FPGA chip being in an operation stage and the domestic FPGA chip being connected to an external device through a first pin, state information of the first pin is collected based on a working mode of the first pin.
[0006] The collected status information of the first pin is sent to the host computer at a preset time interval.
[0007] In some embodiments of the present invention, based on the working mode of the first pin, collecting the state information of the first pin includes: In response to the working mode of the first pin being the input mode, receiving a signal input by an external device based on the first pin working in the input mode, and storing the received signal input by the external device in a predefined register variable; The signal input by the external device is read from the register variable to collect the state information of the first pin whose working mode is the input mode.
[0008] In some embodiments of the present invention, the method further comprises: In response to receiving a pin status monitoring instruction sent by a host computer based on the domestic FPGA chip, the collected status information of the first pin is sent to the host computer.
[0009] In some embodiments of the present invention, the method further comprises: In response to receiving a pin state control instruction sent by a host computer based on the domestic FPGA chip, the operation of the first pin is controlled based on the pin state control instruction.
[0010] In some embodiments of the present invention, the pin state control instruction includes a first control instruction, and controlling the operation of the first pin based on the pin state control instruction includes: The sending behavior of the first pin whose working mode is the input mode is controlled based on the first control instruction.
[0011] In some embodiments of the present invention, the pin state control instruction includes a second control instruction, and controlling the operation of the first pin based on the pin state control instruction includes: Based on the second control instruction, the direction of the first pin whose working mode is the output mode and / or the level state of the output signal are controlled.
[0012] In some embodiments of the present invention, the method further comprises: Establish an encrypted communication connection with the host computer based on domestic FPGA chips.
[0013] In some embodiments of the present invention, establishing a communication connection with a host computer based on a domestic FPGA chip includes: Generate the information to be encrypted based on the domestic FPGA chip, send the information to be encrypted to the host computer and receive the public key returned by the host computer; Based on the domestic FPGA chip, the encrypted information is encrypted according to the public key sent by the host computer, the encrypted information is obtained, and the encrypted information is sent to the host computer and the decrypted information returned by the host computer is received; Based on the domestic FPGA chip, it determines whether the decrypted information is consistent with the information to be encrypted, and establishes a communication connection with the host computer when the decrypted information is consistent with the information to be encrypted.
[0014] In some embodiments of the present invention, the method further comprises: The host computer generates a public key and a private key based on the information to be encrypted sent by the domestic FPGA chip, and sends the public key to the domestic FPGA chip; The host computer decrypts the encrypted information sent by the domestic FPGA chip through the private key to obtain the decrypted information, and sends the decrypted information to the domestic FPGA chip.
[0015] In some embodiments of the present invention, after configuring the corresponding working mode of each first pin in the tri-state gate state, the method further includes: The operating frequency and the pin status acquisition frequency of the first pin are configured, and the pin status acquisition frequency is ≥ 1 / 2* the operating frequency.
[0016] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a pin monitoring system based on a domestic FPGA chip, comprising: a domestic FPGA chip and a host computer; The domestic FPGA chip includes a plurality of first pins, each of which is configured as a tri-state gate and has a corresponding working mode; The domestic FPGA chip is also configured to respond to being in an operating stage and connected to an external device through a first pin, collect status information of the first pin based on the working mode of the first pin, and send the collected status information of the first pin to the host computer at a preset time interval.
[0017] The present invention provides a pin monitoring method and system based on a domestic FPGA chip, which has the following advantages: 1) It realizes a high degree of integration of signal processing, which can not only accurately control the pin status, but also perform real-time signal acquisition and preliminary processing, greatly improving the integration and reliability of the applied system.
[0018] 2) Bidirectional communication between the FPGA chip and the host computer is realized through the internal interface. The host computer can send query instructions, and the FPGA chip returns the current pin signal status according to the instructions, so as to obtain the operating status of the external device in time, ensuring the real-time and accuracy of the information.
[0019] 3) During the communication process, domestic FPGA chips and host computers use encryption mechanisms to verify the identities of both communicating parties through encryption and decryption, effectively preventing data leakage and illegal access, and improving the security of the system.
[0020] 4) After the data received by the host computer is processed, detailed real-time reports can be generated. These reports provide users with an intuitive display of pin status, facilitating system monitoring and maintenance.
[0021] 5) It is suitable for a variety of industries and application scenarios, such as industrial control, aerospace, communication networks, etc., meeting the needs of different fields for pin signal status monitoring. BRIEF DESCRIPTION OF THE DRAWINGS
[0022] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention. For ordinary technicians in this field, other embodiments can be obtained based on these drawings without paying creative work.
[0023] Figure 1 A flowchart of a pin monitoring method based on a domestic FPGA chip provided by an embodiment of the present invention; Figure 2 A flowchart of a pin monitoring method based on a domestic FPGA chip provided by an embodiment of the present invention; Figure 3 A flowchart of a pin monitoring method based on a domestic FPGA chip provided by an embodiment of the present invention; Figure 4 A schematic diagram of the structure of a pin monitoring system based on a domestic FPGA chip provided by an embodiment of the present invention; Figure 5 A schematic structural diagram of a pin monitoring system based on a domestic FPGA chip provided in an embodiment of the present invention. DETAILED DESCRIPTION
[0024] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the embodiments of the present invention are further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.
[0025] It should be noted that all expressions using "first" and "second" in the embodiments of the present invention are for distinguishing two non-identical entities with the same name or non-identical parameters. It can be seen that "first" and "second" are only for the convenience of expression and should not be understood as limitations on the embodiments of the present invention. The subsequent embodiments will not explain this one by one.
[0026] For domestic FPGA chips, there is currently no effective technical means to monitor their pin status, and thus it is impossible to obtain the operating status of external devices connected to them in a timely manner through the device pin status. Once a problem occurs in the operation of an external device, it cannot be monitored in time, which is not conducive to the monitoring and maintenance of the external device. Therefore, how to realize the pin status monitoring of FPGA chips is a technical problem that needs to be urgently solved in the current application of domestic FPGA chips.
[0027] In view of this, in order to solve at least one of the above technical problems, an embodiment of the present invention provides a pin monitoring method and system based on a domestic FPGA chip. The present invention is described in detail below in conjunction with the embodiments and drawings.
[0028] The first aspect of the embodiment of the present invention provides a pin monitoring method based on a domestic FPGA chip, such as Figure 1 As shown, the method specifically includes steps S10 to S12.
[0029] S10, configuring several first pins of the domestic FPGA chip as tri-state gates, and configuring the corresponding working mode of each first pin in the tri-state gate state; S11. In response to the domestic FPGA chip being in an operating stage and the domestic FPGA chip being connected to an external device via a first pin configured as a tri-state gate, based on a working mode of the first pin, collecting status information of the first pin.
[0030] S12: Send the collected status information of the first pin to the host computer at a preset time interval.
[0031] In response to the working mode of the first pin being the input mode, state information of the first pin whose working mode is the input mode is collected.
[0032] Specifically, if the monitoring and control of the domestic FPGA chip is to be realized, the domestic FPGA chip needs to be configured during the initialization phase of the domestic FPGA chip. Only the pins configured as tri-state gates can be monitored and controlled in the subsequent working process.
[0033] In one configuration method, the pin is first configured as a tri-state gate, thereby realizing the change of the input and output direction of the pin and the monitoring of the pin. Then, according to the actual application scenario of the domestic FPGA chip, the working mode of the first pin configured as the tri-state gate is configured. The working mode can be an output mode or an input mode, which depends on the actual application scenario of the domestic FPGA chip.
[0034] During the operation phase of the domestic FPGA chip, the first pin configured as a tri-state gate in the domestic FPGA chip is connected to an external device. For the first pin whose working mode is input mode, the state information of the first pin can be collected, and the collected state information of the first pin is sent to the host computer at a preset time interval. The state information can be a signal input by an external device to the domestic FPGA chip, such as a high-level signal or a low-level signal. The preset time interval can be set according to actual usage and is not specifically limited here. For the first pin whose working mode is output mode, when receiving the pin state collection command of the host computer, the output signal of the first pin whose working mode is output mode can be collected.
[0035] External devices may include processors, fans, hard disks, graphics cards, and other external devices.
[0036] The domestic FPGA chip sends the status information of the first pin at a preset time interval with a first timestamp, and sends the status information of the first pin and the first timestamp corresponding to the information to the host computer. The timestamp increases from 0, and can be configured to update the pin status once every 1ms or 1us when sending.
[0037] The host computer can generate a detailed real-time report based on the received pin status information to display the pin status. In some examples, the host computer can synchronously receive the first pin status information and the accompanying first timestamp sent by the FPGA through a USART receiving tool, and generate a state diagram of the first pin with the help of a graphics drawing tool. For example, the received first pin status information can be drawn as a corresponding timing diagram through the Matplotlib tool. For example, the status information of 10 first pins can also be sent synchronously and drawn into the timing sequence relationship of multiple signals.
[0038] By monitoring the FPGA's pin status information, including input / output levels, current / voltage values, and the status of specific functional pins, you can timely understand the working conditions of each peripheral and detect whether the data collected by each sensor is normal; the host computer generates a real-time report in the form of a chart, including but not limited to pin number, current status, historical change trends, abnormal alarms, etc. These data help end users quickly understand the system operation status and perform necessary maintenance operations.
[0039] According to an embodiment of the present invention, during the initialization phase of the domestic FPGA chip, the first pin of the domestic FPGA chip is configured as a three-state gate, and the working mode of the first pin in the three-state gate state is configured, so that when the domestic FPGA chip is in the operation phase, the first pin configured as the three-state gate is connected to an external device, and based on the working mode of the first pin configured as the three-state gate, the state information of the first pin is collected, and the collected state information of the first pin is sent to a host computer at a preset time interval, thereby realizing the monitoring of the pins of the domestic FPGA chip, so that based on the monitoring of the pins of the domestic FPGA chip, the operation status of the external device connected thereto can be timely understood.
[0040] In some embodiments of the present invention, after configuring the corresponding working mode of the first pin in the tri-state gate state, the method further includes: configuring the working frequency of the first pin and the pin state acquisition frequency, the pin state acquisition frequency ≥ 1 / 2*working frequency.
[0041] Specifically, the built-in phase-locked loop (PLL) module of the domestic FPGA chip can be used to set the pin status acquisition frequency of the first pin to more than twice the operating frequency, thereby distinguishing the operating frequency and the pin status acquisition frequency, avoiding mutual interference of clock signals, and ensuring the integrity of each collected signal.
[0042] In some examples, the pin status acquisition frequency of the first pin may be set to 2 to 3 times the operating frequency.
[0043] In some embodiments of the present invention, the first pin of the domestic FPGA chip is configured as a tri-state gate, and the corresponding working mode of the first pin in the tri-state gate state is configured to include: When the first pin of a domestic FPGA chip is initialized, the direction of the pin to be detected is set to inout, the drive strength is set to the required value (such as 10, 15, 20, 25, 30 or 35, etc.) according to the actual application scenario, and the pull-up type is set to None. By setting the first pin to a tri-state gate state, the direction of the first pin can be set to input mode or output mode through the built-in control signal, thereby completing the control of the pin direction.
[0044] In some examples, assuming that the working mode of the first pin in the tri-state gate state is set to input mode, the value of the external device input (i.e., a high level signal or a low level signal input by the external device) can also be stored through a register variable (e.g., the always keyword), and the register variable can be saved in the built-in SRAM.
[0045] A register variable can store values input from several external devices. In some examples, each register variable can store up to 4096 values, and the first stored value can be discarded when it exceeds the limit.
[0046] In some examples, it is assumed that the working mode of the first pin in the tri-state gate state is set to output mode, and the level state of the pin output can be controlled by external instructions and internal logic. In this mode, no storage operation is performed, but the level state of the pin output can be obtained through external instructions when needed.
[0047] In some embodiments of the present invention, based on the working mode of the first pin, collecting the status information of the first pin may include: in response to the working mode of the first pin being an input mode, based on the first pin whose working mode is the input mode, receiving a signal input by an external device, and storing the received signal input by the external device in a predefined register variable, and reading the signal input by the external device from the register variable to collect the status information of the first pin whose working mode is the input mode.
[0048] In some examples, predefined register variables may also be stored in the memory of a domestic FPGA chip.
[0049] In some embodiments of the present invention, Figure 2 As shown, the method includes the following Figure 1 In addition to steps S10 to S12 shown, S13 may also be included.
[0050] S13, in response to receiving a pin status monitoring instruction sent by a host computer based on the domestic FPGA chip, sending the collected status information of the first pin to the host computer.
[0051] In some embodiments of the present invention, Figure 2 As shown, the method includes the following Figure 1 In addition to steps S10 to S12 shown, the method may further include S14.
[0052] S14, in response to receiving a pin state control instruction sent by a host computer based on the domestic FPGA chip, controlling the operation of the first pin based on the pin state control instruction.
[0053] In some embodiments of the present invention, the pin state control instruction may include a first control instruction, and controlling the operation of the first pin based on the pin state control instruction may include: controlling the sending behavior of the first pin whose working mode is input mode based on the first control instruction.
[0054] The first control instruction may be in a hexadecimal string format, but is not limited thereto, and may also be in other formats. When the first pin is in Input mode, the host computer may send a custom hexadecimal string to control the sending behavior of the FPGA chip. The hexadecimal string may include a stop sending behavior field and / or a start sending behavior field. For example, sending (0xAA, 0xFF, 0xBB) stops all sending behaviors on the FPGA side, where 0xAA represents the start field, 0xBB represents the end field, and 0xFF represents the stop sending behavior field for all pins. For example, sending (0xAA, 0x01, 0xBB) starts the sending process of a pin signal separately. For example, sending (0xAA, 0x01, 0x00, 0xCC) starts the signal edge-triggered sending mode, and the sending process is started only when the signal has a rising edge or a falling edge.
[0055] In one application scenario, during the startup phase of the FPGA chip, it is possible to monitor the pin status of the FPGA chip to observe whether the external device connected to it starts normally. If the external device starts normally, an instruction to stop sending the pin connected to the external device is sent to the FPGA chip to stop sending the collected status information of the pin to the host computer.
[0056] In one application scenario, one of the pins of the FPGA chip is connected to the CPU, and the other pin is connected to the memory. When the FPGA chip is running, the CPU sends a low pulse to the pin connected to the FPGA chip when it is turned off. When the FPGA chip pin status is monitored and the CPU connected to it is observed to be turned off, a pin status control instruction is sent to the FPGA chip to control the memory shutdown by controlling the pin connected to the memory.
[0057] In some embodiments of the present invention, the pin state control instruction may include a second control instruction, and controlling the operation of the first pin based on the pin state control instruction may include: controlling the direction of the first pin whose working mode is an output mode and / or the level state of the output signal based on the second control instruction.
[0058] The first control instruction can be in a hexadecimal string format, but is not limited to this, and can also be in other formats. When the first pin is in Output mode, the host computer can control the pin direction and high and low level states by sending a custom hexadecimal string. The hexadecimal string may include a pin direction field, a pin level field, and a pin number field. For example, the host computer can send (0xEE, 0x02, 0x01, 0x00, 0xFF) to the FPGA chip to control the pin direction and high and low level states of the FPGA chip. Among them, 0x02 means that the pin number is 02, 0x01 means that the pin direction is output, and 0x00 means that the pin level is low.
[0059] In some embodiments of the present invention, the method further includes: establishing an encrypted communication connection with a host computer based on a domestic FPGA chip.
[0060] Bidirectional communication between the FPGA chip and the host computer can be achieved through the internal interface. The interface can be any one of a USB interface, a USART serial port, and an I / O interface, which is not specifically limited here.
[0061] In some embodiments of the present invention, Figure 3 As shown, establishing an encrypted communication connection with a host computer based on a domestic FPGA chip may include the following steps S30-S34.
[0062] S30, generating information to be encrypted based on the domestic FPGA chip, and sending the information to be encrypted to the host computer.
[0063] Specifically, when the FPGA chip is burned, a 9-bit unique device identification code DSN can be written into the ROM storage. When the FPGA chip is started, a random function, such as the random() function, can be used to generate an 18-bit random encryption code RSN as the information to be encrypted.
[0064] When starting for the first time, it must be in a trusted environment. The FPGA chip sends a handshake request to the host computer to establish a communication connection. The handshake request contains the DSN.
[0065] S31, based on the upper computer, generates a public key and a private key according to the information to be encrypted sent by the domestic FPGA chip, and sends the public key to the domestic FPGA chip.
[0066] Specifically, the FPGA chip shakes hands with the host computer and prepares for key exchange. After receiving the handshake request sent by the FPGA chip, the host computer identifies the DSN and uses a random algorithm to generate a pair of public and private keys. The DSN of each FPGA chip corresponds to the public and private key pair generated by the host computer. The host computer returns the generated public key to the FPGA chip.
[0067] S32. Encrypt the information to be encrypted based on the public key sent by the host computer based on the domestic FPGA chip, obtain the encrypted information, and send the encrypted information to the host computer.
[0068] Specifically, the FPGA chip uses the public key to encrypt RSN and sends it to the host computer. Different encryption algorithms have different corresponding encryption processes. An encryption process using the RSA algorithm as the encryption algorithm is as follows: the public key transmitted by the host computer consists of two parts: the public key exponent e and the modulus e, which is usually the product of two large prime numbers, denoted as the public key (e, n), and the data to be encrypted is m; the random encryption code RSN is encrypted using the public key (e, n), and the resulting ciphertext is c. The encryption formula is ; Send c to the host computer.
[0069] S33, decrypting the encrypted information sent by the domestic FPGA chip through the private key based on the upper computer, obtaining decrypted information, and sending the decrypted information to the domestic FPGA chip.
[0070] The host computer decrypts the ciphertext. The decryption process is as follows: the private key is generated together with the public key. The private key consists of two parts, the exponent d and the modulus n, recorded as the private key (d, n); the encrypted data c is decrypted using the private key (d, n). In RSA, the decryption operation is to perform a d-power operation on the encrypted data c and then take the modulus n. This operation can be implemented using the pow(c, d, n) function, which is equivalent to . The decrypted m is sent back to the FPGA chip.
[0071] S34. Based on the domestic FPGA chip, determine whether the decrypted information is consistent with the information to be encrypted, and establish a communication connection with the host computer when the decrypted information is consistent with the information to be encrypted.
[0072] Based on the domestic FPGA chip, it is determined whether the decrypted information m is consistent with the information to be encrypted RSN. If m is consistent with RSN, the encryption and decryption test passes, the FPGA chip establishes a communication connection with the host computer, and writes the public key into the RAM storage for backup.
[0073] In some examples, when the FPGA chip is not started for the first time, the FPGA chip detects whether there is a public key in the ROM. If the public key is detected in the ROM, the host computer handshake operation is directly performed. The chip generates a new RSN through a random function, encrypts it with the public key and sends it to the host computer. If the decrypted information sent back by the host computer is consistent with the new RSN, the verification is passed and communication is established; if it is inconsistent, the operation stops.
[0074] After the encrypted communication connection between the FPGA chip and the host computer is established, the FPGA chip will regularly send various information to the host computer, including its own operating status, the level status of each pin, etc. At the same time, the FPGA chip will also receive instructions from the host computer and adjust its own operating parameters or perform specific operations according to these instructions.
[0075] The embodiments of the present invention achieve a high degree of integration of signal processing, which can not only accurately control the pin status, but also perform real-time acquisition and preliminary processing of signals, thereby greatly improving the integration and reliability of the applied system.
[0076] The embodiment of the present invention realizes two-way communication between the FPGA chip and the host computer through the internal interface. The host computer can send a query instruction, and the FPGA chip returns the current pin signal state according to the instruction, so as to obtain the operating state of the external device in time, ensuring the real-time and accuracy of the information.
[0077] In the embodiment of the present invention, the domestic FPGA chip and the host computer adopt an encryption mechanism during the communication process, and verify the identities of the communicating parties by encryption and decryption, which effectively prevents data leakage and illegal access and improves the security of the system.
[0078] In the embodiment of the present invention, after the data received by the host computer is processed, detailed real-time reports can be generated. These reports provide users with an intuitive display of the pin status, which is convenient for system monitoring and maintenance.
[0079] The embodiments of the present invention are applicable to a variety of industries and application scenarios, such as industrial control, aerospace, communication networks, etc., and meet the needs of different fields for pin signal status monitoring.
[0080] Based on the same inventive concept, according to another aspect of the present invention, the embodiment of the present invention also provides a pin monitoring system based on a domestic FPGA chip, such as Figure 4 As shown, the pin system 40 based on the domestic FPGA chip includes: a domestic FPGA chip 41 and a host computer 42.
[0081] The domestic FPGA chip 41 includes a plurality of first pins, each of which is configured as a three-state gate and has a corresponding working mode.
[0082] The domestic FPGA chip 41 is further configured to, in response to being in the running stage and the first pin being connected to an external device, collect the status information of the first pin based on the working mode of the first pin, and send the collected status information of the first pin to the host computer 42 at a preset time interval.
[0083] In the embodiment of the present invention, in the initialization stage of the domestic FPGA chip, several first pins of the domestic FPGA chip are configured as tri-state gates, and different working modes of each first pin in the tri-state gate state are configured. Thus, when the domestic FPGA chip is in the running stage, it can be connected to an external device through the first pin configured as a tri-state gate, and based on the working mode of the first pin configured as a tri-state gate, collect the status information of the first pin, and send the collected status information of the first pin to the host computer at a preset time interval. Thereby, the monitoring of the pins of the domestic FPGA chip is realized, and based on the monitoring of the pins of the domestic FPGA chip, the operation status of the external device connected thereto can be understood in a timely manner.
[0084] In some embodiments of the present invention, as Figure 5 shown, the pin system 40 based on the domestic FPGA chip further includes an encryption module 43 in addition to the domestic FPGA chip 41 and the host computer 42.
[0085] The encryption module 43 is configured to adopt an encryption mechanism to verify the identities of both parties when establishing a communication connection between the FPGA chip and the host computer.
[0086] After the communication connection between the FPGA chip 41 and the host computer 42 is established, the FPGA chip will collect the pin status information and regularly send the collected pin status information to the host computer. At the same time, the FPGA chip will also receive instructions from the host computer and adjust its own pin status according to these instructions.
[0087] Based on the same inventive concept, according to another aspect of the present invention, the FPGA chip provided by the embodiment of the present invention includes a processor and a memory, the memory stores a computer program that can run on the processor, and when the processor executes the program, it executes the steps of the above method.
[0088] Among them, as a non-volatile storage medium, the memory can be used to store non-volatile software programs, non-volatile computer executable programs, and modules, such as the program instructions / modules corresponding to the compression method in the embodiment of the present application. The processor runs the non-volatile software programs, instructions, and modules stored in the memory, thereby implementing various functional applications and data processing of the device, that is, implementing the compression method in the above method embodiment.
[0089] The memory may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the device, etc. In addition, the memory may include a high-speed random access memory, and may also include a non-volatile memory, such as at least one disk storage device, a flash memory device, or other non-volatile solid-state storage device. In some embodiments, the memory may optionally include a memory remotely arranged relative to the processor, and these remote memories may be connected to the local module via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.
[0090] Based on the same inventive concept, according to another aspect of the present invention, an embodiment of the present invention further provides a computer storage medium, which stores a computer program that performs the above method when executed by a processor.
[0091] Finally, it should be noted that a person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiments can be implemented by instructing the relevant hardware through a computer program, and the program can be stored in a computer-readable storage medium. When the program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, the storage medium of the program can be a disk, an optical disk, a read-only storage memory (ROM) or a random access memory (RAM), etc. The above-mentioned computer program embodiments can achieve the same or similar effects as the corresponding above-mentioned any method embodiments.
[0092] It will also be appreciated by those skilled in the art that various exemplary logic blocks, modules, circuits and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software or a combination of the two. In order to clearly illustrate this interchangeability of hardware and software, a general description has been given to the functions of various schematic components, blocks, modules, circuits and steps. Whether this function is implemented as software or hardware depends on specific applications and the design constraints imposed on the entire system. Those skilled in the art can implement the function in various ways for each specific application, but this implementation decision should not be interpreted as causing a departure from the disclosed scope of the embodiments of the present invention.
[0093] The above are exemplary embodiments disclosed in the present invention, but it should be noted that various changes and modifications may be made without departing from the scope of the embodiments disclosed in the present invention as defined in the claims. The functions, steps and / or actions of the method claims according to the disclosed embodiments described herein do not need to be performed in any particular order. The serial numbers of the embodiments disclosed in the above embodiments of the present invention are for description only and do not represent the advantages and disadvantages of the embodiments. In addition, although the elements disclosed in the embodiments of the present invention may be described or required in individual form, they may also be understood as multiple unless explicitly limited to the singular.
[0094] It should be understood that, as used herein, the singular forms "a", "an" are intended to include the plural forms as well, unless the context clearly supports an exception. It should also be understood that, as used herein, "and / or" refers to any and all possible combinations including one or more of the associated listed items.
[0095] A person skilled in the art should understand that the discussion of any of the above embodiments is only exemplary and is not intended to imply that the scope of the disclosure of the embodiments of the present invention (including the claims) is limited to these examples; under the concept of the embodiments of the present invention, the technical features in the above embodiments or different embodiments can also be combined, and there are many other changes in different aspects of the above embodiments of the present invention, which are not provided in detail for the sake of simplicity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present invention should be included in the protection scope of the embodiments of the present invention.
Claims
1. A pin monitoring method based on domestic FPGA chip, characterized in that: include: Configure several first pins of the domestic FPGA chip as tri-state gates, and configure the corresponding working mode of each of the first pins in the tri-state gate state; In response to the domestic FPGA chip being in an operation stage and the domestic FPGA chip being connected to an external device through a first pin, based on a working mode of the first pin, collecting state information of the first pin; The collected state information of the first pin is sent to a host computer at a preset time interval.
2. The method according to claim 1, characterized in that Based on the working mode of the first pin, collecting the state information of the first pin includes: In response to the working mode of the first pin being the input mode, receiving a signal input by an external device based on the first pin working in the input mode, and storing the received signal input by the external device in a predefined register variable; A signal input from an external device is read from the register variable to collect state information of the first pin whose working mode is an input mode.
3. The method according to claim 1, characterized in that Also includes: In response to receiving a pin status control instruction sent by a host computer based on the domestic FPGA chip, the operation of the first pin is controlled based on the pin status control instruction.
4. The method according to claim 3, characterized in that The pin state control instruction includes a first control instruction, and controlling the operation of the first pin based on the pin state control instruction includes: The sending behavior of the first pin whose working mode is the input mode is controlled based on the first control instruction.
5. The method according to claim 3, characterized in that: The pin state control instruction includes a second control instruction, and the controlling the operation of the first pin based on the pin state control instruction includes: Based on the second control instruction, the direction of the first pin whose working mode is the output mode and / or the level state of the output signal are controlled.
6. The method according to claim 1, characterized in that Also includes: An encrypted communication connection is established with the host computer based on the domestic FPGA chip.
7. The method according to claim 6, characterized in that Establishing an encrypted communication connection between the domestic FPGA chip and the host computer includes: Generate information to be encrypted based on the domestic FPGA chip, send the information to be encrypted to a host computer, and receive a public key returned by the host computer; Encrypting the information to be encrypted based on the domestic FPGA chip according to the public key to obtain encrypted information, sending the encrypted information to the host computer and receiving decrypted information returned by the host computer; Based on the domestic FPGA chip, it is determined whether the decrypted information is consistent with the information to be encrypted, and a communication connection is established with the host computer when the decrypted information is consistent with the information to be encrypted.
8. The method according to claim 7, characterized in that Also includes: Based on the upper computer, a public key and a private key are generated according to the information to be encrypted sent by the domestic FPGA chip, and the public key is sent to the domestic FPGA chip; The encrypted information sent by the domestic FPGA chip is decrypted by the host computer through the private key to obtain decrypted information, and the decrypted information is sent to the domestic FPGA chip.
9. The method according to claim 1, characterized in that: After configuring the corresponding working mode of each of the first pins in the tri-state gate state, the method further includes: The operating frequency and the pin status acquisition frequency of the first pin are configured, and the pin status acquisition frequency is ≥ 1 / 2*the operating frequency.
10. A pin monitoring system based on domestic FPGA chip, characterized in that: include: Domestic FPGA chips and host computers; The domestic FPGA chip includes a plurality of first pins, each of which is configured as a tri-state gate and has a corresponding working mode; The domestic FPGA chip is also configured to respond to being in an operating stage and having the first pin connected to an external device, collect status information of the first pin based on the working mode of the first pin, and send the collected status information of the first pin to the host computer at a preset time interval.