MCU parameter test system and test method

Abstract

The invention relates to the technical field of MCU service, and discloses an MCU parameter test system and method, and the system comprises an ATE test platform which employs a PPMU module, provides an analog input signal for an ADC module in a to-be-tested MCU, obtains an actual output signal of the ADC module, compares the actual output signal with a theoretical expected output, and determines whether the performance of the ADC module meets a preset standard or not; and the ATE test platform, when the test value of the oscillator in the to-be-tested MCU deviates from the preset target value, querying the optimal trimming code matched with the preset target value according to a full search algorithm by using the trimming function module, and correcting the parameters of the oscillator by using the optimal trimming code. According to the system provided by the embodiment of the invention, through the modules in the ATE test platform, automatic test of multiple parameters of the MCU is realized, manual intervention is reduced, and the test efficiency is improved. An analog voltage signal provided by the PPMU module is adopted, so that the accurate test of each high-integration-level functional module of the MCU is ensured, and the test accuracy is improved.

Description

Technical Field

[0001] The present disclosure relates to the field of MCU service technology, and in particular to an MCU parameter testing system and testing method. Background Art

[0002] For testing of microcontroller units (MCU) chips, related technologies often use traditional automatic test equipment platforms (Automatic Test Equipment, ATE) to perform functional tests and electrical performance tests.

[0003] However, as the integration and complexity of MCUs increase, the ATE system in the related art cannot test the highly integrated modules in the MCU chip well, resulting in low test efficiency for the MCU chip. Therefore, how to enable the ATE system to efficiently test the highly integrated modules in the MCU chip and improve the test efficiency for the MCU chip has become an urgent problem to be solved. Summary of the invention

[0004] In view of this, the present disclosure provides an MCU parameter testing system and a testing method to solve the problem of how to enable the ATE system to efficiently test highly integrated modules in the MCU chip and improve the testing efficiency of the MCU chip.

[0005] On the one hand, the present disclosure provides an MCU parameter testing system, the system includes: a test adapter, a power module and an ATE test platform, the ATE test platform includes: a signal generator, a measurement unit, a control software module, a PPMU module, a trimming function module, and a statistical analysis module, wherein: the test adapter connects the pins of the MCU to be tested to the ATE test platform so that the MCU to be tested is electrically connected to the ATE test platform; the test adapter is composed of a test board and a test socket; the power module provides a preset constant voltage to the MCU to be tested; the ATE test platform generates an excitation signal based on the signal generator, inputs the excitation signal to the MCU to be tested, captures the output information generated by the MCU to be tested according to the excitation signal based on the measurement unit, and adopts the control software module to analyze the output The ATE test platform uses the PPMU module to provide analog input signals to the ADC module in the MCU under test, obtains the actual output signal of the ADC module, compares the actual output signal with the theoretical expected output, and determines whether the performance of the ADC module meets the preset standard. The ATE test platform uses the trimming function module to query the best trimming code that matches the preset target value according to the full search algorithm when the test value of the oscillator in the MCU under test deviates from the preset target value, and uses the best trimming code to correct the parameters of the oscillator. The ATE test platform uses the statistical analysis module to perform statistical analysis on the LDO output voltage of at least one sample of the MCU under test, and screens out abnormal samples whose output voltage deviates from the preset qualified range in at least one sample.

[0006] On the other hand, the present disclosure also provides a testing method, which includes: connecting the pins of the MCU to be tested to the ATE test platform based on a test adapter, and electrically connecting the MCU to be tested to the ATE test platform; the test adapter is composed of a test board and a test socket; using a power supply module to provide a preset constant voltage to the MCU to be tested; using a signal generator in the ATE test platform to generate an excitation signal, and inputting the excitation signal into the MCU to be tested; using a measurement unit in the ATE test platform to capture output information generated by the MCU to be tested according to the excitation signal; using a control software module in the ATE test platform to analyze the output information and generate a test report for the MCU to be tested; using a PP in the ATE test platform The MU module provides an analog input signal to the ADC module in the MCU to be tested, obtains the actual output signal of the ADC module, compares the actual output signal with the theoretical expected output, and determines whether the performance of the ADC module meets the preset standard; when the test value of the oscillator in the MCU to be tested deviates from the preset target value, the trimming function module in the ATE test platform is used to query the best trimming code that matches the preset target value according to the full search algorithm, and the parameters of the oscillator are corrected by using the best trimming code; the statistical analysis module in the ATE test platform is used to perform statistical analysis on the LDO output voltage of at least one sample of the MCU to be tested, and screen out abnormal samples whose output voltage deviates from the preset qualified range in at least one sample.

[0007] On the other hand, the present disclosure further provides a computer-readable storage medium, on which computer instructions are stored, and the computer instructions are used to enable a computer to implement the above-mentioned test method.

[0008] Another aspect of the present disclosure further provides a computer program product, including computer instructions, where the computer instructions are used to enable a computer to execute the above-mentioned testing method.

[0009] Through the MCU parameter test system and test method of the above-mentioned embodiment of the present disclosure, the excitation signal generated by the signal generator and the analog voltage signal provided by the PPMU module ensure accurate testing of the highly integrated functional modules of the MCU (such as ADC module, oscillator, etc.). By comparing with the preset standard, the test system can accurately evaluate the performance of the MCU, ensure its stability and reliability in use, and improve the test efficiency of the MCU. Through the modules in the ATE test platform, automated testing of multiple parameters of the MCU can be achieved, reducing manual intervention and improving test efficiency. At the same time, the system can quickly complete the test in mass production, which is particularly suitable for large-scale MCU testing on production lines.

[0010] In addition, through the modules in the ATE test platform, it is possible to realize automated testing of multiple parameters of the MCU, reduce manual intervention, and improve test efficiency. At the same time, the system can quickly complete the test in mass production, which is especially suitable for large-scale MCU testing on the production line. Through the trimming function module, when it is detected that the MCU's oscillator deviates from the target frequency, it can automatically perform a full search algorithm to find the best trimming code and burn it to ensure that the oscillator performance meets the design standard, improve the production test accuracy of the MCU, and reduce the need for manual adjustment and repeated debugging, further improving the test efficiency for the MCU. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the specific embodiments of the present disclosure or the technical solutions in the related technologies, the drawings required for use in the specific embodiments or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0012] Figure 1 An exemplary schematic diagram showing the architecture of an MCU parameter testing system according to an embodiment of the present disclosure;

[0013] Figure 2 A schematic diagram of the adjustment principle of an MCU parameter testing system according to an embodiment of the present disclosure is shown;

[0014] Figure 3 A schematic diagram of a control software module architecture of an MCU parameter testing system according to an embodiment of the present disclosure is shown;

[0015] Figure 4 Another control software module architecture schematic diagram of an MCU parameter testing system according to an embodiment of the present disclosure is shown;

[0016] Figure 5 An ADC analog input-output relationship diagram of an MCU parameter test system according to an embodiment of the present disclosure is shown;

[0017] Figure 6 is a flow chart of a testing method provided by an embodiment of the present disclosure;

[0018] Figure 7 It is a structural diagram of an MCU parameter testing system provided by an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] For the testing of MCU chips, the related technologies often use traditional ATE platforms for functional testing and electrical performance testing. ATE platforms usually include components such as signal generators, measurement units, and control software, which are used to generate stimulus signals, capture output waveforms, and analyze results; for example, Teradyne J750 series ATE is widely used in mass production testing of MCU chips. It can provide high-precision digital channel resources and independent parameter measurement units, and support multi-site parallel testing.

[0020] However, with the increase in MCU integration and complexity, the ATE system in related technologies has gradually become a bottleneck in the MCU testing process, and there are the following problems:

[0021] 1. The ATE platform in related technologies is usually designed and configured for testing specific chips or fixed-function modules. With the diversification of MCU chip functions and the improvement of integration, testing requirements are becoming more and more complex. Each different model of MCU requires customized test procedures based on its specific functions. The ATE platform in related technologies is not flexible enough, resulting in a long development cycle and high costs.

[0022] 2. When performing tests on highly integrated modules in MCUs, ATE platforms in related technologies usually have difficulty in providing real-time adjustment and flexibility, resulting in low test efficiency and accuracy.

[0023] 3. The ATE platform in the related art relies too much on manual adjustment or simple automatic adjustment strategies during the adjustment process, resulting in slow adjustment speed and poor accuracy.

[0024] In order to solve the above problems, various embodiments of the present disclosure provide an MCU parameter testing system, the system includes: a test adapter, a power module and an ATE test platform, the ATE test platform includes: a signal generator, a measurement unit, a control software module, a PPMU module, a trimming function module, and a statistical analysis module, wherein: the test adapter connects the pins of the MCU to be tested to the ATE test platform so that the MCU to be tested is electrically connected to the ATE test platform; the test adapter is composed of a test board and a test socket; the power module provides a preset constant voltage to the MCU to be tested; the ATE test platform generates an excitation signal based on the signal generator, inputs the excitation signal to the MCU to be tested, and captures the output information generated by the MCU to be tested according to the excitation signal based on the measurement unit, and adopts the control software module , analyze the output information, and generate a test report for the MCU to be tested; the ATE test platform uses the PPMU module to provide an analog input signal to the ADC module in the MCU to be tested, obtain the actual output signal of the ADC module, compare the actual output signal with the theoretical expected output, and determine whether the performance of the ADC module meets the preset standard; the ATE test platform, when the test value of the oscillator in the MCU to be tested deviates from the preset target value, uses the trimming function module to query the best trimming code that matches the preset target value according to the full search algorithm, and uses the best trimming code to correct the parameters of the oscillator; the ATE test platform uses the statistical analysis module to perform statistical analysis on the LDO output voltage of at least one sample of the MCU to be tested, and screens out abnormal samples whose output voltage deviates from the preset qualified range in at least one sample.

[0025] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present disclosure.

[0026] Please refer to Figure 1 , Figure 1 FIG. 1 is an exemplary schematic diagram showing the architecture of an MCU parameter test system according to an embodiment of the present disclosure. Figure 1 As shown, the system includes: a test adapter, a power module and an ATE test platform. The ATE test platform includes: a signal generator, a measurement unit, a control software module, a PPMU module, a trimming function module, and a statistical analysis module, wherein:

[0027] The test adapter connects the pins of the MCU to be tested to the ATE test platform so that the MCU to be tested and the ATE test platform are electrically connected; the test adapter is composed of a test board and a test socket.

[0028] In this embodiment, the MCU to be tested refers to an MCU that is being tested, which may be a newly produced chip or an existing chip that needs further verification and debugging.

[0029] The test adapter is composed of a test board (Loadboard) and a test socket (Socket). The test adapter uses the test board to connect the pins of the MCU to be tested to the ATE test platform to achieve electrical connection between the MCU to be tested and the ATE test platform (hereinafter referred to as the platform). The test adapter uses the test socket to ensure the stability of the physical contact between the MCU to be tested and the platform.

[0030] As an example, the test board in the test adapter can be provided with at least one external frequency input interface for accessing the interface of the external oscillator to ensure that the clock source of the MCU to be tested can be correctly input. Here, the external oscillator can be 32.768kHz or 8MHz. The platform can use Teradyne J750Ex-HD with high-precision digital channel resources, independent parameter measurement units and multi-site parallel measurement capabilities.

[0031] Preferably, the test board in the test adapter can adopt a four-layer circuit board structure, and the dimensional tolerance of the circuit board can be controlled within 0.1 mm. The characteristic impedance of the circuit board is continuous, and the wiring of two adjacent layers follows the principle of vertical routing to reduce crosstalk between power signal routing. The operating current on the circuit board is set to 10 mA. The resistor R0 at the output end is set to 10 kΩ, the other resistor R1 is set to 5.1 Ω, the first capacitor C1 is set to 1 μF, and the second capacitor C0 is set to 0.1 μF. Among them, the larger 1 μF capacitor of C1 can be used for low-frequency filtering, and the smaller 0.1 μF capacitor of C0 can be used for high-frequency filtering. Furthermore, the reset terminal is connected to the power supply voltage V through a 1 kΩ resistor. cc , ensure that the reset terminal level is high. Connect the reset terminal to ground through a 1μF capacitor to filter or eliminate noise in the reset signal to ensure the stability of the reset action.

[0032] Preferably, the Teradyne J750Ex-HD can specifically include at least one of the following: a high-speed digital 800 board (HSD800), which provides digital function and characteristic analysis tests; a memory test option (MTO) for embedded memory testing; a digital signal transmission and reception (DSSC), which is installed behind each pin and is used to store and mix signals; a deep scan history RAM (DSHRAM), which is suitable for DFT-based SCAN testing; a high-voltage digital (HVD) function, which is used for embedded flash memory testing; a high-density chip power supply board (HDDPS), which is used to provide high-performance precision-controlled chip power supply; a high-density VI source board (HDVIS), which is used for high-bit number testing, and precise control of measurement time points using test vectors; a mixed signal option (MSO), which is used for audio testing of embedded analog components; a high-density converter test option (HDCTO), which is used to test embedded ADC / DAC converters; a high-density analog pin measurement unit (HDAPMU), which is used for mixed signal testing.

[0033] The power module provides a preset constant voltage to the MCU under test.

[0034] In this embodiment, the power module provides the required voltage source for the MCU to be tested, so as to ensure that the MCU to be tested obtains a stable power supply during the test process, thereby avoiding the impact of voltage fluctuations on the function and performance of the MCU. The preset constant voltage can be a 5V power supply voltage V cc .

[0035] The ATE test platform generates an excitation signal based on a signal generator, inputs the excitation signal into the MCU under test, captures the output information generated by the MCU under test according to the excitation signal based on the measurement unit, uses the control software module to analyze the output information, and generates a test report for the MCU under test.

[0036] In this embodiment, the signal generator can be a device in the platform for generating a standard electrical signal, which can provide a known and stable signal to stimulate the MCU under test by serving as a test input signal source. The stimulus signal can include but is not limited to: sine wave, square wave, pulse, etc.

[0037] The measurement unit can be a component in the platform that captures the signal output by the MCU under test and performs precise measurement.

[0038] Preferably, the measuring unit can perform measurements at a resolution of 1 millivolt level, so as to accurately compare the output information of the MCU to be tested with the theoretical expected output value and determine whether the specification requirements are met.

[0039] The control software module can be a software system running on a preset operating system, which is used to perform functional and performance tests on the MCU to be tested. The control software module can provide a control and operation interface for the platform, and perform analysis and data processing. For example, the control software module can run on the Windows NT operating system and support Visual Basic language development.

[0040] Furthermore, the test report of the MCU to be tested generated by the control software module may include at least one of the following: basic information of the MCU, power supply voltage parameters, function test results, performance test results, adjustment results, etc.

[0041] The ATE test platform uses the PPMU module to provide analog input signals to the ADC module in the MCU under test, obtain the actual output signal of the ADC module, compare the actual output signal with the theoretical expected output, and determine whether the performance of the ADC module meets the preset standards.

[0042] In this embodiment, the precision power measurement unit (PPMU) module may be a module in the platform for accurately measuring and controlling parameters such as current and voltage of the MCU to be tested.

[0043] Specifically, the PPMU module can accurately provide a certain range of voltage signals to the MCU under test, and can control the amplitude and stability of the voltage, and can also accurately apply current and simulated current driving conditions to the MCU under test.

[0044] Preferably, the accuracy of the PPMU module may be at the 1 millivolt level.

[0045] In a possible implementation, the analog input signal provided to the ADC module in the MCU to be tested by the PPMU module may be an analog voltage signal; the actual output signal of the ADC module may be a digital signal corresponding to the analog voltage signal converted by the ADC module; the theoretical expected output may be a digital output signal that is expected to be obtained under ideal conditions based on known analog input signals and conversion characteristics of the ADC, which may be calculated based on the conversion formula or characteristics of the ADC module.

[0046] The ATE test platform uses a trimming function module to query the best trimming code that matches the preset target value according to the full search algorithm when the test value of the oscillator in the MCU to be tested deviates from the preset target value, and uses the best trimming code to correct the parameters of the oscillator.

[0047] In this embodiment, the oscillator in the MCU to be tested can provide a clock signal to drive each module in the chip.

[0048] The query according to the full search algorithm may include: the adjustment function module tries different adjustment codes one by one to find the best adjustment code that matches the preset target value. Wherein, matching may refer to finding the best adjustment code that is closest to the preset target value; the full search algorithm is an exhaustive method.

[0049] As an example, see Figure 2 , Figure 2 The present invention shows a tuning principle diagram of an MCU parameter test system according to an embodiment of the present invention, wherein the tuning code is written into the memory, and the corresponding data controls different switches to control the logic circuit, and the resistor / capacitor network is tuned to make the output parameters of the circuit close to the ideal value.

[0050] Furthermore, after finding the best trimming code, the platform writes the best trimming code into the oscillator control register of the MCU to be tested to adjust the parameters of the oscillator so that the output frequency of the oscillator is closer to the preset target value.

[0051] The ATE test platform adopts a statistical analysis module to perform statistical analysis on the LDO output voltage of at least one sample of the MCU to be tested, and screens out abnormal samples whose output voltage deviates from a preset qualified range in the at least one sample.

[0052] In this embodiment, a statistical analysis module is used to perform statistical analysis on the trimmed output voltage of the low-dropout (LDO) regulator in the mass-produced MCU samples to be tested, and unqualified abnormal samples are eliminated to ensure that the remaining large samples meet the predetermined quality standards.

[0053] As an example, the preset qualified range may be 1.45V to 1.55V, and any sample with an output voltage lower than 1.45V or higher than 1.55V is considered an abnormal sample; the ideal value is set to 1.5V, which is the ideal output voltage of the LDO.

[0054] In the MCU parameter test system and test method of the above-mentioned embodiment of the present disclosure, the excitation signal generated by the signal generator and the analog voltage signal provided by the PPMU module ensure the accurate test of the highly integrated functional modules of the MCU (such as ADC module, oscillator, etc.). By comparing with the preset standard, the test system can accurately evaluate the performance of the MCU, ensure its stability and reliability in use, improve the test efficiency of the MCU, and reduce the development cycle and test costs. Through the modules in the ATE test platform, it is possible to realize automated testing of multiple parameters of the MCU, reduce manual intervention, and improve test efficiency. At the same time, the system can quickly complete the test in mass production, which is particularly suitable for large-scale MCU testing on production lines.

[0055] In addition, through the modules in the ATE test platform, it is possible to realize automated testing of multiple parameters of the MCU, reduce manual intervention, and improve test efficiency. At the same time, the system can quickly complete the test in mass production, which is especially suitable for large-scale MCU testing on the production line. Through the trimming function module, when it is detected that the MCU's oscillator deviates from the target frequency, it can automatically perform a full search algorithm to find the best trimming code and burn it to ensure that the oscillator performance meets the design standard, improve the production test accuracy of the MCU, and reduce the need for manual adjustment and repeated debugging, further improving the test efficiency for the MCU.

[0056] In a possible implementation of the above embodiment, please refer to Figure 3 , Figure 3 FIG. 1 is a schematic diagram showing a control software module architecture of an MCU parameter test system according to an embodiment of the present disclosure. Figure 3 As shown, the control software module includes: waveform analysis tool, vector analysis tool, debugging hardware Debug window tool, memory test tool, among which:

[0057] The control software module uses a waveform analysis tool to analyze the waveform signal in the output information of the MCU to be tested;

[0058] The control software module uses vector analysis tools to analyze the digital signals in the output information of the MCU under test;

[0059] The control software module uses the debugging hardware Debug window tool to display and debug the hardware status in the output information of the MCU under test;

[0060] The control software module uses the memory test tool to perform read and write tests on the internal memory of the MCU to be tested;

[0061] The control software module also includes the IG-XL software environment module, which is used to write the corresponding test code for the PLL module in the MCU to be tested, including:

[0062] IG-XL software environment module sends test code to the ATE test platform and starts the target test mode in the ATE test platform. The target test mode is used to test the PLL module.

[0063] The ATE test platform, in the target test mode, generates a preset square wave signal as a test signal, inputs the test signal to the input end of the PLL module, measures the actual output frequency of the output end of the PLL module, and tests the performance of the PLL module based on the actual output frequency.

[0064] In this embodiment, the control software module uses at least one of a waveform analysis tool, a vector analysis tool, a debugging hardware Debug window tool, and a memory test tool to test and analyze the output information of the MCU to be tested.

[0065] Furthermore, the IG-XL software environment module also included in the control software module can be a software environment specially designed for ATE test systems, which can be widely used in chip testing and system verification, especially in high-precision and high-complexity test scenarios.

[0066] Specifically, the functions of the IG-XL software environment module may include at least one of the following: test program writing and management, hardware and equipment control, and test report generation and analysis. Among them, test program writing and management means that the IG-XL software environment module can support the use of high-level programming languages ​​to write test programs, automate the test process, and save time for manual testing; hardware and equipment control means that the IG-XL software environment module can control the test hardware through the software interface, send excitation signals, receive measurement data, and control external devices; test report generation and analysis means that the IG-XL software environment module can support real-time data collection, analysis, and processing of test results, and generate detailed test reports to facilitate subsequent quality control and troubleshooting.

[0067] In one possible implementation, the IG-XL software environment module may include multiple configuration and test steps when testing the MCU to be tested, for example, including but not limited to pin definition, test system channel configuration, power supply and I / O configuration, voltage / current / timing test configuration, and ATE test vector generation.

[0068] As an example, during the test of the Phase-Locked Loop (PLL) module in the MCU to be tested, the IG-XL software environment controls the platform by writing specific test codes, generates input signals suitable for testing the PLL module, and measures the output frequency.

[0069] The IG-XL software environment module sends test code to the ATE test platform and starts the target test mode in the ATE test platform. The target test mode is used to test the PLL module and may include:

[0070] The IG-XL software environment module writes test codes for the control platform, and defines the operations for functional verification of the PLL module in the test codes, including but not limited to: setting input frequency, duty cycle setting, and adjusting level setting;

[0071] The IG-XL software environment module loads the test code to the platform through the software interface and starts the target test mode.

[0072] The ATE test platform generates a preset square wave signal as a test signal in a target test mode, inputs the test signal to an input end of a PLL module, measures an actual output frequency of an output end of the PLL module, and tests the performance of the PLL module based on the actual output frequency, which may include:

[0073] In the target test mode, the platform inputs a preset square wave signal with a frequency of 10 MHz and a duty cycle of 50% to the input end of the PLL module as a test signal to simulate the input excitation signal to the PLL module;

[0074] The platform measures the actual output frequency at the output end, compares the actual output frequency with the theoretical expected frequency, and determines whether the working performance of the PLL module meets the preset standards; the IG-XL software environment module generates a test report on the PLL module.

[0075] Among them, the input end refers to the PLLCKI end, and the output end refers to the PLLCKOT end.

[0076] In a possible implementation of the above embodiment, please refer to Figure 4 , Figure 4 FIG. 2 is a schematic diagram showing another control software module architecture of an MCU parameter test system according to an embodiment of the present disclosure. Figure 4 As shown, the control software module may also include a memory built-in self-test (MBIST) module, which can be used to perform read and write tests on the static random-access memory (SRAM) and flash memory of the MCU to ensure that the memory functions normally. Among them, the MBIST test can be a self-test method for memory, which automatically performs memory testing through a hardware module integrated into the chip without the need for external testing equipment.

[0077] As an example, the read and write test of the MBIST module may include an SRAM test and a Flash test, wherein the SRAM test may include but is not limited to an all-0 test, an all-1 test, a checkerboard method, a step-by-step method, and a March algorithm.

[0078] Preferably, the March algorithm can be used to perform MBIST testing, the IG-XL software environment module sends the MBIST test code to the ATE test platform, starts the MBIST test mode in the ATE test platform, and the BIST module in the MCU to be tested starts the memory test and executes the March algorithm. When the test is completed, a high level is output through MBIST-DONE to indicate that the test is completed. The MBIST_FAIL output is given according to the test result: if the test result is a failure, MBIST_FAIL outputs a high level, indicating that the memory is defective; if the test passes, MBIST_FAIL outputs a low level.

[0079] For embedded Flash testing, related technologies often use traversal of all storage units to perform programming, reading, writing, erasing and other operations on the Flash for verification. However, directly traversing all data units is inefficient, especially for larger Flash memories. This method will result in a long test time.

[0080] Preferably, the Flash test in the present disclosure can be performed by dividing the Flash into Pages (1KB), and dividing the Flash into multiple smaller units (Pages); making each 4 Pages into a group, and each group corresponding to different address bits for operation; performing programming, reading, writing, erasing and other operations on each Page to ensure the reliability and correctness of the Flash storage unit under different operations.

[0081] In the MCU parameter test system and test method of the above-mentioned embodiment of the present disclosure, by providing advanced programming support for the ATE test platform, the test process is automated, and the need for manual operation is reduced. Automated test code generation and management not only improves test efficiency, but also reduces human errors and ensures the consistency and repeatability of the test. By using the IG-XL software environment module to automate test code writing, equipment control and test report generation, the burden on developers can be significantly reduced, the test cycle can be shortened, and the development cost can be reduced. Through the synergy of the control software module and the IG-XL software environment module, a detailed test report can be automatically generated. For the testing of multiple modules such as PLL modules, SRAM, Flash, etc., it can ensure the full verification of all important functions, reducing the time and cost of manual testing and debugging. The March algorithm is used for memory testing, providing a more comprehensive and efficient memory detection method. Through built-in self-test, it does not rely on external test equipment, reduces external interference, and improves the test coverage and accuracy of memory. During the Flash test, the page division method is adopted. Each test only operates on the 1KB unit, avoiding the inefficient process of traversing the entire memory; the address bit grouping method is adopted, and every 4 pages are divided into a group, and programming, reading, writing and erasing operations are performed on different address bits. This grouping method can not only ensure the coverage, but also improve the pertinence of the operation and avoid redundant testing.

[0082] In a possible implementation of the above embodiment, the ATE test platform is specifically used for:

[0083] Use any of the 16 analog input channels in the PPMU module, send an analog voltage signal to the ADC module based on the input range of the ADC module in the MCU to be tested, obtain 16 digital output results determined by the ADC module based on the conversion of the 16 analog voltage signals, compare the 16 digital output results with the theoretical expected output, and determine whether the performance of the ADC module meets the preset standards.

[0084] In this embodiment, the ADC module in the MCU to be tested may be a 12-bit high-precision ADC module, so that the test of the MCU to be tested becomes a test of a mixed signal chip in which digital signals and analog signals are mixed.

[0085] Specifically, the platform uses each analog input channel (XAIN_0~XAIN_15) in the PPMU module to apply preset voltage values ​​to the ADC module as analog voltage signals; the ADC module performs corresponding digital output for each voltage value and obtains 16 digital output results; according to the accuracy and input range of the ADC module, the theoretical expected output corresponding to each voltage is calculated; the 16 digital output results are compared with the theoretical expected output to determine whether the performance of the ADC module meets the preset standards.

[0086] As an example, 16 analog voltage signals may look like this:

[0087] V in

[16]

[0088] ={0.10,0.42,0.74,1.06,1.38,1.70,2.02,2.34,2.66,2.98,3.30,3.62,3.94,4.26,4.58,4.90}

[0089] The 16 digital output results can be shown as follows:

[0090] Output Result

[16] = {82,344,606,868,1131,1393,1655,1917,2179,2441,2703,2966,3228,3490,3752,4014}

[0091] Please refer to Figure 5 , Figure 5 FIG. 2 shows an ADC analog input-output relationship diagram of an MCU parameter test system according to an embodiment of the present disclosure. Figure 5 As shown, the digital output result of the ADC module is consistent with the theoretical expected output.

[0092] In the MCU parameter test system and test method of the above embodiment of the present disclosure, the PPMU module of the ATE platform is used to provide accurate analog voltage input, which ensures the high accuracy of the test signal and can accurately measure the conversion result of the ADC module. In this way, the tester can quickly verify the performance of the ADC module through the analog input signal, saving a lot of manual test time and cost, and improving the efficiency of MCU testing.

[0093] In a possible implementation of the above embodiment, the ATE test platform further includes a POR / PDR function module and a GPIO function module, wherein:

[0094] The POR / PDR function module verifies whether the power-on reset and power-down reset functions of the MCU under test are triggered by changing the power supply voltage of the MCU under test;

[0095] The GPIO function module tests the input detection function of the MCU's GPIO pins as input ports, and the correctness of the output level and the load function when the GPIO pins are used as output ports.

[0096] In this embodiment, the power-on reset (POR) function and the power-down reset (PDR) function refer to mechanisms for ensuring that the MCU chip can automatically restart or resume normal working state when the power supply fluctuates. Specifically, the POR function is used to ensure the stable startup of the internal circuit of the chip when the chip power is first powered on; and the PDR function is used to trigger the chip restart when the power supply fails or fluctuates, ensuring that the chip can work normally and return to a safe state.

[0097] In a possible implementation, the POR / PDR functional module verifies whether the power-on reset and power-off reset functions of the MCU under test are triggered by changing the power supply voltage of the MCU under test, including:

[0098] In the MCU parameter testing system and testing method of the above embodiment of the present disclosure, the power module adjusts the power supply voltage V cc , so that the supply voltage is close to or lower than the voltage threshold of the POR function, or is reduced to the voltage threshold of the PDR. Among them, if the voltage value of the supply voltage is less than the POR threshold, the POR function module should detect this change and trigger a restart; if the voltage value of the supply voltage rises back to greater than the POR threshold, the POR function module should restore the chip to normal operation.

[0099] During the measurement of the POR function module, the core voltage inside the MCU to be tested is measured to check whether the POR / PDR restart process is triggered when the power supply voltage fluctuates; if the core voltage change is as expected and the chip can start correctly after power is restored, it indicates that the POR / PDR function is normal.

[0100] Furthermore, a general purpose input / output (GPIO) interface may be a hardware module in the MCU under test for performing general purpose input / output operations, which may be configured as an input port or an output port to interact with external devices by detecting input signals or controlling output levels.

[0101] Among them, when the GPIO pin is configured as an input port, it can be used to receive external signals. During the test, it is necessary to verify whether the pin can correctly read the input level (such as high level or low level) and can accurately reflect the changes of external signals. When the GPIO pin is configured as an output port, it can be used to output level signals to control external devices. During the test, it can be verified whether the level output by the pin meets the predetermined standard, and when the output port has a load, it can drive the load normally.

[0102] In the MCU parameter test system and test method of the above-mentioned embodiment of the present disclosure, the platform performs automated POR / PDR function verification and GPIO function testing on the MCU to be tested, avoiding manual intervention and greatly improving the test efficiency. Since the platform supports multi-channel parallel testing, multiple GPIO pins can be tested at the same time, or the POR / PDR function can be verified at the same time. This not only improves the speed of the test, but also saves hardware resources and improves the overall work efficiency. In addition, the platform can accurately control the power supply voltage to the POR / PDR voltage threshold, thereby verifying the reset function of the MCU. The accuracy of the platform can usually reach the 1mV level, ensuring the high accuracy of the test conditions.

[0103] In a possible implementation of the above embodiment, the GPIO function module is specifically used for:

[0104] Through the ATE test platform, the MCU under test is put into the GPI functional test mode. In the GPI functional test mode, the pin multiplexing register of the MCU under test is configured using the SWD interface, and the GPIO pin of the MCU under test is configured as the input mode. The ATE test platform is used to send a preset stimulus signal to the MCU under test to test the pull-up enable function and the pull-up disable function when the GPIO pin is used as an input port; or

[0105] Through the ATE test platform, the MCU to be tested enters the GPO functional test mode. In the GPO functional test mode, the SWD interface is used to download the preset program to the SRAM of the MCU to be tested. The preset program is used to make the even-numbered pins in the GPIO pins output a high level and the odd-numbered pins output a low level. Through the PPMU module, a sink current is input to the even-numbered pins and a pull current is input to the odd-numbered pins, and the voltage values ​​of the even-numbered pins and the odd-numbered pins are measured to see if they meet the expected level standards.

[0106] In this embodiment, when performing the GPI function test, the MCU to be tested is made to enter the GPI function test mode through the ATE test platform;

[0107] Configure the PINMUX register through the SWD interface to configure specific GPIO pins (GPIO_pins) to GPI mode;

[0108] Through the programming of the SWD interface, the input function of the GPIO pin is enabled so that it can receive external signals;

[0109] The platform sends a preset excitation signal to the MCU under test through the PPMU module, simulates the external input voltage, covers different voltage ranges, enables the pull-up resistor of the GPIO pin, or turns off the pull-up resistor to test the detection capability of the input level in different states;

[0110] Verify that the GPIO pins correctly detect high-level inputs when the pull-up resistors are enabled, and that the GPIO pins correctly detect low-level inputs when the pull-up resistors are disabled.

[0111] Alternatively, when performing a GPO functional test, the MCU to be tested is put into a GPO functional test mode through the ATE test platform;

[0112] Download the preset program to the SRAM of the MCU to be tested through the SWD interface and start executing it. In the program, all GPIO interfaces are set as GPO ports;

[0113] Using a preset program, the even-numbered pins in the GPIO pins output a high level, and the odd-numbered pins output a low level; through the PPMU module, a sink current is input to the even-numbered pins, and a source current is input to the odd-numbered pins, and the voltage values ​​of the even-numbered pins and the odd-numbered pins are measured to see if they meet the expected level standards.

[0114] Conversely, a source current may be input to the even-numbered GPO pins and a sink current may be input to the odd-numbered GPO pins; the voltage of the even-numbered GPO pins and the voltage of the odd-numbered GPO pins may be measured to ensure that the expected level requirements are met.

[0115] Furthermore, the load capacity test may refer to testing the level stability of the GPIO pin under load, to ensure that the output level does not fluctuate significantly under a certain load.

[0116] In the MCU parameter test system and test method of the above-mentioned embodiment of the present disclosure, the GPIO function is comprehensively and meticulously verified through the platform, focusing on accurately testing the performance of the input (GPI) and output (GPO) functions of the GPIO pins under different voltage, current and load conditions. By testing the pull-up resistor enable / disable, reverse current drive, load capacity, etc., the coverage and reliability of the test are further improved. In this way, not only can the MCU be ensured to run stably in actual work, but also the test efficiency can be greatly improved and the blind spots that may occur in the test can be reduced.

[0117] In one embodiment, further reference is made to Figure 6 , Figure 6 is a flow chart of a test method provided by an embodiment of the present disclosure, which is applied to the above Figure 1 The MCU parameter test system shown in the figure, the process of the method may include the following steps:

[0118] Step S601: Connect the pins of the MCU to be tested to the ATE test platform based on the test adapter, and electrically connect the MCU to be tested and the ATE test platform.

[0119] In this embodiment, the test adapter is composed of a test board and a test socket.

[0120] Step S602: using a power supply module to provide a preset constant voltage to the MCU to be tested.

[0121] Step S603, using the signal generator in the ATE test platform to generate an excitation signal, and inputting the excitation signal into the MCU to be tested; using the measurement unit in the ATE test platform to capture the output information generated by the MCU to be tested according to the excitation signal; using the control software module in the ATE test platform to analyze the output information and generate a test report for the MCU to be tested.

[0122] Step S604, using the PPMU module in the ATE test platform to provide an analog input signal to the ADC module in the MCU to be tested, obtain the actual output signal of the ADC module, compare the actual output signal with the theoretical expected output, and determine whether the performance of the ADC module meets the preset standard.

[0123] Step S605, when the test value of the oscillator in the MCU to be tested deviates from the preset target value, the trimming function module in the ATE test platform is used to query the best trimming code that matches the preset target value according to the full search algorithm, and the best trimming code is used to correct the parameters of the oscillator.

[0124] Step S606, using the statistical analysis module in the ATE test platform to perform statistical analysis on the LDO output voltage of at least one sample of the MCU to be tested, and screening out abnormal samples whose output voltage deviates from a preset qualified range from the at least one sample.

[0125] It should be noted that: the MCU parameter test system provided in the above embodiment only uses the division of the above program modules as an example to illustrate when implementing the corresponding test method. In actual applications, the above processing can be assigned to different program modules as needed, that is, the internal structure of the above system can be divided into different program modules to complete all or part of the above-described processing. Figure 6 The embodiments of the method shown belong to the same concept, and the specific implementation process is detailed in the method embodiments, which will not be repeated here.

[0126] The present disclosure also provides a computer device having the above Figure 1 MCU parameter test system shown.

[0127] See also Figure 7 , Figure 7 is a structural diagram of an MCU parameter testing system provided by an embodiment of the present disclosure, such as Figure 7 As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Figure 7 A processor 10 is taken as an example.

[0128] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0129] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0130] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0131] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0132] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Figure 7 The example of connecting through bus is taken in the following.

[0133] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0134] The computer device also includes a communication interface, which is used for the computer device to communicate with other devices or a communication network.

[0135] The embodiments of the present disclosure also provide a computer-readable storage medium. The above-mentioned method according to the embodiments of the present disclosure can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium and downloaded through a network, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state drive, etc.; further, the storage medium can also include a combination of the above-mentioned types of memory. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0136] A part of the present disclosure may be applied as a computer program product, such as a computer program instruction, which, when executed by a computer, can call or provide the method and / or technical solution according to the present disclosure through the operation of the computer. Those skilled in the art should understand that the existence of computer program instructions in computer-readable media includes, but is not limited to, source files, executable files, installation package files, etc., and accordingly, the way in which computer program instructions are executed by a computer includes, but is not limited to: the computer directly executes the instruction, or the computer compiles the instruction and then executes the corresponding compiled program, or the computer reads and executes the instruction, or the computer reads and installs the instruction and then executes the corresponding installed program. Here, the computer-readable medium can be any available computer-readable storage medium or communication medium accessible to the computer.

[0137] Although the embodiments of the present disclosure have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present disclosure, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A MCU parameter testing system, characterized in that: The system includes: a test adapter, a power module and an ATE test platform, wherein the ATE test platform includes: a signal generator, a measurement unit, a control software module, a PPMU module, a trimming function module, and a statistical analysis module, wherein: A test adapter connects the pins of the MCU to be tested to the ATE test platform so that the MCU to be tested is electrically connected to the ATE test platform; the test adapter is composed of a test board and a test socket; A power supply module, providing a preset constant voltage to the MCU to be tested; The ATE test platform generates an excitation signal based on a signal generator, inputs the excitation signal into the MCU to be tested, captures output information generated by the MCU to be tested according to the excitation signal based on a measurement unit, uses the control software module to analyze the output information, and generates a test report for the MCU to be tested; The ATE test platform uses a PPMU module to provide an analog input signal to the ADC module in the MCU to be tested, obtain an actual output signal of the ADC module, compare the actual output signal with a theoretical expected output, and determine whether the performance of the ADC module meets a preset standard; The ATE test platform, when the test value of the oscillator in the MCU to be tested deviates from the preset target value, uses the trimming function module to query the best trimming code that matches the preset target value according to the full search algorithm, and uses the best trimming code to correct the parameters of the oscillator; The ATE test platform uses a statistical analysis module to perform statistical analysis on the LDO output voltage of at least one sample of the MCU to be tested, and screens out abnormal samples whose output voltage deviates from a preset qualified range from the at least one sample.

2. The system according to claim 1, characterized in that The control software module includes: a waveform analysis tool, a vector analysis tool, a debugging hardware Debug window tool, and a memory test tool, wherein: The control software module uses a waveform analysis tool to analyze the waveform signal in the output information of the MCU to be tested; The control software module uses a vector analysis tool to analyze the digital signal in the output information of the MCU to be tested; The control software module uses a debugging hardware Debug window tool to display and debug the hardware status in the output information of the MCU to be tested; The control software module uses a memory test tool to perform a read and write test on the internal memory of the MCU to be tested; The control software module also includes an IG-XL software environment module, which is used to write corresponding test codes for the PLL module in the MCU to be tested, wherein: The IG-XL software environment module sends the test code to the ATE test platform and starts a target test mode in the ATE test platform, wherein the target test mode is used to test the PLL module; The ATE test platform, in the target test mode, generates a preset square wave signal as a test signal, inputs the test signal to the input end of the PLL module, measures the actual output frequency of the output end of the PLL module, and tests the performance of the PLL module based on the actual output frequency.

3. The system according to claim 1, characterized in that The ATE test platform is specifically used for: Using any one of the 16 analog input channels in the PPMU module, based on the input range of the ADC module in the MCU to be tested, an analog voltage signal is sent to the ADC module, 16 digital output results determined by the ADC module based on the conversion of the 16 analog voltage signals are obtained, and the 16 digital output results are compared with the theoretical expected output to determine whether the performance of the ADC module meets the preset standard.

4. The system according to claim 1, characterized in that The ATE test platform also includes a POR / PDR functional module and a GPIO functional module, wherein: The POR / PDR function module verifies whether the power-on reset and power-off reset functions of the MCU under test are triggered by changing the power supply voltage of the MCU under test; The GPIO function module tests the input detection function of the GPIO pin of the MCU to be tested when it is used as an input port, and the correctness of the output level and the load function when the GPIO pin is used as an output port.

5. The system according to claim 4, characterized in that The GPIO functional module is specifically used for: By using an ATE test platform, the MCU to be tested is made to enter a GPI function test mode. In the GPI function test mode, a pin multiplexing register of the MCU to be tested is configured using an SWD interface, and a GPIO pin of the MCU to be tested is configured as an input mode. By using the ATE test platform, a preset excitation signal is sent to the MCU to be tested, and a pull-up enable function and a pull-up disable function of the GPIO pin when the GPIO pin is used as an input port are tested; or Through the ATE test platform, the MCU to be tested enters the GPO functional test mode. In the GPO functional test mode, the SWD interface is used to download a preset program to the SRAM of the MCU to be tested. The preset program is used to make the even-numbered pins in the GPIO pins output a high level and the odd-numbered pins output a low level. Through the PPMU module, a sink current is input to the even-numbered pins and a pull current is input to the odd-numbered pins, and it is measured whether the voltage values ​​of the even-numbered pins and the odd-numbered pins meet the expected level standards respectively.

6. A testing method, characterized in that: The method comprises: Connecting the pins of the MCU to be tested to the ATE test platform based on a test adapter, and electrically connecting the MCU to be tested to the ATE test platform; the test adapter is composed of a test board and a test socket; A power supply module is used to provide a preset constant voltage to the MCU to be tested; A signal generator in an ATE test platform is used to generate an excitation signal, and the excitation signal is input into the MCU to be tested; a measurement unit in the ATE test platform is used to capture output information generated by the MCU to be tested according to the excitation signal; a control software module in the ATE test platform is used to analyze the output information and generate a test report for the MCU to be tested; Using the PPMU module in the ATE test platform, providing an analog input signal to the ADC module in the MCU to be tested, obtaining an actual output signal of the ADC module, comparing the actual output signal with the theoretical expected output, and determining whether the performance of the ADC module meets the preset standard; When the test value of the oscillator in the MCU to be tested deviates from the preset target value, the adjustment function module in the ATE test platform is used to query the best adjustment code matching the preset target value according to the full search algorithm, and the parameters of the oscillator are corrected by using the best adjustment code; The statistical analysis module in the ATE test platform is used to perform statistical analysis on the LDO output voltage of at least one sample of the MCU to be tested, and abnormal samples whose output voltage deviates from a preset qualified range are screened out from the at least one sample.

7. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the test method described in claim 6 by executing the computer instructions.

8. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the testing method described in claim 6.

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