Display device

Abstract

A display device is provided. The display device includes a substrate, a plurality of patterns disposed on the substrate, the plurality of patterns being a closed curve, a reflective plate disposed on the plurality of patterns, and a light emitting element disposed on the reflective plate.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the priority of Korean Patent Application No. 10-2023-0158032 filed in the Korean Intellectual Property Office on November 15, 2024, the disclosure of which is incorporated herein by reference. Technical Field

[0003] The present disclosure relates to a display device, and more particularly to a display device capable of improving transmission accuracy of a plurality of light emitting diodes. Background Art

[0004] As display devices used for monitors of computers, televisions, cellular phones, and the like, there are organic light emitting display (OLED) devices that are self-luminous devices, liquid crystal display (LCD) devices that require a separate light source, and the like.

[0005] The application range of the display device is diversified to personal digital assistants as well as monitors of televisions and computers, and display devices having a large display area and reduced volume and weight are being studied.

[0006] In addition, in recent years, a display device including a light emitting diode is attracting attention as a next-generation display device. Since the light emitting diode is formed of an inorganic material rather than an organic material, the reliability is excellent, so that its life is longer than that of a liquid crystal display device or an organic light emitting display device. In addition, the light emitting diode has a fast light emission speed, excellent light emission efficiency, and strong impact resistance, so that the stability is excellent, and an image with high brightness can be displayed. Summary of the invention

[0007] An object to be achieved by the present specification is to provide a display device with improved front brightness.

[0008] Another object to be achieved by the present specification is to provide a display device that reduces the degree of loss of light propagating toward a side surface due to total reflection.

[0009] Another object to be achieved by the present specification is to provide a high-brightness display device.

[0010] The objects of the present disclosure are not limited to the above-mentioned objects, and other objects not mentioned above can be clearly understood by those skilled in the art from the following description.

[0011] According to one aspect of the present disclosure, a display device is provided, including a substrate, a plurality of patterns disposed on the substrate, a reflection plate disposed on the plurality of patterns, and a light emitting element disposed on the reflection plate, wherein the plurality of patterns are closed curves.

[0012] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a light-emitting area and a non-light-emitting area; a reflective plate disposed on the substrate; a light-emitting element disposed on the reflective plate; and a plurality of patterns disposed below the reflective plate, wherein the reflective plate has a concave-convex shape along the surface of the plurality of patterns, and the planar shapes of the plurality of patterns are concentric in shape.

[0013] Additional details of example embodiments are included in the detailed description and the accompanying drawings.

[0014] According to the present specification, a plurality of patterns are provided under the light emitting element, which can improve light extraction efficiency.

[0015] According to the present specification, the inclined surfaces are formed on a plurality of patterns, which can improve the front brightness.

[0016] According to the present specification, the inclination angles of the plurality of patterns vary according to the brightness distribution of the light emitting element, which can minimize the brightness deviation according to the viewing angle.

[0017] The effects according to the present disclosure are not limited to those exemplified above, and more various effects are included in the present specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0019] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present specification;

[0020] Figure 2 is a cross-sectional view of a pixel region of a display device according to an embodiment of the present specification;

[0021] Figure 3 is a top plan view of a pixel region of a display device according to an embodiment of the present specification;

[0022] Figure 4 is a cross-sectional view of a pixel region of a display device according to another embodiment of the present specification;

[0023] Figure 5 is a graph for explaining brightness distribution of a display device according to another embodiment of the present specification;

[0024] Fig. 6A and Figure 6B It is shown by Figure 4 a view of a propagation path of light reflected by a reflective plate of a display device in FIG. 1 ; and

[0025] Figure 7is a graph for explaining the effect of a display device according to another embodiment of the present specification. DETAILED DESCRIPTION

[0026] By referring to the exemplary embodiments described in detail below in conjunction with the accompanying drawings, the advantages and characteristics of the present disclosure and the methods for achieving these advantages and characteristics will be clear. However, the present disclosure is not limited to the exemplary embodiments disclosed herein, but will be implemented in various forms. The exemplary embodiments are provided only by way of example so that those skilled in the art can fully understand the disclosure of the present disclosure and the scope of the present disclosure.

[0027] The shapes, sizes, ratios, angles, numbers, etc. shown in the accompanying drawings for describing the exemplary embodiments of the present disclosure are merely examples, and the present disclosure is not limited thereto. Throughout the specification, similar reference numerals generally represent similar elements. In addition, in the following description of the present disclosure, detailed descriptions of known related technologies may be omitted to avoid unnecessarily obscuring the subject matter of the present disclosure. Terms such as "including", "comprising", "having" and "consisting of..." are generally intended to allow the addition of other components unless these terms are used together with the term "only". Unless otherwise expressly stated, any reference to the singular may include the plural.

[0028] Even if not explicitly stated, the components are interpreted as including the ordinary error range.

[0029] When terms such as "on," "over," "below," and "adjacent" are used to describe the positional relationship between two parts, one or more parts may be positioned between the two parts unless these terms are used together with the terms "immediately" or "directly."

[0030] When an element or layer is referred to as being “on” another element or layer, the other layer or element may be directly on the other element or interposed therebetween.

[0031] Although the terms "first", "second", etc. are used to describe various components, these components are not limited by these terms. These terms are only used to distinguish one component from other components. Therefore, the first component mentioned below can be the second component in the technical concept of the present disclosure.

[0032] Like reference numbers generally refer to like elements throughout the specification.

[0033] For convenience of description, the size and thickness of each component shown in the drawings are illustrated, and the present disclosure is not limited to the size and thickness of the components shown.

[0034] The features of the various embodiments of the present disclosure may be partially or completely dependent on or combined with each other, and may be technically interlocked and operated in various ways, and the embodiments may be performed independently of each other or in association with each other.

[0035] Hereinafter, a display device according to an exemplary embodiment of the present disclosure will be described in detail with reference to the accompanying drawings.

[0036] Figure 1 is a schematic configuration diagram of a display device according to an embodiment of the present specification. Figure 2 is a cross-sectional view of a pixel region of a display device according to an embodiment of the present specification. Figure 3 is a top plan view of a pixel region of a display device according to an embodiment of the present specification. For ease of description, Figure 1 Only the display panel PN, the gate driving unit GD, the data driving unit DD and the timing controller TC among the various components of the display device 100 are shown. Figure 3 Only the plurality of patterns 119 and the light emitting elements ED are shown.

[0037] Reference Figure 1 , the display device 100 includes: a display panel PN, which includes a plurality of sub-pixels SP; a gate driving part GD, which is configured to supply various types of signals to the display panel PN; and a timing controller TC, which is configured to control a data driving part DD, the gate driving part GD and the data driving part DD.

[0038] The gate driving part GD supplies a plurality of scan signals to the plurality of scan lines SL in response to a plurality of gate control signals provided from the timing controller TC. Figure 1 It is shown that a single gate driving part GD is disposed to be spaced apart from one side of the display panel PN. However, the number and arrangement of the gate driving parts GD are not limited thereto.

[0039] The data driving part DD converts the image data input from the timing controller TC into data voltages by using the reference gamma voltages in response to a plurality of data control signals provided from the timing controller TC. The data driving part DD may supply the converted data voltages to a plurality of data lines DL.

[0040] The timing controller TC aligns the image data input from the outside and supplies the image data to the data driving part DD. The timing controller TC can generate a gate control signal and a data control signal by using a synchronization signal (i.e., a dot clock signal, a data enable signal, and a horizontal / vertical synchronization signal input from the outside). In addition, the timing controller TC can control the gate driving part GD and the data driving part DD by supplying the generated gate control signal and data control signal to the gate driving part GD and the data driving part DD.

[0041] The display panel PN is configured to display an image to a user, and includes a plurality of sub-pixels SP. In the display panel PN, a plurality of scan lines SL and a plurality of data lines DL cross each other, and each of the plurality of sub-pixels SP is connected to the scan line SL and the data line DL. In addition, although not shown in the drawings, the plurality of sub-pixels SP may be respectively connected to a high potential power line, a low potential power line, a reference line, etc.

[0042] The display panel PN may have a display area AA and a non-display area NA configured to surround the display area AA.

[0043] The display area AA is an area of ​​the display device 100 that displays an image. The display area AA may include a plurality of sub-pixels SP constituting a plurality of pixels and a circuit configured to operate the plurality of sub-pixels SP. The plurality of sub-pixels SP are the smallest units constituting the display area AA. n sub-pixels SP may constitute a single pixel. A light-emitting element, a thin film transistor for operating the light-emitting element, and the like may be provided in each of the plurality of sub-pixels SP. Depending on the type of the display panel PN, the plurality of light-emitting elements may be defined in different ways. For example, in the case where the display panel PN is an inorganic light-emitting display panel, the light-emitting element may be a light-emitting diode (LED) or a micro light-emitting diode (micro LED).

[0044] A plurality of lines for transmitting various types of signals to a plurality of sub-pixels SP are provided in the display area AA. For example, the plurality of lines may include a plurality of data lines DL for supplying data voltages to the plurality of sub-pixels SP and a plurality of scan lines SL for supplying scan signals to the plurality of sub-pixels SP. The plurality of scan lines SL may extend in one direction in the display area AA and be connected to the plurality of sub-pixels SP. The plurality of data lines DL may extend in a direction different from the one direction in the display area AA and may be connected to the plurality of sub-pixels SP. In addition, a low potential power line, a high potential power line, etc. may also be provided in the display area AA. However, the present specification is not limited thereto.

[0045] The non-display area NA may be defined as an area where an image is not displayed, that is, an area extending from the display area AA. The non-display area NA may include connection lines and pad electrodes for transmitting signals to the sub-pixels SP in the display area AA. Alternatively, the non-display area NA may include a driving IC, such as a gate driver IC and a data driver IC.

[0046] Meanwhile, the driving parts such as the gate driving part GD, the data driving part DD, and the timing controller TC may be connected to the display panel PN in various ways. For example, the gate driving part GD may be installed in the non-display area NA by a gate-in-panel (GIP) method, or may be installed between a plurality of sub-pixels SP in the display area AA by a gate-in-active-area (GIA) method. For example, the data driving part DD and the timing controller TC may be formed on a separate flexible film and a printed circuit board PCB. The data driving part DD and the timing controller TC may be electrically connected to the display panel PN by bonding the flexible film and the printed circuit board PCB to a pad electrode formed in the non-display area NA of the display panel PN.

[0047] First, refer to Figure 2 , the display panel PN includes a substrate 110. The substrate 110 may be an insulating substrate configured to support constituent elements disposed on an upper portion of the display device 100. A plurality of pixels may be formed on the substrate 110 so that an image may be displayed. For example, the substrate 110 may be made of glass, resin, or the like. In addition, the substrate 110 may include a polymer or plastic. In some embodiments, the substrate 110 may be made of a plastic material having flexibility.

[0048] A plurality of sub-pixels SP may be disposed in a plurality of rows and a plurality of columns on the substrate 110. The plurality of sub-pixels SP may each include a light emitting element ED and a pixel circuit, and independently emit light.

[0049] A plurality of lines for sending various types of signals to a plurality of sub-pixels SP are provided on the substrate 110. For example, a plurality of data lines DL extending in the column direction, a plurality of high potential power lines VL1, and a plurality of low potential power lines may be provided on the substrate 110. For example, a plurality of light emitting control signal lines extending in the row direction, a plurality of auxiliary high potential power lines, a plurality of auxiliary low potential power lines, and a plurality of scan lines may be provided on the substrate 110. In addition, the high potential power lines VL1 extending in the column direction and the auxiliary high potential power lines extending in the row direction may be electrically connected to each other through contact holes. In this case, the light emitting control signal line sends a light emitting control signal to the pixel circuits of the plurality of sub-pixels SP to control the light emitting timing of the plurality of sub-pixels SP. However, the types of the plurality of lines are provided only for illustrative purposes, and the types of the plurality of lines actually used may be changed differently according to the design.

[0050] A pixel circuit for operating the light emitting element ED is provided in each of the plurality of sub-pixels SP on the substrate 110. The pixel circuit may include a plurality of thin film transistors and a plurality of capacitors. For ease of description, Figure 2Only the driving transistor DT, the first capacitor C1, and the second capacitor C2 among the components of the pixel circuit are shown. However, the pixel circuit may further include a switching transistor, a sensing transistor, a light emission control transistor, etc. However, the present specification is not limited thereto.

[0051] A light blocking layer BSM, a driving transistor DT, a first capacitor C1, a second capacitor C2, multiple patterns 119, a reflective plate RF, multiple light emitting elements ED, a first connecting electrode CE1, a second connecting electrode CE2, a dam BB, a protective layer 117, an encapsulation layer 160, a bonding portion 118, an optical film MF, and an insulating layer including multiple inorganic insulating layers and multiple organic insulating layers can be arranged on the substrate 110.

[0052] Among the insulating layers disposed on the substrate 110 , the plurality of inorganic insulating layers include a buffer layer 111 , a gate insulating layer 112 , a first interlayer insulating layer 113 , a second interlayer insulating layer 114 , and a first passivation layer 115 a .

[0053] Furthermore, among the insulating layers disposed on the substrate 110 , the plurality of organic insulating layers may include a first planarization layer 116 a , a second planarization layer 116 b , a bonding layer AD, a third planarization layer 116 c , and a fourth planarization layer 116 d .

[0054] Reference Figure 2 , a light blocking layer BSM is provided on the substrate 110. The light blocking layer BSM can block light from entering the active layer ACT of the plurality of transistors, thereby minimizing leakage current. For example, the light blocking layer BSM can be provided below the active layer ACT of the driving transistor DT, and blocks light from entering the active layer ACT. If light is emitted to the active layer ACT1, leakage current occurs, which may deteriorate the reliability of the transistor. Therefore, a light blocking layer BSM for blocking light can be provided on the substrate 110, thereby improving the reliability of the driving transistor DT. The light blocking layer BSM can be made of an opaque conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr) or an alloy thereof. However, the present specification is not limited thereto.

[0055] A buffer layer 111 is provided on the light blocking layer BSM. The buffer layer 111 is an inorganic insulating layer capable of reducing the penetration of moisture or impurities through the substrate 110. For example, the buffer layer 111 may be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto. However, depending on the type of the substrate 110 or the type of the thin film transistor, the buffer layer 111 may not be included. However, the present specification is not limited thereto.

[0056] A driving transistor DT is disposed on the buffer layer 111. The driving transistor DT includes an active layer ACT, a gate electrode GE, a source electrode SE, and a drain electrode DE.

[0057] Meanwhile, although Figure 2 not shown in [reference], an additional buffer layer may be provided between the substrate 110 and the light-blocking layer BSM. Similar to the buffer layer 111, the additional buffer layer may be an inorganic insulating layer capable of reducing the penetration of moisture or impurities through the substrate 110. For example, the additional buffer layer may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto.

[0058] First, the active layer ACT of the driving transistor DT is disposed on the buffer layer 111. The active layer ACT may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present specification is not limited thereto. In addition, although not shown in the drawings, other transistors such as a switching transistor, a sensing transistor, and a light-emitting control transistor may be additionally provided in addition to the driving transistor DT. The active layers of these transistors may be made of a semiconductor material such as an oxide semiconductor, amorphous silicon, or polycrystalline silicon. However, the present specification is not limited thereto. In addition, the active layers of the transistors such as the driving transistor DT, the switching transistor, the sensing transistor, and the light-emitting control transistor included in the pixel circuit may be made of the same material or different materials.

[0059] A gate insulating layer 112 is disposed on the active layer ACT. The gate insulating layer 112 may be an inorganic insulating layer for electrically insulating the active layer ACT and the gate electrode GE. The gate insulating layer 112 may be configured as a single layer or multiple layers made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto.

[0060] The gate electrode GE is disposed on the gate insulating layer 112. The gate electrode GE may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present specification is not limited thereto.

[0061] A first interlayer insulating layer 113 and a second interlayer insulating layer 114 are disposed on the gate electrode GE. Contact holes are formed in the first interlayer insulating layer 113 and the second interlayer insulating layer 114, through which the source electrode SE and the drain electrode DE are connected to the active layer ACT. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 are inorganic insulating layers for protecting components disposed under the first interlayer insulating layer 113 and the second interlayer insulating layer 114. The first interlayer insulating layer 113 and the second interlayer insulating layer 114 may each be configured as a single layer or a multilayer made of silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto.

[0062] A source electrode SE and a drain electrode DE are disposed on the second interlayer insulating layer 114 and are electrically connected to the active layer ACT. The source electrode SE is connected to the second capacitor C2 and the first electrode 134 of the light emitting element ED, and the drain electrode DE is connected to another component of the pixel circuit. The source electrode SE and the drain electrode DE may each be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present specification is not limited thereto.

[0063] A plurality of high potential power lines VL1 are disposed on the second interlayer insulating layer 114. The plurality of high potential power lines VL1 may transmit high potential power voltages to the light emitting elements ED of the plurality of sub-pixels SP. The plurality of high potential power lines VL1 may be made of a conductive material such as copper (Cu), aluminum (Al), molybdenum (Mo), nickel (Ni), titanium (Ti), chromium (Cr), or an alloy thereof. However, the present specification is not limited thereto.

[0064] Next, a first capacitor C1 is disposed on the gate insulating layer 112. The first capacitor C1 includes a first-first capacitor electrode C1a and a first-second capacitor electrode C1b.

[0065] First, the first-first capacitor electrode C1a is disposed on the gate insulating layer 112. The first-first capacitor electrode C1a and the gate electrode GE of the driving transistor DT may be integrated.

[0066] The first-second capacitor electrode C1b is disposed on the first interlayer insulating layer 113. The first-second capacitor electrode C1b is disposed to overlap the first-first capacitor electrode C1a with the first interlayer insulating layer 113 interposed therebetween.

[0067] Therefore, the first capacitor C1 may be connected to the gate electrode GE of the driving transistor DT and maintain the voltage of the gate electrode GE of the driving transistor DT for a predetermined period.

[0068] Next, a second capacitor C2 is disposed on the substrate 110. The second capacitor C2 includes a second-first capacitor electrode C2a, a second-second capacitor electrode C2b, and a second-third capacitor electrode C2c. The second capacitor C2 includes: a second-first capacitor electrode C2a as a lower capacitor electrode; a second-second capacitor electrode C2b as a middle capacitor electrode; and a second-third capacitor electrode C2c as an upper capacitor electrode.

[0069] The second-first capacitor electrode C2a is disposed on the substrate 110. The second-first capacitor electrode C2a may be disposed on the same layer as the light blocking layer BSM and made of the same material as the light blocking layer BSM.

[0070] The second-second capacitor electrode C2b is disposed on the buffer layer 111 and the gate insulating layer 112. The second-second capacitor electrode C2b may be disposed on the same layer as the gate electrode GE and made of the same material as the gate electrode GE.

[0071] The second-third capacitor electrode C2c is disposed on the first interlayer insulating layer 113. The second-third capacitor electrode C2c may include a first layer C2c1 and a second layer C2c2. The first layer C2c1 of the second-third capacitor electrode C2c may be disposed on the same layer as the first-second capacitor electrode C1b and made of the same material as the first-second capacitor electrode C1b. The first layer C2c1 may be disposed to overlap the second-first capacitor electrode C2a and the second-second capacitor electrode C2b, with the first interlayer insulating layer 113 interposed therebetween.

[0072] The second layer C2c2 of the second-third capacitor electrode C2c is disposed on the second interlayer insulating layer 114. The second layer C2c2 is a portion extending from the source electrode SE of the driving transistor DT and may be connected to the first layer C2c1 through a contact hole of the second interlayer insulating layer 114.

[0073] Therefore, the second capacitor C2 may be electrically connected between the light emitting element ED and the source electrode SE of the driving transistor DT and increase the inherent capacitance of the light emitting element ED so that the light emitting element ED may emit light with higher brightness.

[0074] A first passivation layer 115a is disposed on the driving transistor DT, the first capacitor C1, and the second capacitor C2. The first passivation layer 115a may be an inorganic insulating layer for protecting components disposed under the first passivation layer 115a. The first passivation layer 115a may be made of an inorganic material such as silicon oxide (SiOx) or silicon nitride (SiNx). However, the present specification is not limited thereto.

[0075] A first planarization layer 116a is disposed on the first passivation layer 115a. The first planarization layer 116a may planarize the upper portion of the pixel circuit including the driving transistor DT. The first planarization layer 116a may be configured as a single layer or multiple layers. For example, the first planarization layer 116a may be configured as an organic insulating layer made of benzocyclobutene or an acrylic-based organic material.

[0076] Reference Figure 2 and Figure 3 , a plurality of patterns 119 each having a closed loop shape may be provided on the first planarization layer 116a. The plurality of patterns 119 may be concentric in shape, and the spacing distances between the plurality of patterns 119 may be equal to each other. However, the present specification is not limited thereto. The plurality of patterns 119 may have various closed loop shapes, and the spacing distances between the plurality of patterns 119 may be different from each other.

[0077] The plurality of patterns 119 may be arranged to overlap with the plurality of light emitting elements ED arranged above the plurality of patterns 119. At the same time, the plurality of patterns 119 may be arranged not to overlap with the dam BB. That is, the plurality of patterns 119 may be arranged to overlap only with the light emitting elements ED, and not to overlap with the dam BB arranged to surround the pattern 119 arranged at the outermost periphery among the plurality of patterns 119, to suppress color mixing. However, the present specification is not limited thereto.

[0078] Reference Figure 2 , the plurality of patterns 119 may each have a side surface inclined with respect to a bottom surface of each of the plurality of patterns 119. Therefore, a cross-sectional shape of each of the plurality of patterns 119 may be, for example, a trapezoidal shape. However, the present specification is not limited thereto.

[0079] Reference Figure 2 , a plurality of reflection plates RF are disposed on the first planarization layer 116a and the plurality of patterns 119. The reflection plate RF may be disposed to cover the top surface and the side surface of the plurality of patterns 119, and to cover the top surface of the region of the first planarization layer 116a where the plurality of patterns 119 are not disposed. Therefore, the top surface of the reflection plate RF may have a concavo-convex shape according to the shape of each of the plurality of patterns 119, and have a concavo-convex shape having a closed loop shape corresponding to the plurality of patterns 119.

[0080] In addition, when the side surfaces of the plurality of patterns 119 are inclined relative to the top surface of the first planarization layer 116a, the reflection plate RF may be disposed to be inclined relative to the top surface of the first planarization layer 116a in a region overlapping the side surfaces of the plurality of patterns 119.

[0081] The reflector RF may be configured to reflect the light emitted from the plurality of light emitting elements ED toward the upper side of the substrate 110, and have a shape corresponding to each of the plurality of sub-pixels SP. One reflector RF may be arranged to cover most of the area of ​​one sub-pixel SP. The reflector RF may also be used as an electrode that can reflect the light emitted from the light emitting element ED and electrically connect the light emitting element ED and the pixel circuit. Therefore, considering the light reflection efficiency and resistance, the reflector RF may include various conductive layers. For example, the reflector RF may be made by using an opaque conductive layer made of silver (Ag), aluminum (Al), molybdenum (Mo), titanium (Ti) or an alloy thereof, and a transparent conductive layer made of indium tin oxide (ITO). However, the structure of the reflector RF is not limited thereto.

[0082] The reflection plate RF may include a plurality of first reflection plates RFa and a plurality of second reflection plates RFb disposed in each of the plurality of sub-pixels SP.

[0083] The plurality of first reflective plates RFa may reflect light emitted from the light emitting element ED to the outside of the display device 100. The plurality of first reflective plates RFa may be provided for each of the driving transistors DT in the plurality of subpixels SP and electrically connected to the second capacitor C2 and the source electrode SE of the driving transistor DT through the first contact hole CH1.

[0084] A plurality of second reflective plates RFb may be arranged to overlap with the light emitting element ED. A plurality of second reflective plates RFb may be arranged for each of the driving transistors DT in the plurality of sub-pixels SP, and may be connected to the high potential power line VL1 through the second contact hole CH2. Therefore, the plurality of second reflective plates RFb may reflect light emitted from the light emitting element ED to the outside of the display device 100 while supplying a high potential power voltage to the light emitting element ED. Therefore, a plurality of patterns 119 may be arranged under the plurality of second reflective plates RFb arranged to overlap with the plurality of light emitting elements ED in the reflective plate RF. However, the present specification is not limited thereto.

[0085] Meanwhile, all of the plurality of light emitting elements ED may be individually connected to the high potential power line VL1 without being connected to the reflective plate RF. However, the present specification is not limited thereto.

[0086] Reference Figure 2 , a second planarization layer 116b is disposed on the plurality of reflection plates RF. The second planarization layer 116b may planarize the upper portion of the plurality of patterns 119. The second planarization layer 116b may be configured as a single layer or multiple layers. For example, the second planarization layer 116b may be configured as an organic insulating layer made of benzocyclobutene or an acrylic-based organic material. However, the present specification is not limited thereto.

[0087] A bonding layer AD is provided on the second planarization layer 116b. The bonding layer AD may be formed on the front surface of the substrate 110 and fix the light emitting element ED provided on the bonding layer AD. The bonding layer AD may be configured as an organic insulating layer. The bonding layer AD may be made of a light-curable bonding material that can be cured by light. For example, the bonding layer AD may be made of an acrylic-based material including a photosensitizer. However, the present specification is not limited thereto.

[0088] A plurality of light emitting elements ED are disposed on the bonding layer AD in each of the plurality of sub-pixels SP. The light emitting element ED may be an element configured to emit light by current, and include a first light emitting element configured to emit red light, a second light emitting element configured to emit green light, and a third light emitting element configured to emit blue light. The combination of the light emitting elements ED may realize various colors including white. For example, the light emitting element ED may be a light emitting diode (LED) or a micro LED. However, the present specification is not limited thereto.

[0089] Each of the plurality of light emitting elements ED includes a first semiconductor layer 131 , an active layer 132 , a second semiconductor layer 133 , a first electrode 134 , and a second electrode 135 .

[0090] The plurality of light emitting elements ED may have various structures, such as a lateral structure, a vertical structure, and a flip chip structure. The lateral light emitting element includes a first electrode and a second electrode horizontally arranged at two opposite sides of the active layer. The vertical light emitting element includes a first electrode arranged at the upper side of the active layer and a second electrode arranged at the lower side of the active layer. The flip chip light emitting element is substantially the same in structure as the lateral light emitting element. The lateral light emitting element has a first electrode and a second electrode horizontally arranged at the upper side of the active layer, while the flip chip light emitting element has a first electrode and a second electrode horizontally arranged at the lower side of the active layer. In the following, a description is made assuming that the plurality of light emitting elements ED have a lateral structure. However, the types of the plurality of light emitting elements ED are not limited thereto.

[0091] The first semiconductor layer 131 is disposed on the bonding layer AD, and the second semiconductor layer 133 is disposed on the first semiconductor layer 131. The first semiconductor layer 131 and the second semiconductor layer 133 may each be a layer formed by doping a specific material with n-type and p-type impurities. For example, the first semiconductor layer 131 and the second semiconductor layer 133 may each be a layer formed by doping a material such as gallium nitride (GaN), indium aluminum phosphide (InAlP) or gallium arsenide (GaAs) with n-type and p-type impurities. In addition, the p-type impurity may be magnesium, zinc (Zn), beryllium (Be), etc. The n-type impurity may be silicon (Si), germanium, tin (Sn), etc. However, the present specification is not limited thereto.

[0092] The active layer 132 is disposed between the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can emit light by receiving positive holes and electrons from the first semiconductor layer 131 and the second semiconductor layer 133. The active layer 132 can be configured as a single layer or a multi-quantum well (MQW) structure. For example, the active layer 132 can be made of indium gallium nitride (InGaN), gallium nitride (GaN), etc. However, the present specification is not limited thereto.

[0093] Meanwhile, a portion of the first semiconductor layer 131 may protrude to the outside of the second semiconductor layer 133 and the active layer 132 and be exposed from the second semiconductor layer 133 and the active layer 132 .

[0094] The first semiconductor layer 131 may have a shape surrounding the active layer 132 and the second semiconductor layer 133 in a plan view. That is, both the active layer 132 and the second semiconductor layer 133 may be disposed to overlap with the first semiconductor layer 131, and only a portion of the inner side of the first semiconductor layer 131 may overlap with the active layer 132 and the second semiconductor layer 133.

[0095] In this case, the second semiconductor layer 133 and the active layer 132 protruding in shape from the first semiconductor layer 131 may be referred to as a mesa portion (MESA). The side surfaces of the mesa portion (i.e., the side surfaces of the second semiconductor layer 133 and the active layer 132) may be arranged to be inclined relative to the bottom surface of the first semiconductor layer 131.

[0096] The first electrode 134 is disposed on the first semiconductor layer 131. The first electrode 134 is an electrode that electrically connects the driving transistor DT and the first semiconductor layer 131. In this case, the first semiconductor layer 131 may be a semiconductor layer doped with n-type impurities, and the first electrode 134 may be a cathode. The first electrode 134 may be disposed on the top surface of the first semiconductor layer 131 exposed from the active layer 132 and the second semiconductor layer 133. The first electrode 134 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu) or an alloy thereof. However, the present specification is not limited thereto.

[0097] The second electrode 135 is disposed on the second semiconductor layer 133. The second electrode 135 may be disposed on the top surface of the second semiconductor layer 133. The second electrode 135 is an electrode that electrically connects the high potential power line VL1 to the second semiconductor layer 133. In this case, the second semiconductor layer 133 may be a semiconductor layer doped with p-type impurities, and the second electrode 135 may be an anode. The second electrode 135 may be made of a conductive material, for example, a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO), or an opaque conductive material such as titanium (Ti), gold (Au), silver (Ag), copper (Cu), or an alloy thereof. However, the present specification is not limited thereto.

[0098] Next, an encapsulation film 136 is provided to surround the first semiconductor layer 131, the active layer 132, the second semiconductor layer 133, the first electrode 134, and the second electrode 135. The encapsulation film 136 may be made of an insulating material, and protects the first semiconductor layer 131, the active layer 132, and the second semiconductor layer 133. In addition, a contact hole through which the first electrode 134 and the second electrode 135 are exposed may be formed in the encapsulation film 136 so that the first connection electrode CE1, the second connection electrode CE2, the first electrode 134, and the second electrode 135 may be electrically connected.

[0099] At the same time, a portion of the side surface of the first semiconductor layer 131 may be exposed from the encapsulation film 136. The light emitting element ED manufactured on the wafer may be separated from the wafer and transferred to the display panel PN. However, during the process of separating the light emitting element ED from the wafer, a portion of the encapsulation film 136 may be torn. For example, during the process of separating the light emitting element ED from the wafer, a portion of the encapsulation film 136 adjacent to the lower edge of the first semiconductor layer 131 of the light emitting element ED may be torn, so that a portion of the lower side surface of the first semiconductor layer 131 may be exposed to the outside. However, even if the lower portion of the light emitting element ED is exposed from the encapsulation film 136, the first connection electrode CE1 and the second connection electrode CE2 are formed after forming the third planarization layer 116c and the fourth planarization layer 116c covering the side surface of the first semiconductor layer 131, thereby reducing short circuit defects.

[0100] Next, a third planarization layer 116 c and a fourth planarization layer 116 d are provided on the bonding layer AD and the light emitting element ED.

[0101] The third planarization layer 116c may partially overlap the side surfaces of the plurality of light emitting elements ED, and fix and protect the plurality of light emitting elements ED. The third planarization layer 116c may be configured as a single layer or a multilayer. For example, the third planarization layer 116c may be configured as an organic insulating layer made of benzocyclobutene or an acrylic-based organic material. The third planarization layer 116c may be formed by using a halftone mask. Therefore, the third planarization layer 116c may be formed to have a stepped portion.

[0102] Specifically, a portion of the third planarization layer 116c that is relatively adjacent to the light emitting element ED may be formed to have a relatively small thickness, and a portion of the third planarization layer 116c that is relatively distant from the light emitting element ED may be formed to have a relatively large thickness. The portion of the third planarization layer 116c that is adjacent to the light emitting element ED may be disposed to surround the light emitting element ED and abut against the side surface of the light emitting element ED. Therefore, the third planarization layer 116c may cover a portion of the side surface of the first semiconductor layer 131 of the encapsulation film 136 that is configured to protect the light emitting element ED, which side surface is torn during the process of separating the light emitting element ED from the wafer and transferring the light emitting element ED to the display panel PN. Therefore, the contact between the first connection electrode CE1, the second connection electrode CE2, and the first semiconductor layer 131 and the subsequent short circuit defect may be suppressed.

[0103] The fourth planarization layer 116d may be formed to cover the upper portion of the third planarization layer 116c and the upper portion of the light emitting element ED. A contact hole may be formed in the fourth planarization layer 116d, through which the first electrode 134 and the second electrode 135 of the light emitting element ED are exposed. The first electrode 134 and the second electrode 135 of the light emitting element ED are exposed from the fourth planarization layer 116d, and the fourth planarization layer 116d may be partially disposed in a region between the first electrode 134 and the second electrode 135, thereby reducing a short circuit defect. The third planarization layer 116c and the fourth planarization layer 116d may each be configured as a single layer or a multilayer, and may be made of, for example, a photoresist or an acrylic-based organic insulating material.

[0104] Meanwhile, the fourth planarization layer 116d may cover the light emitting element ED and the region adjacent to the light emitting element ED. The fourth planarization layer 116d may be disposed in the region of the sub-pixel SP surrounded by the dam BB and disposed in the form of an island. Therefore, the dam BB may be disposed on a portion of the top surface of the third planarization layer 116c. For example, the dam BB may be disposed on the fourth planarization layer 116d and overlap a portion of the fourth planarization layer 116d.

[0105] The first and second link electrodes CE1 and CE2 are disposed on the fourth planarization layer 116d.

[0106] The first connection electrode CE1 is an electrode that electrically connects the driving transistor DT and the first electrode 134 of the light emitting element ED. The first connection electrode CE1 may be electrically connected to the first electrode 134 exposed from the fourth planarization layer 116d, and at the same time, electrically connected to the first reflective plate RFa through a contact hole formed in the fourth planarization layer 116d, the third planarization layer 116c, the bonding layer AD, and the second planarization layer 116b. Therefore, the first electrode 134 and the source electrode SE of the driving transistor DT may be electrically connected through the first connection electrode CE1 and the first reflective plate RFa.

[0107] The second connection electrode CE2 is an electrode that electrically connects the high potential power line VL1 and the second electrode 135 of the light emitting element ED. The second connection electrode CE2 may be electrically connected to the second electrode 135 exposed from the fourth planarization layer 116d, and connected to the second reflective plate RFb through a contact hole formed in the fourth planarization layer 116d, the third planarization layer 116c, the bonding layer AD, and the second planarization layer 116b. Therefore, the second electrode 135 and the high potential power line VL1 may be electrically connected through the second connection electrode CE2.

[0108] The first connection electrode CE1 and the second connection electrode CE2 may be made of a transparent conductive material such as indium tin oxide (ITO) or indium zinc oxide (IZO). However, the present specification is not limited thereto.

[0109] Meanwhile, the drawings show that the first electrode 134, the first connection electrode CE1 and the first reflective plate RFa are electrically connected to the source electrode SE of the driving transistor DT. However, the first electrode 134, the first connection electrode CE1 and the first reflective plate RFa may be connected to the drain electrode DE of the driving transistor DT. However, the present specification is not limited thereto.

[0110] Reference Figure 2 , the embankment BB is disposed on the first connection electrode CE1, the second connection electrode CE2, and the third planarization layer 116c exposed from the fourth planarization layer 116d. The embankment BB may be disposed to be spaced apart from the light emitting element ED at a predetermined interval and at least partially overlap the reflective plate RF. For example, the embankment BB may cover a portion of the first connection electrode CE1 and a portion of the second connection electrode CE2 formed in the contact hole of the fourth planarization layer 116d and the contact hole of the third planarization layer 116c. In addition, for example, the embankment BB may be disposed on the third planarization layer 116c and spaced apart from the light emitting element ED at a predetermined interval.

[0111] The bank BB may be made of an opaque material such as a black resin to reduce color mixing between the plurality of sub-pixels SP. However, the present specification is not limited thereto.

[0112] Meanwhile, the thickness of the portion of the bank BB formed in the contact hole of the fourth planarization layer 116d and the contact hole of the third planarization layer 116c and covering a portion of the first connection electrode CE1 and a portion of the second connection electrode CE2 may be different from the thickness of the portion of the bank BB disposed on the third planarization layer 116c. Specifically, in the case of the portion of the bank BB covering a portion of the first connection electrode CE1 and a portion of the second connection electrode CE2 formed in the contact hole of the fourth planarization layer 116d and the contact hole of the third planarization layer 116c, the contact hole is formed from the second planarization layer 116b to the fourth planarization layer 116d, so that the bank BB may be disposed to the lower portion of the light emitting element ED, that is, at a position lower than the light emitting element ED. Therefore, the thickness of the portion of the bank BB covering a portion of the first connection electrode CE1 and a portion of the second connection electrode CE2 formed in the contact hole of the fourth planarization layer 116d and the contact hole of the third planarization layer 116c may be greater than the thickness of the portion of the bank BB disposed on the third planarization layer 116c.

[0113] Meanwhile, the present specification is not limited thereto. The bank BB may be disposed outside the contact hole of the fourth planarization layer 116d and the contact hole of the third planarization layer 116c and cover a portion of the first connection electrode CE1 and a portion of the second connection electrode CE2.

[0114] The protective layer 117 is disposed on the first connection electrode CE1, the second connection electrode CE2 and the bank BB. The protective layer 117 is a layer for protecting components disposed below the protective layer 117. The protective layer 117 may be configured as a single layer or multiple layers. For example, the protective layer 117 may be made of benzocyclobutene, a light-transmitting epoxy resin, a photoresist, or an acrylic-based organic material. However, the present specification is not limited thereto.

[0115] The encapsulation layer 160 may be disposed over the protective layer 117. The encapsulation layer 160 is a layer for minimizing the penetration of moisture from the outside of the display device 100 and encapsulating constituent elements surrounded by the encapsulation layer 160. The encapsulation layer 160 may be disposed to surround the front, side, and rear surfaces of the first substrate 110.

[0116] The encapsulation layer 160 may be made of a material having low moisture permeability and high insulation performance. For example, the encapsulation layer 160 may be made of a material including polyparaxylene. However, the present specification is not limited thereto.

[0117] Reference Figure 2, the optical film MF is disposed on the entire area of ​​the upper portion of the substrate 110 and covers the upper portion of the encapsulation layer 160. The optical film MF may be disposed on the sealing member 150 and the protective layer 117. The optical film MF may be a functional film that realizes an image with higher image quality while protecting the display device 100. For example, the optical film MF may include an anti-scattering film, an anti-glare film, an anti-reflection film, a low-reflection film, an OLED transmittance controllable film, or a polarizing plate. However, the present disclosure is not limited thereto.

[0118] The bonding portion 118 may be disposed above the substrate 110 and between the protective layer 117 and the optical film MF. The bonding portion 118 may be formed on the front surface of the substrate 110 and bond the protective layer 117 and the optical film MF. The bonding portion 118 may be made of a photocurable bonding material that can be cured by light. For example, the bonding portion 118 may be made of an acrylic-based material including a photosensitizer. However, the present specification is not limited thereto.

[0119] Meanwhile, in the present specification, the bonding part 118 and the optical film MF are defined as separate constituent elements. However, the present specification is not limited thereto. The optical film MF and the bonding part 118 may be defined as a single constituent element.

[0120] Reference Figure 2 and Figure 3 , from a plan view, at least one of the plurality of patterns 119 overlaps with the light emitting element ED. For example, the plurality of pattern structures 119 include a first pattern structure PS1, a second pattern structure PS2, a third pattern structure PS3, and a fourth pattern structure PS4. Figure 3 As shown, when the first pattern structure PS1, the second pattern structure PS2 and the third pattern structure PS3 overlap with the light emitting element ED from a plan view, the fourth pattern structure PS4 does not overlap with the light emitting element ED from a plan view. In addition, each of the plurality of pattern structures 119 is spaced apart from each other. This Figure 3 Floor plan and Figure 2 are shown in the cross-sectional views.

[0121] like Figure 3 As shown, from a plan view, the plurality of pattern structures 119 are concentric with each other. In some embodiments, the plurality of pattern structures 119 share a common axis (e.g., X-axis) and are symmetrical about the X-axis. Similarly, the plurality of pattern structures 119 share a common axis (e.g., Y-axis) and are symmetrical about the Y-axis.

[0122] The first pattern structure PS1 may have a diameter D0. The first pattern structure PS1 and the second pattern structure PS2 are spaced apart from each other by a first distance D1. The second pattern structure PS2 and the third pattern structure PS3 are spaced apart from each other by a second distance D2. The third pattern structure PS3 and the fourth pattern structure PS4 are spaced apart from each other by a third distance D3. In some embodiments, each of the plurality of pattern structures 119 is spaced apart from each other uniformly. For example, the first distance D1, the second distance D2, and the third distance D3 are the same as each other. However, in other embodiments, each of the plurality of pattern structures 119 may be spaced apart from each other differently (e.g., D1≠D2≠D3).

[0123] In the display device, brightness deviation according to the viewing angle occurs depending on the shape of the light-emitting element and the tolerance of the components. In the case where a micro light-emitting diode (micro LED) is used for the light-emitting element, the side brightness may be higher than the front brightness. For example, the brightness may increase in the direction of 50 to 70 degrees, and the maximum brightness may be generated in the direction of about 60 degrees. Therefore, the graph of the brightness distribution according to the viewing angle may have an "M" shape, and unevenness may occur.

[0124] In addition, in the case of a micro light emitting diode (micro LED), the brightness distribution according to the viewing angle may vary according to the inclination angle of the area called the mesa portion of the light emitting element (i.e., the inclination angle of the side surface of the second semiconductor layer and the side surface of the active layer). At the same time, because the light emitting element is manufactured to have a small size, even a small tolerance error may affect the shape and inclination angle of the mesa portion. For example, in the case where the light emitting element is manufactured to have a size of about 30 μm, even with a tolerance of μm level, deviations may occur with respect to the inclination angle of the mesa portion. Therefore, it may be difficult to control the viewing angle deviation according to the processing error.

[0125] Therefore, in the display device 100 according to the embodiment of the present specification, the plurality of patterns 119 are disposed under the reflective plate RF, and the side surfaces of the plurality of patterns 119 are formed as inclined surfaces. Therefore, the reflective plate RF may be disposed to have an inclined surface in a region overlapping with the side surfaces of the plurality of patterns 119, and the light emitted from the light emitting element ED may be reflected by the inclined surface of the reflective plate RF and extracted in the direction of the front surface. Therefore, in the display device 100 according to the embodiment of the present specification, the plurality of patterns 119 disposed under the reflective plate RF may reduce the amount of light propagating in the direction of the side surface, and extract light in the direction of the front surface. Therefore, the front brightness of the display device 100 may be increased, and the viewing angle deviation may be reduced.

[0126] In addition, in the display device 100 according to the embodiment of the present specification, a plurality of patterns 119 having a closed curve shape are arranged under the reflective plate RF, and all the plurality of patterns 119 may have the same center. Therefore, the reflective plate RF arranged on the plurality of patterns 119 may include a plurality of concave-convex patterns, the centers of the plurality of concave-convex patterns being the same as the centers of the plurality of patterns 119. Therefore, the light emitted from the light emitting element ED may be reflected by the reflective plate RF arranged on the plurality of patterns 119, and propagates toward the center of the plurality of patterns 119. Therefore, in the case where the reflective plate RF includes a plurality of concave-convex patterns having the same center, the light extracted from the light emitting element ED may be concentrated in the direction of the front surface compared to the case where the reflective plate RF has a concave-convex pattern with an opening shape. Therefore, in the display device 100 according to the embodiment of the present specification, the front brightness of the display device 100 may be increased, so that a high-efficiency, high-brightness display device 100 may be provided.

[0127] Reference Figure 3 , from a plan view, each of the plurality of pattern structures PS1, PS2, PS3, PS4 may have a polygonal shape, a circular shape, a ring shape, a donut shape, or the like.

[0128] Figure 4 is a cross-sectional view of a pixel region of a display device according to another embodiment of the present specification. In addition to the light emitting element ED, Figure 4 The display device 400 shown is similar in configuration to Figures 1 to 3 The display device 100 shown is substantially the same. Therefore, repeated description of the same components will be omitted.

[0129] Reference Figure 4 , Figure 4 The display device 400 in the embodiment includes a light emitting element ED disposed on a bonding layer AD.

[0130] The light emitting element ED may include a plurality of light extraction patterns P. The plurality of light extraction patterns may be disposed to be inclined relative to the substrate 110 and disposed on the bottom surface of the light emitting element ED. In this case, the plurality of light extraction patterns P may be inclined relative to the substrate 110. For example, Figure 4 As shown, the cross-sectional shape of each of the plurality of light extraction patterns P may be a triangular shape. However, the present specification is not limited thereto.

[0131] Meanwhile, the bonding layer AD may fill a plurality of light extraction patterns P. In the case where the light emitting element ED is bonded to the bonding layer AD, the plurality of light extraction patterns P may be filled with the bonding layer AD by an external force. Meanwhile, the bonding layer AD may fill all or only some of the plurality of light extraction patterns P. However, the present specification is not limited thereto.

[0132] In some embodiments, the plurality of light extraction patterns P overlap the light emitting element ED from a plan view. In some embodiments, the plurality of light extraction patterns P, the reflection plate RF, the plurality of patterns 119 and the light emitting element ED at least partially overlap each other from a plan view.

[0133] At the same time, as the number of light extraction patterns P in the same area increases, the efficiency of the light emitting element ED can be increased. Therefore, the light extraction pattern P can be set to have a high tilt angle to increase the number of light extraction patterns P set on the bottom surface of the light emitting element ED. For example, a plurality of light extraction patterns P can be set to be tilted 70° to 80° relative to the substrate 110. However, the present specification is not limited thereto.

[0134] Meanwhile, in the case where the tilt angle of the light extraction pattern P with respect to the substrate 110 is 70 to 80 degrees, the tilt angle of the tilt surface of each of the plurality of patterns 119 with respect to the substrate 110 may be 25 to 40 degrees.

[0135] In the following, reference will be made to Figures 5 to 6B The inclined surfaces of the plurality of patterns 119 and the inclined angles of the light extraction patterns P are described.

[0136] Figure 5 This is used to explain this manual. Figure 4 A curve diagram of the brightness distribution of the display device 400 in FIG.

[0137] Figure 5 is a graph showing luminance distribution according to viewing angles measured in Embodiments 1 and 2. Figure 5 Embodiments 1 and 2 in the present invention show the direction Figure 4 Brightness distribution of light propagating from the lower part of the light emitting element ED in the display device 400. Figure 5 The X-axis in the graph in represents an angle (°), and the central portion of the light emitting element ED is set to 0°. Figure 5 The Y axis in the graph in represents brightness (nit), that is, the brightness of the light beam propagating in the direction of the side surface among the light beams propagating to the lower part of the light emitting element ED. Embodiment 1 is a case where the inclination angle of the plurality of light extraction patterns P is 70°, and embodiment 2 is a case where the inclination angle of the plurality of light extraction patterns P is 80°.

[0138] Reference Figure 5 In Embodiments 1 and 2, the luminance of the side surface of the light emitting element ED is higher than the luminance of the central portion of the light emitting element ED. Specifically, in Embodiment 1, the maximum luminance is generated at an angle of about 60°, and in Embodiment 2, the maximum luminance is generated at an angle of about 70°.

[0139] In the following, we will refer to Fig. 6A and Figure 6B Give a description.

[0140] Fig. 6A and Figure 6B It is shown by Figure 4 A view of a propagation path of light reflected by the reflective plate RF of the display device 400. Fig. 6A and Figure 6B 11 is a view showing a propagation path of light reflected by a region of the reflection plate RF overlapping with the inclined surfaces of the plurality of patterns 119 . Fig. 6A 1 is a view showing a propagation path of light in a case where the angle of the inclined surfaces (eg, the first side surface SS1 , the second side surface SS2 ) of the plurality of patterns 119 is 30°. Figure 6B 1 is a view showing a propagation path of light when the angle of the inclined surfaces (e.g., the first side surface SS1, the second side surface SS2) of the plurality of patterns 119 is 35°. Here, the pattern structure has a top surface TS, a bottom surface BS opposite to the top surface TS, and a first side surface SS1 (also referred to as an inclined surface) facing the second side surface SS2. Fig. 6A and Figure 6B As shown, in some embodiments, the reflective plate RF covers and directly contacts the first side surface SS1 , the second side surface SS2 , and the top surface TS of each pattern structure of the plurality of patterns 119 .

[0141] Fig. 6A 1 shows a light beam propagating at an angle of 60° among the light beams propagating in the direction of the side surfaces (e.g., the first side surface SS1, the second side surface SS2). The light propagating at an angle of 60° is reflected by the area overlapping the inclined surfaces of the plurality of patterns 119. In this case, as Fig. 6A As shown, in the case where light propagating at an angle of 60° is reflected by the inclined surface of the plurality of patterns 119 having an inclined angle of 30°, the reflected light may propagate in the direction of the front surface.

[0142] Therefore, among the light beams propagating toward the lower portion of the light emitting element ED, the light beams propagating at an angle of 60° may be reflected by the inclined surfaces of the plurality of patterns 119 having an inclination angle of 30° and propagate in the direction of the front surface. Figure 5 In Embodiment 1, in the case where light propagating toward the lower portion of the light emitting element ED has maximum brightness at an angle of about 60°, a plurality of patterns 119 having an inclination angle of 30° may be provided to reduce brightness deviation according to a viewing angle.

[0143] Figure 6B1 shows a light beam propagating at an angle of 70° among the light beams propagating in the direction of the side surface. The light propagating at an angle of 70° is reflected by a region overlapping with the inclined surfaces (eg, first side surface SS1, second side surface SS2) of the plurality of patterns 119. In this case, as Figure 6B As shown, in the case where light propagating at an angle of 70° is reflected by the inclined surfaces (eg, first side surface SS1, second side surface SS2) of the plurality of patterns 119 having an inclined angle of 35°, the reflected light may propagate in a direction of the front surface.

[0144] Therefore, among the light beams propagating toward the lower portion of the light emitting element ED, the light beams propagating at an angle of 70° may be reflected by the inclined surfaces of the plurality of patterns 119 having an inclination angle of 35° and propagate in the direction of the front surface. Figure 5 In Embodiment 2, in the case where light propagating toward the lower portion of the light emitting element ED has maximum brightness at an angle of about 70°, a plurality of patterns 119 having an inclination angle of 35° may be provided to reduce brightness deviation according to a viewing angle.

[0145] Therefore, in the case where the light propagating toward the lower portion of the light emitting element ED has the maximum brightness at an angle of about 60° to 70°, a plurality of patterns 119 having an inclination angle of about 30° to 40° may be provided to reduce the brightness deviation. Meanwhile, in consideration of the process margin, the inclination angles of the inclined surfaces (e.g., the first side surface SS1, the second side surface SS2) of the plurality of patterns 119 may be designed to be 25° to 40°. That is, in some embodiments, the inclination angle defined between the bottom surface BS and the first side surface SS1 is about 25° to 40°. However, the present specification is not limited thereto.

[0146] Reference Figure 2 6 , according to some embodiments, a bottom surface BS of each pattern structure of the plurality of patterns 119 is on and directly contacts the planarization layer 116a. The reflection plates RFa, RFb directly contact the planarization layer 116a.

[0147] Figure 7 is a graph for explaining the effect of a display device according to another embodiment of the present specification. Figure 7 The embodiment in is a display device 400 according to another embodiment of the present specification. Figure 7 The comparative embodiment in FIG. 4 is different from the display device 400 according to another embodiment of the present specification only in that the plurality of patterns 119 are not provided and the reflection plate RF is provided along the flat top surface of the first planarization layer 116 a .

[0148] Figure 7 Brightness distributions according to viewing angles measured in the comparative embodiment and the embodiment are shown. Figure 7 The X-axis in the graph in represents the viewing angle (°). Figure 7 The Y-axis in the graph in represents brightness (nits).

[0149] Reference Figure 7 , in the comparative embodiment and the embodiment, the brightness of the side surface at 50° to 70° is higher than the brightness of the front surface, and the maximum brightness is generated in the direction of the side surface at about 60°.

[0150] Specifically, in the direction of the side surface at about 60°, the comparative embodiment shows a maximum brightness of about 220,000 nits, and the embodiment shows a maximum brightness of about 240,000 nits. Therefore, it can be determined that the maximum brightness of the embodiment is higher than that of the comparative embodiment.

[0151] Reference Figure 7 , the comparative embodiment shows a front brightness of about 170,000 nits, and the embodiment shows a front brightness of about 200,000 nits. Therefore, it can be determined that the front brightness is improved in the embodiment in which the plurality of patterns 119 are set, compared with the comparative embodiment in which the plurality of patterns 119 are not set.

[0152] Therefore, in the display device 400 according to another embodiment of the present specification, a plurality of patterns 119 having inclined surfaces are disposed under the reflective plate RF, so that the front brightness of the display device 400 can be improved and the viewing angle deviation can be reduced.

[0153] In addition, in a display device 400 according to another embodiment of the present specification, a plurality of patterns 119 having a closed curve shape with the same center are disposed under the reflective plate RF, so that the front brightness of the display device 400 can be increased, and a high-efficiency, high-brightness display device 400 can be provided.

[0154] In addition, in the display device 400 according to another embodiment of the present specification, a plurality of light extraction patterns P are provided on the light emitting element ED, so that the light extraction efficiency of the display device 400 may be improved.

[0155] In addition, in a display device 400 according to another embodiment of the present specification, the inclination angle of the plurality of patterns 119 can be adjusted to correspond to the maximum brightness of the light-emitting element ED. For example, light propagating toward the lower portion of the light-emitting element ED has a maximum brightness at an angle of about 60° to 70°, and a plurality of patterns 119 having an inclination angle of about 30° to 40° are disposed below the light-emitting element ED. Therefore, light propagating at an angle of about 60° to 70° can be reflected by the inclined surface of the plurality of patterns 119 having an inclination angle of about 30° to 40°, and propagates in the direction of the front surface. Therefore, in a display device 400 according to another embodiment of the present specification, the propagation direction of light having the maximum brightness is reflected in the direction of the front surface, so that the front brightness of the display device 400 can be improved, and the viewing angle deviation can be reduced.

[0156] Exemplary embodiments of the present disclosure may also be described as follows:

[0157] According to one aspect of the present disclosure, a display device is provided, including a substrate, a plurality of patterns arranged on the substrate, a reflection plate arranged on the plurality of patterns, and a light-emitting element arranged on the reflection plate, wherein the plurality of patterns are closed curves.

[0158] The top surface of the reflection plate may have a concavo-convex shape along the shape of the plurality of patterns.

[0159] A plurality of patterns may be disposed to overlap the light emitting element.

[0160] The plurality of patterns may have a trapezoidal shape with an inclined surface.

[0161] The reflective plate may cover the top surface and the side surfaces of the plurality of patterns.

[0162] The display device may further include a bank disposed in a peripheral region of the light emitting element, wherein the plurality of patterns may be disposed not to overlap the bank.

[0163] The light emitting element may include a plurality of light extraction patterns disposed on a bottom surface of the light emitting element and tilted with respect to the substrate, wherein the tilt angle of the plurality of light extraction patterns with respect to the substrate may be 70° to 80°.

[0164] The plurality of patterns may be disposed to overlap the light emitting element, wherein an inclination angle of a side surface of the plurality of patterns with respect to the substrate may be 25° to 40°.

[0165] The display device may further include a first planarization layer disposed between the substrate and the plurality of patterns, a second planarization layer on the reflective plate and configured to planarize upper portions of the plurality of patterns, and a bonding layer disposed on the second planarization layer, wherein the light emitting element may be disposed on the bonding layer.

[0166] According to another aspect of the present disclosure, a display device is provided. The display device includes: a substrate including a light-emitting area and a non-light-emitting area; a reflective plate disposed on the substrate; a light-emitting element disposed on the reflective plate; and a plurality of patterns disposed below the reflective plate, wherein the reflective plate has a concave-convex shape along the surface of the plurality of patterns, and the planar shapes of the plurality of patterns are concentric in shape.

[0167] The display device may further include a bank disposed on the light emitting element and configured to surround the light emitting element, wherein the bank may be disposed to surround a pattern disposed at an outermost periphery among the plurality of patterns.

[0168] The display device may further include a planarization layer disposed below the plurality of patterns, wherein the reflection plate may cover top surfaces of the plurality of patterns and a portion of a top surface of the planarization layer.

[0169] Side surfaces of the plurality of patterns may be inclined with respect to a top surface of the planarization layer.

[0170] The reflection plate may be disposed to be inclined with respect to a top surface of the planarization layer in a region overlapping with side surfaces of the plurality of patterns.

[0171] The light emitting element may include a plurality of light extraction patterns on a bottom surface of the light emitting element and tilted with respect to the substrate, wherein the tilt angle of the plurality of light extraction patterns with respect to the substrate may be 70° to 80°.

[0172] The plurality of patterns may be disposed to overlap the light emitting element, wherein an inclination angle of a side surface of the plurality of patterns with respect to the substrate may be 25° to 40°.

[0173] Although the exemplary embodiments of the present disclosure have been described in detail with reference to the accompanying drawings, the present disclosure is not limited thereto and can be implemented in many different forms without departing from the technical concept of the present disclosure. Therefore, the exemplary embodiments of the present disclosure are provided for illustrative purposes only and are not intended to limit the technical concept of the present disclosure. The scope of the technical concept of the present disclosure is not limited thereto. Therefore, it should be understood that the above exemplary embodiments are illustrative in all aspects and do not limit the present disclosure. The scope of protection of the present disclosure should be interpreted based on the attached claims, and all technical concepts within their equivalent scope should be interpreted as falling within the scope of the present disclosure.

Claims

1. A display device, comprising: substrate; a plurality of patterns on the substrate; Reflective plates on the plurality of patterns; as well as The light emitting element on the reflecting plate, Wherein, the multiple patterns are closed curves.

2. The display device according to claim 1, wherein: The top surface of the reflection plate has a concavo-convex shape along the shape of the plurality of patterns.

3. The display device according to claim 1, wherein: The plurality of patterns are disposed to overlap with the light emitting element.

4. The display device according to claim 1, wherein: The plurality of patterns have a trapezoidal shape with inclined surfaces.

5. The display device according to claim 4, wherein: The reflection plate covers top and side surfaces of the plurality of patterns.

6. The display device according to claim 1, further comprising: A bank in the peripheral region of the light emitting element, The plurality of patterns are arranged not to overlap with the bank.

7. The display device according to claim 1, wherein: The light emitting element includes a plurality of light extraction patterns on a bottom surface of the light emitting element and tilted with respect to the substrate, and Wherein, the inclination angle of the plurality of light extraction patterns relative to the substrate is 70° to 80°.

8. The display device according to claim 7, wherein: The plurality of patterns are arranged to overlap with the light emitting element, and Wherein, the inclination angle of the side surfaces of the plurality of patterns relative to the substrate is 25° to 40°.

9. The display device according to claim 1, further comprising: a first planarization layer disposed between the substrate and the plurality of patterns; a second planarization layer on the reflection plate and configured to planarize upper portions of the plurality of patterns; as well as a bonding layer on the second planarization layer, Wherein, the light emitting element is arranged on the bonding layer.

10. A display device, comprising: A substrate including a light emitting region and a non-light emitting region; a reflective plate on the substrate; The light emitting element on the reflecting plate; as well as A plurality of patterns are arranged below the reflecting plate, The reflection plate has a concavo-convex shape along the surface of the plurality of patterns, and the planar shapes of the plurality of patterns are concentric in shape.

11. The display device according to claim 10, further comprising: a bank on the light emitting element and arranged to surround the light emitting element, The bank is arranged to surround a pattern arranged at the outermost periphery among the plurality of patterns.

12. The display device according to claim 10, further comprising: a planarization layer disposed below the plurality of patterns, The reflective plate covers top surfaces of the plurality of patterns and a portion of a top surface of the planarization layer.

13. The display device according to claim 12, wherein: Side surfaces of the plurality of patterns are inclined with respect to a top surface of the planarization layer.

14. The display device according to claim 13, wherein: The reflection plate is disposed to be inclined with respect to a top surface of the planarization layer in a region overlapping with side surfaces of the plurality of patterns.

15. The display device according to claim 10, wherein: The light emitting element includes a plurality of light extraction patterns on a bottom surface of the light emitting element and tilted with respect to the substrate, and Wherein, the inclination angle of the plurality of light extraction patterns relative to the substrate is 70° to 80°.

16. The display device according to claim 15, wherein: The plurality of patterns are arranged to overlap with the light emitting element, and Wherein, the inclination angle of the side surfaces of the plurality of patterns relative to the substrate is 25° to 40°.

17. A display device comprising: a thin film transistor on a substrate; a light emitting element electrically connected to the thin film transistor; A plurality of pattern structures between the thin film transistor and the light emitting element, Wherein, from a plan view, at least one of the plurality of pattern structures overlaps with the light emitting element, and Wherein, each of the plurality of pattern structures is spaced apart from each other.

18. The display device according to claim 17, wherein: Each of the plurality of pattern structures is evenly spaced apart from each other.

19. The display device according to claim 17, wherein: Each of the plurality of pattern structures has a circular shape or a ring shape in a plan view.

20. The display device according to claim 17, wherein: The plurality of pattern structures are concentric with each other when viewed in plan view.

21. The display device according to claim 17, wherein: The plurality of pattern structures share a common axis and are symmetrical about the common axis.

22. The display device according to claim 17, wherein: Each of the plurality of pattern structures has a top surface, a bottom surface opposite to the top surface, a first side surface facing the second side surface, and Wherein, an inclination angle defined between the bottom surface and the first side surface is about 25° to 40°.

23. The display device according to claim 17, further comprising: The reflective plates on the plurality of pattern structures, Each of the plurality of pattern structures has a top surface, a bottom surface opposite to the top surface, and a first side surface facing the second side surface, and The reflective plate covers the first side surface, the second side surface and the top surface of each of the plurality of pattern structures.

24. The display device according to claim 23, further comprising: A planarization layer on the thin film transistor; wherein the bottom surface of each of the plurality of pattern structures is on the planarization layer and directly contacts the planarization layer, and Wherein, the reflection plate directly contacts the planarization layer.

25. The display device according to claim 17, further comprising: A plurality of light extraction patterns on the reflective plate, Wherein, from a plan view, the plurality of light extraction patterns overlap with the light emitting element.

26. The display device according to claim 25, wherein: The plurality of light extraction patterns, the reflection plate, the plurality of pattern structures, and the light emitting element at least partially overlap one another in a plan view.

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