Display device

Abstract

A display device according to one exemplary embodiment includes: a substrate having a pixel including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels; and a bank disposed between adjacent sub-pixels on the first electrode, in which the first electrode of a second sub-pixel of the plurality of sub-pixels is positioned lower than the first electrode of the first sub-pixel, the bank including a plurality of side surfaces, and lengths between the plurality of side surfaces are different.

Description

Technical Field

[0001] The present disclosure relates to a display device, and more specifically, for example but not limited to, to a display device that achieves ultra-high resolution by forming transistors on an insulating layer without depositing the transistors separately on a substrate, and depositing the insulating layer with the transistors formed on it on the substrate when manufacturing the display device. Background Art

[0002] As the information society develops, various demands for display devices for displaying images are increasing, and various types of display devices such as liquid crystal display (LCD) devices and organic light emitting diode (OLED) display devices are utilized.

[0003] Among display devices, the advantages are that, as a self-luminous type, OLED display devices have a better viewing angle and contrast than LCD devices, and because they do not require a separate backlight, they are lighter, thinner, and consume less power. In addition, OLED display devices have the advantages of being able to be driven at a low DC voltage, having a fast response time, and, in particular, having a low manufacturing cost.

[0004] Recently, the demand for augmented reality (AR), virtual reality (VR), or equivalent ultra-high-resolution displays using OLED display devices is increasing.

[0005] Meanwhile, the common light emitting layer of the OLED display device includes a conductive charge generating layer.

[0006] The description provided in this discussion of related art section should not be assumed to be prior art simply because it is mentioned in or associated with the discussion of related art section. The discussion of related art section may include information that describes one or more aspects of the subject technology, and the descriptions in this section do not limit the present disclosure. Summary of the invention

[0007] Therefore, as recognized by the inventors of the present disclosure, when the charge generation layer is integrally formed in the red sub-pixel, the green sub-pixel, and the blue sub-pixel, color mixing may occur between the sub-pixels.

[0008] In view of the above, the present disclosure is intended to provide a display device that can achieve ultra-high resolution by forming transistors on an insulating layer without depositing the transistors separately on a substrate, and depositing the insulating layer formed with the transistors on the substrate when manufacturing the display device.

[0009] The present disclosure also aims to provide a display device that can improve the occurrence of light color mixing between adjacent sub-pixels by forming a charge generation layer with a smaller thickness in adjacent sub-pixels to induce disconnection of the charge generation layer.

[0010] The present disclosure also aims to provide a display device that can improve the occurrence of light color mixing between adjacent sub-pixels by separating the charge generation layers in the adjacent sub-pixels.

[0011] The purpose of the present specification is not limited to the above-mentioned purpose, and other technical purposes can be inferred from the following embodiments.

[0012] To achieve the objective, a display device according to an exemplary embodiment includes: a substrate having pixels including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels; and a dam disposed between adjacent sub-pixels on the first electrode, wherein a first electrode of a second sub-pixel among the plurality of sub-pixels is positioned lower than a first electrode of the first sub-pixel, and the dam includes a plurality of side surfaces having different lengths therebetween.

[0013] To achieve the objective, a display device according to another exemplary embodiment includes: a substrate having pixels including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels; a dam disposed between adjacent sub-pixels on the first electrode; and a common light-emitting layer disposed on an upper surface of the first electrode exposed by the dam and on the dam, wherein the dam has an asymmetric shape and at least one of the common light-emitting layers is separated from the dam having the asymmetric shape.

[0014] Details of other embodiments are included in the detailed description and accompanying drawings.

[0015] According to an embodiment, when manufacturing the display device, ultra-high resolution can be achieved by forming transistors on an insulating layer without separately depositing the transistors on a substrate, and depositing the insulating layer formed with the transistors on the substrate when manufacturing the display device.

[0016] Furthermore, in adjacent sub-pixels, by forming an indentation in the insulating layer and positioning the first electrode located in the indentation lower than the first electrode not located in the indentation, the length of the side surface of the bank formed on each first electrode can be adjusted differently.

[0017] A common light emitting layer including a relatively thin charge generation layer may be disposed on the bank, and the charge generation layer may be separated by becoming thinner at the side surface as the bank becomes longer.

[0018] Therefore, light color mixing between adjacent sub-pixels can be prevented.

[0019] However, effects obtainable from the present disclosure are not limited to the above-mentioned effects, and other effects that are not mentioned will be clearly understood from the following description by those skilled in the art to which the present disclosure pertains.

[0020] The effects according to the present disclosure are not limited to the above-exemplified contents, and more various effects are included in the present disclosure.

[0021] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the inventive concepts as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] The above and other aspects, features and other advantages of the present disclosure will be more clearly understood from the following detailed description taken in conjunction with the accompanying drawings, in which:

[0023] Figure 1 is a plan view of a display device according to an exemplary embodiment.

[0024] Figure 2 Is the display device along Figure 1 Cross-sectional view along line AA'.

[0025] Figure 3 is based on Figure 2 A cross-sectional view of an organic light-emitting diode (OLED).

[0026] Figure 4 is based on Figure 2 A cross-sectional view of an OLED of a modified example.

[0027] Figure 5 yes Figure 2 Magnified view of area Q1 in FIG.

[0028] Figure 6 yes Figure 5 Magnified view of area Q2 in FIG.

[0029] Figure 7 Based on the modified example Figure 5 An enlarged view of region Q2 of the display device.

[0030] Figures 8 to 18 are cross-sectional views of each process in a method of manufacturing a display device according to an exemplary embodiment.

[0031] Fig.19 According to another exemplary embodiment Figure 5 An enlarged view of region Q2 of the display device.

[0032] Fig. 20 According to yet another exemplary embodiment Figure 5 An enlarged view of region Q2 of the display device.

[0033] Description of Reference Numerals

[0034] 1: Display device

[0035] 2: Substrate

[0036] 3: Insulation layer

[0037] 4: First electrode

[0038] 5: Public luminous layer

[0039] 6: Second electrode

[0040] 7: Covering layer

[0041] 8: Encapsulation layer

[0042] 9: Color filter layer

[0043] BK: Bank

[0044] Throughout the drawings and detailed description, unless otherwise described, the same reference numerals should be understood to refer to the same elements, features, and structures. The sizes, lengths, and thicknesses of these layers, regions, and elements and their descriptions may be exaggerated for clarity, illustration, and convenience. DETAILED DESCRIPTION

[0045] Reference will now be made in detail to embodiments of the present disclosure, examples of which may be illustrated in the accompanying drawings. The described progression of processing steps and / or operations is an example; however, the order of steps and / or operations is not limited to the order set forth herein, and may be varied as is known in the art, except for steps and / or operations that must occur in a particular order. The names of corresponding elements used in the following description may be selected solely for ease of writing the specification, and therefore may differ from the names used in the actual product.

[0046] Hereinafter, exemplary embodiments will be described with reference to the accompanying drawings. In this specification, when a first component (or region, layer, portion, etc.) is described as being "on," "connected," or "coupled" to a second component, this means that the first component may be directly connected / coupled to the second component, or a third component may be disposed between the first component and the second component.

[0047] The same reference numerals indicate the same components. In addition, in the drawings, in order to effectively describe the technical content, the thickness, proportion and size of the components are exaggerated. The term "and / or" includes all one or more combinations that can be defined by the associated configurations.

[0048] Terms such as first, second, A, B, (a), (b) and the like may be used to describe various components, but these components are not limited by these terms. Terms are used only for the purpose of distinguishing one component from another component. For example, a first component may be referred to as a second component, and similarly, a second component may be referred to as a first component without departing from the scope of the embodiments. Unless the context clearly dictates otherwise, a singular expression includes a plural expression.

[0049] Terms such as "below," "under," "on the lower side," "above," "over," and "on the upper side" are used to describe the relationship between components shown in the drawings. The terms are relative concepts and are described according to the directions marked in the drawings.

[0050] It should be understood that terms such as “include” or “have” are intended to specify the existence of the features, numbers, steps, operations, components, parts, or a combination thereof described in the specification, and do not exclude the possibility of pre-existing or adding one or more other features, numbers, steps, operations, components, parts, or a combination thereof.

[0051] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which the exemplary embodiments belong. It will also be understood that terms (such as those defined in commonly used dictionaries) should be interpreted as having, for example, a meaning consistent with their meaning in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense unless explicitly defined as such herein. For example, the term "component" or "unit" may apply, for example, to a separate circuit or structure, an integrated circuit, a computing block of a circuit device, or any structure configured to perform the described function, as will be understood by one of ordinary skill in the art.

[0052] In addition, when referring to any size, relative size, etc., it should be considered that the numerical value or corresponding information (e.g., level, range, etc.) of the element or feature includes a tolerance or error range that may be caused by various factors (e.g., process factors, internal or external influences, noise, etc.), even if no relevant description is specified. In addition, the term "may" fully encompasses all meanings of the term "can".

[0053] Hereinafter, exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. For ease of description, the scale of each element shown in the drawings is different from the actual scale and is therefore not limited to the scale shown in the drawings.

[0054] Figure 1 is a plan view of a display device according to an exemplary embodiment. Figure 2 Is the display device along Figure 1 Cross-sectional view along line AA'. Figure 3 is based on Figure 2 A cross-sectional view of an organic light-emitting diode (OLED). Figure 4 is based on Figure 2 A cross-sectional view of an OLED of a modified example.

[0055] Reference Figures 1 to 4 The display device 1 according to an exemplary embodiment may include at least a substrate 2 , a first electrode 4 , a bank BK, a common light emitting layer 5 , a second electrode 6 , and the like.

[0056] A plurality of sub-pixels (such as sub-pixels 21, 22, and 23) are formed on the substrate 2, but are not limited thereto. In addition, more or fewer sub-pixels may be formed on the substrate 2. A plurality of sub-pixels 21, 22, and 23 may form one pixel. A plurality of pixels may be formed on the substrate 2.

[0057] The plurality of sub-pixels 21, 22, and 23 include a first sub-pixel 21, a second sub-pixel 22, and a third sub-pixel 23. Since the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 may be sequentially disposed, the second sub-pixel 22 may be disposed adjacent to one side (e.g., the left side of the first sub-pixel 21), and the third sub-pixel 23 may be disposed adjacent to one side (e.g., the left side of the second sub-pixel 22). As an example, the second sub-pixel 22 may be disposed between the first sub-pixel 21 and the third sub-pixel 23, but is not limited thereto.

[0058] Throughout the present disclosure, when two sub-pixels are disposed adjacent to each other, it should be interpreted to mean that no other sub-pixel is disposed between the two sub-pixels.

[0059] Although the first sub-pixel 21 may be provided to emit red (R) light, the second sub-pixel 22 may be provided to emit blue (B) light, and the third sub-pixel 23 may be provided to emit green (G) light, the present disclosure is not necessarily limited thereto. Alternatively, the sub-pixels 21, 22, and 23 may be implemented to emit light of other colors, such as cyan, magenta, or yellow, etc.

[0060] Although Figure 1 It is shown that the pixel includes only three sub-pixels 21, 22 and 23, but the present disclosure is not limited thereto, and the pixel may include more or fewer sub-pixels, for example, four sub-pixels. When the pixel includes four sub-pixels, the pixel may further include a fourth sub-pixel provided to emit white (W) light, but is not limited thereto.

[0061] Each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 may be configured to have the same size, but is not limited thereto. For example, each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 may be configured to have the same width and the same height, but is not limited thereto. Here, although the width may be determined according to Figure 1 Indicates the horizontal direction, and the height can be based on Figure 1 A direction perpendicular to the width is indicated, but the present disclosure is not necessarily limited thereto.

[0062] The bank BK may be disposed between the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. The bank BK according to one exemplary embodiment serves to distinguish the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23.

[0063] The bank BK is used to define a sub-pixel. Therefore, the bank BK may be made of an insulating material including a black material. The bank BK may be made of, for example, a transparent carbon-based mixture. Specifically, the bank BK may include carbon black, but is not limited thereto. The bank BK may also be made of a transparent insulating material.

[0064] The first electrode 4 is patterned for each of the sub-pixels 21, 22, and 23. In other words, one first electrode 4 is formed in the first sub-pixel 21, another first electrode 4 is formed in the second sub-pixel 22, and the remaining first electrode 4 is formed in the third sub-pixel 23. The first electrode 4 may be used as an anode of the display device 1, but is not limited thereto. A bank BK may be provided to cover an edge of the first electrode 4 provided in each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 to distinguish the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. Therefore, the luminous area may be defined by the bank BK.

[0065] In the display device, the first electrode 4 may be provided as a plurality of layers including the reflective layer 41 , thereby further improving light extraction efficiency using microcavity characteristics.

[0066] The microcavity characteristic refers to the following characteristic, namely, when the distance between the reflective layer 41 and the second electrode 6 is an integer multiple of half the wavelength (λ / 2) of the light emitted from the sub-pixel, constructive interference occurs to amplify the light, and when the reflection and re-reflection process occurs repeatedly between the reflective layer 41 and the second electrode 6, the degree to which the light is amplified continues to increase, thereby improving the external extraction efficiency of the light.

[0067] The common light emitting layer 5 may be provided to emit white light. For example, the common light emitting layer 5 may be provided to emit white light by being in the form of a two-layer structure including a blue light emitting layer, a yellow-green light emitting layer, and a charge generating layer, or in the form of a three-layer structure including a blue light emitting layer, a green light emitting layer, a red light emitting layer, and a charge generating layer, but is not necessarily limited thereto, and may be provided in a multilayer of more than three layers as long as it can emit white light.

[0068] The common light-emitting layer 5 may be formed as a common layer that runs through all the first sub-pixels 21, the second sub-pixels 22, and the third sub-pixels 23, but is not limited thereto. Therefore, the common light-emitting layer 5 may cover the first electrode 4 provided in each sub-pixel and the bank BK provided between the sub-pixels. However, the charge generation layer of the common light-emitting layer 5 may have conductivity. Therefore, when the charge generation layer of the common light-emitting layer 5 is continuously provided in all the first sub-pixels 21, the second sub-pixels 22, and the third sub-pixels 23, light color mixing may occur at the boundaries of the adjacent first sub-pixels 21, the second sub-pixels 22, and the third sub-pixels 23. Therefore, in the case of the display device 1 according to an exemplary embodiment, the charge generation layer of the common light-emitting layer 5 may be separated at one or more boundaries of the boundaries of the adjacent sub-pixels (such as the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23). It will be described in detail below.

[0069] The second electrode 6 is used to form an electric field with the first electrode 4 and can be used as a cathode, but is not limited thereto. The second electrode 6 can be provided on the upper surface of the common light-emitting layer 5 opposite to the lower surface of the common light-emitting layer 5, the lower surface of the common light-emitting layer 5 is in contact with the first electrode 4, and is provided to penetrate the common layer of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. Each of the first electrode 4 and the second electrode 6 may include a metal material such as Au, W, Pt, Si, Ir, Ag, Cu, Ni, Ti, or Cr and an alloy thereof. Alternatively, each of the first electrode 4 and the second electrode 6 may include a transparent conductive material such as indium tin oxide ITO or indium zinc oxide IZO, but is not limited thereto.

[0070] In the case of the top emission type, the second electrode 6 may be provided as a transparent electrode, and in the case of the bottom emission type, the second electrode 6 may be provided as an opaque electrode including a reflective material. In the case of the top emission type, the second electrode 6 may be formed as a semi-transparent electrode to improve light extraction efficiency by utilizing microcavity characteristics. Since the display device utilizes the microcavity characteristics of the top emission type to improve light extraction efficiency, an example in which the second electrode 6 is formed as a semi-transparent electrode will be described.

[0071] A color filter layer 9 is provided in each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 to block a specific color of light emitted from the light-emitting layer of each sub-pixel. A first color filter 91 provided in the first sub-pixel 21 may be provided to block light of other colors other than the first color light such as red (R) light. In this case, the first color filter 91 may be provided as a red color filter. A second color filter 92 provided in the second sub-pixel 22 may be provided to block light of other colors other than the second color light such as blue (B) light. In this case, the second color filter 92 may be provided as a blue color filter. A third color filter 93 provided in the third sub-pixel 23 may be provided to block light of other colors other than the third color light such as green (G) light. In this case, the third color filter 93 may be provided as a green color filter. However, the present disclosure is not necessarily limited thereto.

[0072] The first color filter 91, the second color filter 92 and the third color filter 93 respectively arranged in the first sub-pixel 21, the second sub-pixel 22 and the third sub-pixel 23 can be set to the same size as each sub-pixel, or set by reducing or enlarging at a constant ratio relative to each sub-pixel.

[0073] Hereinafter, a stacked structure of a display device 1 according to an exemplary embodiment will be described in detail.

[0074] The display device 1 according to an exemplary embodiment may include a substrate 2 , an insulating layer 3 , a first electrode 4 , a bank BK, a common light emitting layer 5 , a second electrode 6 , a cover layer 7 , an encapsulation layer 8 , a color filter layer 9 , etc., but is not limited thereto.

[0075] The substrate 2 may be a plastic film, a glass substrate, a semiconductor substrate such as silicon, or a flexible polymer film. For example, the flexible polymer film may be made of any of the following: polyethylene terephthalate (PET), polycarbonate (PC), acrylonitrile-butadiene-styrene copolymer (ABS), polymethyl methacrylate (PMMA), polyethylene naphthalate (PEN), polyether sulfone (PES), cyclic olefin copolymer (COC), triacetyl cellulose (TAC) film, polyvinyl alcohol (PVA) film, polyimide (PI) film, and polystyrene (PS), which are only examples and are not necessarily limited thereto.

[0076] The substrate 2 may be made of a transparent material or an opaque material. The first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 are disposed on the substrate 2. The first sub-pixel 21 may be provided to emit a first color light such as red (R) light, the second sub-pixel 22 may be provided to emit a second color light such as blue (B) light, and the third sub-pixel 23 may be provided to emit a third color light such as green (G) light, but is not limited thereto. Alternatively, the sub-pixels 21, 22, and 23 may be implemented to emit light of other colors, such as cyan, magenta, or yellow, etc.

[0077] The display device 1 according to an exemplary embodiment is configured as a so-called top emission type in which emitted light is emitted upward, and therefore the material of the substrate 2 may include not only a transparent material but also an opaque material. Color filters 91, 92, and 93 may be respectively disposed on the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 from which light is emitted to transmit light of the same color.

[0078] The insulating layer 3 is formed on the substrate 2. The insulating layer 3 may include a plurality of stacked insulating layers 3a, 3b, 3c, and 3d. The insulating layers 3a, 3b, 3c, and 3d according to an exemplary embodiment may be stacked sequentially in the thickness direction and may include the same material. However, the present disclosure is not limited thereto, and the insulating layers 3a, 3b, 3c, and 3d may include different materials. The insulating layer 3 is provided with circuit elements, which include a plurality of thin film transistors 31, 32, and 33, various signal lines, capacitors, and the like for each sub-pixel 21, 22, and 23. The signal line may include a gate line, a data line, a power line, and a reference line, and the thin film transistors 31, 32, and 33 may include a switch thin film transistor, a drive thin film transistor, and a sensing thin film transistor, and the like. Each of the sub-pixels 21, 22, and 23 is defined by the intersection structure of the gate line and the data line.

[0079] The switching thin film transistor is used to perform switching according to a gate signal supplied to the gate line, thereby supplying a data voltage supplied from the data line to the driving thin film transistor.

[0080] The driving thin film transistor is used to perform switching according to the data voltage supplied from the switching thin film transistor, thereby generating a data current according to the power supplied from the power line and supplying it to the first electrode 4 .

[0081] The sensing thin film transistor is used to sense a threshold voltage deviation of the driving thin film transistor causing image quality degradation, and supplies a current of the driving thin film transistor to the reference line in response to a sensing control signal supplied from a gate line or a separate sensing line.

[0082] The capacitor serves to maintain a data voltage supplied to the driving thin film transistor for one frame, and is connected to each of a gate terminal and a source terminal of the driving thin film transistor.

[0083] The first transistor 31 , the second transistor 32 , and the third transistor 33 are provided in the first insulating layer 3 a for each individual sub-pixel 21 , 22 , and 23 .

[0084] The first transistor 31 according to an exemplary embodiment may be connected to the first electrode 4 disposed on the first sub-pixel 21 to apply a driving voltage for emitting light of a color corresponding to the first sub-pixel 21 , such as red (R) light.

[0085] The second transistor 32 according to an exemplary embodiment may be connected to the first electrode 4 disposed on the second sub-pixel 22 to apply a driving voltage for emitting light of a color corresponding to the second sub-pixel 22 , such as blue (B) light.

[0086] The third transistor 33 according to an exemplary embodiment may be connected to the first electrode 4 disposed on the third sub-pixel 23 to apply a driving voltage for emitting light of a color corresponding to the third sub-pixel 23 , such as green (G) light.

[0087] When receiving a gate signal from a gate line using each of transistors 31, 32, and 33, each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 according to an exemplary embodiment provides a predetermined current to the light emitting layer of each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 according to the data voltage of the data line. Therefore, the light emitting layer of each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 can emit light with a predetermined brightness according to the predetermined current. For example, the light emitting layer may include one or more of a hole injection layer (HIL), a hole transport layer (HTL), an electron transport layer (ETL), and an electron injection layer (EIL), but the present disclosure is not limited thereto.

[0088] refer to Figure 2 , a first insulating layer 3a is formed on the substrate 2. The first insulating layer 3a can protect the transistors 31, 32, and 33. The first insulating layer 3a can be made of an organic insulating material, but is not necessarily limited thereto, and can be made of an inorganic insulating material. In each of the sub-pixels 21, 22, and 23, the transistors 31, 32, and 33 can be located in the first insulating layer 3a.

[0089] The first electrode 4 of the first sub-pixel 21 or a reflective layer to be described below may be disposed on the first insulating layer 3 a .

[0090] The first electrode 4 is patterned for each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. The first electrode 4 is connected to the driving thin film transistor disposed in the insulating layer 3. Specifically, the first electrode 4 is connected to the source terminal or the drain terminal of the driving thin film transistor. To this end, a contact hole for exposing the source terminal or the drain terminal of the driving thin film transistor is formed in the insulating layer 3, and the first electrode 4 is connected to the source terminal or the drain terminal of the driving thin film transistor through the contact hole.

[0091] The display device 1 according to an exemplary embodiment may be provided in a top emission type, and for this purpose, the first electrode 4 may be provided to reflect upward the light emitted from the common light emitting layer 5. In this case, the first electrode 4 may be formed as a double-layer structure of a reflective layer 41 (or a reflective electrode or a reflector) for reflecting light and a transparent layer 42 (or a transparent electrode, an ITO electrode, or an anode) for providing holes to the common light emitting layer 5, but may have more layers.

[0092] The reflective layer 41 can reflect the light emitted toward the reflective layer 41 among the light emitted from the common light emitting layer 5 of each of the sub-pixels 21, 22, and 23 toward the second electrode 6 or the encapsulation layer 8. In addition, the reflective layer 41 is used to realize the microcavity characteristics through reflection and re-reflection with the second electrode 6, thereby improving the external extraction efficiency of light. To this end, the reflective layer 41 may include a reflective material for reflecting light. For example, the reflective material may be a metal, but is not necessarily limited thereto, and may be any other material as long as it can reflect light.

[0093] Since the reflective layer 41 of each of the sub-pixels 21, 22, and 23 is disposed at a relatively lower position than the common light-emitting layer 5 for emitting light, the light emitted from the common light-emitting layer 5 can be reflected upward by the reflective layer 41. Here, upward means a direction in which the user can perceive the light, for example, a side where the encapsulation layer 8 or the color filter layer 9 is disposed. Therefore, compared with a case where there is no reflective layer 41, the light efficiency of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 can be further improved, and the user can perceive high brightness, that is, a clear image, through the increased light efficiency.

[0094] The reflective layer 41 may be disposed inside the insulating layer 3. Specifically, the reflective layer 41 disposed in the first sub-pixel 21 may be disposed in the second insulating layer 3b, the reflective layer 41 disposed in the second sub-pixel 22 may be disposed in the fourth insulating layer 3d, and the reflective layer 41 disposed in the third sub-pixel 23 may be disposed in the third insulating layer 3c, but is not limited thereto. Figure 2As shown, the reflective layer 41 disposed in the first sub-pixel 21 may be disposed such that the upper surface of the first insulating layer 3a or the lower surface of the second insulating layer 3b is positioned collinearly with the lower surface of the reflective layer 41, the reflective layer 41 disposed in the second sub-pixel 22 may be disposed such that the upper surface of the third insulating layer 3c or the lower surface of the fourth insulating layer 3d is positioned collinearly with the lower surface of the reflective layer 41, and the reflective layer 41 disposed in the third sub-pixel 23 may be disposed such that the upper surface of the fourth insulating layer 3d or the lower surface of the third insulating layer 3c is positioned collinearly with the lower surface of the reflective layer 41. In the second sub-pixel 22, the upper surface of the reflective layer 41 may be positioned collinearly with the upper surface of the insulating layer 3 by the indentation IDP of the insulating layer 3, which will be described below.

[0095] The reflective layer 41 of each of the sub-pixels 21 , 22 , and 23 may be electrically connected to the transistors 31 , 32 , and 33 through a contact hole and a connection electrode.

[0096] The reflective layer 41 positioned in the first sub-pixel 21 may be positioned closest to the substrate 2, then the reflective layer 41 positioned in the third sub-pixel 23 may be positioned close to the substrate 2, and finally the reflective layer 41 positioned in the second sub-pixel 22 may be positioned farthest from the substrate 2, but is not limited thereto. Conversely, the reflective layer 41 positioned in the first sub-pixel 21 may be positioned farthest from the second electrode 6, then the reflective layer 41 positioned in the third sub-pixel 23 may be positioned far from the second electrode 6, and finally the reflective layer 41 positioned in the second sub-pixel 22 may be positioned closest to the second electrode 6, but is not limited thereto.

[0097] As described above, this is because when the reflective layer 41 is formed to have a different separation distance (or resonance distance) from the second electrode 6, the light extraction efficiency of different colors in different sub-pixels can be improved by reflection and re-reflection between the reflective layer 41 and the second electrode 6 according to the separation distance. Therefore, the light extraction efficiency of the first color light such as red light in the first sub-pixel 21 can be improved, the light extraction efficiency of the second color light such as blue light in the second sub-pixel 22 can be improved, and the light extraction efficiency of the third color light such as green light in the third sub-pixel 23 can be improved.

[0098] In the second sub-pixel 22, the transparent layer 42 is arranged on the reflective layer 41, and in each of the first sub-pixel 21 and the third sub-pixel 23, the transparent layer 42 is arranged on the fourth insulating layer 3d. The transparent layer 42 is used to provide holes to the common light-emitting layer 5. The transparent layer 42 can be transparently arranged so that the light reflected from the reflective layer 41 can propagate upward. The transparent layer 42 can be made of a transparent material, but is not limited to this, and can be made of a thin metal material as long as it can transmit light. In addition, in the present disclosure, the first electrode 4 is described as having a double-layer structure of a reflective layer 41 and a transparent layer 42, but may have more or less layers. For example, the first electrode 4 can be formed by including a highly reflective metal material, such as a laminated structure (ITO / Al / ITO) of aluminum and ITO, an APC alloy, and a laminated structure (ITO / APC / ITO) of an APC alloy and ITO. The APC alloy represents an alloy of silver (Ag), palladium (Pb) and copper (Cu), but is not limited to this.

[0099] The transparent layer 42 may be electrically connected to the reflective layer 41 by directly contacting the reflective layer 41, or may be electrically connected to the reflective layer 41 by indirectly connecting to the reflective layer 41 through a contact hole and a connection electrode. As an example, in the second sub-pixel 22, the transparent layer 42 may be electrically connected to the reflective layer 41 by directly contacting the reflective layer 41, and in each of the first sub-pixel 21 and the third sub-pixel 23, the transparent layer 42 may be electrically connected to the reflective layer 41 by indirectly connecting to the reflective layer 41, but is not limited thereto. The reflective layer 41 may be connected to each of the first transistor 31, the second transistor 32, and the third transistor 33 through another contact hole to transmit a driving voltage provided by each of the first transistor 31, the second transistor 32, and the third transistor 33 to the transparent layer 42. When a driving voltage is applied from the first transistor 31, the second transistor 32, and the third transistor 33, the transparent layer 42 may provide holes to the common light emitting layer 5. In the second sub-pixel 22, the transparent layer 42 may be in direct contact with the reflective layer 41.

[0100] The transparent layer 42 may be provided for each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23 so as to have substantially the same height on the upper surface of the reflective layer 41 or the insulating layer 3. However, the present disclosure is not limited thereto. In addition, the reflective layer 41 may be provided to have the same width as the transparent layer 42, but is not necessarily limited thereto, and may be provided to have a greater width than the transparent layer 42 to further increase the amount of light reflected upward.

[0101] In addition, the insulating layer 3 according to an exemplary embodiment may include at least one indentation IDP. For example, the indentation IDP may be formed by being recessed from the upper surface of the fourth insulating layer 3d in the thickness direction. The thickness T2 of the fourth insulating layer 3d formed with the indentation IDP may be less than the thickness T1 of the fourth insulating layer 3d without forming the indentation IDP. The indentation IDP may be formed in the second sub-pixel 22. In this case, the width of the indentation IDP may be less than the width of the second sub-pixel 22. However, the present disclosure is not limited thereto. Alternatively, the width of the indentation IDP may be greater than the width of the second sub-pixel 22. In this case, the indentation IDP may be formed in the entire second sub-pixel 22 and in portions of the sub-pixels 21 and 23 adjacent to the second sub-pixel 22. However, the present disclosure is not limited thereto, and the width of the indentation IDP may be the same as the width of the second sub-pixel 22. In this case, the indentation IDP may be formed only in the second sub-pixel 22. The indentation IDP may be formed to have a greater width than the transparent layer 42. Since the transparent layer 42 is disposed in the space where the indentation IDP is formed in the second subpixel 22, the width of the indentation IDP is preferably greater than that of the transparent layer 42. However, the present disclosure is not limited thereto, and the width of the indentation IDP may be the same as that of the transparent layer 42.

[0102] In addition, the indentation IDP is shown as being formed only in a portion of the entire second sub-pixel 22 and the adjacent sub-pixels 21 and 23, but is not limited thereto, and may be formed in a portion of the entire first sub-pixel 21 and the adjacent sub-pixels 22 and 23, or in a portion of the entire third sub-pixel 23 and the adjacent sub-pixels 21 and 22. Hereinafter, for ease of description, the description will focus on a case where the indentation IDP is formed only in a portion of the entire second sub-pixel 22 and the adjacent sub-pixels 21 and 23.

[0103] In one exemplary embodiment, since the indentation IDP is formed on the entire second sub-pixel 22, the transparent layer 42 of the second sub-pixel 22 disposed on the insulating layer 3 in which the indentation IDP is formed may be disposed lower than the transparent layer 42 of the adjacent sub-pixels 21 and 23 disposed on the insulating layer 3 in which the indentation IDP is not formed. In other words, the transparent layer 42 of the second sub-pixel 22 disposed on the insulating layer 3 in which the indentation IDP is formed may be disposed closer to the substrate 2 than the transparent layer 42 of the adjacent sub-pixels 21 and 23 disposed on the insulating layer 3 in which the indentation IDP is not formed. Since the transparent layer 42 of each of the sub-pixels 21, 22, and 23 is made of the same material and formed in the same process, the thickness of the transparent layer 42 of each of the sub-pixels 21, 22, and 23 may all be the same, but the present disclosure is not limited thereto. Therefore, the height of the surface of the transparent layer 42 of the second sub-pixel 22 may be positioned lower than the height of the surface of the transparent layer 42 of the adjacent sub-pixels 21 and 23, but the present disclosure is not limited thereto.

[0104] The bank BK may be provided to cover the edge of the transparent layer 42 or the edges of the transparent layer 42 and the reflective layer 41 , but is not limited thereto. The bank BK may be provided at the boundary of the adjacent sub-pixels 21 , 22 , and 23 .

[0105] The bank BK is formed to surround and cover the edge of the transparent layer 42 or the reflective layer 41 on the insulating layer 3. Specifically, in the first sub-pixel 21 and the third sub-pixel 23, the bank BK is formed to surround and cover the edge of the transparent layer 42 on the insulating layer 3, and in the second sub-pixel 22, the bank BK is formed to surround and cover the edge of the transparent layer 42 on the reflective layer 41. Figure 2 As shown in the cross-sectional view of , the bank BK may cover both ends of the transparent layer 42 disposed in each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. Specifically, the bank BK may be formed to cover a portion of the upper surface of the transparent layer 42 and the side surfaces of both ends of the transparent layer 42 and a portion of the upper surface of the insulating layer 3, so that the current can be concentrated at both ends of the transparent layer 42, thereby solving the problem of reduced luminous efficiency. The upper surface of the transparent layer 42 that is not covered by the bank BK and is exposed becomes a light-emitting area. The bank BK may be made of an organic insulating film including an organic insulating material (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin, etc.) or an inorganic insulating film including an inorganic insulating material (such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide or titanium oxide, etc.). In addition, the bank BK may include a black dye to absorb light incident from the outside.

[0106] The bank BK between the adjacent sub-pixels 21 and 22 may fill a portion of the indentation IDP, may contact the upper surface and the side surface of the fourth insulating layer 3d adjacent to the indentation IDP, and may directly contact the side surface and the upper surface of each transparent layer 42 of the sub-pixels 21 and 22, but is not limited thereto. The bank BK between the adjacent sub-pixels 22 and 23 may fill a portion of the indentation IDP, may contact the upper surface and the side surface of the fourth insulating layer 3d adjacent to the indentation IDP, and may directly contact the side surface and the upper surface of each transparent layer 42 of the sub-pixels 22 and 23, but is not limited thereto.

[0107] The bank BK according to an exemplary embodiment may have an asymmetric shape, but is not limited thereto. In the present disclosure, when the bank BK has an asymmetric shape, it may mean that the bank BK has a left-right asymmetric shape relative to the boundary line of the adjacent sub-pixels 21, 22, and 23. For example, the bank BK may include two side surfaces, and the bank BK having an asymmetric shape may have two side surfaces of different lengths. In the present disclosure, the length of the side surface may represent the length in the direction in which the side surface extends. The reason why the bank BK has an asymmetric shape is that the upper and lower positions of the transparent layers 42 of the adjacent sub-pixels 21, 22, and 23 are different. For example, the transparent layer 42 of the second sub-pixel 22 is set lower than the transparent layer 42 of the first sub-pixel 21, and the bank BK is directly set on the transparent layer 42 of the sub-pixels 21 and 22. For example, the transparent layer 42 of the second sub-pixel 22 is set lower than the transparent layer 42 of the third sub-pixel 23, and the bank BK is directly set on the transparent layer 42 of the sub-pixels 22 and 23. When manufacturing the bank BK, after the bank insulating film including the organic insulating film is deposited across the sub-pixels 21, 22, and 23, the bank BK may be patterned to meet the boundaries of the sub-pixels 21, 22, and 23. The upper surface of the patterned bank BK may extend in the horizontal direction, and each side surface thereof may extend to the transparent layer 42 adjacent to the upper surface, and as described above, since the upper and lower positions of the transparent layers 42 of the adjacent sub-pixels 21, 22, and 23 are different, the length between the side surfaces of the bank BK may be formed differently.

[0108] For example, Figure 2 As shown, the embankment BK located at the boundary of adjacent sub-pixels 21 and 22 may have a length of a side surface located on the second sub-pixel 22 side that is greater than the length of a side surface located on the first sub-pixel 21 side, and the embankment BK located at the boundary of adjacent sub-pixels 22 and 23 may have a length of a side surface located on the second sub-pixel 22 side that is greater than the length of a side surface located on the third sub-pixel 23 side.

[0109] The common light emitting layer 5 is formed on the first electrode 4 and the insulating layer 3. The common light emitting layer 5 may be formed on the bank BK disposed between the plurality of sub-pixels 21, 22, and 23 and the transparent layer 42 of the first electrode 4. Therefore, the common light emitting layer 5 may be in contact with the upper surface of the transparent layer 42 of the first electrode 4. The common light emitting layer 5 may be in contact with the upper surface of the transparent layer 42 exposed by the bank BK, the side surface of the adjacent bank BK, and the upper surface of the bank BK.

[0110] The OLED according to an exemplary embodiment may include a first electrode 4, a second electrode 6, and a common light emitting layer 5 between the first electrode 4 and the second electrode 6. The first electrode 4 may be used as an anode, but is not limited thereto. The second electrode 6 may be used as a cathode, but is not limited thereto.

[0111] The common light emitting layer 5 may be provided to emit white (W) light. To this end, the common light emitting layer 5 may include a plurality of stacks for emitting light of different colors. Specifically, the common light emitting layer 5 may include a first stack, a second stack, and a charge generation layer CGL disposed between the first stack and the second stack, but is not limited thereto.

[0112] The second electrode 6 is formed on the upper surface of the common light emitting layer 5. The second electrode 6 may function as a cathode of the display device 1. Like the common light emitting layer 5, the second electrode 6 is formed in each of the sub-pixels 21, 22, and 23 and between the sub-pixels 21, 22, and 23.

[0113] In the display device 1 according to an exemplary embodiment, the second electrode 6 may be formed as a semi-transparent electrode to realize white light with luminous efficiency of a top emission type. Therefore, a microcavity effect may be obtained for each of a plurality of sub-pixels such as the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. When the second electrode 6 is formed as a semi-transparent electrode, light may be repeatedly reflected and re-reflected between the second electrode 6 and the reflective layer 41 to obtain a microcavity effect, thereby improving light extraction efficiency.

[0114] In addition, since the second electrode 6 is formed on the upper surface of the common light-emitting layer 5, the second electrode 6 can be formed along the contour of the common light-emitting layer 5. Since the common light-emitting layer 5 is formed along the contour of the transparent layer 42 of the first electrode 4 in the light-emitting region, the second electrode 6 can be formed along the contour of the transparent layer 42 of the first electrode 4. In addition, the cover layer 7 on the second electrode 6 can also be formed along the contour of the second electrode 6. That is, the cover layer 7 can be formed along the contour of the transparent layer 42 of the first electrode 4.

[0115] The cover layer 7 may be made of an inorganic insulating material, but is not limited thereto. The cover layer 7 may be disposed on the second electrode 6 to protect the OLED.

[0116] The encapsulation layer 8 is formed on the second electrode 6 and serves to prevent external moisture from entering the common light emitting layer 5. Specifically, the encapsulation layer 8 is formed on the cover layer 7. The encapsulation layer 8 may be made of an inorganic insulating material, or may be formed in a structure in which an inorganic insulating material and an organic insulating material are alternately stacked, but is not necessarily limited thereto.

[0117] The color filter layer 9 is formed on the encapsulation layer 8. The color filter layer 9 may include a first color filter 91 disposed in the first sub-pixel 21, a second color filter 92 disposed in the second sub-pixel 22, and a third color filter 93 disposed in the third sub-pixel 23, but is not necessarily limited thereto. Specifically, the color filter layer 9 may include a red (R) first color filter 91 disposed in the first sub-pixel 21, a blue (B) second color filter 92 disposed in the second sub-pixel 22, and a green (G) third color filter 93 disposed in the third sub-pixel 23, but is not necessarily limited thereto.

[0118] like Figure 3 As shown, the common light emitting layer 5 may include a first stack EL1 , a second stack EL2 disposed on the first electrode 4 , and a first charge generation layer CGL1 between the first stack EL1 and the second stack EL2 , but is not limited thereto.

[0119] The first stack EL1 may be disposed on the first electrode 4 and configured as a structure in which a hole injection layer HIL, a hole transport layer HTL, a blue (B) light emitting layer EML1 , and an electron transport layer (ETL) may be sequentially stacked from bottom to top, but is not limited thereto.

[0120] The first stack EL1 may be disposed between the first sub-pixel 21 and the second sub-pixel 22 , and between the second sub-pixel 22 and the third sub-pixel 23 , that is, on the bank BK.

[0121] The first charge generation layer CGL1 is used to provide charges to the first stack EL1 and the second stack EL2. The first charge generation layer CGL1 may include an N-type charge generation layer for providing electrons to the first stack EL1 and a P-type charge generation layer for providing holes to the second stack EL2. The N-type charge generation layer may include a metal material as a dopant, but is not limited thereto.

[0122] The first charge generation layer CGL1 may be disposed on the bank BK between adjacent sub-pixels. As an example, the first charge generation layer CGL1 may be disposed between the first sub-pixel 21 and the second sub-pixel 22, and between the second sub-pixel 22 and the third sub-pixel 23, that is, disposed on the bank BK. In addition, in the display device 1 according to an exemplary embodiment, since the common light emitting layer 5 is also disposed between the sub-pixels 21, 22, and 23, when any one of the sub-pixels emits light, a lateral leakage current may be generated to the adjacent sub-pixels 21, 22, and 23 through the first charge generation layer CGL1, but since the bank BK having a predetermined height is disposed between the sub-pixels 21, 22, and 23, the current path may be increased, thereby preventing the occurrence of the lateral leakage current. In addition, since the bank BK has an asymmetric shape, the thickness of the first charge generation layer CGL1 may be reduced at one or more side surfaces of the bank BK. Therefore, the first charge generation layer CGL1 may be physically separated from at least one side surface of the bank BK. This will be described in detail below.

[0123] The second stack EL2 can be disposed above the first stack EL1, wherein the first charge generation layer CGL1 is located between the second stack EL2 and the first stack EL1, and the second stack EL2 is configured as a structure in which a hole transport layer HTL, a yellow-green (YG) light-emitting layer EML2, an electron transport layer ETL and an electron injection layer EIL are stacked sequentially from bottom to top, but is not limited thereto.

[0124] The second stack EL2 may be disposed on the bank BK between adjacent sub-pixels. As an example, the second stack EL2 may be disposed between the first sub-pixel 21 and the second sub-pixel 22 and between the second sub-pixel 22 and the third sub-pixel 23, that is, on the bank BK.

[0125] Therefore, if Figure 2 As shown, the common light emitting layer 5 may be provided as a common layer that runs through a plurality of sub-pixels such as the first sub-pixel 21 , the second sub-pixel 22 , and the third sub-pixel 23 .

[0126] like Figure 4 As shown, the common light emitting layer 5_1 of the OLED according to an exemplary embodiment may include a first stack EL1, a second stack EL2, a third stack EL3, a first charge generation layer CGL1 between the first stack EL1 and the second stack EL2, and a second charge generation layer CGL2 between the second stack EL2 and the third stack EL3, but is not limited thereto. For example, the common light emitting layer 5 may include other numbers of stacks and charge generation layers.

[0127] The first stack EL1 may be disposed on the first electrode 4 and configured as a structure in which a hole injection layer HIL, a hole transport layer HTL, a blue (B) light emitting layer EML1 , and an electron transport layer ETL are sequentially stacked from bottom to top, but is not limited thereto.

[0128] The first stack EL1 may be disposed between the first sub-pixel 21 and the second sub-pixel 22 , and between the second sub-pixel 22 and the third sub-pixel 23 , that is, on the bank BK.

[0129] The first charge generation layer CGL1 is used to provide charges to the first stack EL1 and the second stack EL2. The first charge generation layer CGL1 may include an N-type charge generation layer for providing electrons to the first stack EL1 and a P-type charge generation layer for providing holes to the second stack EL2. The N-type charge generation layer may include a metal material as a dopant, but is not limited thereto.

[0130] The first charge generation layer CGL1 may be disposed on the bank BK between adjacent sub-pixels. As an example, the first charge generation layer CGL1 may be disposed between the first sub-pixel 21 and the second sub-pixel 22, and between the second sub-pixel 22 and the third sub-pixel 23, that is, disposed on the bank BK. In addition, in the display device 1 according to an exemplary embodiment, since the common light emitting layer 5 is also disposed between the sub-pixels 21, 22, and 23, when any one of the sub-pixels emits light, a lateral leakage current may be generated to the adjacent sub-pixels 21, 22, and 23 through the first charge generation layer CGL1, but since the bank BK having a predetermined height is disposed between the sub-pixels 21, 22, and 23, the current path may be increased, thereby preventing the generation of the lateral leakage current. In addition, since the bank BK has an asymmetric shape, the thickness of the first charge generation layer CGL1 may be reduced at one or more side surfaces of the bank BK. Therefore, the first charge generation layer CGL1 may be physically separated from at least one side surface of the bank BK. This will be described in detail below.

[0131] The second stack EL2 can be arranged above the first stack EL1, wherein the first charge generation layer CGL1 is arranged between the first stack EL1 and the second stack EL2, and the second stack EL2 is configured as a structure in which a hole transport layer HTL, a green (G) light emitting layer EML2, and an electron transport layer ETL are stacked sequentially from bottom to top, but is not limited thereto.

[0132] The second stack EL2 may be disposed on the bank BK between adjacent sub-pixels. As an example, the second stack EL2 may be disposed between the first sub-pixel 21 and the second sub-pixel 22 and between the second sub-pixel 22 and the third sub-pixel 23, that is, on the bank BK.

[0133] The second charge generation layer CGL2 is used to provide charges to the second stack EL2 and the third stack EL3. The second charge generation layer CGL2 may include an N-type charge generation layer for providing electrons to the second stack EL2 and a P-type charge generation layer for providing holes to the third stack EL3. The N-type charge generation layer may include a metal material as a dopant, but is not limited thereto.

[0134] The second charge generation layer CGL2 may be disposed on the bank BK between adjacent sub-pixels. As an example, the second charge generation layer CGL2 may be disposed between the first sub-pixel 21 and the second sub-pixel 22, and between the second sub-pixel 22 and the third sub-pixel 23, that is, disposed on the bank BK. In addition, in the display device 1 according to an exemplary embodiment, since the common light-emitting layer 5 is also disposed between the sub-pixels 21, 22, and 23, when any one of the sub-pixels emits light, a lateral leakage current may be generated to the adjacent sub-pixels 21, 22, and 23 through the second charge generation layer CGL2, but since a bank BK having a predetermined height is disposed between the sub-pixels 21, 22, and 23, the current path may be increased, thereby preventing the generation of a lateral leakage current. In addition, since the bank BK has an asymmetric shape, the thickness of the second charge generation layer CGL2 may be reduced at one or more side surfaces of the bank BK. Therefore, the second charge generation layer CGL2 may be physically separated from at least one side surface of the bank BK. This will be described in detail below.

[0135] The third stack EL3 can be arranged above the second stack EL2, wherein the second charge generation layer CGL2 is arranged between the third stack EL3 and the second stack EL2, and the third stack EL3 is configured as a structure in which a hole transport layer HTL, a red (R) light emitting layer EML3, an electron transport layer ETL and an electron injection layer EIL are stacked in sequence from bottom to top, but is not limited thereto.

[0136] Return to reference Figure 2 , a second electrode 6 is formed on the common light emitting layer 5 , an encapsulation layer 8 is formed on the second electrode 6 , and a color filter layer 9 is formed on the encapsulation layer 8 .

[0137] Although not shown, a black matrix for preventing color mixing between sub-pixels may be disposed between the first color filter 91 , the second color filter 92 , and the third color filter 93 .

[0138] Hereinafter, the bank BK having an asymmetric shape according to one exemplary embodiment will be described in detail.

[0139] Figure 5 yes Figure 2 Magnified view of area Q1 in FIG. Figure 6 yes Figure 5 Magnified view of area Q2 in FIG. Figure 7 Based on the modified example Figure 5 An enlarged view of region Q2 of the display device.

[0140] Reference Figures 5 to 7 The bank BK has an asymmetric shape, and may include a first portion BK1, a second portion BK2, and a third portion BK3, but is not limited thereto.

[0141] like Figure 5 As shown, a portion (or a lower end portion) of the first portion BK1 may be disposed in the indentation IDP, and another portion (or an upper portion) of the first portion BK1 may protrude upward from the indentation IDP. The side surfaces of the first portion BK1 may be in contact with the transparent layer 42 of the adjacent sub-pixels 21 and 22, respectively. The upper surface and the lower surface of the first portion BK1 may be flat. The second portion BK2 may be disposed in the first sub-pixel 21. The second portion BK2 may be in direct contact with the first portion BK1. The inner surface of the second portion BK2 may be in direct contact with the first portion BK1, and the outer surface of the second portion BK2 may be inclined. In the present disclosure, the term "inclined" may mean in the extension direction (or horizontal direction) of the substrate 2 (see Figure 2 ) and the vertical direction (vertical direction or thickness direction) of the substrate 2. The third part BK3 may be arranged in the second sub-pixel 22. The third part BK3 may be in direct contact with the first part BK1. The inner surface of the third part BK3 may be in direct contact with the first part BK1, and the outer surface of the third part BK3 may be inclined. The second part BK2 and the third part BK3 may be asymmetric with respect to the first part BK1. For example, the thickness of the third part BK3 may be greater than the thickness of the second part BK2, and the length of the outer surface of the third part BK3 may be greater than the length of the outer surface of the second part BK2, but is not limited thereto. The outer surface of the third part BK3 and the outer surface of the second part BK2 may each be one of the side surfaces of the embankment BK. The upper surfaces of the second part BK2 and the third part BK3 may each be flat.

[0142] The lower surface of the second portion BK2 may directly contact the upper surface of the transparent layer 42 of the first sub-pixel 21. The lower surface of the third portion BK3 may directly contact the upper surface of the transparent layer 42 of the second sub-pixel 22. The lower surface of the first portion BK1 may directly contact the upper surface of the fourth insulating layer 3d.

[0143] like Figure 6As shown, the thickness T6 of the first portion BK1 may be greater than the thickness T4 of the second portion BK2 and the thickness T5 of the third portion BK3. The thickness T5 of the third portion BK3 may be greater than the thickness T4 of the second portion BK2, but is not limited thereto. The length L2 of the outer surface of the third portion BK3 may be greater than the length L1 of the outer surface of the second portion BK2, but is not limited thereto. As described above, the reason why the second portion BK2 and the third portion BK3 have different shapes relative to the first portion BK1 is that, as described above, the upper and lower positions of the transparent layers 42 of the adjacent sub-pixels 21, 22, and 23 are different. For example, the transparent layer 42 of the second sub-pixel 22 is disposed lower than the transparent layer 42 of the first sub-pixel 21, and the embankment BK is disposed directly on the transparent layer 42 of the sub-pixels 21 and 22. For example, the transparent layer 42 of the second sub-pixel 22 is disposed lower than the transparent layer 42 of the third sub-pixel 23, and the embankment BK is disposed directly on the transparent layer 42 of the sub-pixels 22 and 23. When manufacturing the bank BK, after the bank insulating film including the organic insulating film is deposited across the sub-pixels 21, 22, and 23, the bank BK may be patterned to meet the boundaries of the sub-pixels 21, 22, and 23. The upper surface of the patterned bank BK may extend in the horizontal direction, and the side surfaces thereof may extend to the transparent layer 42 adjacent to the upper surface, respectively, and as described above, since the upper and lower positions of the transparent layer 42 of the adjacent sub-pixels 21, 22, and 23 are different, the length between the side surfaces of the bank BK may be formed differently. For example, the thickness T6 of the first portion BK1 may be greater than the thickness T4 of the second portion BK2 and the thickness T5 of the third portion BK3, the thickness T5 of the third portion BK3 may be greater than the thickness T4 of the second portion BK2, and the length L2 of the outer surface of the third portion BK3 may be greater than the length L1 of the outer surface of the second portion BK2, but is not limited thereto.

[0144] In addition, as above Figure 4 The plurality of layers EL1 , CGL1 , and EL2 of the common light emitting layer 5 of the OLED described in the accompanying drawings may have different thicknesses according to regions disposed on the bank BK, but is not limited thereto.

[0145] For example, the thicknesses TEL1a, TCGL1a and TEL2a of the multiple layers EL1, CGL1 and EL2 on the upper surface of the embankment BK may be respectively greater than the thicknesses TEL1b, TCGL1b and TEL2b of the multiple layers EL1, CGL1 and EL2 on the first side surface of the embankment BK of the first sub-pixel 21 and the thicknesses TEL1c, TCGL1c and TEL2c of the multiple layers EL1, CGL1 and EL2 on the second side surface of the embankment BK of the second sub-pixel 22, and the thicknesses TEL1b, TCGL1b and TEL2b of the multiple layers EL1, CGL1 and EL2 on the first side surface of the embankment BK of the first sub-pixel 21 may be respectively greater than the thicknesses TEL1c, TCGL1c and TEL2c of the multiple layers EL1, CGL1 and EL2 on the second side surface of the embankment BK of the second sub-pixel 22, but are not limited to this.

[0146] The thicknesses TEL1a, TCGL1a and TEL2a of the multiple layers EL1, CGL1 and EL2 on the upper surface of the embankment BK may be respectively greater than the thicknesses TEL1b, TCGL1b and TEL2b of the multiple layers EL1, CGL1 and EL2 on the first side surface of the embankment BK of the first sub-pixel 21 and the thicknesses TEL1c, TCGL1c and TEL2c of the multiple layers EL1, CGL1 and EL2 on the second side surface of the embankment BK of the second sub-pixel 22, and the thicknesses TEL1b, TCGL1b and TEL2b of the multiple layers EL1, CGL1 and EL2 on the first side surface of the embankment BK of the first sub-pixel 21 may be respectively greater than the thicknesses TEL1c, TCGL1c and TEL2c of the multiple layers EL1, CGL1 and EL2 on the second side surface of the embankment BK of the second sub-pixel 22, because when a common light-emitting material layer including an organic material is applied, the common light-emitting material layer may flow downward to reduce the thickness on the side surface of the embankment BK. Therefore, the thicknesses TEL1a, TCGL1a and TEL2a of the multiple layers EL1, CGL1 and EL2 on the upper surface of the embankment BK may be respectively greater than the thicknesses TEL1b, TCGL1b and TEL2b of the multiple layers EL1, CGL1 and EL2 on the first side surface of the embankment BK of the first sub-pixel 21 and the thicknesses TEL1c, TCGL1c and TEL2c of the multiple layers EL1, CGL1 and EL2 on the second side surface of the embankment BK of the second sub-pixel 22.

[0147] Therefore, since the length L2 of the second side surface of the embankment BK is greater than the length L1 of its first side surface, the thicknesses TEL1b, TCGL1b and TEL2b of the multiple layers EL1, CGL1 and EL2 on the first side surface of the embankment BK of the first sub-pixel 21 can be respectively greater than the thicknesses TEL1c, TCGL1c and TEL2c of the multiple layers EL1, CGL1 and EL2 on the second side surface of the embankment BK of the second sub-pixel 22.

[0148] In addition, the thicknesses TCGL1a, TCGL1b, and TCGL1c of the first charge generation layer CGL1 may be smaller than the thicknesses of other layers of the common light emitting layer 5. In other words, the first charge generation layer CGL1 may have a thickness smaller than that of each of the layers HIL, HTL, EML1, ETL, EML2, and EIL forming the first and second stacks EL1 and EL2, but is not limited thereto.

[0149] In the present disclosure, when the thickness between other layers or stacked layers of the common light emitting layer 5 positioned on the bank BK and the first charge generation layer CGL1 is large or small, it may represent an average thickness.

[0150] Therefore, the first charge generation layer CGL1 may have a very high possibility of physical separation compared with other layers of the common light emitting layer 5 on the side surface of the bank BK.

[0151] In addition, as described above, since the length L2 of the second side surface of the bank BK is greater than the length L1 of the first side surface thereof, the thickness TCGL1c of the first charge generation layer CGL1 on the second side surface of the bank BK of the second sub-pixel 22 is less than the thickness TCGL1b of the first charge generation layer CGL1 on the first side surface of the bank BK of the first sub-pixel 21, and thus the first charge generation layer CGL1 on the second side surface of the bank BK can be more easily separated from at least one side surface of the bank BK. In summary, in an exemplary embodiment, since the bank BK has an asymmetric shape that induces the first charge generation layer CGL1 to be physically separated from at least one side surface of the bank BK, the first charge generation layer CGL1 may not be integrally formed with the sub-pixels 21, 22, and 23, but may be physically separated from at least one side surface of the bank BK. Specifically, the bank BK has an asymmetric shape that induces the first charge generation layer CGL1 on the second side surface of the bank BK to be physically separated from the second side surface of the bank BK. Therefore, the lateral leakage current between the adjacent sub-pixels 21, 22, and 23 can be prevented. Therefore, color mixing between adjacent sub-pixels 21, 22, and 23 can be prevented in advance.

[0152] Figure 7 Based on the modified example Figure 5 An enlarged view of region Q2 of the display device.

[0153] Reference Figures 1 to 7 According to the present embodiment, the first charge generation layer CGL1_1 of the common light emitting layer 5' of the display device 1 can be formed by the above Figure 6 The mechanism described in the embodiment is physically separated from at least one side surface of the bank BK, such as physically separated from the outer surface of the third portion BK3 (or the second side surface of the bank BK). The first opening OP1 may be formed between the physically separated first charge generation layers CGL1_1. The second stack EL2 positioned on the first charge generation layer CGL1_1 may directly contact the first stack EL1 through the first opening OP1.

[0154] Since the remaining description is the same as above, Figure 6 Therefore, its detailed description will be omitted or briefly given below.

[0155] Hereinafter, a method for manufacturing a display device according to an exemplary embodiment or a modified example will be described. Figures 1 to 7 Overlapping description of the components described in .

[0156] Figures 8 to 18 is a cross-sectional view of each process in a method of manufacturing a display device according to an exemplary embodiment. Figures 8 to 18 When describing the method of manufacturing a display device, reference may also be made to Figures 1 to 7 .

[0157] Reference Figure 2 and Figure 8 , a first insulating layer 3a is formed on the substrate 2. In each of the sub-pixels 21, 22, and 23, transistors 31, 32, and 33 may be located in the first insulating layer 3a. The first insulating layer 3a may protect the transistors 31, 32, and 33. The first insulating layer 3a may be made of an organic insulating material, but is not necessarily limited thereto, and may be made of an inorganic insulating material.

[0158] Then, refer to Figure 2 and Fig. 9 The reflective layer 41 is formed on the first insulating layer 3a of the first sub-pixel 21, but is not limited thereto. The reflective layer 41 is connected to a source terminal or a drain terminal of the driving thin film transistor of the first transistor 31 through a contact hole.

[0159] Then, refer to Figure 2 and Fig.10, a second insulating layer 3b is formed on the first insulating layer 3a and the reflective layer 41 of the first sub-pixel 21 and the first insulating layer 3a of each of the second sub-pixel 22 and the third sub-pixel 23. The second insulating layer 3b may be made of an organic insulating material, but is not necessarily limited thereto, and may be made of an inorganic insulating material. The second insulating layer 3b may cover and protect the reflective layer 41 of the first sub-pixel 21.

[0160] Then, refer to Figure 2 and Fig.11 The reflective layer 41 is formed on the second insulating layer 3b of the third sub-pixel 23. The reflective layer 41 is connected to a source terminal or a drain terminal of the driving thin film transistor of the third transistor 33 through a contact hole.

[0161] Then, refer to Figure 2 and Fig.12 , a third insulating layer 3c is formed on the second insulating layer 3b and the reflective layer 41 of the third sub-pixel 23 and the second insulating layer 3b of each of the first sub-pixel 21 and the second sub-pixel 22. The third insulating layer 3c may be made of an organic insulating material, but is not necessarily limited thereto, and may be made of an inorganic insulating material. The third insulating layer 3c may cover and protect the reflective layer 41 of the third sub-pixel 23.

[0162] Then, refer to Figure 2 and Fig.13 , a reflective layer 41 is formed on the third insulating layer 3c of the second sub-pixel 22. The reflective layer 41 is connected to a source terminal or a drain terminal of the driving thin film transistor of the second transistor 32 through a contact hole.

[0163] Then, refer to Figure 2 and Fig.14 , a fourth insulating layer 3d is formed on the third insulating layer 3c and the reflective layer 41 of the second sub-pixel 22 and the third insulating layer 3c of each of the first sub-pixel 21 and the third sub-pixel 23. The fourth insulating layer 3d may be made of an organic insulating material, but is not necessarily limited thereto, and may be made of an inorganic insulating material. The fourth insulating layer 3d may cover and protect the reflective layer 41 of the second sub-pixel 22.

[0164] Then, refer to Figure 2 and Fig.15, an indentation IDP is formed in the fourth insulating layer 3d of the second sub-pixel 22. For example, the indentation IDP may be formed by being recessed from the upper surface of the fourth insulating layer 3d in the thickness direction, but is not limited thereto. The thickness T2 of the fourth insulating layer 3d formed with the indentation IDP may be less than the thickness T1 of the fourth insulating layer 3d where the indentation IDP is not formed. The indentation IDP may be formed in the second sub-pixel 22. The width of the indentation IDP may be greater than the width of the second sub-pixel 22, but is not limited thereto. In this case, the indentation IDP may be formed in the entire second sub-pixel 22 and in the portions of the sub-pixels 21 and 23 adjacent to the second sub-pixel 22. However, the present disclosure is not limited thereto, and the width of the indentation IDP may be the same as the width of the second sub-pixel 22. In this case, the indentation IDP may be formed only in the second sub-pixel 22. The indentation IDP may be formed to have a greater width than the transparent layer 42. Since the transparent layer 42 is disposed in the space in which the indentation IDP is formed in the second sub-pixel 22, the width of the indentation IDP is preferably greater than the width of the transparent layer 42. However, the present disclosure is not limited thereto, and the width of the indentation IDP may be the same as the width of the transparent layer 42 .

[0165] Furthermore, the indentation IDP is shown to be formed only in a portion of the entire second sub-pixel 22 and the adjacent sub-pixels 21 and 23, but is not limited thereto, and may be formed in a portion of the entire first sub-pixel 21 and the adjacent sub-pixels 22 and 23, or in a portion of the entire third sub-pixel 23 and the adjacent sub-pixels 21 and 22. Hereinafter, for ease of description, the description will focus on a case in which the indentation IDP is formed only in a portion of the entire second sub-pixel 22 and the adjacent sub-pixels 21 and 23.

[0166] The upper surface of the fourth insulating layer 3 d where the indentation IDP is formed may be located in line with the upper surface of the reflective layer 41 of the second sub-pixel 22 .

[0167] Then, refer to Figure 2 and Fig.16 , a transparent layer 42 is formed on the fourth insulating layer 3 d of each of the sub-pixels 21 , 22 , and 23 .

[0168] In one exemplary embodiment, since the indentation IDP is formed on the entire second sub-pixel 22, the transparent layer 42 of the second sub-pixel 22 disposed on the insulating layer 3 in which the indentation IDP is formed may be disposed lower than the transparent layer 42 of the adjacent sub-pixels 21 and 23 disposed on the insulating layer 3 in which the indentation IDP is not formed. In other words, the transparent layer 42 of the second sub-pixel 22 disposed on the insulating layer 3 in which the indentation IDP is formed may be disposed closer to the substrate 2 than the transparent layer 42 of the adjacent sub-pixels 21 and 23 disposed on the insulating layer 3 in which the indentation IDP is not formed. Since the transparent layer 42 of each of the sub-pixels 21, 22, and 23 is made of the same material and formed in the same process, the thickness of the transparent layer 42 of each of the sub-pixels 21, 22, and 23 may all be the same, but the present disclosure is not limited thereto. Therefore, the height of the surface of the transparent layer 42 of the second sub-pixel 22 may be positioned lower than the height of the surface of the transparent layer 42 of the adjacent sub-pixels 21 and 23, but the present disclosure is not limited thereto.

[0169] In the second sub-pixel 22, the transparent layer 42 is arranged on the reflective layer 41, and in each of the first sub-pixel 21 and the third sub-pixel 23, the transparent layer 42 is arranged on the fourth insulating layer 3d. The transparent layer 42 is used to provide holes to the common light-emitting layer 5. The transparent layer 42 can be transparently arranged so that the light reflected from the reflective layer 41 can propagate upward. The transparent layer 42 can be made of a transparent material, but is not limited to this, and can be made of a thin metal material as long as it can transmit light. In addition, in the present disclosure, the first electrode 4 is described as having a double-layer structure of a reflective layer 41 and a transparent layer 42, but may have more or less layers. For example, the first electrode 4 can be formed by including a highly reflective metal material, such as a laminated structure (ITO / Al / ITO) of aluminum and ITO, an APC alloy, and a laminated structure (ITO / APC / ITO) of an APC alloy and ITO. The APC alloy represents an alloy of silver (Ag), palladium (Pb) and copper (Cu), but is not limited to this.

[0170] The transparent layer 42 may be electrically connected to the reflective layer 41 by directly contacting the reflective layer 41, or may be electrically connected to the reflective layer 41 by indirectly connecting to the reflective layer 41 through a contact hole and a connection electrode. As an example, in the second sub-pixel 22, the transparent layer 42 may be electrically connected to the reflective layer 41 by directly contacting the reflective layer 41, and in each of the first sub-pixel 21 and the third sub-pixel 23, the transparent layer 42 may be electrically connected to the reflective layer 41 by indirectly connecting to the reflective layer 41, but is not limited thereto. The reflective layer 41 may be connected to each of the first transistor 31, the second transistor 32, and the third transistor 33 through another contact hole to transmit a driving voltage provided by each of the first transistor 31, the second transistor 32, and the third transistor 33 to the transparent layer 42. When a driving voltage is applied from the first transistor 31, the second transistor 32, and the third transistor 33, the transparent layer 42 may provide holes to the common light emitting layer 5. In the second sub-pixel 22, the transparent layer 42 may be in direct contact with the reflective layer 41.

[0171] Then, refer to Figure 2 and Fig.17 , the bank BK is formed to surround and cover the edge of the transparent layer 42 or the reflective layer 41 on the insulating layer 3. Specifically, in the first sub-pixel 21 and the third sub-pixel 23, the bank BK is formed to surround and cover the edge of the transparent layer 42 on the insulating layer 3, and in the second sub-pixel 22, the bank BK is formed to surround and cover the edge of the transparent layer 42 on the reflective layer 41. Therefore, the bank BK can cover both ends of the transparent layer 42 provided in each of the first sub-pixel 21, the second sub-pixel 22, and the third sub-pixel 23. Specifically, the bank BK can be formed to cover a portion of the upper surface of the transparent layer 42 and the side surfaces of both ends of the transparent layer 42 and a portion of the upper surface of the insulating layer 3, so that the current can be concentrated at both ends of the transparent layer 42, thereby solving the problem of reduced luminous efficiency. The upper surface of the transparent layer 42 that is not covered by the bank BK and is exposed becomes a light-emitting area. The bank BK may be made of an organic insulating film including an organic insulating material such as acrylic resin, epoxy resin, phenolic resin, polyamide resin and / or polyimide resin, etc., or an inorganic insulating film including an inorganic insulating material such as silicon nitride, aluminum nitride, zirconium nitride, titanium nitride, hafnium nitride, tantalum nitride, silicon oxide, aluminum oxide or titanium oxide, etc. In addition, the bank BK may include a black dye to absorb light incident from the outside.

[0172] The bank BK between the adjacent sub-pixels 21 and 22 may fill a portion of the indentation IDP, may contact the upper surface and the side surface of the fourth insulating layer 3d adjacent to the indentation IDP, and may directly contact the side surface and the upper surface of each transparent layer 42 of the sub-pixels 21 and 22, but is not limited thereto. The bank BK between the adjacent sub-pixels 22 and 23 may fill a portion of the indentation IDP, may contact the upper surface and the side surface of the fourth insulating layer 3d adjacent to the indentation IDP, and may directly contact the side surface and the upper surface of each transparent layer 42 of the sub-pixels 22 and 23, but is not limited thereto.

[0173] The bank BK according to an exemplary embodiment may have an asymmetric shape, but is not limited thereto. The reason why the bank BK has an asymmetric shape is that the upper and lower positions of the transparent layers 42 of the adjacent sub-pixels 21, 22, and 23 are different. Figure 2 , Figure 5 and Figure 6 Detailed description is given in , so its detailed description will be omitted or briefly given.

[0174] Then, refer to Figure 2 and Fig.18 , a common light emitting layer 5 is formed on the first electrode 4 and the insulating layer 3. The common light emitting layer 5 may be formed on the bank BK disposed between the plurality of sub-pixels 21, 22, and 23 and the transparent layer 42 of the first electrode 4. Therefore, the common light emitting layer 5 may be in contact with the upper surface of the transparent layer 42 of the first electrode 4. The common light emitting layer 5 may be in contact with the upper surface of the transparent layer 42 exposed by the bank BK, the side surface of the adjacent bank BK, and the upper surface of the bank BK. Figure 3 As described above, the common light emitting layer 5 may include a first stacked layer EL1, a second stacked layer EL2, and a first charge generating layer CGL1 disposed on the first electrode 4, or as described above, Figure 4 As described above, the common light emitting layer 5_1 may include a first stack EL1, a second stack EL2, a third stack EL3, a first charge generation layer CGL1 between the first stack EL1 and the second stack EL2, and a second charge generation layer CGL2 between the second stack EL2 and the third stack EL3, but is not limited thereto.

[0175] As above Figure 6As described above, the thickness T6 of the first part BK1 may be greater than the thickness T4 of the second part BK2 and the thickness T5 of the third part BK3, and the thickness T5 of the third part BK3 may be greater than the thickness T4 of the second part BK2, but is not limited thereto. The length L2 of the outer surface of the third part BK3 may be greater than the length L1 of the outer surface of the second part BK2, but is not limited thereto. Accordingly, the plurality of layers EL1, CGL1, and EL2 of the common light-emitting layer 5 of the OLED may have different thicknesses according to the regions provided on the bank BK.

[0176] When a common light-emitting material layer including an organic material is applied, the common light-emitting material layer may flow downward to reduce the thickness on the side surface of the bank BK. Accordingly, the thicknesses TEL1a, TCGL1a, and TEL2a of the plurality of layers EL1, CGL1, and EL2 on the upper surface of the bank BK may be greater than the thicknesses TEL1b, TCGL1b, and TEL2b of the plurality of layers EL1, CGL1, and EL2 on the first side surface of the bank BK of the first sub-pixel 21 and the thicknesses TEL1c, TCGL1c, and TEL2c of the plurality of layers EL1, CGL1, and EL2 on the second side surface of the bank BK of the second sub-pixel 22, respectively, and the thicknesses TEL1b, TCGL1b, and TEL2b of the plurality of layers EL1, CGL1, and EL2 on the first side surface of the bank BK of the first sub-pixel 21 may be greater than the thicknesses TEL1c, TCGL1c, and TEL2c of the plurality of layers EL1, CGL1, and EL2 on the second side surface of the bank BK of the second sub-pixel 22, respectively, but is not limited thereto.

[0177] In addition, the thicknesses TCGL1a, TCGL1b, and TCGL1c of the first charge generation layer CGL1 may be less than the thicknesses of the other layers of the common light-emitting layer 5. In other words, the first charge generation layer CGL1 may have a thickness smaller than the thickness of each of the layers HIL, HTL, EML1, ETL, EML2, and EIL forming the first stack EL1 and the second stack EL2.

[0178] Accordingly, the first charge generation layer CGL1 may have a very high possibility of physical separation compared to the other layers of the common light-emitting layer 5 on the side surface of the bank BK.

[0179] In addition, as described above, since the length L2 of the second side surface of the bank BK is greater than the length L1 of the first side surface thereof, the thickness TCGL1c of the first charge generation layer CGL1 on the second side surface of the bank BK of the second sub-pixel 22 is less than the thickness TCGL1b of the first charge generation layer CGL1 on the first side surface of the bank BK of the first sub-pixel 21, and thus the first charge generation layer CGL1 on the second side surface of the bank BK can be more easily separated from at least one side surface of the bank BK. In summary, in an exemplary embodiment, since the bank BK has an asymmetric shape that induces the first charge generation layer CGL1 to be physically separated from at least one side surface of the bank BK, the first charge generation layer CGL1 may not be integrally formed with the sub-pixels 21, 22, and 23, but may be physically separated from at least one side surface of the bank BK. Specifically, the bank BK has an asymmetric shape that induces the first charge generation layer CGL1 on the second side surface of the bank BK to be physically separated from the second side surface of the bank BK. Therefore, the lateral leakage current between the adjacent sub-pixels 21, 22, and 23 can be prevented. Therefore, color mixing between adjacent sub-pixels 21, 22, and 23 can be prevented in advance.

[0180] Hereinafter, a display device according to another exemplary embodiment will be described.

[0181] Fig.19 According to another exemplary embodiment Figure 5 An enlarged view of region Q2 of the display device.

[0182] Reference Fig.19 According to the display device 1_2 of this embodiment, Figure 2 The display device 1 shown is different in that it can be applied Figure 4 As shown in the common light-emitting layer 5_1. Figure 4 The common light emitting layer 5_1 is described in the accompanying drawings, and thus a detailed description thereof will be omitted or briefly given below.

[0183] Fig. 20 According to yet another exemplary embodiment Figure 5 An enlarged view of region Q2 of the display device.

[0184] Reference Fig. 20 According to the display device 1_2 of this embodiment, Fig.19 The display device shown is different in that the first charge generation layer CGL1_1 may be physically separated from the second side surface of the bank BK (or the outer surface of the third portion BK3) (see FIG. 2 ). Figure 7 ),and Fig. 20 The second charge generation layer CGL2_1 may also be physically separated from the second side surface of the bank BK (or the outer surface of the third portion BK3). Fig. 20 The first charge generation layer CGL1_1 may also be physically separated from the second side surface of the bank BK (or the outer surface of the third portion BK3 ).

[0185] More specifically, the second opening OP2 may be formed between the physically separated second charge generation layers CGL2_1. Figure 7 , the first opening OP1 may be formed between the physically separated first charge generation layers CGL1_1. The second stack EL2 located on the first charge generation layer CGL1_1 may directly contact the first stack EL1 through the first opening OP1. The third stack EL3 located on the second charge generation layer CGL2_1 may directly contact the second stack EL2 through the second opening OP2. Since the contact relationship between the first opening OP1, the second stack EL2 and the first stack EL1 has been described above, Figure 7 Therefore, the detailed description thereof will be omitted or briefly given below.

[0186] Although the embodiments have been described above with reference to the accompanying drawings, it will be understood by those skilled in the art that the above technical configurations can be performed in other specific forms without changing their technical spirit or their essential features. Therefore, it should be understood that the above embodiments are illustrative in all aspects and not restrictive. In addition, the scope of the embodiments is indicated by the attached claims rather than by the detailed description. In addition, the meaning and scope of the claims and all changes or modified forms derived from their equivalent concepts should be interpreted as being included within the scope of the embodiments.

[0187] CROSS-REFERENCE TO RELATED APPLICATIONS

[0188] This application claims priority to Korean Patent Application No. 10-2023-0162100, filed on November 21, 2023, which is hereby incorporated by reference in its entirety for all purposes as if fully set forth herein.

Claims

1. A display device, comprising: a substrate having a pixel including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels; as well as a bank, the bank being arranged between adjacent sub-pixels on the first electrode, wherein a first electrode of a second sub-pixel among the plurality of sub-pixels is positioned lower than a first electrode of the first sub-pixel, and The bank includes a plurality of side surfaces, and lengths between the plurality of side surfaces are different.

2. The display device according to claim 1, further comprising: An insulating layer between the substrate and the first electrode, wherein the insulating layer includes an indentation recessed in a thickness direction in the second sub-pixel, and the first electrode of the second sub-pixel is located in the indentation.

3. The display device according to claim 2, wherein: The indentation is formed throughout the second sub-pixel and a portion of the first sub-pixel.

4. The display device according to claim 2, wherein: The plurality of sub-pixels further include a third sub-pixel, and the indentation is formed in the entire second sub-pixel and a portion of the first sub-pixel and a portion of the third sub-pixel.

5. The display device according to claim 2, wherein: The bank includes a first portion, a second portion connected to the first portion to overlap with the first electrode of the first subpixel, and a third portion connected to the first portion to overlap with the first electrode of the second subpixel, and a portion of the first portion is disposed in the indentation.

6. The display device according to claim 5, wherein: The second portion and the third portion are asymmetric relative to the first portion.

7. The display device according to claim 5, wherein: The thickness of the third portion is greater than the thickness of the second portion.

8. The display device according to claim 5, wherein: A length of a side surface of the third portion is greater than a length of a side surface of the second portion. 9 . The display device according to claim 5 , further comprising a common light emitting layer provided on an upper surface of the first electrode exposed by the bank and the bank.

10. The display device according to claim 9, wherein: The common light emitting layer includes a first stacked layer, a first charge generating layer on the first stacked layer, and a second stacked layer on the first charge generating layer.

11. The display device according to claim 10, wherein: Each of the first stack and the second stack includes a plurality of layers.

12. The display device according to claim 11, wherein: The first charge generation layer has a thickness smaller than that of each of the plurality of layers of the first stack, and smaller than that of each of the plurality of layers of the second stack.

13. The display device according to claim 10, wherein: A thickness of the first charge generation layer on a side surface of the second portion is greater than a thickness of the first charge generation layer on a side surface of the third portion.

14. The display device according to claim 10, wherein: A thickness of the first charge generation layer on a side surface of the second portion and a thickness of the first charge generation layer on a side surface of the third portion are smaller than a thickness of the first charge generation layer on an upper surface of the first portion.

15. The display device according to claim 10, wherein: The first charge generation layer is separated from a side surface of the third portion.

16. The display device according to claim 15, wherein: The second laminate is in direct contact with the first laminate on a side surface of the third portion.

17. The display device according to claim 16, wherein: A first opening is formed between the physically separated first charge generation layers, and the second stack directly contacts the first stack on the side surface of the third portion through the first opening.

18. The display device according to claim 10, wherein: The common light emitting layer further includes a second charge generation layer on the second stack and a third stack on the second charge generation layer.

19. The display device according to claim 18, wherein: The second charge generation layer is separated from a side surface of the third portion.

20. The display device according to claim 19, wherein: The third laminate is in direct contact with the second laminate on a side surface of the third portion.

21. The display device according to claim 1, wherein: A height of a surface of the first electrode of the second sub-pixel is lower than a height of a surface of the first electrode of the first sub-pixel.

22. The display device according to claim 4, wherein: A height of a surface of the first electrode of the second sub-pixel is lower than a height of a surface of the first electrode of the third sub-pixel.

23. A display device, comprising: a substrate having a pixel including a plurality of sub-pixels; a first electrode disposed in each of the plurality of sub-pixels; a bank, the bank being disposed on the first electrode between adjacent sub-pixels; as well as a common light-emitting layer, the common light-emitting layer being disposed on the upper surface of the first electrode exposed by the bank and the bank, wherein the bank has an asymmetric shape, and At least one of the common light emitting layers is separated from the bank having the asymmetric shape.

24. The display device according to claim 23, wherein: The embankment includes a first portion, a second portion connected to the first portion to overlap with a first electrode of a first sub-pixel among the plurality of sub-pixels, a third portion connected to the first portion to overlap with a first electrode of a second sub-pixel among the plurality of sub-pixels, and a side surface length of the third portion is greater than a side surface length of the second portion.

25. The display device according to claim 24, wherein: The common light emitting layer includes a first stacked layer, a first charge generating layer on the first stacked layer, and a second stacked layer on the first charge generating layer.

26. The display device according to claim 25, wherein: The first stack and the second stack each include a plurality of layers, and the first charge generation layer has a thickness smaller than that of each of the plurality of layers of the first stack and smaller than that of each of the plurality of layers of the second stack.

27. The display device according to claim 25, wherein: A thickness of the first charge generation layer on a side surface of the second portion is greater than a thickness of the first charge generation layer on a side surface of the third portion.

28. The display device according to claim 25, wherein: A thickness of the first charge generation layer on a side surface of the second portion and a thickness of the first charge generation layer on a side surface of the third portion are smaller than a thickness of the first charge generation layer on an upper surface of the first portion.

29. The display device according to claim 25, wherein: The first charge generation layer is separated from a side surface of the third portion, and the second stack is in direct contact with the first stack on the side surface of the third portion.

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