3D display panel, manufacturing method and 3D display device

Abstract

The invention discloses a 3D display panel, a manufacturing method and a 3D display device. The 3D display panel according to one embodiment comprises: a substrate; the pixel units are arranged on the substrate in an array mode, and at least one pixel unit comprises K sub-pixels arranged in the first direction; the # imgabs0 # first signal lines are arranged in the first direction, each first signal line extends in the second direction perpendicular to the first direction, and each first signal line is located on the same side of N adjacent sub-pixels; the K data signal lines are arranged along the first direction, each data signal line extends along the second direction, and each data signal line is in one-to-one correspondence with each sub-pixel. According to the 3D display panel provided by the embodiment of the invention, the positions of the signal lines are reasonably arranged, so that the space required by arrangement can be reduced, the transparency is increased, and a 3D display product with high transparency and high uniformity is realized.

Description

Technical Field

[0001] The present invention relates to the field of display technology. More specifically, it relates to a 3D display panel, a manufacturing method, and a 3D display device. Background Art

[0002] Compared with bottom-emission products, top-emission products have a high space utilization rate because the pixel light-emitting area and the pixel driving circuit can be overlapped in design, and it is easier to achieve a high PPI or a high aperture ratio design, and it is easier to achieve a high transparency design in transparent products. Therefore, how to use top-emission products to improve the transparency of 3D display products is an urgent problem to be solved. Summary of the Invention

[0003] The purpose of the present invention is to provide a 3D display panel, a manufacturing method, and a 3D display device to solve at least one of the problems existing in the prior art.

[0004] To achieve the above purpose, the present invention adopts the following technical solutions:

[0005] In a first aspect of the present invention, a 3D display panel is provided, and the 3D display panel includes:

[0006] A substrate;

[0007] A plurality of pixel units arranged in an array on the substrate, and at least one of the pixel units includes K sub-pixels arranged along a first direction;

[0008] Arranged along the first direction A plurality of first signal lines, each of the first signal lines extends along a second direction perpendicular to the first direction, and each of the first signal lines is located on the same side of N adjacent sub-pixels;

[0009] K data signal lines arranged along the first direction, each of the data signal lines extends along the second direction, and each of the data signal lines corresponds to each sub-pixel one by one.

[0010] In an optional embodiment, in a pixel unit,

[0011] Taking the first axis parallel to the second direction in the gap between the -th and the -th sub-pixels as the axis of symmetry, the data signal lines corresponding to the 1st to the -th sub-pixels and the data signal lines corresponding to the -th to the K-th sub-pixels are symmetrical about the first axis;

[0012] Taking the first axis parallel to the second direction in the gap between the -th and the The second axis parallel to the second direction in the gap between sub-pixels is used as the axis of symmetry, and the data signal lines corresponding to the 1st to the sub-pixels and the the data signal lines corresponding to the to

[0013] the sub-pixels corresponding to the data signal lines are symmetric about the second axis;

[0014] In an alternative embodiment, each of the first signal lines includes:

[0015] A first sub-signal line that provides a first voltage signal to the 1st to Nth sub-pixels of the pixel unit, and the first sub-signal line is located on the left side of the 1st sub-pixel;

[0016] A second sub-signal line that provides a first voltage signal to the (N + 1)th to 2Nth sub-pixels of the pixel unit, and the second sub-signal line is located on the left side of the (N + 1)th sub-pixel;

[0017] A third sub-signal line that provides a first voltage signal to the (2N + 1)th to Kth sub-pixels of the pixel unit, and the third sub-signal line is located on the left side of the (2N + 1)th sub-pixel.

[0018] In an alternative embodiment, the 3D display panel further includes second signal lines arranged along the first direction, each of the second signal lines extending along the second direction, and the second signal lines include:

[0019] A fourth sub-signal line that provides a second voltage signal to the 1st to Nth sub-pixels of the pixel unit, and the fourth sub-signal line is located between the sub-pixel and the sub-pixel;

[0020] A fifth sub-signal line that provides a second voltage signal to the (N + 1)th to 2Nth sub-pixels of the pixel unit, and the fifth sub-signal line is located between the sub-pixel and the sub-pixel;

[0021] A sixth sub-signal line that provides a second voltage signal to the (2N + 1)th to Kth sub-pixels of the pixel unit, and the sixth sub-signal line is located between the sub-pixel and the sub-pixel.

[0022] In an optional embodiment, the 3D display panel further includes M third signal lines arranged along the first direction, where M > N, and each third signal line extends along the second direction. The third signal lines include:

[0023] A seventh sub-signal line that provides a sensing signal to the first to Mth sub-pixels of the pixel unit and is located between the th sub-pixel and the th sub-pixel;

[0024] An eighth sub-signal line that provides a sensing signal to the (M + 1)th to Kth sub-pixels of the pixel unit and is located between the th sub-pixel and the th sub-pixel.

[0025] In an optional embodiment, the pixel unit further includes a sub-pixel driving circuit electrically connected to the light-emitting device of each sub-pixel. Each sub-pixel driving circuit includes at least a first transistor, a second transistor, a third transistor, and a storage capacitor.

[0026] Wherein, the first signal line is electrically connected to the second electrode of the light-emitting device;

[0027] The second signal line is electrically connected to the first transistor,

[0028] The third signal line is electrically connected to the third transistor,

[0029] The data signal line is electrically connected to the second transistor.

[0030] In an optional embodiment, the first transistor includes a first control electrode, a first pole, a second pole, and a first active layer. One end of the first active layer is connected to the first pole, and the other end of the first active layer is connected to the second pole;

[0031] The second transistor includes a second control electrode, a third pole, a fourth pole, and a second active layer. One end of the second active layer is connected to the third pole, and the other end of the second active layer is connected to the fourth pole;

[0032] The third transistor includes a third control electrode, a fifth pole, a sixth pole, and a third active layer. One end of the third active layer is connected to the fifth pole, and the other end of the third active layer is connected to the sixth pole;

[0033] The second signal line is electrically connected to the first pole,

[0034] The third signal line is electrically connected to the fifth pole,

[0035] The data signal line is electrically connected to the third pole,

[0036] The second pole, the sixth pole, and the first electrode are connected to the first electrode plate of the storage capacitor;

[0037] The fourth pole and the first control pole are connected to the second electrode plate of the storage capacitor.

[0038] In an optional embodiment, the 3D display panel further includes:

[0039] Scanning signal lines extending in a first direction, each of the scanning signal lines being configured to provide a control signal to the sub-pixel driving circuits arranged in the first direction, the scanning signal lines being electrically connected to the second control pole and the third control pole,

[0040] The orthographic projection of the scanning signal lines on the substrate and the orthographic projection of the second channel region of the second active layer and the third channel region of the third active layer on the substrate at least partially overlap,

[0041] The orthographic projection of the scanning signal lines on the substrate and the orthographic projection of the first signal line, the second signal line, the third signal line, and the data signal line on the substrate at least partially overlap.

[0042] In an optional embodiment, the scanning signal lines include alternately arranged first transmission portions and second transmission portions,

[0043] The orthographic projection of the first transmission portion on the substrate and the orthographic projection of at least one of the first signal line, the second signal line, the third signal line, and the data signal line on the substrate partially overlap,

[0044] The orthographic projection of the second transmission portion on the substrate and the orthographic projection of at least one of the second transistor and the third transistor on the substrate partially overlap,

[0045] The width of the first transmission portion in the second direction is a first width, the width of the second transmission portion in the second direction is a second width, and the first width is greater than the second width.

[0046] In an optional embodiment, at least one of the first transmission portions includes a hollow portion, the first transmission portion includes a first scanning portion and a second scanning portion that are opposite and parallel to each other, and the hollow portion is located between the first scanning portion and the second scanning portion.

[0047] In an optional embodiment, the 3D display panel further includes:

[0048] Arranged in each pixel unit A first connecting line, one of the first connecting lines is electrically connected to one of the third signal lines, and a first through hole is formed at an overlapping position of the orthographic projection of the first connecting line on the substrate and the orthographic projection of the corresponding third signal line on the substrate.

[0049] In an optional embodiment, the 3D display panel further includes:

[0050] A second connecting line extending in the first direction, and a second through hole is formed at an overlapping position of the orthographic projection of the second connecting line and all the second signal lines arranged in the first direction on the substrate;

[0051] A third connecting line corresponding to each sub-pixel, one end of each third connecting line is connected to the first pole of the first transistor, and the other end is connected to the second connecting line,

[0052] Fifth through holes are provided at a plurality of overlapping positions of the orthographic projection of the second connecting line and each third connecting line on the substrate.

[0053] In an optional embodiment, the orthographic projection of the pixel unit on the substrate includes a light-emitting area and a transparent area,

[0054] The light-emitting area includes the orthographic projection of the first connecting line and the second connecting line on the substrate, and the area between the orthographic projections of the first connecting line and the second connecting line on the substrate,

[0055] The transparent area includes the part of the orthographic projection of the pixel unit on the substrate that is outside the light-emitting area.

[0056] In an optional embodiment, the width of the first signal line in the first direction is greater than the width of the data signal line in the first direction,

[0057] The first signal line includes:

[0058] A first trace located on the substrate; and

[0059] A second trace located on the side of the first trace away from the substrate;

[0060] The 3D display panel includes at least one first via hole, and the first trace and the second trace are connected through the first via hole.

[0061] In an optional embodiment,

[0062] The width of the second signal line in the first direction is greater than the width of the data signal line in the first direction,

[0063] The second signal line includes:

[0064] A third trace located on the substrate; and a fourth trace located on a side of the third trace away from the substrate;

[0065] The 3D display panel includes at least one second via hole, and the third trace and the fourth trace are connected through the second via hole.

[0066] In an optional embodiment, the width of the third signal line in the first direction is greater than the width of the first signal line in the first direction, or greater than the width of the second signal line in the first direction.

[0067] The third signal line includes:

[0068] A fifth trace located on the substrate; and

[0069] A sixth trace located on a side of the third trace away from the substrate;

[0070] The 3D display panel includes at least one third via hole, and the fifth trace and the sixth trace are connected through the third via hole.

[0071] In an optional embodiment, the first trace, the third trace, and the fifth trace are disposed on the same layer.

[0072] The second trace, the fourth trace, and the sixth trace are disposed on the same layer, and the first via hole, the second via hole, and the third via hole are formed by the same process.

[0073] A second aspect of the present invention provides a method for manufacturing the 3D display panel according to the first aspect of the present invention. The method includes:

[0074] Forming a plurality of pixel units arranged in an array on a substrate, each pixel unit including K sub-pixels extending in a first direction;

[0075] Forming M first signal lines extending in a second direction perpendicular to the first direction on the substrate, each first signal line being located on the same side of all the sub-pixels among the N sub-pixels; Forming K data signal lines extending in the second direction on the substrate, each data signal line corresponding to each sub-pixel one by one.

[0076]

[0077] A third aspect of the present invention provides a 3D display device, and the 3D display device includes the 3D display panel according to the first aspect of the present invention. Description of the Drawings

[0078] The following further describes in detail the specific embodiments of the present invention with reference to the accompanying drawings.

[0079] Figure 1 Schematic diagram of the wiring of a pixel unit of a 3D display panel showing an embodiment of the present invention;

[0080] Figure 2 Schematic diagram of the wiring layout of the pixel unit showing an embodiment of the present invention;

[0081] Figure 3 Schematic circuit diagram of the sub-pixel driving circuit showing an embodiment of the present invention;

[0082] Figure 4 Schematic layout diagram of a sub-pixel showing an embodiment of the present invention;

[0083] Figure 5 Schematic layout diagram of each signal line showing an embodiment of the present invention;

[0084] Figure 6 Show Figure 1 Schematic diagram of the layer structure at the position of cross-section BB shown:

[0085] Figure 7 Show Figure 1 Schematic diagram of the layer structure at the position of cross-section CC shown:

[0086] Figure 8 Show Figure 1 Schematic diagram of the layer structure at the position of cross-section DD shown:

[0087] Figures 9 to 14 Show the formation of Figure 1 Schematic layout diagram of different processes of the pixel unit shown;

[0088] Figure 15 Schematic diagram of the layer structure process for manufacturing the 3D display panel showing an embodiment of the present invention. Detailed implementation manners

[0089] To illustrate the present invention more clearly, the present invention will be further described below in conjunction with embodiments and drawings. Similar components in the drawings are denoted by the same reference numerals. Those skilled in the art should understand that the content specifically described below is illustrative rather than restrictive, and should not be used to limit the protection scope of the present invention.

[0090] Compared with bottom-emission products, top-emission products have a high space utilization rate because the pixel light-emitting area and the pixel driving circuit can be overlapped in design, and it is easier to achieve high PPI or high aperture ratio design, and it is easier to achieve high transparency design in transparent products. Since each pixel of a 3D display product requires more than a dozen viewing zones, and each viewing zone is equivalent to a sub-pixel, the wiring layout space is more tense and difficult under limited space, posing a greater challenge to the pixel aperture ratio and the transmittance of the transparent area.

[0091] The present invention provides a 3D display panel, a manufacturing method, and a 3D display device to solve the above problems.

[0092] The first embodiment of the present invention provides a 3D display panel, as Figure 1 shown. The 3D display panel includes: a substrate 10 and a plurality of pixel units PIX arranged in an array on the substrate 10. At least one of the pixel units PIX includes K sub-pixels Px arranged in a first direction, where x ∈ [1, K]. In this example, x is the serial number value of the sub-pixel at a certain position among the K sub-pixels of the pixel unit.

[0093] The 3D display panel according to the embodiment of the present invention further includes a plurality of first signal lines 20, second signal lines 30, third signal lines 40, and data signal lines 50.

[0094] In the 3D display panel of the first embodiment of the present invention, as Figure 1 shown, the 3D display panel includes:

[0095] A plurality of first signal lines 20 arranged in the first direction. Each of the first signal lines 20 extends in a second direction perpendicular to the first direction. Each of the first signal lines 20 is located on the same side of N adjacent sub-pixels. Preferably, N < K, where N is an integer, so as to drive N adjacent sub-pixels with one first signal line 20; A plurality of K data signal lines 50 arranged in the first direction. Each of the data signal lines 50 extends in the second direction. Each data signal line 50 corresponds to each sub-pixel one by one.

[0096] In the 3D display panel according to the embodiment of the present invention, considering the 3D display effect and the design requirements of the limited wiring layout, the first signal lines and data signal lines among the multiple sub-pixels in the pixel unit are reasonably arranged. By reducing the number of signal lines and reasonably arranging the positions of each signal line, the effective driving of K sub-pixels can be achieved, which can reduce the space required for layout, increase transparency, and realize a 3D display product with high transparency and high uniformity.

[0097] In an alternative embodiment, as

[0098] shown, the 3D display panel further includes: Figure 1 A plurality of second signal lines 30 arranged in the first direction. Each of the second signal lines 30 is located between the

[0099] th sub-pixel and the th sub-pixel among the N sub-pixels Px; and sub-pixel and sub-pixel; and

[0100] The third signal lines 40 arranged along the first direction, each of the third signal lines 40 is located at the th sub-pixel among the M sub-pixels and the th sub-pixel. Preferably, N < M, N < K, and are all integers, that is, M and N are even numbers.

[0101] In this embodiment, the second signal lines and the third signal lines among multiple sub-pixels in the pixel unit are reasonably arranged. By reducing the number of signal lines, the space required for layout can be reduced, the area of the transparent region can be maximized, and a 3D display product with high transparency and high uniformity can be realized.

[0102] Based on the above design of the first signal line 20 and the third signal line 40 of the present invention, in an alternative embodiment, the number of sub-pixels in a pixel unit PIX is a common multiple of the number of the first signal lines and the number of the third signal lines. With this setting, on the basis of achieving a good 3D display effect with multiple sub-pixels in a pixel unit, it is further ensured that K sub-pixels in the pixel unit are simultaneously driven by less than K first signal lines and third signal lines, thereby reducing the wiring area of the 3D display product and further improving the display effect.

[0103] Preferably, in this embodiment, K is a multiple of 12, that is, a pixel unit includes at least 12 sub-pixels, and each sub-pixel serves as an independent viewing area to achieve 3D display. Compared with a 3D display panel formed with 6 sub-pixels as a pixel unit, when K is 12, it has a better 3D display effect, and when K is a multiple of 12, it can achieve a higher-performance 3D display effect.

[0104] Taking K as 12, N as 4, and M as 6 as an example, a pixel unit PIX includes 12 sub-pixels, and the number of each signal line of the 3D display panel is: 3 first signal lines 20, 3 second signal lines 30, 2 third signal lines 40, and 12 data signal lines 50. The layout of the 3D display panel of the embodiment of the present invention will be described in detail below.

[0105] In the embodiment of the present invention, for the first signal lines 20, each of the first signal lines 20 is located on the same side of all the sub-pixels among the N sub-pixels, that is, the adjacent first signal lines 20 are separated by the N sub-pixels.

[0106] In an alternative embodiment, each of the first signal lines 20 provides a first voltage signal to N sub-pixels. The first to the Nth sub-pixels are connected to the same first signal line 20, the (N + 1)th to the 2Nth sub-pixels are connected to the same first signal line 20, and the (2N + 1)th to the Kth sub-pixels are connected to the same first signal line 20. Exemplarily, the first voltage signal is a low-voltage power signal.

[0107] In the layout of the first signal line 20 according to the embodiment of the present invention, as Figure 1 shown, one first signal line 20 drives 4 sub-pixels simultaneously, that is, 3 first signal lines 20 drive 12 sub-pixels in total.

[0108] In an alternative embodiment, as Figure 1 and Figure 2 shown, each of the first signal lines 20 includes:

[0109] A first sub-signal line 201 that provides a first voltage signal to the first to the Nth sub-pixels of the pixel unit. For example, Figure 1 as shown, the first sub-signal line 201 drives the first sub-pixel P 1 to the fourth sub-pixel P 4 , and the first sub-signal line 201 is located on the left side of the first sub-pixel P 1 ;

[0110] A second sub-signal line 202 that provides a first voltage signal to the (N + 1)th to the 2Nth sub-pixels of the pixel unit. The second sub-signal line 202 is located on the left side of the (N + 1)th sub-pixel. For example, Figure 1 as shown, the second sub-signal line 202 drives the fifth sub-pixel P 5 to the eighth sub-pixel P 8 , and the second sub-signal line 202 is located on the left side of the fifth sub-pixel P 5 ;

[0111] A third sub-signal line 203 that provides a first voltage signal to the (2N + 1)th to the Kth sub-pixels of the pixel unit. The third sub-signal line 203 is located on the left side of the (2N + 1)th sub-pixel. For example, Figure 1 as shown, the third sub-signal line 203 drives the ninth sub-pixel P 9 to the twelfth sub-pixel P 12 , and the third sub-signal line 203 is located on the left side of the ninth sub-pixel P 9 ;

[0112] Based on the above embodiments, the number of first signal lines corresponding to 12 sub-pixels is reduced to 3, and each first signal line is evenly distributed among the 12 sub-pixels, ensuring stable transmission of the first voltage signal.

[0113] In the embodiments of the present invention, as Figure 1 shown, the second signal lines 30 of the 3D display panel are arranged along the first direction, and each of the second signal lines 30 provides a second voltage signal different from the first voltage signal to N sub-pixels. The second voltage signal is higher than the first voltage signal, and the second voltage signal is a power supply voltage signal.

[0114] For the second signal lines, the first to the Nth sub-pixels are connected to the same second signal line 30, the (N + 1)th to the 2Nth sub-pixels are connected to the same second signal line 30, and the (2N + 1)th to the Kth sub-pixels are connected to the same second signal line 30.

[0115] In an alternative embodiment, as Figure 1 and Figure 2 shown, the second signal line 30 includes:

[0116] A fourth sub-signal line 304 that provides a second voltage signal to the first to the Nth sub-pixels of the pixel unit. The fourth sub-signal line 304 is located between the sub-pixel and the sub-pixel. For example, as Figure 1 shown, the fourth sub-signal line 304 drives the first sub-pixel P 1 to the fourth sub-pixel P 4 , and the fourth sub-signal line 304 is located between the second sub-pixel and the third sub-pixel;

[0117] A fifth sub-signal line 305 that provides a second voltage signal to the (N + 1)th to the 2Nth sub-pixels of the pixel unit. The fifth sub-signal line 305 is located between the sub-pixel and the sub-pixel. For example, as Figure 1 shown, the fifth sub-signal line 305 drives the fifth sub-pixel P 5 to the eighth sub-pixel P 8 , and the fifth sub-signal line 305 is located at the gap position between the sixth sub-pixel and the seventh sub-pixel;

[0118] A sixth sub-signal line 306 that provides a second voltage signal to the (2N + 1)th to the Kth sub-pixels of the pixel unit. The sixth sub-signal line 306 is located between the sub-pixel and the sub-pixel. For example, as Figure 1 shown, the sixth sub-signal line 306 drives the ninth sub-pixel P 9 to the twelfth sub-pixel P 12, the sixth sub-signal line 306 is located at the gap position between the 10th sub-pixel P 10 and the 11th sub-pixel P 11 .

[0119] In the layout of the second signal line 30 of the embodiment of the present invention, as Figure 1 shown, the number of second signal lines corresponding to 12 sub-pixels is reduced to 3. Through this setting, the number of routing of the second signal line 30 can be reduced, thereby reducing the occupied space of the second signal line 30, maximizing the area of the transparent region, and each side of each second signal line in this embodiment drives 2 sub-pixels, so that the transmission rate of the second signal line to the sub-pixels on both sides is balanced and stable, and the display uniformity is relatively high.

[0120] Based on the layout settings of the above-mentioned first signal line 20 and second signal line 30, the number of sub-pixels arranged between adjacent first signal line 20 and second signal line 30 in the embodiment of the present invention is the same. For example Figure 1 shown, 2 sub-pixels are arranged between the first sub-signal line 201 and the fourth sub-signal line 304, between the fourth sub-signal line 304 and the second sub-signal line 202, and between the second sub-signal line 202 and the fifth sub-signal line 305. That is to say, the first signal line 20 and the second signal line 30 are evenly distributed in the pixel unit PIX, so that the opening of each sub-pixel is uniform, and the display uniformity of the 3D display panel is further improved.

[0121] In an alternative embodiment, as Figure 1 and Figure 2 shown, the 3D display panel further includes M third signal lines 40 arranged along the first direction, M > N, and each third signal line 40 extends along the second direction. Exemplarily, the third signal line 40 transmits a sensing signal to the sub-pixel. M third signal lines 40, M > N, each of the third signal lines 40 extends along the second direction. Exemplarily, the third signal line 40 transmits a sensing signal to the sub-pixel.

[0122] As Figure 1 and Figure 2 shown, taking K as 12 and M as 6 as an example, 2 third signal lines 40 provide sensing signals for a total of 12 sub-pixels, and each third signal line 40 senses 6 sub-pixels respectively. In this embodiment, one third signal line is used to drive multiple sub-pixels, and modular sensing is performed on multiple sub-pixels to improve the driving stability of multiple sub-pixels in the pixel unit PIX.

[0123] In an alternative embodiment, as Figure 1 and Figure 2 shown, the third signal line 40 includes:

[0124] The seventh sub-signal line 407 provides sensing signals to the 1st to Mth sub-pixels of the pixel unit, and is located at the sub-pixel and the Among the sub-pixels, for example, the seventh sub-signal line 407 supplies a sensing signal to the first sub-pixel P 1 to the sixth sub-pixel P 6 and is disposed between the third sub-pixel P 3 and the fourth sub-pixel P 4 .

[0125] The eighth sub-signal line 408 supplies a sensing signal to the (M + 1)-th to K-th sub-pixels of the pixel unit and is located between the sub-pixel and the sub-pixel. For example, the eighth sub-signal line 408 supplies a sensing signal to the seventh sub-pixel P 7 to the twelfth sub-pixel P 12 and is disposed between the ninth sub-pixel P 9 and the tenth sub-pixel P 10 .

[0126] In this embodiment, the number of sub-pixels connected to both sides of each third signal line 40 is the same. That is, three sub-pixels are provided and connected on both the left and right sides of the seventh sub-signal line 407. The left side is the sub-pixel P 1 to the sub-pixel P 3 , and the right side is the sub-pixel P 4 to the sub-pixel P 6 ; the left side of the eighth sub-signal line 408 is the sub-pixel P 7 to the sub-pixel P 9 , and the right side is the sub-pixel P 10 to the sub-pixel P 12 .

[0127] On the basis of reducing the first signal line 20 and the second signal line 30 in the foregoing embodiment, this embodiment further reduces the number of the third signal lines 40, thereby further reducing the space occupied by the signal lines, improving the transparent area of the 3D display panel, and improving the display effect of the 3D display panel.

[0128] Based on the above wiring layout, as shown in Figure 1 and Figure 2 , in the arrangement of all 12 sub-pixels of a pixel unit PIX,

[0129] a first sub-signal line 201 is disposed on the left side of the first sub-pixel P 1 ,

[0130] a fourth sub-signal line 304 is disposed between the second sub-pixel P 2 and the third sub-pixel P 3 ,

[0131] a fourth sub-signal line 304 is disposed between the third sub-pixel P 3and the fourth sub-pixel P 4 A seventh sub-signal line 407 is provided therebetween.

[0132] In the fourth sub-pixel P 4 and the fifth sub-pixel P 5 A second sub-signal line 202 is provided therebetween.

[0133] In the sixth sub-pixel P 6 and the seventh sub-pixel P 7 A fifth sub-signal line 305 is provided therebetween.

[0134] In the eighth sub-pixel P 8 and the ninth sub-pixel P 9 A third sub-signal line 203 is provided therebetween.

[0135] In the ninth sub-pixel P 9 and the tenth sub-pixel P 10 An eighth sub-signal line 408 is provided therebetween.

[0136] In the tenth sub-pixel P 10 and the eleventh sub-pixel P 11 A sixth sub-signal line 306 is provided therebetween.

[0137] Based on the above settings, the first signal line 20, the second signal line 30, and the third signal line 40 are not simultaneously provided between two adjacent sub-pixels. Through this setting, the gaps between adjacent sub-pixels are ensured to be uniform, further ensuring that the opening areas of the sub-pixels are uniformly arranged, avoiding wire congestion, and maximizing the display uniformity and aperture ratio.

[0138] For the K data signal lines 50 arranged along the first direction, exemplarily, when the pixel unit PIX is provided with 12 sub-pixels, the number of data signal lines 50 is also 12, realizing the transmission of control signals for each sub-pixel in the pixel unit PIX.

[0139] In an alternative embodiment, as Figure 1 and Figure 2 shown, in a pixel unit PIX, with the first axis ZX01 parallel to the second direction in the gap between the th sub-pixel and the th sub-pixel as the axis of symmetry, the data signal lines 50 corresponding to the first sub-pixel to the th sub-pixel and the data signal lines 50 corresponding to the th to the Kth sub-pixels are symmetrical about the first axis ZX01.

[0140] As Figure 1 and Figure 2 shown, the first axis ZX01 is located in the sixth sub-pixel P6 and the 7th sub-pixel P 7 Among them, for the first 6 sub-pixels (P 1 ~P 6 ), the data signal lines 50 corresponding to them and the data signal lines 50 corresponding to the last 6 sub-pixels (P 7 ~P 12 ) are symmetrical.

[0141] In this embodiment, the first axis ZX01 is also the axis of symmetry of the second signal line 30 located between the 6th sub-pixel P 6 and the 7th sub-pixel P 7 . That is, no data signal line 50 is provided at the gap position of adjacent sub-pixels corresponding to the first axis ZX01.

[0142] In an alternative embodiment, as shown in Figure 1 and Figure 2 , taking the second axis ZX02 parallel to the second direction in the gap between the th sub-pixel and the th sub-pixel as the axis of symmetry, the data signal lines 50 corresponding to the 1st to th sub-pixels and the data signal lines 50 corresponding to the ~ th sub-pixels are symmetrical about the second axis ZX02.

[0143] In this embodiment, the second axis ZX02 is located between the 3rd sub-pixel P 3 and the 4th sub-pixel P 4 . Therefore, the 1st sub-pixel to the 3rd sub-pixel (P 1 ~P 3 ) and the 4th sub-pixel to the 6th sub-pixel (P 4 ~P 6 ) are symmetrical with respect to the corresponding data signal lines 50.

[0144] Based on the symmetry of the first axis ZX01 and the second axis ZX02, the 7th sub-pixel to the 12th sub-pixel (P 7 ~P 12 ) are also symmetrically arranged. That is, there is also the second axis ZX02 between the 9th sub-pixel P 9 and the 10th sub-pixel P 10 . The 7th sub-pixel to the 9th sub-pixel (P 7 ~P 9 ) and the 10th to the 12th sub-pixel (P 10 ~P 12 ) are symmetrical about the second axis ZX02.

[0145] In this embodiment, the second axis ZX02 is also located in the 3rd sub-pixel P 3 and the 4th sub-pixel P 4 and is the axis of symmetry of the 1st third signal line 40 therebetween. That is, no data signal line 50 is provided at the gap position between adjacent sub-pixels corresponding to the second axis ZX02. Only the third signal line 40 is provided in the gap at the position of the second axis ZX02, avoiding the simultaneous provision of the third signal line 40 and the data signal line 50 from affecting the routing layout.

[0146] In an alternative embodiment, as Figure 1 and Figure 2 shown, the data signal lines 50 corresponding to two sub-pixels between adjacent first signal lines 20 and second signal lines 30 are symmetrically arranged with respect to the third axis ZX03 parallel to the second direction at the middle position of the two sub-pixels as the axis of symmetry.

[0147] In the embodiment of the present invention, two data signal lines 50 are provided in the gap corresponding to the position of the third axis ZX03, and no first signal line 20 or second signal line 30 is provided at this position, avoiding the simultaneous routing of multiple first signal lines 20 and second signal lines 30 from affecting the routing layout.

[0148] In an alternative embodiment, as Figure 1 and Figure 2 shown, the width of the third signal line 40 in the first direction is greater than the width of the first signal line 20 in the first direction, the width of the third signal line 40 in the first direction is greater than the width of the second signal line 30 in the first direction, the width of the first signal line 20 in the first direction is greater than the width of the data signal line 50 in the first direction, and the width of the second signal line 30 in the first direction is greater than the width of the data signal line 50 in the first direction. That is, in the embodiment of the present invention, the widths of the respective signal lines from largest to smallest are the third signal line 40 > the first signal line 20 = the second signal line 30 > the data signal line 50.

[0149] Based on the signal routing arrangement and routing width setting of the above embodiment, in the gap between adjacent sub-pixels, there are arrangement modes of simultaneously providing two data signal lines 50, simultaneously providing the first signal line 20 and the data signal line 50, providing the third signal line 40 alone, and simultaneously providing the second signal line 30 and the data signal line 50. That is, only one signal line is provided at the position where the third signal line 40 with the largest width is located, and the two signal lines with the smallest width and the middle width can be provided at the positions where the remaining signal lines are located. Based on the above routing layout design, the routing occupied space can be reduced, the structure is simple, the layout is reasonable, the layout space is fully utilized, the space utilization rate is improved, and it is beneficial to improving the resolution.

[0150] In an alternative embodiment, the pixel unit further includes a sub-pixel driving circuit electrically connected to the light-emitting device of each sub-pixel, such as Figure 3 , Figure 4 and Figure 5 shown. The sub-pixel driving circuit in the embodiment of the present invention is a 3T1C circuit. The sub-pixel driving circuit 70 includes a first transistor 71, a second transistor 72, a third transistor 73, and a storage capacitor 74.

[0151] Wherein, as Figure 5 shown, the first signal line 20 is electrically connected to the second electrode 76 of the light-emitting device;

[0152] The second signal line 30 is electrically connected to the first transistor 71,

[0153] The third signal line 40 is electrically connected to the third transistor 73,

[0154] The data signal line 50 is electrically connected to the second transistor 72.

[0155] In an alternative embodiment, the connection manners of the various devices of the sub-pixel driving circuit 70 are as follows:

[0156] The first transistor 71 includes a first control electrode 711, a first pole 71D, a second pole 71S, and a first active layer 712. The first drain region 712D of the first active layer 712 is connected to the first pole 71D. The first source region 712S of the first active layer 712 is connected to the second pole 71S. The first channel region 7121 of the first active layer 712 is connected to the first source region 712S and the first drain region 712D. The first pole 71D is electrically connected to the second signal line 30;

[0157] The second transistor 72 includes a second control electrode 721, a third pole 72D, a fourth pole 72S, and a second active layer 722. The second drain region 722D of the second active layer 722 is connected to the third pole 72D. The second source region 722S of the second active layer 722 is connected to the fourth pole 72S. The second channel region 7221 of the second active layer 722 is connected to the second source region 722S and the second drain region 722D. The third pole 72D is electrically connected to the data signal line 50;

[0158] The third transistor 73 includes a third control electrode 731, a fifth pole 73D, a sixth pole 73S, and a third active layer 732. The third drain region 732D of the third active layer 732 is connected to the fifth pole 73D. The third source region 732S of the third active layer 732 is connected to the sixth pole 73S. The third channel region 7321 of the third active layer 732 is connected to the third source region 732S and the third drain region 732D. The fifth pole 73D is electrically connected to the third signal line 40.

[0159] Both the second control electrode 721 and the third control electrode 731 are electrically connected to the scan signal line 60. In this way, the number of scan signal lines 60 can be reduced, the layout space for routing can be saved, and the resolution of the 3D display panel can be improved.

[0160] The second pole 71S, the sixth pole 73S, and the first electrode 75 of the light-emitting device are connected to the first electrode plate 74S of the storage capacitor 74.

[0161] The fourth pole 72S and the first control electrode 711 are connected to the second electrode plate 74G of the storage capacitor 74.

[0162] In the embodiment of the present invention, as Figure 7 shown, the storage capacitor 74 includes a plurality of capacitive conductive layers (741 - 743) located in different layers. The orthographic projections of the respective capacitive conductive layers (741 - 743) on the substrate 10 have overlapping projections, which can increase the capacitance of the storage capacitor 74. Exemplarily, the first capacitive conductive layer 741 closest to the substrate 10 among the plurality of capacitive conductive layers (741 - 743) is the second electrode plate 74G. The third capacitive conductive layer 743 farthest from the substrate 10 among the plurality of capacitive conductive layers (741 - 743) is the first electrode plate 74S. The film layer located between the first capacitive conductive layer 741 and the third capacitive conductive layer 743 is the second capacitive conductive layer 742.

[0163] Exemplarily, the first transistor 71, the second transistor 72, and the third transistor 73 are top-gate thin-film transistors. More specifically, each transistor is a metal-oxide thin-film transistor.

[0164] It can be understood that the sub-pixel driving circuit 70 of the embodiment of the present invention may further include other transistors or capacitors to enable the sub-pixel driving circuit 70 to have better driving performance. For example, the sub-pixel driving circuit 70 can be 7T1C (7 thin-film transistors and one storage capacitor 74), 8T1C (8 thin-film transistors and one storage capacitor 74), or a sub-pixel driving circuit 70 with other architectures. Again, for example, the sub-pixel driving circuit 70 further includes a detection transistor to provide a more stable driving signal for the sub-pixel driving circuit 70.

[0165] In an alternative embodiment, as Figure 1 and Figure 2 shown, the 3D display panel further includes a scan signal line 60 extending in a first direction, and a positive projection of the scan signal line 60 on the substrate 10 and positive projections of the first signal line 20, the second signal line 30, the third signal line 40, and the data signal line 50 on the substrate 10 at least partially overlap.

[0166] In an embodiment of the present invention, the scan signal line 60 extending horizontally and the first signal line 20, the second signal line 30, the third signal line 40, and the data signal line 50 extending vertically have overlapping projections. The metal layers of the scan signal line 60 and the first signal line 20, the second signal line 30, the third signal line 40, and the data signal line 50 are arranged in different layers, ensuring the transmission stability of horizontal and vertical signals. In the 3D display panel provided by the embodiment of the present invention, considering the 3D display effect and the limited routing layout design, the routing between multiple sub-pixels in a pixel unit PIX is arranged, which can maximize the transparent area and realize a 3D display product with high transparency and high uniformity.

[0167] In an alternative embodiment, each of the scan signal lines 60 is used to provide a control signal to the sub-pixel driving circuit 70 arranged in the first direction to perform timing control on the sub-pixel driving circuit 70. Based on the sub-pixel driving circuit 70 in the embodiment of the present invention, the scan signal line 60 is electrically connected to the second control electrode 721 of the second transistor 72 and the third control electrode 731 of the third transistor 73, and a positive projection of the scan signal line 60 on the substrate 10 and positive projections of the second active layer 722 of the second transistor 72 and the third active layer 732 of the third transistor 73 on the substrate 10 at least partially overlap.

[0168] In an alternative embodiment, as Figure 2 , Figure 4 and Figure 5 shown, the scan signal line 60 includes an alternating first transmission portion 61 and second transmission portion 62,

[0169] The positive projection of the first transmission portion 61 on the substrate 10 and positive projections of at least one of the first signal line 20, the second signal line 30, the third signal line 40, and the data signal line 50 on the substrate 10 partially overlap.

[0170] As Figure 5 shown, the positive projection of the second transmission portion 62 on the substrate 10 and the second channel region 7221 of the second active layer 722 and the third channel region 7321 of the third active layer 732 at least one positive projection on the substrate 10 partially overlap,

[0171] As Figure 5 shown, the width of the first transmission portion 61 in the second direction is a first width D1, the width of the second transmission portion 62 in the second direction is a second width D2, and the first width D1 is greater than the second width D2.

[0172] In this embodiment, the scanning signal lines 60 at different positions are locally thickened. The first width D1 is greater than the second width D2, that is, the line width of the scanning signal lines 60 is thickened at the overlapping projection positions of the scanning signal lines 60 with the first signal lines 20, the second signal lines 30, and the third signal lines 40. Through this setting, the resistance value of the scanning signal lines 60 can be reduced, preventing the scanning signal from being unable to be accurately transmitted to the last column and ensuring the 3D display effect of the 3D display panel.

[0173] In an alternative embodiment, as Figure 2 、 Figure 4 and Figure 5 shown, at least one of the first transmission portions 61 includes a hollow portion 613. The first transmission portion 61 includes a first scanning portion 611 and a second scanning portion 612 that are opposite and parallel to each other, and the hollow portion 613 is located between the first scanning portion 611 and the second scanning portion 612.

[0174] In this embodiment, since parasitic capacitance will be generated after the first width D1 of the scanning signal lines 60 is thickened, therefore, as Figure 2 、 Figure 4 and Figure 5 shown, at the overlapping projection positions formed by the scanning signal lines 60 with the first signal lines 20, the second signal lines 30, and the third signal lines 40, the first transmission portion 61 at the overlapping projection positions is hollowed out to form a hollow portion 613 disposed between the first scanning portion 611 and the second scanning portion 612. Through this setting, the parasitic capacitance between the scanning signal lines 60 and the first signal lines 20, the second signal lines 30, and the third signal lines 40 can be reduced, ensuring the accurate transmission of the scanning signal to the last column and guaranteeing the 3D display effect of the 3D display panel.

[0175] Based on the design of dividing the scanning signal lines 60 into parallel first scanning portion 611 and second scanning portion 612 in the above embodiments of the present invention, when a penetration short circuit occurs at this position and it is detected that a short circuit occurs at one of the positions of the first scanning portion 611 or the second scanning portion 612, during the detection and repair stage, the first scanning portion 611 or the second scanning portion 612 at the defective position can be burned out by laser, and then the normal second scanning portion 612 or the first scanning portion 611 on the other side is used as the signal transmission trace to form a double insurance structure, thereby improving the yield of the 3D display panel.

[0176] In an alternative embodiment, as Figure 1 and Figure 2 shown, the 3D display panel further includes a first connection line 21 disposed within each pixel unit PIX, and each of the first connection lines 21 is electrically connected to each of the third signal lines 40. As Figure 1 and Figure 2 shown, the third signal line 40 is a vertically disposed trace, and in this embodiment, the first connection line 21 disposed horizontally is used to supply a sensing signal from one third signal line 40 to M sub-pixels.

[0177] In an embodiment of the present invention, a first via hole 21H is formed at an overlapping position of the orthographic projection of each of the first connection lines 21 on the substrate 10 and the orthographic projection of each corresponding third signal line 40 on the substrate 10. The third signal line 40 and the first connection line 21 are located on different layers, and the first via hole 21H is used to achieve cross-layer signal transmission and reduce the complexity of traces on the same layer.

[0178] As Figure 1 and Figure 2 shown, the first connection line 21 includes a first sub-connection line 211 and a second sub-connection line 212.

[0179] Exemplarily, as Figure 2 shown, a first via hole 21H is formed at an overlapping position of the orthographic projection of the first sub-connection line 211 and the seventh sub-signal line 407 on the substrate 10, and the first via hole 21H is used to achieve cross-layer electrical connection between the first sub-connection line 211 and the seventh sub-signal line 407. In this embodiment, the first sub-connection line 211 extends from the first sub-pixel to the Mth sub-pixel (P 1 ~P 6 ) in the first direction, so as to connect the first sub-pixel to the Mth sub-pixel (P 1 ~P 6 ) to the same seventh sub-signal line 407.

[0180] Exemplarily, as Figure 1 shown, a first via hole 21H is formed at an overlapping position of the orthographic projection of the second sub-connection line 212 and the eighth sub-signal line 408 on the substrate 10, and the first via hole 21H is used to achieve cross-layer electrical connection between the second sub-connection line 212 and the eighth sub-signal line 408. In this embodiment, the second sub-connection line 212 extends from the (M + 1)th sub-pixel to the Kth sub-pixel (P 7 ~P 12 ) in the first direction, so as to connect the (M + 1)th sub-pixel to the Kth sub-pixel (P 7 ~P 12 ) to the same eighth sub-signal line 408.

[0181] In an alternative embodiment, as Figure 2 shown, the 3D display panel further includes a second connection line 31 and a third connection line 34.

[0182] In this embodiment, the second connection line 31 extends in the first direction. A second via hole 31H2 is provided at an overlapping position between the orthographic projection of the second connection line 31 on the substrate 10 and the orthographic projection of all the second signal lines 30 arranged in the first direction on the substrate 10, so as to realize the electrical connection between the second connection line 31 and all the second signal lines 30.

[0183] As Figure 1 shown, second via holes 31H2 are provided at overlapping positions between the orthographic projection of the second connection line 31 and the fourth sub-signal line 304 on the substrate 10, between the orthographic projection of the second connection line 31 and the fifth sub-signal line 305 on the substrate 10, and between the orthographic projection of the second connection line 31 and the sixth sub-signal line 306 on the substrate 10, so that the fourth sub-signal line 304, the fifth sub-signal line 305, and the sixth sub-signal line 306 all provide stable second voltage signals.

[0184] In this embodiment, the third connection line 34 corresponds to each sub-pixel. One end of each third connection line 34 is connected to the first pole 71D of the first transistor 71, and the other end of each third connection line 34 is connected to the second connection line 31. Fifth via holes 31H5 are provided at a plurality of overlapping positions between the orthographic projection of the second connection line 31 on the substrate 10 and the orthographic projection of each third connection line 34 on the substrate, so as to form a stable transmission circuit for the second voltage signal.

[0185] As Figure 1 shown, 12 sub-pixels (P 1 ~P 12 ) are provided in one pixel unit PIX. Each sub-pixel is provided with a third connection line 34 extending in the second direction. Then, 12 third connection lines 34 are provided in one pixel unit PIX.

[0186] Based on the above design, in this embodiment, the second connection line 31 is used to connect all the fourth sub-signal lines 304, the fifth sub-signal lines 305, and the sixth sub-signal lines 306 of a plurality of pixel units arranged in the first direction, and is connected to each third connection line 34 corresponding to each sub-pixel, so as to provide a stable second voltage signal for the entire 3D display panel.

[0187] In an alternative embodiment, as Figure 1 , Figure 2 and Figure 4As shown, the orthographic projection of the pixel unit PIX on the substrate 10 includes a light-emitting region AA01 and a transparent region AA02. The light-emitting region AA01 includes the orthographic projections of the first connection line 21 and the second connection line 31 on the substrate 10, and the region between the orthographic projections of the first connection line 21 and the second connection line 31 on the substrate 10. The transparent region AA02 includes the part of the orthographic projection of the pixel unit PIX on the substrate 10 that is outside the light-emitting region AA02.

[0188] In this embodiment, the first end of the light-emitting region AA01 corresponds to the orthographic projection of the first connection line 21 on the substrate 10, and the second end of the light-emitting region AA01 and the first end of the transparent region AA02 correspond to the orthographic projection of the second connection line 31 on the substrate 10.

[0189] In this embodiment, the second end of the transparent region AA02 corresponds to the orthographic projection of the pixel unit PIX away from the first connection line 21 on the substrate 10. The scan signal line 60, the first transistor 71, the second transistor 72, the third transistor 73, and the storage capacitor 74 are disposed in the orthographic projection of the light-emitting region AA01 on the substrate 10.

[0190] In an embodiment of the present invention, in each sub-pixel, the second connection line 31 divides each pixel unit PIX into a light-emitting region AA01 and a transparent region AA02. The region formed between the first connection line 21 and the second connection line 31 is the light-emitting region AA01. Each driving device of the sub-pixel driving circuit 70 is disposed at the light-emitting region AA01, and the light-emitting region AA01 is used as the opening of the pixel unit PIX. No driving device is disposed in the transparent region AA02. Through this setting, the aperture ratio can be maximized, the concentration of the transparent region AA02 can be ensured, the transparent area can be maximized, and both the 3D display effect of the 3D display panel and the transparent effect can be ensured.

[0191] The uniformity of the 3D display panel is related to the voltage drop (IR Drop) of the first signal line 20 and the second signal line 30. Figure 6 shows Figure 1 A schematic diagram of the layer structure of various signal lines at the cross-sectional position BB shown. At this cross-sectional position, from left to right, it includes the first sub-signal line 201 of the first signal line 20, sub-pixel P 1 , sub-pixel P 1 corresponding data signal line 50, sub-pixel P 2 corresponding data signal line 50, sub-pixel P 2 , and the fourth sub-signal line 304 of the second signal line 30.

[0192] In an alternative embodiment, as Figure 6As shown, the first signal line 20 includes:

[0193] A first trace 22 located on the substrate 10; and

[0194] A second trace 23 located on a side of the first trace 22 away from the substrate 10;

[0195] The 3D display panel includes at least one first via 23H that connects the first trace 22 and the second trace 23.

[0196] It should be noted that Figure 6 shows a schematic layer structure when the first signal line 20 is the first sub-signal line 201. The second sub-signal line 202 and the third sub-signal line 203 of the first signal line 20 are based on the same principle and are also of a double-layer structure. The first via 23H is used to connect the first trace 22 and the second trace 23, and the first signal line 20 forms a structure of parallel double-row traces, thereby reducing the voltage drop of the first signal line 20.

[0197] Based on the same principle, in an alternative embodiment, Figure 7 shows Figure 1 a schematic layer structure at the position of the cross-section CC shown. The second signal line 30 includes:

[0198] A third trace 32 located on the substrate 10; and

[0199] A fourth trace 33 located on a side of the third trace 32 away from the substrate 10;

[0200] The 3D display panel includes at least one second via 33H that connects the third trace 32 and the fourth trace 33.

[0201] Figure 7 shows a schematic layer structure when the second signal line 30 is the fourth sub-signal line 304 and the first signal line 20 is the second sub-signal line 202. The second sub-signal line 202 is also of a double-layer structure.

[0202] Based on the same principle, the fourth sub-signal line 304, the fifth sub-signal line 305, and the sixth sub-signal line 306 of the second signal line 30 can also be of a double-layer structure. In the embodiment of the present invention, the second via 33H is used to connect the third trace 32 and the fourth trace 33, and the second signal line 30 forms a structure of parallel double-row traces, thereby reducing the voltage drop of the second signal line 30.

[0203] The display uniformity of the 3D display panel is also related to the third signal line 40. During the driving process of the 3D display panel, if the power supply voltage of the first signal line 20 cannot drop to the vicinity of the driving voltage of the third signal line 40 in time during the charging stage, then during the light-emitting stage, the driving voltage difference between the power supply voltage of the first signal line 20 and the data signal line 50 becomes smaller, which will cause the driving current of the sub-pixel driving circuit 70 to decrease, resulting in poor uniformity of the 3D display panel. To improve this phenomenon, it can be improved by reducing the capacitive load of the third signal line 40 and increasing the width of the third signal line 40. However, in the related art, it is difficult to reduce the capacitive width of the third signal line 40, and increasing the width of the third signal line 40 will have a greater impact on the routing layout and reduce the transmittance of the 3D display panel.

[0204] Figure 7 shows Figure 1 a schematic diagram of the layer structure of various signal lines at the position of the cross-section CC shown, at this cross-section position, from left to right, it includes the fourth sub-signal line 304, the 3rd data signal line 50, the sub-pixel P 3 , the seventh sub-signal line 407, the sub-pixel P 4 , the 4th data signal line 50, and the second sub-signal line 202.

[0205] In an optional embodiment of the present invention, as Figure 7 shown, the third signal line 40 includes:

[0206] a fifth trace 41 located on the substrate 10; and

[0207] a sixth trace 42 located on the side of the fifth trace 41 away from the substrate 10;

[0208] The 3D display panel includes at least one third via hole 42H, and the third via hole 42H connects the fifth trace 41 and the sixth trace 42.

[0209] In the embodiment of the present invention, under the cross-section shown as Figure 7 shown, the embodiment of the present invention uses the third via hole 42H to connect the fifth trace 41 and the sixth trace 42, and the third signal line 40 forms a structure of double-row traces in parallel, thereby reducing the voltage drop of the third signal line 40 and achieving the purpose of improving the uniformity of the 3D display panel.

[0210] As Figure 6 and Figure 7 shown, the number of the first via holes 23H in the width direction (in the first direction) of the first signal line 20 in the embodiment of the present invention is at least one, and the number in the length direction (the second direction) of the first signal line 20 is multiple, so as to perform wire merging and further reduce the occupied area of the signal traces.

[0211] Based on the same principle, the number of the second vias 33H in the width direction (in the first direction) of the second signal line 30 is at least one, and the number of the second vias 33H in the length direction (the second direction) of the second signal line 30 is multiple; the number of the third vias 42H in the width direction (in the first direction) of the third signal line 40 is at least one, and the number of the third vias 42H in the length direction (the second direction) of the third signal line 40 is multiple, so as to reduce the occupied area of the signal traces, and improve the aperture ratio and the transparent area AA02 of the 3D display panel.

[0212] Based on the double-layer arrangement design of the first signal line 20, the second signal line 30, and the third signal line 40 in the above embodiments of the present invention, insulation between the first trace 22 and the second trace 23, between the third trace 32 and the fourth trace 33, and between the fifth trace 41 and the sixth trace 42 is achieved through the interlayer dielectric layer 806 in the process.

[0213] In the manufacturing process, the first trace 22, the third trace 32, and the fifth trace 41 can be arranged on the same layer by the same process, the second trace 23, the fourth trace 33, and the sixth trace 42 are arranged on the same layer, and the first via 23H, the second via 33H, and the third via 42H are formed by the same process, thereby improving the manufacturing efficiency of the 3D display panel.

[0214] As Figure 6 and Figure 7 shown, a storage capacitor 74 is provided at each position corresponding to a sub-pixel. The storage capacitor 74 includes a plurality of capacitor conductive layers, such as a first-layer capacitor conductive layer 741 provided on the substrate 10, a second-layer capacitor conductive layer 742 provided on the buffer layer 802, and a third-layer capacitor conductive layer 743 provided on the interlayer dielectric layer 806. Exemplarily, the second-layer capacitor conductive layer 742 and the first trace 22 in this embodiment can be arranged on the same layer, and the third-layer capacitor conductive layer 743 and the second trace 23 can also be arranged on the same layer, thereby improving the manufacturing efficiency of the 3D display panel.

[0215] Figure 8 shows a schematic diagram of the 3D display panel according to the embodiment of the present invention Figure 1 under the DD cross-section in the 3D display panel. As Figure 8 shown, the layer structure at this position includes:

[0216] An occlusion layer 801 provided on the substrate 10, and the orthographic projection of the occlusion layer 801 on the substrate 10 covers the orthographic projection of the third transistor 73 on the substrate 10, so as to play a role in shielding and protecting the third transistor 73;

[0217] A buffer layer 802 provided on the occlusion layer 801;

[0218] The active material layers 803 of the respective transistors disposed on the side of the buffer layer 802 away from the substrate 10, and the active material layer 803 is used to form a first active layer 712, a second active layer 722, and a third active layer 732;

[0219] The gate insulating layer 804 disposed on the surface of the active material layer 803 away from the substrate 10;

[0220] The control electrode material layer 805 disposed on the side of the gate insulating layer 804 away from the substrate 10, and the control electrode material layer 805 is used to form a first control electrode 711, a second control electrode 721, and a third control electrode 731;

[0221] The interlayer dielectric layer 806 covering the control electrode material layer 805, and the thickness of the interlayer dielectric layer 806 is greater than the total thickness of the active material layer 803, the gate insulating layer 804, and the control electrode material layer 805;

[0222] The electrode conductive layer 807 disposed on the interlayer dielectric layer 806, and the electrode conductive layer includes material layers of a first pole 71D and a second pole 71S of the first transistor 71, material layers of a third pole 72D and a fourth pole 72S of the second transistor 72, and material layers of a fifth pole 73D and a sixth pole 73S of the third transistor 73;

[0223] The passivation layer 808 disposed on the side of the electrode conductive layer 807 away from the substrate 10;

[0224] The second interlayer insulating layer 809 disposed on the side of the passivation layer 808 away from the substrate 10;

[0225] The first electrode 75 of the light-emitting device disposed on the side of the second interlayer insulating layer 809 away from the substrate 10;

[0226] The pixel defining layer 811 disposed on the side of the first electrode 75 away from the substrate 10, and the pixel defining layer 811 is provided with a plurality of sub-pixel openings arranged in an array;

[0227] The light-emitting functional layer 812 of the light-emitting device disposed in the sub-pixel opening and on the side of the pixel defining layer 811 away from the substrate 10;

[0228] The second electrode 76 of the light-emitting device covering the side of the light-emitting functional layer 812 away from the substrate 10. Exemplarily, the first electrode 75 of the light-emitting device is an anode, and the second electrode 76 of the light-emitting device is a cathode.

[0229] For the 3D display panel according to the embodiments of the present invention, the layer structures at different positions can be formed simultaneously. Exemplarily, the shielding layer 801 is disposed in the same layer as the first connection line 21, the second connection line 31, and the first layer capacitor conductive layer 741 of the storage capacitor 74.

[0230] The control electrode material layer 805 is disposed in the same layer as the scan signal line 60, the first trace 22, the third trace 32, the fifth trace 41, and the second layer capacitor conductive layer 742 of the storage capacitor 74.

[0231] The electrode conductive layer 807 is disposed in the same layer as the second trace 23, the fourth trace 33, the sixth trace 42, and the third layer capacitor conductive layer 743 of the storage capacitor 74. The above-mentioned respective film layers can be formed by the same process to improve the process efficiency.

[0232] Taking a 95-inch 2K, single-end IC-driven product as an example, the 3D display panel adopting the layout design of the above 3D display panel can achieve the following parameters: resolution 1920*1080, screen ratio 16:9, 23PPI, 30% aperture ratio, transparency nearly 70%, single-gate drive, refresh rate 60Hz, pixel size 1089um*1089um, a sub-pixel size 99um*363um, and the uniformity effect of the full-panel simulation is good. As shown in Table 1, the simulation results of the current uniformity at the nine-point positions of the 3D display panel are as follows. The current value uniformity at each point is above 90%, and it has a good display effect.

[0233] Table 1

[0234]

[0235] Another embodiment of the present invention provides a method for manufacturing the 3D display panel of the above embodiment. The method includes:

[0236] Forming a plurality of pixel units PIX arranged in an array on the substrate 10, and each pixel unit PIX includes K sub-pixels extending in the first direction;

[0237] Forming on the substrate 10 a first signal line 20 extending in a second direction perpendicular to the first direction where each first signal line 20 is located on the same side of all the sub-pixels in N sub-pixels;

[0238] Forming K data signal lines 50 extending in the second direction on the substrate 10, and each data signal line 50 corresponds to each sub-pixel one by one.

[0239] Now, taking the formation of the embodiments of the present invention Figures 1 to 8The 3D display panel of the illustrated embodiment is taken as an example, and the layout of each film layer in the manufacturing process is described by way of example:

[0240] As Figure 9 shown, a first connection line 21, a second connection line 31, and a first conductive layer 91 of the shielding layer 801 are formed on the substrate 10. As Figure 9 and Figure 15 shown in 9a, in this embodiment, the first connection line 21 and the second connection line 31 extend along the first direction, and the region formed by the first connection line 21 and the second connection line 31 adjacent in the second direction corresponds to the light-emitting region AA01. The shielding layer 801 corresponding to each sub-pixel is formed within the light-emitting region AA01 of each sub-pixel.

[0241] In this embodiment, as Figure 9 shown, the shielding layer 801 can also serve as the first capacitive conductive layer 741 of the storage capacitor 74.

[0242] In this embodiment, a pixel unit PIX corresponds to multiple first connection lines 21. For example, in this embodiment, 12 sub-pixels correspond to Figure 1 the two first connection lines 21 (the first sub-connection line 211 and the second sub-connection line 212) shown. Each first connection line 21 electrically connects 6 sub-pixels to one third signal line 40 formed in a subsequent process.

[0243] All pixel units PIX adjacent in the first direction correspond to one second connection line 31. That is, one second connection line 31 connects all sub-pixels of multiple pixel units PIX. For example, if 1080 pixel units PIX are arranged horizontally, then the second connection line 31 can connect 1080 * 12 sub-pixels.

[0244] In one example, as Figure 9 shown, the first conductive layer 91 further includes a connection pad 911 for electrically connecting the second transistor 72 and the data signal line 50 in a subsequent process.

[0245] Further, as Figure 15 shown in 9a, a buffer layer 802 is formed on the first conductive layer 91.

[0246] Further, as Figure 10 and Figure 15As shown by 10a, an active material layer 803 of each transistor (the first transistor 71, the second transistor 72, and the third transistor 73) is formed on the buffer layer 802. In this embodiment, the orthographic projection of the first active layer 712 of the entire first transistor 71 falls within the orthographic projection of the first layer of capacitive conductive layer 741, that is, the orthographic projections of the first drain region 712D, the first channel region 7121, and the first source region 712S of the first active layer 712 all fall within the orthographic projection of the first layer of capacitive conductive layer 741. For the second active layer 722 of the second transistor 72, the orthographic projections of the second drain region 722D, the second channel region 7221, and the second source region 722S of the second active layer 722 do not overlap with the orthographic projection of the first connection line 21 on the substrate 10, wherein the orthographic projection of the second drain region 722D at least partially overlaps with the orthographic projection of the connection pad 911 on the substrate 10.

[0247] For the third active layer 732 of the third transistor 73, the orthographic projection of the third drain region 732D at least partially overlaps with the orthographic projection of the raised end portion of the first connection line 21, the orthographic projection of the third source region 732S forms an overlap with the orthographic projection of the first layer of capacitive conductive layer 741 of the storage capacitor 74, and the orthographic projections of the third channel region 7321 do not overlap with the orthographic projection of the raised end portion of the first connection line 21 and the orthographic projection of the first layer of capacitive conductive layer 741 of the storage capacitor 74.

[0248] Furthermore, as Figure 15 shown by 11a, a gate insulating layer 804 is formed on the active material layer 803.

[0249] Furthermore, as Figure 12 and Figure 15 shown by 11a, a first via process is performed on the buffer layer 802 to form buffer layer vias 802H.

[0250] In this embodiment, the buffer layer vias 802H include a first transfer hole 21H, a second transfer hole 31H2, a third transfer hole H03, a fourth transfer hole H04, and a fifth transfer hole 31H5. The buffer layer vias 802H penetrate through the buffer layer 802 and expose the first conductive layer 91.

[0251] Among them, as Figure 12 shown, the first transfer hole 21H is provided within the width region of the first connection line 21 corresponding to the fifth trace 41 in the first direction;

[0252] The second transfer hole 31H2 is provided at the position corresponding to each sub-pixel of the second connection line 31;

[0253] The fifth transfer hole 31H5 is provided within the width region of the second connection line 31 corresponding to all the third traces 32 in the first direction;

[0254] The third connection hole H03 is disposed at a non-overlapping position between the protruding end of the first connection line 21 and the orthographic projection of the third active layer 732, and is disposed at a non-overlapping position between the first layer capacitor conductive layer 741 and the orthographic projection of the third active layer 732;

[0255] The fourth connection hole H04 is disposed at a non-overlapping position between the connection pad 911 and the second active layer 722 corresponding to the third pole 72D region.

[0256] Further, as shown in Figure 11 and Figure 15 12a in, a second conductive layer 92 is formed on the gate insulating layer 804 and on the buffer layer 802. The second conductive layer 92 includes: the control electrode material layers 805 of the respective transistors (the first transistor 71, the second transistor 72, the third transistor 73), the scan signal line 60, the first trace 22 of the first signal line 20, the third trace 32 of the second signal line 30, the fifth trace 41 of the third signal line 40, and the material layers of the respective film layers such as the second layer capacitor conductive layer 742 of the storage capacitor 74, etc.

[0257] Further, as shown in Figure 15 12a in, an interlayer dielectric layer 806 is formed on a side of the second conductive layer 92 away from the substrate 10.

[0258] Further, as shown in Figure 13 and Figure 15 13a of, a second via process is performed on the interlayer dielectric layer 806 to form a dielectric layer via 806H.

[0259] In this embodiment, the dielectric layer via 806H includes:

[0260] The first via hole 23H, and the first via hole 23 is disposed at an overlapping position between the first trace 22 and the second trace 23 in the orthographic projection of the substrate 10;

[0261] The second via hole 33H, and the second via hole 33H is disposed at an overlapping position between the third trace 32 and the fourth trace 33 in the orthographic projection of the substrate 10;

[0262] The third via hole 42H, and the second via hole 33H is disposed at an overlapping position between the fifth trace 41 and the sixth trace 42 in the orthographic projection of the substrate 10;

[0263] The first set of holes TK42 is disposed at a position corresponding to the first connection hole 21H. Exemplarily, the orthographic projection of the first stepped hole TK42 on the substrate 10 falls within the orthographic projection of the first connection hole 21H on the substrate 10;

[0264] The second set of holes TK33 is disposed at a position corresponding to the second transfer hole 31H2. Exemplarily, the orthographic projection of the second set of holes TK33 on the substrate 10 falls within the orthographic projection of the second transfer hole 31H2 on the substrate 10;

[0265] The third set of holes TK23 is disposed at a position corresponding to the fifth transfer hole 31H5. Exemplarily, the orthographic projection of the third set of holes TK23 on the substrate 10 falls within the orthographic projection of the second transfer hole 31H2 on the substrate 10;

[0266] The first electrode connection hole DH1 is disposed at the position of the orthographic projection on the substrate of the first drain region 712D and the first source region 712S of the first active layer 712 of the first transistor 71:

[0267] The second electrode connection hole DH2 is disposed at the position of the orthographic projection on the substrate 10 of the second source region 722S of the second active layer of the second transistor T2;

[0268] The third electrode connection hole DH3 is disposed at the position of the orthographic projection on the substrate 10 of the protruding end of the second capacitor conductive layer 742 on the side close to the second source region 722S;

[0269] The fourth electrode connection hole DH4 is disposed at a position corresponding to the fourth transfer hole H04. The fourth electrode connection hole DH4 and the fourth transfer hole H04 have an overlapping projection on the substrate 10, and the fourth electrode connection hole DH4 and the second drain region 722D have an overlapping projection on the substrate;

[0270] The fifth electrode connection holes DH5 are respectively disposed at positions corresponding to the third transfer hole H03. One of the fifth electrode connection holes DH5 and the third drain region 732D of the third active layer 732 of the third transistor 73 have an overlapping projection on the substrate 10, and the other fifth electrode connection hole DH5 and the third source region 732S of the third active layer 732 of the third transistor 73 have an overlapping projection on the substrate 10.

[0271] The dielectric layer vias 806H formed by the above process are used for subsequent process cross-layer transfer and electrical connection of the sub-pixel driving circuit.

[0272] Further, as Figure 14 and Figure 15As shown in 14a, a third conductive layer 93 is formed on the surface of the interlayer dielectric layer 806 away from the substrate 10. Exemplarily, the third conductive layer 93 is the material layer of the second trace 23, the fourth trace 33, the sixth trace 42, the electrode conductive layers 807 of each transistor, the data signal line 50, the third connection line 34, and the third layer capacitor conductive layer 743 of the storage capacitor 74. The conductive film layers of each device or trace can be formed simultaneously in this process. The conductive film layers of each device or trace are transferred across layers through vias at corresponding positions to reduce the space occupied by the traces and improve the process efficiency.

[0273] As Figure 14 shown, the electrode conductive layers 807 of each transistor include the material layers of the first pole 71D and the second pole 71S, the material layers of the third pole 72D and the fourth pole 72S, and the material layers of the fifth pole 73D and the sixth pole 73S.

[0274] Further, as Figure 15 shown in Figure 14 a, a passivation layer 808 is formed on the surface of the third conductive layer 93 away from the substrate 10.

[0275] On Figure 14 the basis of the layout shown, a passivation layer 808 is further formed on the side of the electrode conductive layer 807 away from the substrate 10; a second interlayer insulating layer 809 is formed on the side of the passivation layer 808 away from the substrate 10; a first electrode 75 is formed on the side of the second interlayer insulating layer 809 away from the substrate 10; a pixel defining layer 811 with a plurality of sub-pixel openings is formed on the side of the first electrode 75 away from the substrate 10, and a light-emitting functional layer 812 of the light-emitting device is formed inside the pixel opening and on the surface of the pixel defining layer 811 away from the substrate 10; and a second electrode 76 is formed on the side of the light-emitting functional layer 812 away from the substrate 10, forming a layer structure as Figure 8 shown.

[0276] Based on the above steps, the pixel layout structure of the embodiment shown in the present invention Figure 1 is formed. The manufacturing method of the 3D display panel of the embodiment of the present invention does not add complex process steps. Through the layout design of sub-pixels, each signal line and device, and the arrangement of each signal line, the area of the transparent region AA02 is maximized to achieve high-transparency 3D display.

[0277] Another embodiment of the present invention proposes a 3D display device, and the 3D display device includes the 3D display panel of the above embodiment of the present invention. The 3D display device can be any product or component with a display function, such as a liquid crystal display panel, an electronic paper, a mobile phone, a tablet computer, a television, a monitor, a notebook computer, a digital photo frame, a navigator, etc.

[0278] It should be noted that for the specific embodiments of the method for manufacturing the 3D display panel according to the embodiments of the present invention, reference may be made to the 3D display panel in the foregoing embodiments, which will not be elaborated herein.

[0279] In the description of the present invention, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprising", "including" or any other variant thereof are intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising a..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0280] Obviously, the above embodiments of the present invention are merely examples for clearly illustrating the present invention, rather than limitations on the implementation manners of the present invention. For those of ordinary skill in the art, other different forms of changes or modifications can be made on the basis of the above description. It is impossible to enumerate all the implementation manners here. Any obvious changes or modifications derived from the technical solutions of the present invention still fall within the protection scope of the present invention.

Claims

1. A 3D display panel, characterized in that: The 3D display panel comprises: substrate; A plurality of pixel units arranged in an array on the substrate, at least one of the pixel units comprising K sub-pixels arranged along a first direction; Arranged along the first direction first signal lines, each of the first signal lines extending along a second direction perpendicular to the first direction, and each of the first signal lines being located on a same side of N adjacent sub-pixels; K data signal lines are arranged along the first direction, each of the data signal lines extends along the second direction, and each of the data signal lines corresponds to each sub-pixel one by one.

2. The 3D display panel according to claim 1, characterized in that: In a pixel unit, Located in and The first axis parallel to the second direction in the gap between the sub-pixels is the symmetry axis, and the first to the second sub-pixels are The data signal line corresponding to the sub-pixel and the The data signal lines corresponding to the kth to kth sub-pixels are symmetrical about the first axis; Located in and The second axis parallel to the second direction in the gap between the sub-pixels is the symmetry axis, and the first to the second sub-pixels are The data signal line corresponding to the sub-pixel and the ~ The data signal lines corresponding to the sub-pixels are symmetrical about the second axis; The data signal lines corresponding to two sub-pixels between the adjacent first signal line and the second signal line are symmetrically arranged with a third axis parallel to the second direction at a middle position of the two sub-pixels as a symmetry axis.

3. The 3D display panel according to claim 1, characterized in that: Each of the first signal lines comprises: A first sub-signal line, providing a first voltage signal to the first to Nth sub-pixels of the pixel unit, wherein the first sub-signal line is located on the left side of the first sub-pixel; a second sub-signal line, providing a first voltage signal to the (N+1)th to 2Nth sub-pixels of the pixel unit, wherein the second sub-signal line is located on the left side of the (N+1)th sub-pixel; The third sub-signal line provides a first voltage signal to the (2N+1)th to Kth sub-pixels of the pixel unit, and the third sub-signal line is located on the left side of the (2N+1)th sub-pixel.

4. The 3D display panel according to claim 3, characterized in that: The 3D display panel further includes second signal lines, each of which extends along the second direction, and the second signal lines include: The fourth sub-signal line provides a second voltage signal to the first to Nth sub-pixels of the pixel unit, and the fourth sub-signal line is located at the sub-pixels and Between sub-pixels; The fifth sub-signal line provides a second voltage signal to the (N+1)th to 2Nth sub-pixels of the pixel unit. The fifth sub-signal line is located at the sub-pixels and Between sub-pixels; The sixth sub-signal line provides a second voltage signal to the (2N+1)th to Kth sub-pixels of the pixel unit. The sixth sub-signal line is located between the (2N+1)th sub-pixel and the (2N+1)th sub-pixel. between sub-pixels.

5. The 3D display panel according to claim 4, characterized in that: The 3D display panel further includes third signal lines, M>N, each of the third signal lines extending along the second direction, and the third signal lines comprising: The seventh sub-signal line provides sensing signals to the first to Mth sub-pixels of the pixel unit, and is located at the sub-pixels and Between sub-pixels; The eighth sub-signal line provides sensing signals to the (M+1)th to Kth sub-pixels of the pixel unit, and is located at the sub-pixels and between sub-pixels.

6. The 3D display panel according to claim 5, characterized in that: The pixel unit further includes a sub-pixel driving circuit electrically connected to the light-emitting device of each sub-pixel, and each sub-pixel driving circuit at least includes a first transistor, a second transistor, a third transistor and a storage capacitor. Wherein, the first signal line is electrically connected to the second electrode of the light emitting device; The second signal line is electrically connected to the first transistor, The third signal line is electrically connected to the third transistor, The data signal line is electrically connected to the second transistor.

7. The 3D display panel according to claim 6, characterized in that: The first transistor includes a first control electrode, a first electrode, a second electrode and a first active layer, one end of the first active layer is connected to the first electrode, and the other end of the first active layer is connected to the second electrode; The second transistor comprises a second control electrode, a third electrode, a fourth electrode and a second active layer, one end of the second active layer is connected to the third electrode, and the other end of the second active layer is connected to the fourth electrode; The third transistor comprises a third control electrode, a fifth electrode, a sixth electrode and a third active layer, one end of the third active layer is connected to the fifth electrode, and the other end of the third active layer is connected to the sixth electrode; The second signal line is electrically connected to the first electrode, The third signal line is electrically connected to the fifth electrode, The data signal line is electrically connected to the third electrode, The second electrode, the sixth electrode, and the first electrode are connected to a first electrode plate of a storage capacitor; The fourth electrode and the first control electrode are connected to the second electrode plate of the storage capacitor.

8. The 3D display panel according to claim 7, characterized in that: The 3D display panel further includes: scanning signal lines extending along the first direction, each of the scanning signal lines is used to provide a control signal to the sub-pixel driving circuits arranged in the first direction, and the scanning signal lines are electrically connected to the second control electrode and the third control electrode, The orthographic projection of the scanning signal line on the substrate at least partially overlaps with the orthographic projection of the second channel region of the second active layer and the orthographic projection of the third channel region of the third active layer on the substrate. The orthographic projection of the scanning signal line on the substrate at least partially overlaps with the orthographic projection of the first signal line, the second signal line, the third signal line and the data signal line on the substrate.

9. The 3D display panel according to claim 8, characterized in that: The scanning signal line includes a first transmission part and a second transmission part which are alternately arranged. The orthographic projection of the first transmission portion on the substrate overlaps with the orthographic projection of at least one of the first signal line, the second signal line, the third signal line and the data signal line on the substrate. The orthographic projection of the second transmission portion on the substrate partially overlaps with the orthographic projection of at least one of the second transistor and the third transistor on the substrate, The width of the first transmission portion in the second direction is a first width, the width of the second transmission portion in the second direction is a second width, and the first width is greater than the second width.

10. The 3D display panel according to claim 9, characterized in that: At least one of the first transmission parts includes a hollow portion, the first transmission part includes a first scanning part and a second scanning part which are arranged opposite to and in parallel, and the hollow portion is located between the first scanning part and the second scanning part.

11. The 3D display panel according to claim 5, characterized in that: The 3D display panel further includes: Set in each pixel unit A first connecting line is electrically connected to a third signal line, and a first transfer hole is provided at an overlapping position of the orthographic projection of the first connecting line on the substrate and the orthographic projection of the corresponding third signal line on the substrate.

12. The 3D display panel according to claim 11, characterized in that: The 3D display panel further includes: A second connecting line extending along the first direction, wherein a second transfer hole is provided at an overlapping position of the orthographic projection of the substrate between the second connecting line and all the second signal lines arranged in the first direction; and A third connection line corresponding to each sub-pixel, one end of each of the third connection lines is connected to the first electrode of the first transistor, and the other end is connected to the second connection line, The second connecting line and each third connecting line are provided with fifth transfer holes at a plurality of overlapping positions of the orthographic projection of the substrate.

13. The 3D display panel according to claim 12, characterized in that: The orthographic projection of the pixel unit on the substrate includes a light-emitting area and a transparent area. The light emitting area includes the orthographic projections of the first connecting line and the second connecting line on the substrate, and an area between the orthographic projections of the first connecting line and the second connecting line on the substrate, The transparent area includes a portion of the pixel unit located outside the light emitting area in an orthographic projection of the substrate.

14. The 3D display panel according to claim 5, characterized in that: The width of the first signal line in the first direction is greater than the width of the data signal line in the first direction, The first signal line comprises: a first trace located on the substrate; and a second routing line located at a side of the first routing line away from the substrate; The 3D display panel includes at least one first conductive via, and the first wiring and the second wiring are connected through the first conductive via.

15. The 3D display panel according to claim 14, characterized in that: The width of the second signal line in the first direction is greater than the width of the data signal line in the first direction, The second signal line includes: a third routing line located on the substrate; and a fourth routing line located on a side of the third routing line away from the substrate; The 3D display panel includes at least one second conductive via, and the third wiring and the fourth wiring are connected through the second conductive via.

16. The 3D display panel according to claim 15, characterized in that: The width of the third signal line in the first direction is greater than the width of the first signal line in the first direction, or greater than the width of the second signal line in the first direction, The third signal line includes: a fifth trace located on the substrate; and a sixth routing line located on a side of the third routing line away from the substrate; The 3D display panel includes at least one third conductive via, and the fifth wiring and the sixth wiring are connected through the third conductive via.

17. The 3D display panel according to claim 16, characterized in that: The first routing line, the third routing line, and the fifth routing line are arranged on the same layer. The second routing line, the fourth routing line, and the sixth routing line are arranged in the same layer, and the first conductive via hole, the second conductive via hole, and the third conductive via hole are formed by the same process.

18. A method for manufacturing the 3D display panel according to any one of claims 1 to 17, characterized in that: The method comprises: Forming a plurality of pixel units arranged in an array on a substrate, each of the pixel units comprising K sub-pixels extending along a first direction; A second direction extending in a second direction perpendicular to the first direction is formed on the substrate. first signal lines, each of the first signal lines being located on a same side of all the N sub-pixels; K data signal lines are extended on the substrate along the second direction, and each of the data signal lines corresponds to each sub-pixel one by one.

19. A 3D display device, characterized in that: The 3D display device comprises the 3D display panel according to any one of claims 1 to 17.

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