Method and device for processing FPGA (Field Programmable Gate Array) engineering file

Abstract

The invention relates to the field of computers, in particular to an FPGA engineering file processing method and device. The method comprises the steps of obtaining a to-be-tested project file package; the to-be-tested project file package comprises a plurality of FPGA project files; determining a top-layer file from the plurality of FPGA engineering files; obtaining a corresponding relationship between the keywords in the target keyword set and the configuration information in the top-layer file; wherein the target keyword set comprises a plurality of keywords; each keyword in the plurality of keywords corresponds to one of three file types; the three file types comprise an IP core file, a constraint file and a handwritten file; and determining file types respectively corresponding to the plurality of FPGA engineering files according to a corresponding relationship between the keywords in the target keyword set and the configuration information in the top-layer file and a corresponding relationship between the configuration information in the top-layer file and the FPGA engineering files.

Description

Technical Field

[0001] This application relates to the field of computers, and in particular, to a method and device for processing FPGA project files. Background Art

[0002] A Field-Programmable Gate Array (FPGA) is a commonly used programmable logic device.

[0003] In the prior art, each time FPGA software testing is performed, usually testers need to manually classify multiple FPGA project files included in the FPGA software to select Intellectual Property (IP) core files, constraint files, and handwritten files included in the multiple FPGA project files, and then the subsequent testing process can be carried out. This seriously affects the testing efficiency.

[0004] Therefore, how to avoid the low testing efficiency caused by manually classifying FPGA project files is a problem that needs to be solved currently. Summary of the Invention

[0005] To solve the above technical problems, this application provides a method and device for processing FPGA project files.

[0006] In a first aspect, this application provides a method for processing FPGA project files, the method includes: obtaining a to-be-tested project file package; the to-be-tested project file package includes multiple FPGA project files; determining a top-level file of the to-be-tested project file package from the multiple FPGA project files; the top-level file includes multiple pieces of configuration information; obtaining a correspondence between keywords in a target keyword set and the configuration information in the top-level file by identifying keywords in the target keyword set in the top-level file; where the target keyword set includes multiple keywords; each keyword in the multiple keywords respectively corresponds to one of three file types; the three file types include: IP core files, constraint files, and handwritten files; determining the file types corresponding to the multiple FPGA project files respectively according to the correspondence between keywords in the target keyword set and the configuration information in the top-level file, and the correspondence between the configuration information in the top-level file and the FPGA project files.

[0007] In some implementations, determining the top-level file of the to-be-tested project file package from the multiple FPGA project files includes: determining a target search rule corresponding to the target FPGA development tool from a preset rule library according to the target FPGA development tool corresponding to the to-be-tested project file package; the preset rule library includes search rules respectively corresponding to multiple FPGA development tools; each of the search rules is respectively used to indicate at least one of the position of the top-level file in the project file package or the naming rule of the top-level file; determining the top-level file corresponding to the to-be-tested project file package from the multiple FPGA project files according to the target search rule.

[0008] In some implementations, the determining the top-level file corresponding to the to-be-tested project file package from the multiple FPGA project files according to the target search rule includes: determining multiple candidate files that conform to the target search rule from the multiple FPGA project files; displaying a candidate interface; the candidate interface is used to display the multiple candidate files and prompt the user to select a top-level file from the multiple candidate files; in response to a first user operation of selecting a candidate file from the candidate interface, determining the top-level file corresponding to the to-be-tested project file package.

[0009] In some implementations, the method further includes: determining a target keyword set from a preset keyword library according to the target FPGA development tool corresponding to the to-be-tested project file package; the preset keyword library includes keyword sets respectively corresponding to multiple FPGA development tools, and the keywords in each keyword set respectively correspond to one of the three file types.

[0010] In some implementations, obtaining the to-be-tested project file package includes: displaying a device-under-test management interface; the device-under-test management interface includes: a first interaction area for inputting an FPGA device under test, and a second interaction area for inputting the name of the FPGA software project; obtaining a target FPGA device under test according to a second user operation on the first interaction area; determining a target project name according to a third user operation on the second interaction area; determining the to-be-tested project file package whose file name corresponds to the target project name from the target FPGA device under test.

[0011] In some implementations, the method further includes: displaying a file list; the file list includes: the multiple FPGA project files and the file types respectively corresponding to the multiple FPGA project files.

[0012] In some implementations, the method further includes: storing the multiple FPGA project files in a database according to the file types respectively corresponding to the multiple FPGA project files.

[0013] In a second aspect, the present application provides an FPGA test management device, including: an acquisition unit, configured to acquire an engineering file package to be tested; the engineering file package to be tested includes a plurality of FPGA engineering files; a processing unit, configured to determine a top-level file of the engineering file package to be tested from the plurality of FPGA engineering files; the top-level file includes a plurality of configuration information; the processing unit is further configured to obtain a correspondence between the keywords in the target keyword set and the configuration information in the top-level file by identifying the configuration information in the top-level file that matches the keywords in the target keyword set; wherein, the target keyword set includes a plurality of keywords; each keyword in the plurality of keywords respectively corresponds to one of three file types; the three file types include: IP core files, constraint files, and handwritten files; the processing unit is further configured to determine the file types corresponding to the plurality of FPGA engineering files respectively according to the correspondence between the keywords in the target keyword set and the configuration information in the top-level file, and the correspondence between the configuration information in the top-level file and the FPGA engineering files.

[0014] In some implementation manners, the processing unit is configured to determine a top-level file of the engineering file package to be tested from the plurality of FPGA engineering files, including: the processing unit is configured to determine a target search rule corresponding to the target FPGA development tool from a preset rule library according to the target FPGA development tool corresponding to the engineering file package to be tested; the preset rule library includes: search rules respectively corresponding to various FPGA development tools; each of the search rules is respectively used to indicate at least one of: the location of the top-level file in the engineering file package or the naming rule of the top-level file; the processing unit is configured to determine the top-level file corresponding to the engineering file package to be tested from the plurality of FPGA engineering files according to the target search rule.

[0015] In some implementation manners, the processing unit is configured to determine a top-level file corresponding to the engineering file package to be tested from the plurality of FPGA engineering files according to the target search rule, including: the processing unit is configured to determine a plurality of candidate files that meet the target search rule from the plurality of FPGA engineering files; the processing unit is configured to display a candidate interface; the candidate interface is used to display the plurality of candidate files and prompt the user to select a top-level file from the plurality of candidate files; the processing unit is configured to determine the top-level file corresponding to the engineering file package to be tested in response to a first user operation of selecting a candidate file from the candidate interface.

[0016] In some implementations, the processing unit is further configured to determine the target keyword set from a preset keyword library according to the target FPGA development tool corresponding to the engineering file package to be tested; the preset keyword library includes: keyword sets corresponding to multiple FPGA development tools respectively, and the keywords in each keyword set respectively correspond to one of the three file types.

[0017] In some implementations, the acquisition unit is configured to acquire an engineering file package to be tested, including: the acquisition unit is configured to display a device under test management interface; the device under test management interface includes: a first interaction area for inputting an FPGA device under test, and a second interaction area for inputting an FPGA software engineering name; the acquisition unit is configured to acquire a target FPGA device under test according to a second user operation on the first interaction area; the acquisition unit is configured to determine a target project name according to a third user operation on the second interaction area; the acquisition unit is configured to determine the engineering file package to be tested whose file name corresponds to the target project name from the target FPGA device under test.

[0018] In some implementations, the processing unit is further configured to display a file list; the file list includes: the multiple FPGA engineering files and the file types corresponding to the multiple FPGA engineering files respectively.

[0019] In some implementations, the processing unit is further configured to store the multiple FPGA engineering files in a database according to the file types corresponding to the multiple FPGA engineering files respectively.

[0020] In a third aspect, there is provided an FPGA test management device, including: a memory and a processor, the memory is configured to store a computer program, and the processor is configured to, when executing the computer program, enable the FPGA test management device to implement the method according to the first aspect or any implementation manner in the first aspect.

[0021] In a fourth aspect, there is provided a computer-readable storage medium, on which a computer program is stored, and when the computer program is executed by a computing device, the computing device is enabled to implement the method according to the first aspect or any implementation manner in the first aspect.

[0022] In a fifth aspect, there is provided a computer program product, and when the computer program product runs on a computer, the computer is enabled to implement the method according to the first aspect or any implementation manner in the first aspect.

[0023] The technical solution provided by the embodiments of the present application has the following advantages compared with the prior art: In the embodiments of the present application, it is considered that: in the FGPA engineering file, the top-level file, as the main file of the entire FPGA design, is mainly responsible for integrating each sub-module, defining the interface between the entire design and the outside, and describing the connection relationship between each sub-module. Therefore, the top-level file usually includes many configuration information items for the FPGA engineering file. Among them, the configuration information corresponding to different types of FPGA engineering files often includes specific keywords. For example, if a certain configuration information item includes the keyword "IPcore", it can usually be determined that the engineering file corresponding to this configuration information is an IP core file. Another example is that in the top-level file of the FPGA software developed using the Libero development tool, if a certain configuration information item includes the keyword "valuehdl", it can usually be determined that the engineering file corresponding to this configuration information is a handwritten file. Based on the above rules, the embodiments of the present application consider that: the corresponding relationship between the keywords carried by the configuration information in the top-level file and the file type can be summarized, so as to construct a keyword set (hereinafter referred to as the "target keyword set"), and the target keyword set can include: multiple keywords, and each keyword in the multiple keywords respectively corresponds to one of the three file types (i.e., IP core file, constraint file, and handwritten file). In this way, when it is necessary to classify multiple FPGA engineering files included in the engineering file package to be tested, after obtaining the engineering file package to be tested, the top-level file can be determined from the multiple FPGA engineering files first; the top-level file includes multiple configuration information items; and then, by identifying the keywords in the target keyword set in the top-level file, the corresponding relationship between the keywords and the configuration information can be obtained; furthermore, according to the above corresponding relationship and the corresponding relationship between the configuration information and the FPGA engineering file, the file type corresponding to each FPGA engineering file can be determined. In this way, the problem of low test efficiency caused by manual classification of FPGA engineering files can be avoided. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The accompanying drawings herein are incorporated into the specification and form a part of the specification, showing embodiments consistent with the present application and, together with the specification, are used to explain the principles of the present application.

[0025] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the accompanying drawings required for use in the description of the embodiments or the prior art. Obviously, for those of ordinary skill in the art, other drawings can also be obtained based on these drawings without creative efforts.

[0026] Figure 1 One of the methods for processing FPGA engineering files provided by the embodiments of the present application; Figure 2 Another method for processing FPGA engineering files provided by the embodiments of the present application; Figure 3 One of the interface schematic diagrams provided by the embodiments of the present application; Figure 4 The third method for processing an FPGA project file provided by the embodiments of the present application; Figure 5 One of the interface schematic diagrams provided by the embodiments of the present application; Figure 6 The fourth method for processing an FPGA project file provided by the embodiments of the present application; Figure 7 The fifth method for processing an FPGA project file provided by the embodiments of the present application; Figure 8 The sixth method for processing an FPGA project file provided by the embodiments of the present application; Figure 9 One of the structural schematic diagrams of an FPGA test management device provided by the embodiments of the present application; Figure 10 One of the structural schematic diagrams of an FPGA test management device provided by the embodiments of the present application. Detailed implementation manners

[0027] In order to more clearly understand the above objects, features, and advantages of the present application, the solutions of the present application will be further described below. It should be noted that, without conflict, the embodiments of the present application and the features in the embodiments may be combined with each other.

[0028] Many specific details are set forth in the following description in order to fully understand the present application, but the present application may also be implemented in other ways different from those described herein; obviously, the embodiments in the specification are only a part of the embodiments of the present application, rather than all the embodiments.

[0029] First, the related technologies involved in the embodiments of the present application are introduced: A field-programmable gate array (FPGA) is a commonly used programmable logic device, which is widely used in digital circuit design and embedded system development. An FPGA development tool is a set of software tools for designing, implementing, and verifying FPGA circuits. There are currently multiple mainstream FPGA development tools on the market, such as ISE, Vivado, Libero, and Quartus II.

[0030] During the FPGA development process, a large number of FPGA project files are involved. Among them, FPGA project files can specifically include code files written using hardware description languages (such as Very High Speed Integrated Circuit Hardware Description Language (VHDL), or Verilog Hardware Description Language (Verilog HDL), etc.). According to different contents, FPGA project files can be divided into Intellectual Property (IP) core files, constraint files, and handwritten files.

[0031] In the prior art, during each FPGA software test, testers usually need to manually classify multiple FPGA project files included in the FPGA software to select the IP core files, constraint files, and handwritten files included in the multiple FPGA project files, and then the subsequent test process can be carried out. This seriously affects the test efficiency. Further, with different development environments, the structures and naming rules of different types of FPGA project files will also be different, which further increases the difficulty of classifying FPGA project files.

[0032] The following introduces the technical solutions provided in the embodiments of the present application in combination with examples: In view of the above technical problems, in the embodiments of the present application, it is first considered that if the FPGA project files can be automatically classified by software or hardware means, the speed and accuracy of classifying FPGA project files can be improved, and thus the efficiency of FPGA software testing can be improved.

[0033] Further, in the embodiments of the present application, it is considered that in FGPA project files, the top-level file, as the main file of the entire FPGA design, is mainly responsible for integrating each sub-module, defining the interface between the entire design and the outside, and describing the connection relationships between sub-modules. Therefore, the top-level file usually includes a lot of configuration information for FPGA project files. Among them, the configuration information corresponding to different types of FPGA project files often includes specific keywords. For example, if a certain piece of configuration information includes the keyword "IPcore", it can usually be determined that the project file corresponding to this configuration information is an IP core file. For another example, in the top-level file of FPGA software developed using the Libero development tool, if a certain piece of configuration information includes the keyword "value hdl", it can usually be determined that the project file corresponding to this configuration information is a handwritten file.

[0034] Based on the above rules, the embodiments of the present application consider that: the correspondence between the keywords carried in the configuration information in the top-level file and the file types can be summarized, so as to construct a keyword set (hereinafter referred to as the "target keyword set"), and the target keyword set may include: multiple keywords, and each of the multiple keywords corresponds to one of three file types (i.e., IP core file, constraint file, and handwritten file). In this way, when classifying multiple FPGA project files included in the project file package to be tested, as Figure 1 shown, after obtaining the project file package to be tested (i.e., S101), the top-level file can be determined from multiple FPGA project files (i.e., S102), and the top-level file includes multiple pieces of configuration information; then, by identifying the keywords in the target keyword set in the top-level file, the correspondence between the keywords and the configuration information can be obtained (i.e., S103); furthermore, according to the above correspondence and the correspondence between the configuration information and the FPGA project files, the file type corresponding to each FPGA project file can be determined (i.e., S104). In this way, the problem of low test efficiency caused by manual classification of FPGA project files can be avoided.

[0035] Next, a specific example is used to introduce in detail the technical solution provided by the embodiments of the present application. Specifically, the embodiments of the present application provide a method for processing FPGA project files. Among them, the execution subject of the method for processing FPGA project files can be an FPGA test management device. When the FPGA test management device runs, it can be used to execute all or part of the steps in the method for processing FPGA project files provided by the embodiments of the present application. Among them, in the actual application process, the functions of the FPGA test management device can be implemented by electronic devices such as personal computers (including desktop computers, laptop computers, handheld computers, and notebook computers), or smartphones, servers, etc.; alternatively, the functions of the above FPGA test management device can also be implemented by some hardware / software devices in the above electronic devices. The embodiments of the present application do not impose special restrictions on the specific form of the FPGA test management device.

[0036] As Figure 1 shown, the method for processing FPGA project files provided by the embodiments of the present application may include: S101. The FPGA test management device obtains a project file package to be tested.

[0037] Among them, the project file to be tested may include multiple FPGA project files. Among them, the multiple FPGA project files may include: IP core files, constraint files, and handwritten files.

[0038] In the actual application process, the engineering file package to be tested can specifically be an engineering file compression package including multiple FPGA engineering files.

[0039] In one implementation, considering that: in the actual application process, among the devices under test that need to be tested, there may not only be the engineering file package to be tested, but also other technical documents. In order to more quickly locate the engineering file package to be tested including multiple FPGA engineering files in the device under test, in this method, as Figure 2 shown, S101 can specifically include: S1011. The FPGA test management device displays a device-under-test management interface.

[0040] Among them, the device-under-test management interface includes: a first interaction area for inputting the FPGA device under test, and a second interaction area for inputting the FPGA software engineering name.

[0041] S1012. The FPGA test management device obtains the target FPGA device under test according to the second user operation on the first interaction area.

[0042] S1013. The FPGA test management device determines the target project name according to the third user operation on the second interaction area.

[0043] Exemplarily, in the device-under-test management interface 20 as Figure 3 shown, there is a control 201 named "Select Device Under Test". By clicking on this control 201 by the user, the input of the device under test can be realized. At this time, the control 201 can be understood as the above-mentioned first interaction area. In addition, in the device-under-test management interface 20, there is also an input box 202 named "FPGA Software Engineering Name". By the user operation of inputting text into this input box 202, the input of the FPGA software engineering name can be realized. At this time, the input box 202 can be understood as the above-mentioned second interaction area.

[0044] Among them, on the one hand, after receiving the user operation for inputting the device under test on the control 201 (i.e., the second user operation), the FPGA test management device can obtain the target FPGA device under test.

[0045] On the other hand, after receiving the user operation for inputting the FPGA software engineering name on the input box 202 (i.e., the third user operation), the FPGA test management device can determine the FPGA software engineering name (i.e., the target project name) included in the target FPGA device under test.

[0046] S1014. The FPGA test management device determines the engineering file package to be tested whose file name corresponds to the target project name from the target FPGA device under test.

[0047] For example, the FPGA test management device can use the target project name to screen the file packages included in the target FPGA under test, so as to obtain the project file package to be tested whose file name corresponds to the target project name.

[0048] S102. The FPGA test management device determines the top-level file of the project file package from multiple FPGA project files.

[0049] Among them, the top-level file includes multiple configuration information. Among them, each piece of configuration information corresponds to the FPGA project file in the project file package to be tested.

[0050] In some implementation manners, as Figure 4 shown, S102 may specifically include: S1021. The FPGA test management device determines the target search rule corresponding to the target FPGA development tool from the preset rule library according to the target FPGA development tool corresponding to the project file package to be tested.

[0051] Among them, the preset rule library includes: search rules corresponding to various FPGA development tools. Each search rule is respectively used to indicate at least one of the position of the top-level file in the project file package or the naming rule of the top-level file.

[0052] For example, in some FPGA development tools, the storage position of the top-level file in the project file package is preset, then the search rule corresponding to this FPGA development tool includes: the position of the top-level file in the project file package. For another example, in some FPGA development tools, the naming method of the top-level file is preset, then the search rule corresponding to this FPGA development tool includes: the naming rule of the top-level file.

[0053] S1022. The FPGA test management device determines the top-level file corresponding to the project file package to be tested from multiple FPGA project files according to the target search rule.

[0054] For example, the FPGA test management device can determine the file that conforms to the target search rule from multiple FPGA project files according to the target search rule, and use this file as the top-level file corresponding to the project file package to be tested.

[0055] In the above implementation manner of the embodiment of the present application, it is considered that: in an engineering file package, the position of the top-level file in the engineering file package and the naming of the top-level file have corresponding rules. Moreover, for the FPGA project files corresponding to different FPGA development tools, the position of the top-level file in the engineering file package and the naming rules are different. Therefore, the position of the top-level file in the engineering file package and the naming rules can be summarized in advance to construct a rule library (hereinafter referred to as a preset rule library). In this preset rule library, it can include: search rules corresponding to various FPGA development tools respectively. Each search rule is respectively used to indicate at least one of the position of the top-level file in the engineering file package or the naming rule of the top-level file. Furthermore, when it is necessary to determine the top-level file of the engineering file package to be tested, the effect of quickly and accurately determining the top-level file can be achieved by first determining the target search rule corresponding to the target FPGA development tool of the engineering file package to be tested from the preset rule library, and then determining the top-level file corresponding to the engineering file package to be tested from multiple FPGA project files according to the target search rule.

[0056] Further, in some designs, S1022 may specifically include: S1022a. The FPGA test management device determines multiple candidate files that meet the target search rule from multiple FPGA project files.

[0057] S1022b. The FPGA test management device displays a candidate interface.

[0058] Among them, the candidate interface is used to display multiple candidate files and prompt the user to select the top-level file from the multiple candidate files.

[0059] S1022c. The FPGA test management device determines the top-level file corresponding to the engineering file package to be tested in response to a first user operation of selecting a candidate file from the candidate interface.

[0060] Exemplarily, as Figure 5 shown, in the candidate interface 30, there are three candidate files with serial numbers "①", "②", and "③" respectively, and the display of the candidate interface 303 can prompt the user to select the top-level file from the multiple candidate files. After receiving the user's tick operation on the checkbox 304 and click operation on the control 305 (i.e., the first user operation), the FPGA test management device can determine that the candidate file with the serial number "①" is the top-level file corresponding to the engineering file package to be tested.

[0061] In the above design, it is considered that: when multiple candidate files in multiple FPGA project files meet the target search rules, the FPGA test management device may make a misjudgment. Therefore, in this design, when the FPGA test management device determines multiple candidate files that meet the target search rules, it can display the corresponding candidate interface to enable the user to decide which candidate file is the top-level file, thus avoiding misjudgment.

[0062] S103. The FPGA test management device obtains the correspondence between the keyword and the configuration information by identifying the keyword in the target keyword set in the top-level file.

[0063] Exemplarily, in some development tools (such as the VIVAVO development tool), when a certain configuration information in the top-level file includes "<FileSet" and "constrs_1", the project file corresponding to this configuration information is a constraint file. Therefore, the target keyword set may include the keywords "<FileSet" and "constrs_1". Furthermore, the FPGA test management device can identify the keywords in the target keyword set in the multiple configuration information included in the top-level file, so as to obtain the configuration information A corresponding to the keywords "<FileSet" and "constrs_1". At this time, it can be understood that: the correspondence between the keyword and the configuration information obtained in S103 includes: the correspondence between the keywords "<FileSet" and "constrs_1" and the configuration information A.

[0064] It can be understood that, as used in the embodiments of the present application, the correspondence between the keyword and the configuration information may specifically include: the configuration information includes the keyword. In addition, the correspondence between the keyword and the configuration information may specifically further include: the configuration information does not include the keyword. That is to say, in the actual application process, the keywords in the target keyword set can implement the function of a whitelist, that is, when a certain configuration information includes this keyword, it is determined that there is a correspondence between this keyword and this configuration information; in addition, the keywords in the target keyword set can also implement the function of a blacklist, that is, when a certain configuration information does not include this keyword, it is determined that there is a correspondence between this keyword and this configuration information.

[0065] S104. The FPGA test management device determines the file types corresponding to multiple FPGA project files according to the correspondence between the keywords in the target keyword set and the configuration information in the top-level file, and the correspondence between the configuration information in the top-level file and the FPGA project files.

[0066] Continuing with the above example, when the correspondence between the keywords obtained in S103 and the configuration information includes the correspondence between the keywords "<FileSet" and "constrs_1" and the configuration information A, if the configuration information A corresponds to the FPGA project file B (that is, in the correspondence between the configuration information in the top-level file and the FPGA project file, it includes the correspondence between the configuration information A and the FPGA project file B), then the FPGA project file B is determined to be the constraint file.

[0067] In some implementation manners, such as Figure 6 shown, before executing S103, the method may further include: S105. The FPGA test management device determines a target keyword set from a preset keyword library according to the target FPGA development tool corresponding to the project file package to be tested.

[0068] Among them, the preset keyword library includes keyword sets respectively corresponding to multiple FPGA development tools, and the keywords in each keyword set respectively correspond to one of the above three file types.

[0069] In the above implementation manner of the embodiment of the present application, considering that different keywords correspond to different FPGA development tools, a preset keyword library can be constructed in advance. The preset keyword library includes keyword sets respectively corresponding to each FPGA development tool, so that when determining the file type of the FPGA project file in the FPGA project file package, the target keyword set (that is, the keyword set corresponding to the target FPGA development tool corresponding to the current project file package to be tested) can be determined from the preset keyword library first, and then the subsequent steps can be executed using the target keyword set. In this way, the range of the keyword library can be narrowed, thereby improving the screening speed and accuracy.

[0070] In some implementation manners, after determining the file types respectively corresponding to multiple FPGA project files, such as Figure 7 shown, the method may further include: S106. The FPGA test management device displays a file list.

[0071] Among them, the file list includes multiple FPGA project files and the file types respectively corresponding to the multiple FPGA project files.

[0072] Exemplarily, as Figure 5 shown, it includes a file list 306, and the file list 306 includes multiple FPGA project files and the file types respectively corresponding to the multiple FPGA project files.

[0073] After the FPGA test management device determines the file types corresponding to multiple FPGA project files through the above implementation methods, the classification results can also be displayed in the interface by showing a file list, so that users can view the classification results.

[0074] In some implementation methods, such as Figure 8 shown, the method may further include: S107. The FPGA test management device stores multiple FPGA project files in a database according to the file types corresponding to the multiple FPGA project files.

[0075] For example, the FPGA test management device can store FPGA project files of different file types in different file directories in the database according to the file types corresponding to the multiple FPGA project files, so as to perform subsequent software test tasks. For another example, the FPGA test management device can, when storing multiple FPGA project files in the database according to the file types corresponding to the multiple FPGA project files, store the file type identifier (used to identify the file type corresponding to the FPGA project file) of each FPGA project file in the database together, so that when reading the FPGA project file, the file type corresponding to the FPGA project file can be determined according to the file type identifier corresponding to the FPGA project file.

[0076] Based on the same inventive concept, as an implementation of the above method, an embodiment of the present application further provides an FPGA test management device. This embodiment corresponds to the foregoing method embodiment. For the convenience of reading, the details in the foregoing method embodiment will not be repeated one by one in this embodiment. However, it should be clear that the FPGA test management device in this embodiment can correspondingly implement all the contents in the foregoing method embodiment.

[0077] An embodiment of the present application provides an FPGA test management device, Figure 9 which is a schematic structural diagram of the FPGA test management device. As Figure 9 shown, the FPGA test management device 40 includes: An acquisition unit 401, configured to acquire a project file package to be tested; the project file package to be tested includes multiple FPGA project files; A processing unit 402, configured to determine a top-level file of the project file package to be tested from the multiple FPGA project files; the top-level file includes multiple pieces of configuration information; The processing unit 402 is further configured to obtain the correspondence between the keywords in the target keyword set and the configuration information in the top-level file by identifying the configuration information in the top-level file that matches the keywords in the target keyword set; wherein, the target keyword set includes multiple keywords; each keyword in the multiple keywords respectively corresponds to one of three file types; the three file types include: IP core file, constraint file, and handwritten file; The processing unit 402 is further configured to determine the file types corresponding to the multiple FPGA project files respectively according to the correspondence between the keywords in the target keyword set and the configuration information in the top-level file, and the correspondence between the configuration information in the top-level file and the FPGA project file.

[0078] In some implementation manners, the processing unit 402 is configured to determine the top-level file of the to-be-tested project file package from the multiple FPGA project files, including: The processing unit 402 is configured to determine the target search rule corresponding to the target FPGA development tool from a preset rule library according to the target FPGA development tool corresponding to the to-be-tested project file package; the preset rule library includes: search rules corresponding to multiple FPGA development tools respectively; each of the search rules is respectively used to indicate at least one of the position of the top-level file in the project file package or the naming rule of the top-level file; The processing unit 402 is configured to determine the top-level file corresponding to the to-be-tested project file package from the multiple FPGA project files according to the target search rule.

[0079] In some implementation manners, the processing unit 402 is configured to determine the top-level file corresponding to the to-be-tested project file package from the multiple FPGA project files according to the target search rule, including: The processing unit 402 is configured to determine multiple candidate files that conform to the target search rule from the multiple FPGA project files; The processing unit 402 is configured to display a candidate interface; the candidate interface is used to display the multiple candidate files and prompt the user to select a top-level file from the multiple candidate files; The processing unit 402 is configured to determine the top-level file corresponding to the to-be-tested project file package in response to a first user operation of selecting a candidate file from the candidate interface.

[0080] In some implementations, the processing unit 402 is further configured to determine the target keyword set from a preset keyword library according to the target FPGA development tool corresponding to the engineering file package to be tested; the preset keyword library includes: keyword sets respectively corresponding to multiple FPGA development tools, and the keywords in each keyword set respectively correspond to one of the three file types.

[0081] In some implementations, the obtaining unit 401 is configured to obtain an engineering file package to be tested, including: The obtaining unit 401 is configured to display a device under test management interface; the device under test management interface includes: a first interaction area for inputting an FPGA device under test, and a second interaction area for inputting an FPGA software engineering name; The obtaining unit 401 is configured to obtain a target FPGA device under test according to a second user operation on the first interaction area; The obtaining unit 401 is configured to determine a target project name according to a third user operation on the second interaction area; The obtaining unit 401 is configured to determine the engineering file package to be tested whose file name corresponds to the target project name from the target FPGA device under test.

[0082] In some implementations, the processing unit 402 is further configured to display a file list; the file list includes: the multiple FPGA engineering files and the file types respectively corresponding to the multiple FPGA engineering files.

[0083] In some implementations, the processing unit 402 is further configured to store the multiple FPGA engineering files in a database according to the file types respectively corresponding to the multiple FPGA engineering files.

[0084] The FPGA test management device 40 provided by the embodiments of the present application can execute the method provided by any of the above embodiments, and its implementation principle and technical effects are similar, which will not be elaborated here.

[0085] Based on the same inventive concept, the embodiments of the present application further provide an FPGA test management device. Figure 10 As the structural schematic diagram of the FPGA test management device provided by the embodiments of the present application, as Figure 10 shown, the FPGA test management device provided in this embodiment includes: a memory 501 and a processor 502, the memory 501 is used to store a computer program, and the processor 502 is used to execute the method provided by the above embodiment when executing the computer program.

[0086] Based on the same inventive concept, an embodiment of the present application further provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the computing device is enabled to implement the method provided in the above embodiment.

[0087] Based on the same inventive concept, an embodiment of the present application further provides a computer program product. When the computer program product runs on a computer, the computing device is enabled to implement the method provided in the above embodiment.

[0088] Those skilled in the art should understand that the embodiments of the present application can be provided as a method, a system, or a computer program product. Therefore, the present application can adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present application can adopt the form of a computer program product implemented on one or more computer-usable storage media containing computer-usable program code.

[0089] The processor can be a central processing unit (CPU), or can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor, etc.

[0090] The memory may include non-permanent memory in the computer-readable medium, in the form of random access memory (RAM) and / or non-volatile memory, such as read-only memory (ROM) or flash RAM. The memory is an example of a computer-readable medium.

[0091] Computer-readable media include both permanent and non-permanent, removable and non-removable storage media. The storage media can implement information storage by any method or technology, and the information can be computer-readable instructions, data structures, program modules, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technologies, compact disc read-only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette tapes, disk storage or other magnetic storage devices, or any other non-transmission media that can be used to store information accessible by a computing device. As defined herein, computer-readable media do not include transitory media such as modulated data signals and carrier waves.

[0092] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A method for processing FPGA engineering files, characterized in that: The method comprises: Obtain a project file package to be tested; the project file package to be tested includes multiple FPGA project files; Determine the top-level file of the project file package to be tested from the multiple FPGA project files; the top-level file includes multiple configuration information; By identifying keywords in the target keyword set in the top-level file, a correspondence between the keywords in the target keyword set and the configuration information in the top-level file is obtained; wherein the target keyword set includes a plurality of keywords; each keyword in the plurality of keywords corresponds to one of three file types; the three file types include: IP core file, constraint file and handwritten file; The file types corresponding to the multiple FPGA project files are determined according to the correspondence between the keywords in the target keyword set and the configuration information in the top-level file, and the correspondence between the configuration information in the top-level file and the FPGA project file.

2. The method according to claim 1, characterized in that The step of determining the top-level file of the project file package to be tested from the plurality of FPGA project files includes: According to the target FPGA development tool corresponding to the project file package to be tested, determine the target search rule corresponding to the target FPGA development tool from a preset rule library; the preset rule library includes: search rules corresponding to multiple FPGA development tools respectively; each of the search rules is used to indicate: the position of the top-level file in the project file package or at least one of the naming rules of the top-level file; According to the target search rule, a top-level file corresponding to the project file package to be tested is determined from the multiple FPGA project files.

3. The method according to claim 2, characterized in that Determining the top-level file corresponding to the project file package to be tested from the multiple FPGA project files according to the target search rule includes: Determine, from the plurality of FPGA project files, a plurality of candidate files that meet the target search rule; Displaying a candidate interface; the candidate interface is used to display the multiple candidate files and prompt the user to select a top-level file from the multiple candidate files; In response to a first user operation of selecting a candidate file from the candidate interface, a top-level file corresponding to the project file package to be tested is determined.

4. The method according to claim 1, characterized in that The method further comprises: According to the target FPGA development tool corresponding to the project file package to be tested, the target keyword set is determined from a preset keyword library; the preset keyword library includes: keyword sets corresponding to multiple FPGA development tools respectively, and the keywords in each keyword set correspond to one of the three file types respectively.

5. The method according to any one of claims 1 to 4, characterized in that: The step of obtaining the project file package to be tested includes: Displaying a DUT management interface; the DUT management interface includes: a first interactive area for inputting an FPGA DUT, and a second interactive area for inputting an FPGA software project name; Acquire a target FPGA device under test according to a second user operation on the first interactive area; determining a target project name according to a third user operation on the second interactive area; The project file package to be tested corresponding to the name of the target project and having the file name corresponding to the target project name is determined from the target FPGA device under test.

6. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: Display a file list; the file list includes: the multiple FPGA project files and the file types corresponding to the multiple FPGA project files respectively.

7. The method according to any one of claims 1 to 4, characterized in that: The method further comprises: The multiple FPGA project files are stored in a database according to the file types respectively corresponding to the multiple FPGA project files.

8. An FPGA test management device, characterized in that: include: An acquisition unit, used to acquire the file package of the project to be tested; The project file package to be tested includes multiple FPGA project files; A processing unit, used to determine the top-level file of the project file package to be tested from the multiple FPGA project files; The top-level file includes multiple configuration information; The processing unit is further configured to obtain a correspondence between keywords in the target keyword set and the configuration information in the top-level file by identifying configuration information matching keywords in the target keyword set in the top-level file; wherein the target keyword set includes a plurality of keywords; each keyword in the plurality of keywords corresponds to one of three file types; the three file types include: an IP core file, a constraint file, and a handwritten file; The processing unit is also used to determine the file types corresponding to the multiple FPGA project files respectively according to the correspondence between the keywords in the target keyword set and the configuration information in the top-level file, and the correspondence between the configuration information in the top-level file and the FPGA project file.

9. An FPGA test management device, characterized in that: include: A memory and a processor, wherein the memory is used to store a computer program, and the processor is used to enable the FPGA test management device to implement the method described in any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a computing device, the computing device implements the method according to any one of claims 1 to 7.

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