Efficient TM-CFAR implementation method based on FPGA

Abstract

The invention particularly relates to an efficient TM-CFAR implementation method based on an FPGA. The method comprises the following steps: when a CFAR reference unit slides to a current position, determining a current reference unit corresponding to a current detection unit; wherein the current reference unit comprises a first shift-in sample positioned on a left reference unit, a second shift-in sample positioned on a right reference unit, and an original sample; comparing each sample in the current reference unit with the first shift-in sample and the second shift-in sample to obtain a corresponding comparison result of the current reference unit; based on the comparison result of the current reference unit, performing data statistics in combination with a stored historical comparison result, and updating a sorting result corresponding to each sample in the current reference unit according to a data statistics result; and according to the sorting result of the parameters in the current reference unit, a target sample is screened by using a preset parameter selection strategy, and a TM CFAR-based clutter power evaluation result corresponding to the current detection unit is calculated by using the target sample.

Description

Technical Field

[0001] The present invention relates to the technical field of radar, and in particular to an efficient implementation method and device of TM-CFAR based on FPGA, a storage medium, a computer program product, and an electronic device. Background Art

[0002] In the related art, in the field of radar signal processing, constant false alarm rate (CFAR) processing is a commonly used signal processing algorithm. Based on different processing methods for reference unit samples, radar target CFAR processing methods can be divided into two types: mean level (ML) CFAR and ordered statistics (OS) CFAR. As a type of ordered statistics CFAR, trimmed mean (TM) CFAR has certain improvement in detection performance under uniform clutter background compared with classical OS-CFAR, and at the same time retains the strong multi-target detection performance of OS-CFAR. Inevitably, TM-CFAR needs to perform sorting operations on the data in the CFAR reference unit during the operation process, so this algorithm has a high computational complexity. However, for TM-CFAR, there is currently a lack of dedicated optimization methods.

[0003] It should be noted that the information disclosed in the above background art section is only used to enhance the understanding of the background of the present invention, and thus may include information that does not constitute the prior art known to those of ordinary skill in the art. Summary of the Invention

[0004] The present invention provides an efficient implementation method and device of TM-CFAR based on FPGA, a storage medium, a computer program product, and an electronic device, which can reduce the computational complexity of the TM-CFAR algorithm in the sorting stage, significantly reduce the occupation of logic resources, and thus can overcome the defects existing in the prior art to a certain extent.

[0005] Other features and advantages of the present invention will become apparent through the following detailed description, or be learned in part through the practice of the present invention.

[0006] According to a first aspect of the present invention, there is provided an efficient implementation method of TM-CFAR based on FPGA, the method including:

[0007] When the CFAR reference unit slides to the current position, determining a current reference unit corresponding to the current detection unit; wherein, the current reference unit includes: a first incoming sample located in the left reference unit, a second incoming sample located in the right reference unit, and an original sample;

[0008] Compare each sample in the current reference unit with the first incoming sample and the second incoming sample respectively to obtain the corresponding comparison result of the current reference unit;

[0009] Based on the comparison result of the current reference unit, perform data statistics in combination with the stored historical comparison results, and update the sorting results corresponding to each sample in the current reference unit according to the data statistics results;

[0010] According to the sorting results of each sample in the current reference unit, use a preset parameter selection strategy to screen target samples, and use the target samples to calculate the clutter power evaluation result of the current detection unit based on TM CFAR.

[0011] In some exemplary embodiments, the comparing each parameter in the current reference unit with the first incoming sample and the second incoming sample respectively to obtain the corresponding comparison result of the current reference unit includes:

[0012] Use the comparators corresponding to each parameter in the reference unit to obtain whether the current parameter is greater than or equal to the comparison results of the first incoming sample and the second incoming sample;

[0013] Save the comparison result to the comparison result register corresponding to the current sample.

[0014] In some exemplary embodiments, the comparator includes an entrance comparator and an exit comparator;

[0015] The method further includes:

[0016] Use the entrance comparator to compare the samples in the reference unit entrance shift register with all the samples in the reference unit shift register, and store the comparison result in the entrance comparison result register; wherein, the reference unit entrance register includes: a left reference unit entrance register for storing the corresponding samples of the left reference unit, and a right reference unit entrance register for storing the corresponding samples of the right reference unit;

[0017] Use the exit comparator to compare the samples in the reference unit exit shift register with all the samples in the reference unit shift register, and store the comparison result in the exit comparison result register; wherein, the reference unit exit shift register includes a left reference unit exit register for storing the samples to be removed and a right reference unit removal register.

[0018] In some exemplary embodiments, the method includes:

[0019] Use a virtual decimal point processor to add virtual decimals to the comparison results output by each comparator.

[0020] In some exemplary embodiments, determining the sorting result corresponding to each sample in the current reference unit according to the data statistics result includes:

[0021] For each sample in the current reference unit, use the corresponding counter to count the number of parameters in the current reference unit that are smaller than the current sample using the incremental statistics method;

[0022] The sorting result of the sample is determined according to the parameter quantity, and the sorting result is stored in the counting result register.

[0023] In some exemplary embodiments, the ranking result is a sequence number of the parameter ranking;

[0024] The method of screening the target sample by using a preset parameter selection strategy according to the sorting result of each sample in the current reference unit includes:

[0025] The decision device is used to determine whether the current sample is to be removed according to the sequence number, and the corresponding decision result is output; wherein the decision result is identified by binary data;

[0026] The target samples to be extracted are determined according to the binary data identifier, and the clutter power evaluation results are calculated using the target samples.

[0027] In some exemplary embodiments, the method comprises:

[0028] The reference unit shift register is used to realize the window sliding of the CFAR reference unit and store the samples corresponding to the current reference unit.

[0029] According to a second aspect of the present invention, there is provided an efficient TM-CFAR implementation device based on FPGA, comprising:

[0030] The data comparison module is used to determine the current reference unit corresponding to the current detection unit when the CFAR reference unit slides to the current position; and compare each sample in the current reference unit with the first input sample and the second input sample respectively to obtain the corresponding current reference unit comparison result; wherein the current reference unit includes: the first input sample located in the left reference unit, the second input sample located in the right reference unit, and the original sample;

[0031] A data statistics module is used to perform data statistics based on the comparison results of the current reference unit and in combination with the stored historical comparison results, and to update the sorting results corresponding to each sample in the current reference unit according to the data statistics results;

[0032] The clutter power estimation module is used to screen the target samples according to the sorting results of the samples in the current reference unit using a preset parameter selection strategy, and calculate the clutter power evaluation result based on TM CFAR corresponding to the current detection unit using the target samples.

[0033] According to a third aspect of the present invention, there is provided a storage medium having stored thereon a computer program, which when executed by a processor, implements the above-mentioned efficient TM-CFAR implementation method based on FPGA.

[0034] According to a fourth aspect of the present invention, there is provided an electronic device, comprising:

[0035] a processor; and

[0036] a memory for storing executable instructions of the processor;

[0037] wherein the processor is configured to implement the above-mentioned efficient TM-CFAR implementation method based on FPGA when executing the executable instructions.

[0038] According to a fifth aspect of the present invention, there is provided a computer program product having stored thereon a computer program, which when executed by a processor, implements the above-mentioned efficient TM-CFAR implementation method based on FPGA.

[0039] In the efficient TM-CFAR implementation method based on FPGA provided by the embodiments of the present invention, when the CFAR reference unit slides to the current position, it is necessary to compare each sample in the reference unit with the first incoming sample and the second incoming sample respectively to obtain the corresponding comparison result of the current reference unit, and then combine the historical comparison results corresponding to the samples not removed in the current reference unit for data statistics, and determine the sorting results corresponding to each sample in the current reference unit according to the data statistics results, and then use a preset parameter selection strategy to screen the target samples, and use the target samples to calculate the clutter power evaluation result corresponding to the current detection unit. By using the comparison results between the old samples, after the CFAR reference unit moves, only the samples newly introduced into the reference unit are compared with the existing samples, which can greatly reduce the computational complexity of the comparison calculation in the sorting process, thereby greatly reducing the computational resource consumption of the CFAR algorithm.

[0040] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0041] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present invention and, together with the specification, are used to explain the principles of the present invention. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can also obtain other drawings based on these drawings without creative efforts.

[0042] Figure 1Schematic diagram showing a schematic of an efficient TM-CFAR implementation method based on FPGA according to an exemplary embodiment of the present invention;

[0043] Figure 2 Schematic diagram showing a schematic of a method flow according to an exemplary embodiment of the present invention;

[0044] Figure 3 Schematic diagram showing a schematic of the system configuration corresponding to an efficient TM-CFAR implementation method based on FPGA according to an exemplary embodiment of the present invention;

[0045] Figure 4 Schematic diagram showing a schematic of virtual decimal processing according to an exemplary embodiment of the present invention;

[0046] Figure 5, including Figures 5a - 5d , Schematic diagram showing a schematic of the process of a data preparation method according to an exemplary embodiment of the present invention;

[0047] Figure 6, including Figures 6a - 6d , Schematic diagram showing a schematic of data comparison at each stage of the operation process of a comparison result register according to an exemplary embodiment of the present invention;

[0048] Figure 7 Schematic diagram showing a schematic of the system flow of the first data processing according to an exemplary embodiment of the present invention;

[0049] Figure 8 Schematic diagram showing a schematic of the system flow of subsequent data processing according to an exemplary embodiment of the present invention;

[0050] Figure 9 Schematic diagram showing a schematic of the method principle of the first data processing based on the incremental statistics method according to an exemplary embodiment of the present invention;

[0051] Figure 10 Schematic diagram showing a schematic of the method principle of subsequent data processing based on the incremental statistics method according to an exemplary embodiment of the present invention;

[0052] Figure 11 Schematic diagram showing a schematic of the cycle timing diagram of the incremental statistics method according to an exemplary embodiment of the present invention;

[0053] Figure 12 Schematic diagram showing a schematic of the system framework of another efficient TM-CFAR implementation method based on FPGA according to an exemplary embodiment of the present invention;

[0054] Figure 13 Schematic diagram showing a schematic of the change of the lookup table resource usage with the number of reference units for different schemes according to an exemplary embodiment of the present invention;

[0055] Figure 14Schematically showing a schematic diagram of the resource usage of a different scheme trigger varying with the number of reference units in an exemplary embodiment of the present invention;

[0056] Figure 15 Schematically showing a schematic diagram of an FPGA-based high-efficiency TM-CFAR implementation device in an exemplary embodiment of the present invention;

[0057] Figure 16 Schematically showing a schematic diagram of the composition of an electronic device in an exemplary embodiment of the present invention. Detailed implementation manners

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this invention will be more complete and comprehensive, and will fully convey the concept of the example embodiments to those skilled in the art. The features, structures, or characteristics described may be combined in any suitable manner in one or more embodiments.

[0059] In addition, the accompanying drawings are only schematic illustrations of the present invention and are not necessarily drawn to scale. The same reference numerals in the figures denote the same or similar parts, and thus their repeated description will be omitted. Some of the block diagrams shown in the drawings are functional entities and do not necessarily correspond to physically or logically independent entities. These functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0060] In the related art, CFAR (Constant False Alarm Rate) refers to a technique that keeps the false alarm rate of target detection constant during the radar target detection process. The basic CFAR algorithm needs to estimate the noise and interference levels within the detected unit, and calculate the decision threshold based on the estimation results. The decision maker determines whether a target exists by comparing the target unit signal with the decision threshold. The classic CFAR algorithms are classified according to the interference level estimation method, and can be divided into Mean Level (ML) CFAR, Ordered Statistics (OS) CFAR, Adaptive CFAR, etc. Among them, the characteristic of the mean CFAR is that the method of taking the mean is adopted in the process of estimating the local interference power. Its advantage is that it has a good detection effect in a uniform clutter background. However, in a multi-target environment and an environment with non-uniform interference targets, since there are interference targets in the reference unit, and these interference targets are wrongly used as noise to participate in the threshold calculation, which in turn raises the detection threshold and finally reduces the detection probability. The mean CFAR has a high detection loss in a multi-target environment and a non-uniform interference environment. Based on this, the existing technology has proposed an Ordered Statistics (OS) CFAR detector. This type of detector significantly reduces the influence of interference targets in the reference unit on the interference level estimation by sorting the target values of the reference unit from small to large and selecting the k-th value to participate in the interference level estimation. The cost of OS CFAR is that its detection performance in a uniform background is lost compared with CA CFAR, especially when k is small. Considering the disadvantages of OS CFAR, the existing technology has proposed a Trimmed-Mean (TM) CFAR algorithm. TM CFAR first sorts the target values of the reference unit, and then removes the smallest r 1 samples and the largest r 2Samples, and then average the remaining samples to estimate the clutter power level. This method retains the good anti-multiple-target interference ability of OS CFAR. At the same time, in a uniform clutter background, the detection loss of TM CFAR is between that of CA CFAR and OS CFAR. The following examples illustrate the resource usage of several classic CFARs. Mean-based CFARs have a relatively low computational complexity as they only need to calculate the mean of the reference cells and are relatively easy to implement. Considering the sliding characteristics of the CFAR reference cells and using the moving average method to calculate the mean, the computational resource usage is O(1). For OS-CFAR, a prior art FPGA-based OS-CFAR implementation method uses the idea of binary accumulation to skip the sorting step of OS-CFAR and directly perform CFAR decision-making, implementing a parallel pipelined OS-CFAR processing method. Assuming this method is used for one-dimensional CFAR processing, the resource usage of this method in the sorting part is O(N). Commonly used fully parallel sorting networks in FPGAs include the odd-even sorting network, the bitonic sorting network, the AKS sorting network, etc. Such sorting networks can achieve fully parallel pipelined sorting, outputting a set of sorted results every clock cycle, and are suitable for use in the TM-CFAR algorithm. For the odd-even sorting network and the bitonic sorting network, their computational resource usage is O(N log 2 N). For the AKS sorting network, its computational resource usage is O(Nlog N). Although the AKS algorithm has the theoretically optimal resource usage, the coefficient of the resource usage depth of this algorithm is very large [5] . In typical CFAR application scenarios, the resource usage of the AKS sorting network is not as good as that of the odd-even sorting network and the bitonic sorting network. The resource usage of the prior art is significantly higher. In addition, since TM-CFAR needs to estimate the clutter power level by referring to multiple values in the sorted results, it cannot directly utilize the optimization methods proposed in the prior art.

[0061] Aiming at the disadvantages and deficiencies of the prior art, an efficient FPGA-based TM-CFAR implementation method is provided in this exemplary embodiment. In the existing process of implementing the TM CFAR algorithm using a sorting network, whenever the CFAR reference cells move to a new position, the sorting network takes all the data of the CFAR reference cells as new inputs and performs sorting. However, each time the CFAR reference cells move only one target cell, so only two data in the reference cells are new data, and the rest of the data has completed the sorting operation before the CFAR reference cells move. If the old sorted results can be fully utilized, after the CFAR reference cells move, only the data newly moved into the reference cells need to be sorted, which can greatly reduce the computational amount in the sorting process, thereby greatly reducing the computational resource consumption of the CFAR algorithm. Based on the above design idea, in this exemplary embodiment, refer to Figure 1As shown in the figure, the method for efficiently implementing TM-CFAR based on FPGA may specifically include the following steps:

[0062] Step S11, when the CFAR reference unit slides to the current position, determine the current reference unit corresponding to the current detection unit; wherein, the current reference unit includes: a first incoming sample located in the left reference unit, a second incoming sample located in the right reference unit, and an original sample;

[0063] Step S12, compare each sample in the current reference unit with the first incoming sample and the second incoming sample respectively to obtain the comparison result of the current reference unit;

[0064] Step S13, based on the comparison result of the current reference unit, combine the stored historical comparison results for data statistics, and update the sorting results corresponding to each sample in the current reference unit according to the data statistics results;

[0065] Step S14, according to the sorting results of each sample in the current reference unit, use a preset parameter selection strategy to screen target samples, and calculate the clutter power evaluation result based on TM CFAR corresponding to the current detection unit using the target samples.

[0066] Next, each step of the method for efficiently implementing TM-CFAR based on FPGA in this exemplary embodiment will be described in more detail with reference to the accompanying drawings and embodiments.

[0067] In this exemplary embodiment, FPGA (Field Programmable Gate Array, field programmable gate array) is a programmable device, which can change the structure of the internal circuit through programming to realize various logic functions. FPGA has the characteristics of high parallel processing ability and low latency, making it an ideal platform for high-performance implementation of various radar signal processing algorithms. Considering the time complexity and resource occupancy of implementing the CFAR algorithm based on FPGA. Since the implementation of algorithms on FPGA has the characteristics of flexibility and variability. For the same algorithm implementation, a trade-off can be made between time complexity and resource occupancy. Here, the running time of the CFAR algorithm based on FPGA is specified, and then the algorithm resource occupancy situation is considered solely. As Figure 2 shown, assume that the length of the CFAR reference unit is N, and the length of the target unit to be detected is M. When performing CFAR operations in FPGA, a window sliding operation is performed every clock cycle. When the window slides to each new position, the CFAR operation outputs a new background clutter power level estimate and decision threshold. Under this condition, the time complexity of the CFAR algorithm is O(M), and the implementation differences of various algorithms are mainly reflected in the amount of computing resources used.

[0068] Suppose TM-CFAR uses M clock cycles to complete the operation of sliding the reference cell window and outputs a CFAR clutter power estimate in each clock cycle. Then TM-CFAR needs to use a fully parallel sorting network to complete the sorting operation. Commonly used fully parallel sorting networks in FPGA include odd-even sorting network, bitonic sorting network, AKS sorting network, etc. Such sorting networks can achieve fully parallel pipelined sorting, output a set of sorting results in each clock cycle, and are suitable for use in the TM-CFAR algorithm.

[0069] In step S11, when the CFAR reference cell slides to the current position, determine the current reference cell corresponding to the current detection cell; wherein, the current reference cell includes: the first incoming sample located in the left reference cell, the second incoming sample located in the right reference cell, and the original sample.

[0070] Exemplarily, referring to Figure 2 As shown, when the window slides to the right and the CFAR reference cell slides to the current position, cell 4 is the current detection cell, and cells 3 and 5 are the protection cells respectively; cells 0-2 form the left reference cell, cell 2 is the first incoming sample currently incoming, and cells 0 and 1 are the original samples that have not been removed during this window slide; cells 6-8 are the right reference cell, cell 8 is the second incoming sample currently incoming, and cells 6 and 7 are the original samples that have not been removed during this window slide.

[0071] Suppose when the CFAR reference cell slides to the current position, the current reference cell is represented as: [D 0 , D 1 , …, D N-1 . For example, referring to Figure 3 As shown, it is the structure when the lengths of both the left and right reference cells are 3. When the length of the reference cell is any N, the corresponding design can be obtained by reasonably extrapolating from the structure shown in Figure 3 . When the length of the reference cell increases, only the processing modules in the corresponding row need to be increased.

[0072] In step S12, compare each sample in the current reference cell with the first incoming sample and the second incoming sample respectively to obtain the corresponding comparison result of the current reference cell.

[0073] Exemplarily, the comparing each parameter in the current reference cell with the first incoming sample and the second incoming sample respectively to obtain the corresponding comparison result of the current reference cell includes: using the comparators corresponding to each sample in the reference cell to obtain the comparison results of whether the current sample is greater than or equal to the first incoming sample and the second incoming sample; saving the comparison results to the comparison result register corresponding to the current sample.

[0074] Specifically, a data comparison module based on FPGA can be provided to compare the data in the reference unit during CFAR operation and save the comparison result in the comparison result register.

[0075] Exemplarily, the method includes: using a reference unit shift register to implement window sliding of the CFAR reference unit and storing the samples corresponding to the current reference unit.

[0076] For example, refer to Figure 3 As shown, the reference unit shift register stores the data corresponding to the reference unit in CFAR operation, that is, the sample values. This register realizes the translation operation of the reference unit in CFAR operation in the form of a shift register.

[0077] Refer to Figure 3 As shown, the data sources and comparison items involved in the comparison are marked in the comparator. Each comparator needs to perform two "greater than" comparisons and two "equal to" comparisons, for a total of four comparisons.

[0078] The comparison result register is responsible for temporarily storing the comparison results output by the comparator. To minimize resource usage, the comparison result register is implemented by configuring the LUT in the FPGA resource SLICEM as a shift register. Since the function of the comparison result register is closely related to the execution process of the present invention, the specific structure and function of the comparison result register will be described in detail when introducing the execution flow of the present invention later.

[0079] Exemplarily, the method includes: using a virtual decimal point processor to add virtual decimals to the comparison results output by each comparator.

[0080] Specifically, for the convenience of data processing, the subsequent module hopes that the data in the reference unit shift register are not equal to each other. However, the actual radar signal cannot guarantee that the input data are different. Therefore, a virtual decimal point processor is added here. The principle of the virtual decimal point processor is as Figure 4 shown. After the output result of the comparator is processed by the virtual decimal point processor, it is equivalent to adding a "fractional part" to the data in the reference unit shift register. For example, refer to Figure 4 shown. D2 and D0 in the reference unit shift register are equal and both are 0. After adding virtual decimals, since 0.4 is greater than 0.0, D2 > D0. Since the virtual decimals are different from each other, adding virtual decimals to the data in the reference unit shift register can ensure that the data are different from each other.

[0081] If the virtual decimal function is realized by directly expanding the data bit width of the reference unit shift register, the input data bit width of the comparator will inevitably increase, thereby increasing the consumption of computing resources and the number of combinational logic levels. Preferably, in order to save computing resources, the virtual decimal function is realized by adding an additional virtual decimal processor after completing the data comparison. For example, Figure 2 In the code, we agree that the virtual decimal value is larger as it goes down. In the virtual decimal processor, assume that the size relationship between D0 and D2 needs to be processed. When the output pin corresponding to the comparator D0>D2 is 1, the output pin corresponding to the virtual decimal processor D0>D2 is 1, and D2>D0 is 0. When the output pin corresponding to the comparator D0=D2 is 1, considering that the virtual decimal corresponding to D0 is smaller than D2, the output pin corresponding to the virtual decimal processor D0>D2 is 0, and D2>D0 is 1. The virtual decimal processing process of other data is similar.

[0082] When the reference unit length N increases, the data comparison module only needs to add the corresponding comparator. For a single comparator, the amount of resources it occupies does not change with the change of the reference unit length. Therefore, the computing resource occupation of the data comparison module is O(N).

[0083] In step S13, data statistics are performed based on the comparison result of the current reference unit in combination with the stored historical comparison results, and the sorting result corresponding to each sample in the current reference unit is updated according to the data statistical result.

[0084] Exemplarily, determining the sorting result corresponding to each sample in the current reference unit according to the data statistical result includes: for each sample in the current reference unit, using the corresponding counter to count the number of parameters in the current reference unit that are smaller than the current sample using an incremental statistical method;

[0085] The sorting result of the sample is determined according to the parameter quantity, and the sorting result is stored in the counting result register.

[0086] Exemplarily, the target sample is screened using a preset parameter selection strategy, including:

[0087] The decision device is used to determine whether the current sample is to be removed according to the sequence number, and the corresponding decision result is output; wherein the decision result is identified by binary data;

[0088] The target samples to be extracted are determined according to the binary data identifier, and the clutter power evaluation results are calculated using the target samples.

[0089] Specifically, a data statistics module based on FPGA can also be provided to count the comparison results output by the data comparison module. Specifically, a certain row counter in the data statistics module is responsible for counting the number of all data in the reference unit shift register that are smaller than the data in the shift register of the reference unit in this row, and saving the statistical result in the count result register. For example, Figure 3 Currently, the value of the first row of the reference unit shift register in Figure 3 is D1. Therefore, the function of the first row counter in the data statistics module is to count the number of data in the reference unit shift register that are smaller than D1 among all the data D3D3’D2D2’D1D1’. In this embodiment, the statistical result "2" means that there are 2 data in the reference unit shift register that are smaller than D1. In other words, if the reference unit shift register is sorted from small to large and the serial number corresponding to the smallest value is set to 0, the serial number corresponding to D0 is 2.

[0090] Preferably, in order to save computing resources, the incremental statistical method is adopted here for the counting method. Using the incremental statistical method can reduce the computational complexity of the counter in the data statistics module from O(N 2 ) to O(N log N), thereby greatly reducing its resource occupancy. This method will be specifically elaborated through embodiments later. Among them, for the comparison results between the unshifted samples in the left and right reference units, the historical comparison results of the samples can be obtained through the registers corresponding to the samples.

[0091] In this embodiment, the resource occupancy of the comparison result register is O(N 2 ). However, the coefficient of this item is small, so the impact on the overall resource usage is not significant. The actual measurement results show that in most CFAR application scenarios, the resource occupancy of this item does not dominate in the overall resource occupancy.

[0092] In step S14, according to the sorting results of the samples in the current reference unit, the target samples are selected using a preset parameter selection strategy, and the clutter power evaluation result based on TM CFAR corresponding to the current detection unit is calculated using the target samples.

[0093] Exemplarily, the determining the sorting results corresponding to the samples in the current reference unit according to the data statistics results includes:

[0094] For each sample in the current reference unit, the incremental statistical method is used by the corresponding counter to count the number of parameters in the current reference unit that are smaller than this sample;

[0095] And the sorting result of this sample is determined according to the number of parameters, and the sorting result is saved in the count result register.

[0096] Exemplarily, the sorting result is the serial number of the parameter sorting;

[0097] Filtering the target samples according to the sorting results of the samples in the current reference unit by using a preset parameter selection strategy, including:

[0098] Using a discriminator to determine whether to eliminate the current sample according to the serial number and output the corresponding discrimination result; wherein, the discrimination result is identified by binary data;

[0099] Determine the target samples to be extracted according to the binary data identification, and calculate the clutter power evaluation result by using the target samples.

[0100] Specifically, a clutter power estimation module based on FPGA can also be provided, which is used to complete the clutter power estimation function in CFAR operation according to the data sorting serial numbers stored in the count result register and the data values in the reference unit shift register. Specifically, in the clutter power estimation module, the discriminator is responsible for determining whether a number should be eliminated when estimating the clutter power. When the sorting serial number of a number satisfies {x|r 1 ≤x≤N - r 2}, it means that the number should not be eliminated. The corresponding discrimination result of the number is binary "1", otherwise it is binary "0".

[0101] The discrimination result register is responsible for storing the discrimination results of the discriminator. The bit width of the discrimination result register is the same as the number of reference unit registers. In the discrimination result register, each binary bit represents whether the data in the corresponding reference unit shift register should be eliminated.

[0102] The data extraction function is achieved by checking whether the discrimination result is "0"; if it is "0", the corresponding number in the reference unit shift register is set to zero. If it is not "0", it is output as it is. The output result of the data extractor is the unit in the reference unit participating in the calculation of the clutter power.

[0103] After data extraction, sum the units in the reference unit participating in the calculation of the clutter power, and the sum result is averaged after shifting to obtain the estimated value of the clutter power by TM - CFAR.

[0104] When using the method of the present invention for summation, the total amount of data participating in the summation is N. When using a fully parallel sorting network for summation, the total amount of data participating in the summation is N - r 1 - r 2 . Here, the method of the present invention will increase the amount of data participating in the summation. However, considering that the complexity of the summation operation itself is low and it is not the main source of the algorithm complexity. Therefore, the increased operation here can be ignored for the increase in resource usage.

[0105] Exemplarily, the data processing of the above method may include the following steps:

[0106] Step S1, data preparation. Specifically, in the data preparation stage, initial data comparison work is carried out to complete the initialization of the comparison result register. The clutter power is not output externally during the data preparation stage. Refer to Figure 3 As shown, it is an embodiment of a data preparation process. It can be understood that due to the parallel processing characteristics of the FPGA, although the following operation steps are described in sequence, they are parallel processed during the actual operation.

[0107] Step S1a, initialize the reference unit shift register and the comparison result register. Specifically, initializing the reference unit shift register means filling R / 2 - 1 target unit values to be referenced in the left and right reference unit shift registers respectively. Initializing the comparison result register means filling the comparison results in the initialization reference unit shift register stage into the comparison result register. Initializing the reference unit shift register and initializing the comparison result register are carried out simultaneously.

[0108] Refer to Figure 5a 、 Figure 5b As shown, it is the process of initializing the reference unit shift register and the comparison result register in the data preparation stage. Figure 5a In it, the first data D0D0′ is shifted into the left and right reference unit shift registers respectively. After being processed by the comparator and the virtual fractional processor, the comparison results D0 > D0′D0 and D0′ > D0′D0 are output. Figure 5b In it, the data in the left and right reference unit shift registers are shifted upward, and at the same time, the second data D1D1′ is shifted in. The comparison result register saves the comparison results D0 > D0′D0 and D0′ > D0′D0 generated in the previous clock cycle.

[0109] In the present invention, the comparison result register needs to save the comparison results of a certain data in the reference unit shift register with all the other data. The resource occupation increases with the growth of the reference unit length N in the scale of O(N 2 ). Here, in order to reduce the resource occupation of the comparison result register and make it applicable in more CFAR processing application scenarios, the present invention realizes the comparison result register by configuring the LUT resources in the FPGA in the form of a shift register. The structure of the comparison result register is shown in Figure 6.

[0110] Figure 6 shows the structure and operation process of the comparison result register when N = 6. The direction indicated by the arrow in the figure is the data translation direction of the shift register. Figure 6 only shows the storage process of the comparison results of the data in the right entrance unit register and the left and right reference unit shift registers. The corresponding data storage process of the left entrance unit register can be deduced by analogy. Note that the bottom layer in the figure does not belong to the comparison result register, but the comparison result of the data output by the virtual decimal processor. Therefore, the structure of the comparison result register shown in the figure is 2 shift registers with a length of 2 and 2 shift registers with a length of 1. Considering the functions of subsequent modules, the register cells indicated by the dotted lines in the shift registers shown in Figure 6 can be not implemented, and they are drawn here for the symmetry and beauty of the module structure. Figures 6a - 6c They are respectively the schematic diagrams corresponding to stage 0, stage 1, stage 2, and stage 3.

[0111] Step Slb, initialize the count result register. Specifically, after step Sla is completed, the comparison result register and the reference unit shift register stop the translation operation. Fill the left and right reference unit entrance registers with the values in the first step in sequence. For example, Figure 5c fill D0' and D0 into the left and right reference unit entrance registers respectively, Figure 5d and fill D1' and D1 into the left and right reference unit entrance registers respectively in. In step 1b, every time a value in the reference unit entrance register is updated, the virtual decimal processor will update a comparison result. The counter counts these updated comparison results and updates the count result register. Here, the counter adopts the incremental counting function. Specifically, the counter counts the number of binary "1"s in the comparison results output by the virtual decimal processor and adds this number to the count result register. For example, Figure 5c in the first row of, the counter adds the number of binary "1"s in the comparison result corresponding to "D0 > D0'D0" to the count result register in the first row. After one clock cycle, in Figure 5d the first row of, the counter adds the number of binary "1"s in the comparison result corresponding to "D0 > D1'D1" to the count result register in the first row. The other rows are deduced by analogy.

[0112] During the process of initializing the technical result register, the value of the comparison result register does not change. In the foregoing example, the value of the comparison result register will remain in the Figure 6b shown state.

[0113] Step S2, perform the first data operation. Refer to Figure 7 shown. After the data preparation stage is completed, calculate the first clutter power estimate value.

[0114] Step S2a, fill the left and right reference unit entry registers. Specifically, fill the left and right reference unit entry registers with the value of the R-th target unit to be referenced. For example, Figure 7 fill the left reference unit entry register with D2′ and the right reference entry register with D2.

[0115] Step S2b, restore the shift of the comparison result register. Specifically, the comparison result after being processed by the virtual fractional processor reaches the input port of the comparison result register. The shift register in the comparison result register restores the shift and will save the comparison result in the next clock cycle. For example, the data at the input port of the comparison result register in Figure 5 is the comparison result represented by "D2>D2′D2D1′D1 D0′D0". The comparison result register will save this comparison result in the next clock cycle. Figure 7 An exit register is set at the output port of the middle comparison result register. In the next clock cycle, the data at the output port of the comparison result register will be stored in the comparison result register exit register. In the actual implementation process, this exit register can be implemented using a flip-flop or by increasing the length of the shift register in the comparison result register.

[0116] Step S2c, update the count result register. Specifically, in the data statistics module, the counter updates the count result register using the same incremental statistical method as in Step 1. For example, the first row counter adds the number of binary "1"s in the comparison result corresponding to "D0>D2′D2" to the count result register. At this time, the result saved in the count result register is the position number of each value in the reference unit shift register in the sorting result.

[0117] Step S2d, estimate the clutter power. Specifically, in the clutter power estimation module, based on the value of the current count result register, estimate the clutter power at the position of the current CFAR reference unit. The specific calculation method has been given in the previous description of the functional module. Exemplarily, Figure 7 the shown operation results are the clutter power estimation results corresponding to when the data in the CFAR reference unit is D0, D0′, D1, D1′, D2, and D2′ respectively.

[0118] Step S3, subsequent data operations. Specifically, after obtaining the first clutter power estimate value through Step S2, the CFAR reference unit will shift to the right by one target unit. The result of this operation is: two new data are added to the CFAR reference unit, and at the same time, two old data are removed. Corresponding to this method, the two new data appear at the input port of the left reference unit and the input port of the right reference unit respectively.

[0119] Step S3a, update the left and right reference cell shift registers and the entry registers. Specifically, the left and right reference cell shift registers are each translated upward by one reference cell. At the same time, the data at the input ports of the left and right reference cells are saved into the left and right reference cell entry registers. Exemplarily, Figure 8 in D3, D3' are the data newly added to the reference cell shift register, and D0, D0' are the data removed from the reference cell.

[0120] Step S3b, update the comparison result register. Specifically, the comparison result after virtual decimal point processing is saved into the comparison result register. As Figure 8 shown, the comparison results at the entry of the comparison result register are updated to "D3 > D3'D3D2'D2D1'D1" and "D3'D3'D3D2'D2D1'D1". The comparison result register moves the comparison results "D2 > D2'D2D1'D1?" and "D2' > D2'D2D1'D1?" at the entry in the previous cycle into the comparison result register. At the same time, the output registers of each row of the comparison result register will save the values at the exit of the comparison result register. Figure 8 In it, the values of the output registers of the comparison result register are "D1 > D0'D0?", "D1' > D0'D0?", "D2 > D0'D0?", and "D2' > D0'D0?".

[0121] Step S3c, update the count result register. Specifically, a counter in a certain row of the data statistics module is responsible for counting the number of all data in the reference cell shift register that are less than the data of the reference cell shift register in that row, and saves the statistical result in the count result register. Preferably, this number is obtained by the incremental statistical method. The following is an example. As Figure 7 、 Figure 8 the counter structure in, here the counter of the 0th row is separated, as Figure 8 , Figure 9 shown. The partial enlarged views of the counters of the 0th row and the 2nd row in Figure 6 are as Figure 9 shown. Figure 8 The partial enlarged views of the counters of the 0th row and the 2nd row in are as Figure 8 shown. In Figure 8 and Figure 9 a comparison result register of the previous clock cycle is added to save the comparison results in the comparison result register 2 of the previous clock cycle. Figure 11 For Figure 9 、 Figure 10 is the timing diagram of the data change of each register. Figure 7 、 Figure 8 The counter and the count result register of the 0th row in are Figure 9 、 Figure 10 Figure 11The counter 0 and the count result register 0 therein, and the same can be deduced for others.

[0122] Such as Figure 8 , Figure 9 , Figure 10 As shown, the virtual fractional processor of the present invention outputs the first data comparison result in clock cycle 0. The first subsequent data comparison operation is output in clock cycle 1. The count result register saves the first data statistical result in clock cycle 1 and the first subsequent data statistical result in clock cycle 2. The specific method of performing data statistical work in clock cycle 0 has been described in step S2. Such as Figure 10 , Figure 11 As shown, in clock cycle 1, the virtual fractional processor 0 outputs the comparison result "D1 > D3′D3?", and the counter result register 2 saves the first data statistical result of data D1, that is, the serial number of data D1 in the sorting result. In clock cycle 1, the counter 0 calculates the result obtained by adding the number of binary "1"s in "D1 > D3′D3?" to the serial number of data D1 in the sorting result and subtracting the number of binary "1"s in D1 > D0′D0?. This result is the order of D1 in the sorting result of the CFAR reference unit. In clock cycle 2, this sorting result is written into the technology result register 0. And so on, the counter 0 can output the sorting result of the data of the 0th row reference unit in each clock cycle. The above analysis is only for counter 0, and the same applies to other row counters.

[0123] Through the incremental statistical method, the counter only needs 4 binary bits and the previous value of the count result register to update the value of the count result register. When the number of reference units in the CFAR operation changes, this characteristic still holds. Regardless of the length of the reference unit, the counter only needs to refer to 4-bit input data and the log 2 (N)-bit count result value when performing data statistics. Therefore, using this method can effectively reduce the combinational logic level when the counter counts the number of binary "1"s. When the length of the reference unit is N, the counter bit width is log 2 (N). When the length N of the reference unit increases, the computational complexity and resource occupancy of the counter are O(N log N).

[0124] Note that when the last two rows of counters in the figure perform binary "1" statistics, the incremental statistical method cannot be used. Specifically, Figure 8When counting the number of binary "1"s in the comparison results D3>D3′D3D2′D2D1′D1 and D3′>D3′D3D2′D2D1′D1, the incremental counting method cannot be used. Here, it is necessary to count the number of binary "1"s in all binary bits of the comparison result register. It is noted that only the last two rows of counters have this feature. Therefore, the resource occupancy of the last two rows of counters changing with the CFAR reference unit length is still O(N). In summary, the computing resource occupancy of the data statistics module is O(N log N).

[0125] Step S3d, estimate the clutter power. Specifically, in the clutter power estimation module, according to the value of the current count result register, the clutter power at the position where the current CFAR reference unit is located is estimated. As an example, the operation results shown in the figure are the clutter power estimation results corresponding to the data D1, D1′, D2, D2′, D3, D3′ in the CFAR reference unit respectively.

[0126] Step S3e, translate the CFAR reference unit to further complete the data operation. Specifically, shift the CFAR reference unit one target unit to the right. The two new data of the CFAR reference unit at the new position appear at the left reference unit input port and the right reference unit input port respectively. Repeat the operations from the first step to the fourth step in Step S3, and the clutter power estimation value of the CFAR reference unit at the new position can be obtained. Repeat the above operations until the clutter power estimation values of the CFAR reference unit at all positions are calculated.

[0127] In addition, in some exemplary embodiments, the comparator includes an entrance comparator and an exit comparator.

[0128] The method further includes: using the entrance comparator to compare the parameters in the reference unit entrance shift register with all the parameters in the reference unit shift register, and storing the comparison result in the entrance comparison result register; wherein, the reference unit entrance register includes: a left reference unit entrance register for storing the corresponding parameters of the left reference unit, and a right reference unit entrance register for storing the corresponding parameters of the right reference unit.

[0129] Using the exit comparator to compare the parameters in the reference unit exit shift register with all the parameters in the reference unit shift register, and storing the comparison result in the exit comparison result register; wherein, the reference unit exit shift register includes a left reference unit exit register for storing the samples to be shifted out and a right reference unit shift-out register.

[0130] Specifically, this solution further optimizes the comparator and the comparison result register. Refer to Figure 12As shown, for the reference unit shift register, the registers at the data transfer positions in the left and right reference unit shift registers are referred to as the left and right reference unit output registers.

[0131] For the comparator, it is divided into two types: the input comparator and the output comparator. Each comparator is equipped with a corresponding virtual decimal processor. Among them, the function of the input comparator is to compare the data in the reference unit input shift register with all the data in the reference unit shift register.

[0132] The added output comparator is used to compare the data in the reference unit output shift register with all the data in the reference unit shift register. Refer to Figure 12 As shown, the comparator indicated by the solid line is the input comparator, and the comparator indicated by the dotted line is the output comparator. Among them, the data in the input reference unit register of the input comparator includes D2 and D2'; the data in the output reference unit register of the output comparator includes D0 and D0'.

[0133] By increasing the number of comparators by nearly double in the data comparison module, the comparison result register does not require a large number of intermediate comparison results, thereby eliminating the O(N 2 ) item in the resource occupancy of the data statistics module.

[0134] In addition, the newly added output comparator is also equipped with a corresponding virtual decimal processor.

[0135] In addition, the function of the comparison result register is only to store the output results of the virtual decimal processor, without the need to store historical comparison results, and there is no need for initialization during the data processing. Therefore, the resource consumption of the comparison result register can be greatly reduced.

[0136] Exemplarily, when data processing is performed, all 4 binary bits required by the counter directly come from the output of the comparison module. At this time, the count result register does not need to save all the comparison results, but only needs to temporarily store 4 binary bits to improve the working frequency of the module.

[0137] Among them, for the 4 binary bits that the counter needs to refer to, 2 bits come from the input comparator, and the other 2 bits come from the output comparator. For this solution, the data processing steps and the input / output timing characteristics of the module are exactly the same as those of the first embodiment. Before the CFAR reference unit starts to translate, an initialization step is required. But only the count result register needs to be initialized. The required clock cycles and operation timing for initialization are exactly the same as those of the first embodiment described above.

[0138] Exemplarily, the resource usage of the solution using the traditional parallel network to implement TM CFAR is O(N log 2N). In contrast, when implementing the TM CFAR algorithm in the present invention, the resource amount used by the comparator part will reach O(N), and the overall resource usage does not exceed O(N log N).

[0139] Exemplarily, as shown in Table 1, taking N = 16 as an example, a detailed resource usage comparison table between the present invention and the traditional bitonic sorting network scheme under the XILINX ZYNQ 7100 platform is given.

[0140] Table 1

[0141]

[0142] Reference Figure 13 And Figure 14 , as shown, the changing trends of the total resource occupation of each scheme under different numbers of reference cells are given. It can be seen from these data that the present invention has significantly lower resource usage compared to the traditional bitonic sorting network scheme. It can be seen from the table that Scheme 1 has advantages over Scheme 2 in the scenario where N ≤ 256. Further experiments prove that in the usage scenarios described in the present invention, Scheme 1 is more advantageous than Scheme 2 in the scenario where N ≤ 2500. If BRAM is used to implement the comparison result register, the advantageous interval of Scheme 1 can be further extended. Considering that in practical applications, the length of the reference cells in the CFAR algorithm is generally not large, the application value of the further extended scheme is relatively low.

[0143] The method provided by the embodiment of the present invention makes full use of the sliding characteristics in the CFAR operation process and designs a TM CFAR clutter power estimation system based on FPGA. When implementing the TM CFAR algorithm using this method, the resource amount used by the comparator part will reach O(N), and the overall resource usage does not exceed O(N log N), greatly reducing the resource occupation. Moreover, this method also has a fully parallel pipelined structure, and the data throughput can reach the same performance as the traditional fully parallel sorting network.

[0144] It should be noted that the above-mentioned drawings are only schematic illustrations of the processes included in the method according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above-mentioned drawings do not indicate or limit the time sequence of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.

[0145] Furthermore, as shown in reference Figure 15 , in the implementation manner of this example, an efficient FPGA-based TM-CFAR implementation device 150 is further provided, including:

[0146] A data comparison module 1501 is configured to determine a current reference unit corresponding to a current detection unit when a CFAR reference unit slides to the current position; and compare each sample in the current reference unit with a first incoming sample and a second incoming sample respectively to obtain a corresponding comparison result of the current reference unit. Wherein, the current reference unit includes: a first incoming sample located in a left reference unit, a second incoming sample located in a right reference unit, and an original sample.

[0147] A data statistics module 1502 is configured to perform data statistics based on the comparison result of the current reference unit, combine the stored historical comparison results, and update the sorting result corresponding to each sample in the current reference unit according to the data statistics result.

[0148] A clutter power estimation module 1503 is configured to screen target samples according to the sorting result of each sample in the current reference unit by using a preset parameter selection strategy, and calculate a clutter power evaluation result based on TM CFAR corresponding to the current detection unit by using the target samples.

[0149] The device 150 may be an FPGA device, and the functions of each module have been described in detail in the corresponding method embodiments, and will not be elaborated here.

[0150] It should be noted that although several modules or units of a device for action execution are mentioned in the above detailed description, this division is not mandatory. In fact, according to the embodiments of the present invention, the features and functions of two or more modules or units described above may be embodied in one module or unit. Conversely, the features and functions of one module or unit described above may be further divided and embodied by multiple modules or units.

[0151] Figure 16 The figure shows a schematic diagram of an electronic device suitable for implementing the embodiments of the present invention.

[0152] It should be noted that Figure 16 The shown electronic device 1000 is only an example and should not impose any limitation on the functions and usage scope of the embodiments of the present invention.

[0153] Such as Figure 16As shown, the electronic device 1000 includes a Central Processing Unit (CPU) 1001, which can perform various appropriate actions and processes according to the program stored in the Read-Only Memory (ROM) 1002 or the program loaded from the storage section 1008 into the Random Access Memory (RAM) 1003. In the RAM 1003, various programs and data required for system operation are also stored. The CPU 1001, ROM 1002, and RAM 1003 are connected to each other via a bus 1004. An Input / Output (I / O) interface 1005 is also connected to the bus 1004.

[0154] The following components are connected to the I / O interface 1005: an input section 1006 including a keyboard, a mouse, etc.; an output section 1007 including such as a Cathode Ray Tube (CRT), a Liquid Crystal Display (LCD), etc. and a speaker, etc.; a storage section 1008 including a hard disk, etc.; and a communication section 1009 including a network interface card such as a LAN (Local Area Network) card, a modem, etc. The communication section 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I / O interface 1005 as needed. A removable medium 1011, such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed so that a computer program read from it can be installed into the storage section 1008 as needed.

[0155] In particular, according to an embodiment of the present invention, the processes described below with reference to the flowcharts can be implemented as computer software programs. For example, an embodiment of the present invention includes a computer program product, which includes a computer program carried on a storage medium, and the computer program contains program codes for performing the methods shown in the flowcharts. In such an embodiment, the computer program can be downloaded and installed from the network via the communication section 1009, and / or installed from the removable medium 1011. When the computer program is executed by the Central Processing Unit (CPU) 1001, various functions defined in the system of the present application are executed.

[0156] It should be noted that the storage medium shown in the embodiments of the present invention can be a computer-readable signal medium, a computer-readable storage medium, or any combination of the two. A computer-readable storage medium can be, for example, but not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples of a computer-readable storage medium can include, but are not limited to: an electrical connection with one or more wires, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a flash memory, an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above. In the present invention, a computer-readable storage medium can be any tangible medium that contains or stores a program, and this program can be used by or in conjunction with an instruction execution system, apparatus, or device. In the present invention, a computer-readable signal medium can include a data signal propagated in a baseband or as part of a carrier wave, which carries computer-readable program code. Such a propagated data signal can take various forms, including but not limited to electromagnetic signals, optical signals, or any suitable combination of the above. A computer-readable signal medium can also be any storage medium other than a computer-readable storage medium, and this storage medium can send, propagate, or transmit a program for use by or in conjunction with an instruction execution system, apparatus, or device. The program code contained on the storage medium can be transmitted by any appropriate medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

[0157] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present invention. In this regard, each block in the flowchart or block diagram can represent a module, a program segment, or a part of code, and the above module, program segment, or part of code contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, and the combination of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system for performing the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0158] The units involved in the embodiments of the present invention can be implemented in software or in hardware, and the described units can also be provided in a processor. Among them, the names of these units do not constitute a limitation to the units themselves in certain cases.

[0159] It should be noted that, on the other hand, the present application also provides a storage medium, which can be included in an electronic device; or can exist alone without being assembled into the electronic device. The above storage medium carries one or more programs, and when the above one or more programs are executed by an electronic device, the electronic device is caused to implement the methods described in the following embodiments. For example, the electronic device can implement the Figure 1 various steps of the method shown.

[0160] In one embodiment, the present application provides a computer program product, including a computer program, which when executed by a processor implements the steps in the above method embodiments.

[0161] In addition, the above drawings are only schematic illustrations of the processes included in the methods according to the exemplary embodiments of the present invention, rather than for limiting purposes. It is easy to understand that the processes shown in the above drawings do not indicate or limit the chronological order of these processes. Additionally, it is also easy to understand that these processes can be executed synchronously or asynchronously in, for example, multiple modules.

[0162] Those skilled in the art will readily think of other embodiments of the present invention after considering the specification and practicing the invention herein. The present application aims to cover any variations, uses, or adaptations of the present invention, which follow the general principles of the present invention and include the common general knowledge or conventional technical means in the technical field not disclosed in the present invention. The specification and embodiments are only regarded as exemplary, and the true scope and spirit of the present invention are pointed out by the claims.

[0163] It should be understood that the present invention is not limited to the exact structures already described and shown in the drawings, and various modifications and changes can be made without departing from its scope. The scope of the present invention is only limited by the appended claims.

Claims

1. An efficient TM-CFAR implementation method based on FPGA, characterized in that: The method comprises: When the CFAR reference unit slides to the current position, determining the current reference unit corresponding to the current detection unit; wherein the current reference unit includes: a first moving-in sample located at the left reference unit, a second moving-in sample located at the right reference unit, and an original sample; Compare each sample in the current reference unit with the first input sample and the second input sample respectively to obtain a corresponding current reference unit comparison result; Based on the comparison result of the current reference unit, data statistics are performed in combination with the stored historical comparison results, and the sorting results corresponding to each sample in the current reference unit are updated according to the data statistical results; According to the sorting results of each sample in the current reference unit, the preset parameter selection strategy is used to screen the target sample, and the target sample is used to calculate the TM CFAR-based clutter power evaluation result corresponding to the current detection unit.

2. The method according to claim 1, characterized in that The step of comparing each sample in the current reference unit with the first input sample and the second input sample to obtain a corresponding current reference unit comparison result includes: Using the comparator corresponding to each sample in the reference unit, obtaining a comparison result of whether the current sample is greater than or equal to the first input sample and the second input sample; The comparison result is saved in the comparison result register corresponding to the current sample.

3. The method according to claim 2, characterized in that The comparator comprises an input comparator and an output comparator; The method further comprises: Using an entry comparator to compare the sample in the reference unit entry shift register with all the samples in the reference unit shift register, and storing the comparison result in an entry comparison result register; wherein the reference unit entry register includes: a left reference unit entry register for storing samples corresponding to the left reference unit, and a right reference unit entry register for storing samples corresponding to the right reference unit; An exit comparator is used to compare the samples in the reference unit exit shift register with all the samples in the reference unit shift register, and the comparison result is stored in the exit comparison result register; wherein the reference unit exit shift register includes a left reference unit exit register and a right reference unit shift-out register for storing samples to be shifted out.

4. The method according to claim 2 or 3, characterized in that: The method comprises: A virtual decimal point processor is used to add a virtual decimal to the comparison result output by each comparator.

5. The method according to claim 1, characterized in that The step of determining the sorting result corresponding to each sample in the current reference unit according to the data statistics result includes: For each sample in the current reference unit, use the corresponding counter to count the number of parameters in the current reference unit that are smaller than the current sample using the incremental statistics method; The sorting result of the sample is determined according to the number of parameters, and the sorting result is stored in the counting result register.

6. The method according to claim 5, characterized in that The sorting result is the sequence number of the sample sorting; The method of screening the target sample by using a preset parameter selection strategy according to the sorting result of each sample in the current reference unit includes: The decision device is used to determine whether the current sample is to be removed according to the sequence number, and the corresponding decision result is output; wherein the decision result is identified by binary data; The target samples to be extracted are determined according to the binary data identifier, and the clutter power evaluation results are calculated using the target samples.

7. The method according to claim 1, characterized in that The method comprises: The reference unit shift register is used to realize the window sliding of the CFAR reference unit and store the samples corresponding to the current reference unit.

8. An efficient TM-CFAR implementation device based on FPGA, characterized in that: The device comprises: The data comparison module is used to determine the current reference unit corresponding to the current detection unit when the CFAR reference unit slides to the current position; and compare each sample in the current reference unit with the first input sample and the second input sample respectively to obtain the corresponding current reference unit comparison result; wherein the current reference unit includes: the first input sample located in the left reference unit, the second input sample located in the right reference unit, and the original sample; A data statistics module is used to perform data statistics based on the comparison results of the current reference unit and in combination with the stored historical comparison results, and to update the sorting results corresponding to each sample in the current reference unit according to the data statistics results; The clutter power estimation module is used to screen the target samples according to the sorting results of the samples in the current reference unit using a preset parameter selection strategy, and calculate the clutter power evaluation result based on TM CFAR corresponding to the current detection unit using the target samples.

9. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the efficient TM-CFAR implementation method based on FPGA according to any one of claims 1 to 7 is implemented.

10. An electronic device, characterized in that: include: processor; as well as A memory, configured to store executable instructions of the processor; The processor is configured to execute the FPGA-based efficient TM-CFAR implementation method according to any one of claims 1 to 7 by executing the executable instructions.

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