A timing chart fast design update and verification method based on a timing block architecture model

Abstract

The present application relates to the technical field of timing diagram updating, and particularly relates to a method for rapid design updating and verification of an architecture model timing diagram based on a timing block, and proposes the following scheme: a region to be updated is selected, and a timing block and timing attributes thereof are edited in a pop-up editing box; the editing content includes a timing block name, a trigger timing, a message transmission interval, a trigger condition and the like; the editing result is converted into a standardized logic segment through a logic generation box, and is fused with an original timing diagram according to a layout algorithm of the timing diagram. The method realizes efficient updating, verification and layout optimization of the timing block in the timing diagram, ensures the correctness and consistency of the timing relationship, and improves the flexibility and accuracy of the design process.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of timing diagram updating, in particular to a timing diagram fast design updating and verification method based on a timing block architecture model. BACKGROUND

[0002] In the design and development process of modern complex systems, timing diagrams are widely used as an important graphical tool to describe the interaction behavior and time sequence between different components in the system. Especially in architecture model design, timing diagrams are often used to represent message passing, event triggering and timing constraints between modules to facilitate the analysis of timing logic and performance of the system. However, with the increase of system size and complexity, the existing timing diagram design and updating methods face many challenges.

[0003] Traditional timing diagram design methods often rely on manual operation. In large-scale systems, designers need to handle the updating of event order, time interval and message path of each timing block separately. This manual operation not only has a huge workload, but also is prone to errors. Especially when the system requirements change, the timing diagram needs to be updated frequently, and some key timing relationships may be missed during the updating process, resulting in inaccurate design or verification failure.

[0004] For example, the Chinese patent with application number CN116860623A relates to a test case updating method and system based on operation timing diagram. The method includes parsing the updated user operation timing diagram, obtaining and storing the node table of the updated user operation and the pointing relationship table between nodes; comparing the updated pointing relationship table between nodes with the stored pointing relationship table between nodes to obtain a differential node pointing relationship set; and obtaining an updated test case table according to the differential node pointing relationship set. The present application obtains the node pointing relationship set to be updated and deleted by comparing the node pointing relationship before and after the addition or deletion of nodes, and locates and updates the stored branch path according to the pointing relationship set. When updating the test case, the tester does not need to reconfigure the data dictionary or only needs to configure or modify the data dictionary of the updated node. The data dictionary of other nodes without updates is still effective, reducing the maintenance of the test case.

[0005] The above patents all have the problems raised in the background art: insufficient complexity of timing relationship processing and lack of automatic verification mechanism. To solve the above problems, the present application designs a timing diagram fast design updating and verification method based on a timing block architecture model. SUMMARY

[0006] The technical problem solved by the present application is to provide a timing block-based architecture model timing diagram fast design updating and verifying method to solve the problems of the prior art.

[0007] To achieve the above object, the present application provides the following technical scheme.

[0008] A timing block-based architecture model timing diagram fast design updating and verifying method, the method comprising:

[0009] Selecting a region to be updated in a timing diagram interface through an interactive device, the region to be updated being displayed in the form of a dynamic box, the dynamic box comprising timing blocks, interactive relationships and timing attributes, the timing attributes comprising time intervals of message transmission, triggering times of events and transmission relationships between timing blocks;

[0010] According to the region to be updated, a pop-up editing box corresponding to the region is generated, and the timing blocks and their timing attributes are edited in the pop-up editing box, the editing comprising attribute modification of the timing blocks;

[0011] The editing results are converted into standardized logic segments through a logic generation box, and the standardized logic segments are fused with the original timing diagram according to a layout algorithm of the timing diagram.

[0012] The selecting the region to be updated comprises:

[0013] The selecting operation is performed in the timing diagram interface through the interactive device to determine an initial updating range of the region to be updated, the selecting operation comprising a box selecting operation, a timing block selecting operation and a message path selecting operation, wherein the message path selecting operation comprises selecting message transmission paths and timing constraint relationships between the timing blocks;

[0014] The initial updating range is expanded according to time sequences of the timing blocks in the initial updating range, message transmission sequences and timing block dependency relationships;

[0015] The expanded region to be updated is highlighted in the timing diagram interface through the dynamic box, timing logic verification is performed, if the verification is passed, the region to be updated is marked, and if the verification is not passed, the updating range is readjusted according to the timing constraint relationships.

[0016] The expanding the initial updating range comprises:

[0017] analyzing message passing and event triggering relationship between the time sequence blocks within the initial update range to obtain time sequence dependency and time constraint;

[0018] deriving dynamic dependency chain between the time sequence blocks according to the time sequence dependency, generating message path, and calculating synchronization degree and dependency degree of the message path in the time sequence blocks;

[0019] analyzing the time sequence blocks through a time window according to the time constraint to calculate time sequence delay factor of the time sequence blocks, wherein the time sequence delay factor refers to minimum delay time of the time sequence blocks in the message passing or event triggering process under time limitation of other time sequence blocks;

[0020] aggregating the time sequence delay factors of all the time sequence blocks, determining parallel execution relationship between the time sequence blocks according to the time sequence delay factors, and calculating time sequence expansion factor of the time sequence blocks according to the parallel blocks and the message path of the current time sequence block;

[0021] sorting the time sequence expansion factors of all the time sequence blocks, taking the maximum time sequence expansion factor as expansion radius, superimposing the expansion radius with the radius of the initial update range, and obtaining the to-be-updated range.

[0022] The calculation formula of the time sequence expansion factor is:

[0023]

[0024] wherein, A i denotes the time sequence expansion factor of the time sequence block i, δ i denotes the time sequence delay factor of the time sequence block i, n denotes the parallel block quantity of the time sequence block i, j denotes a single event of the time sequence block i, N denotes the total event quantity of the time sequence block i, E j denotes triggering time of the jth event, T max denotes the maximum time delay in the time sequence block i, l denotes a single message path of the time sequence block i, M denotes the total message path quantity of the time sequence block i, P l denotes load quantity of the lth message path, P max denotes the maximum load quantity in the time sequence block i, β l denotes dependency factor of the lth message path, θ l denotes time sequence synchronization factor of the lth message path.

[0025] The pop-up editing box comprises:

[0026] an attribute editing tool, configured to display and modify attribute information of a selected time sequence block, wherein the attribute information comprises triggering time, execution sequence, time interval and message path;

[0027] An event trigger timing adjustment tool is used to adjust the trigger timing of each event in a timing block and provide a graphical display of the time relationship between event triggers.

[0028] A synchronization and dependency relationship editing tool is used to modify the message passing path between timing blocks and adjust the dependency relationship between timing blocks.

[0029] A structure preview tool is used to display a preview of the editing result during the editing process.

[0030] The editing of the timing block and its timing attributes in the pop-up editing box includes:

[0031] The timing block to be edited is selected through an interactive device, and the relevant attributes of the timing block are modified in the pop-up editing box, including the name of the timing block, the event trigger timing, the time interval of message passing, and the trigger condition.

[0032] The interaction relationship between timing blocks is modified by dragging or selecting the trigger order between events through a graphical interface and adjusting the dependency relationship between events.

[0033] During the editing process, the synchronization factor and the delay factor of each event in the timing block are displayed in real time, and the synchronization and delay relationship between events is changed according to the synchronization factor and the delay factor.

[0034] Logical verification is performed on the timing block and its timing attributes, including time dependency, event trigger timing order, and message passing time interval.

[0035] The logic generation box includes:

[0036] A standardized conversion tool is used to convert the modifications made to the timing block and its timing attributes during the editing process into a standardized timing logic segment.

[0037] A timing verification tool is used to check the time dependency, event trigger order, and message passing path in the logic segment and perform functional verification on the generated timing logic segment.

[0038] A timing dependency relationship conversion tool is used to analyze and convert the dependency relationship between the edited timing logic segment and the original timing diagram.

[0039] A timing attribute synchronization tool is used to verify whether the timing attributes of the updated timing block in the entire timing diagram meet the overall consistency and synchronization.

[0040] The layout algorithm of the timing diagram includes:

[0041] When a new timing block or updated content is introduced, the spatial layout is adjusted according to the timing relationship between the timing blocks in the timing diagram, the event triggering timing, the message transmission path and the timing attribute;

[0042] By analyzing the timing dependency chain of each timing block, the relative order and connection relationship of the timing blocks are adjusted, a new message path is generated according to the dependency degree and timing attribute between the timing blocks, and the updated timing blocks are reconnected according to the dependency relationship;

[0043] According to the time constraint of each timing block, the time overlap and parallel execution between the timing blocks are analyzed, and the execution order and spatial distribution between the timing blocks are adjusted.

[0044] A timing diagram fast design update verification system based on a timing block architecture model, the system comprises a selection expansion module, an editing derivation module, a logic verification module and a layout adjustment module;

[0045] The selection expansion module is configured with an intelligent expansion strategy, which is used to determine an initial update range, and expand the initial update range according to the time sequence of the timing blocks in the initial update range, the message transmission sequence and the timing block dependency relationship;

[0046] The editing derivation module is used for editing the timing block and its timing attribute in a pop-up editing box, and the editing includes attribute modification of the timing block;

[0047] The logic verification module is used for converting the editing result into a standardized logic segment through a logic generation box;

[0048] The layout adjustment module is used for fusing the standardized logic segment with the original timing diagram according to a layout algorithm of the timing diagram.

[0049] The selection expansion module comprises:

[0050] An initial circumscription unit is used for performing a selection operation in a timing diagram interface through an interactive device to determine an initial update range of a to-be-updated area;

[0051] An intelligent update unit is used for dynamically expanding the initial update range and generating a new to-be-updated area;

[0052] An area display unit is used for displaying the to-be-updated area in the form of a dynamic box.

[0053] Compared with the prior art, the beneficial effects of the present application are:

[0054] 1.The application can quickly identify and expand the region to be updated, ensure that the dependency relationship and time constraint between the timing blocks are reasonably checked, and effectively reduce the manual intervention and error occurrence through the dynamic frame and real-time checking function. BRIEF DESCRIPTION OF DRAWINGS

[0055] Other features, objects and advantages of the application will become more apparent from the following detailed description of non-limiting embodiments, made with reference to the accompanying drawings:

[0056] Figure 1 A flowchart of a timing diagram fast design update verification method based on a timing block architecture model of an embodiment of the application;

[0057] Figure 2 A module diagram of a timing diagram fast design update verification system based on a timing block architecture model of an embodiment of the application. DETAILED DESCRIPTION

[0058] The technical solutions in the embodiments of the application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the application. Obviously, the described embodiments are only some of the embodiments of the application, not all the embodiments.

[0059] It should be noted that the timing block in the application is applicable to scenarios that focus on the time interaction between components, such as real-time system, event-driven architecture and communication protocol modeling. It can effectively optimize the message passing order and check the consistency of time constraints.

[0060] Specifically, the timing block is applied to the timing diagram, mainly focusing on the time sequence and message interaction between different modules. The focus of the timing block is the time constraint, event triggering time and the time interval of the message path, emphasizing the rationality of the time logic and the execution sequence.

[0061] Embodiment 1

[0062] Please refer to Figure 1 An embodiment provided by the application is a timing diagram fast design update verification method based on a timing block architecture model, and the specific steps of the method are as follows:

[0063] S1: Select the region to be updated in the timing diagram interface through the interactive device, and the region to be updated is displayed in the form of a dynamic frame;

[0064] In this step, a region to be updated is selected in the timing diagram interface through an interactive device such as a mouse, touch screen or other input device. The region is highlighted in the form of a dynamic box, intuitively identifying the part of the timing diagram that needs to be edited or modified. The dynamic box contains relevant timing blocks, interaction relationships and timing attributes, including key timing information such as the time interval of message transmission and the triggering time of events. The timing diagram region to be updated can be precisely located through methods such as box selection, node operation or message path selection, ensuring the effectiveness and accuracy of subsequent operations.

[0065] S2: editing the timing blocks and their timing attributes in the pop-up editing box;

[0066] In this step, once the region to be updated is selected and highlighted, an editing box will pop up, allowing modification of the timing blocks and their related timing attributes. In this editing box, the attributes of the timing blocks can be modified, such as the triggering time of events, the time interval of message transmission, the dependency relationship between timing blocks, etc. The editing box provides a variety of editing tools, supporting graphical operations (such as dragging timing blocks, adjusting message paths, etc.), as well as precise attribute input and adjustment. The modifications made will directly affect the behavior and interaction relationships of the timing diagram.

[0067] S3: converting the editing results into standardized logic fragments through the logic generation box;

[0068] In this step, according to the modification content input in the pop-up editing box, the editing results are converted into standardized logic fragments that conform to the unified specification using the logic generation box. The standardized logic fragments contain verified timing information, message transmission order and their time delay attributes, ensuring that the edited timing diagram is logically valid and conforms to the design specifications and constraints of the timing diagram. The generated standardized logic fragments will provide a basis for subsequent timing diagram fusion.

[0069] S4: fusing the standardized logic fragments with the original timing diagram according to the layout algorithm of the timing diagram.

[0070] In this step, the layout algorithm automatically adjusts the relative positions of new timing blocks and message paths based on the dependency relationships of timing blocks, the order of message transmission and time constraints in the timing diagram, ensuring that the layout of elements in the diagram does not conflict and conforms to timing constraints.

[0071] The S1 specific steps are as follows:

[0072] S1.1: performing a selection operation in the timing diagram interface through an interactive device to determine the initial update range of the region to be updated, the selection operation including box selection, timing block selection and message path selection, wherein the message path selection operation includes selecting the message transmission path and timing constraint relationship between timing blocks;

[0073] Box selection operation: By mouse or touch device, the user selects a region on the timing diagram interface, and selects the timing blocks, events, message paths, etc. in the region. The selection range of the box selection region can be continuous or discontinuous. The box selection operation not only provides the initial range for subsequent updates, but also helps to determine the boundary that needs to be expanded.

[0074] Timing block selection operation: Select one or more timing blocks in the diagram by clicking or dragging the mouse. This selection operation is suitable for the case where it is already known which timing blocks need to be modified or updated. The selection of timing blocks is usually based on the user's understanding of the existing timing diagram and the expected results of the modification target. After selection, the region where the selected timing blocks are located is automatically selected as the initial update range.

[0075] Message path selection operation: Select the message passing path between timing blocks, especially when the timing diagram contains complex message passing logic. By selecting the message path, not only the specific message passing process is selected, but also the related timing constraints are automatically included. For example, when selecting the message passing path between two timing blocks, the related timing constraints such as time interval, timing sequence of message triggering, etc. are automatically identified and considered;

[0076] Through these three selection operations, the target region in the timing diagram can be accurately selected to achieve accurate positioning of the update region without modifying the entire diagram. Compared with traditional methods, the update region can be specified flexibly to avoid unnecessary interference;

[0077] S1.2: Expand the initial update range according to the time sequence of the timing blocks in the initial update range, the message passing sequence, and the timing block dependency relationship;

[0078] Time sequence analysis: Analyze the time relationship between timing blocks according to the time attributes in the timing blocks (such as event triggering time, message passing time interval). For example, the execution of a timing block depends on the triggering of an event in other timing blocks. If these timing blocks are not selected, the system will automatically include them in the expanded region. In this way, all related timing blocks are updated to avoid missing other timing blocks that have a dependency relationship with the target timing block.

[0079] Message passing sequence: The message passing sequence in the timing diagram determines how messages flow between timing blocks, and the order and triggering time of any message will affect the logic of the entire timing diagram. Analyze the message passing path in the selected region, automatically derive the message sequence, and expand the update range according to the passing sequence between timing blocks. If the passing sequence of the message path is not clear or there is a timing conflict, the system will automatically adjust the update range according to the timing constraint conditions.

[0080] Temporal block dependency: There are often complex dependencies between temporal blocks. For example, certain temporal blocks may depend on the event-triggered results of other temporal blocks, or need to wait until the execution of a certain temporal block is completed before starting. The system will automatically identify these dependencies and further expand the initial update range by deriving dynamic dependency chains between temporal blocks. This derivation ensures that the update range covers all dependent or affected temporal blocks, avoiding omissions.

[0081] S1.3: Highlight the expanded update area in the timing diagram interface with a dynamic box, perform timing logic verification, and if the verification passes, mark it as an update area, if the verification fails, adjust the update range according to the timing constraint relationship.

[0082] After expanding the update area, highlight the expanded area in the timing diagram interface with a dynamic box to provide clear visual indication and confirm whether the update area meets expectations. At the same time, the system will automatically perform timing logic verification to ensure that the expanded update range is logically consistent in timing and will not cause conflicts or errors. The specific verification steps include:

[0083] S1.3.1: Analyze the time dependency between all temporal blocks in the expanded area, the order of message transmission paths, the timing of event triggering, etc., and check whether they meet the constraints of the timing diagram. In particular, for cross-temporal block dependencies, ensure that these dependencies are not broken, thus ensuring the overall consistency of the timing diagram. For example, if the execution time of a certain temporal block depends on the completion of another temporal block, ensure that all dependencies are met and there is no unreasonable parallel execution.

[0084] S1.3.2: If the timing logic verification fails, automatically adjust the expanded area. Adjustment can be done in two ways:

[0085] Narrow the expanded range: If certain temporal blocks or message paths introduce conflicts that do not meet timing constraints, the system will automatically narrow the update range based on timing constraint conditions, eliminating the temporal blocks or message paths that cause problems.

[0086] Resequence: The system can also adjust the order of temporal blocks based on their dependencies to ensure the order of message paths and the timing of event triggering are not disrupted. For example, if the update process causes a sequence conflict between temporal blocks, the system will adjust the order of temporal blocks to ensure that there is no time confusion.

[0087] Specifically, the derivation of the extended region not only depends on the user's preliminary selection, but also determines the precise range of updates through the system's automatic analysis of the time relationship of the timing block, the message passing order, and the dependency chain. Through this intelligent derivation, the system can accurately capture and expand all timing elements related to the update, avoiding the omissions or errors that may occur in traditional manual editing. At the same time, the timing logic verification and automatic adjustment mechanism ensures the timing consistency during the update process, avoiding the propagation of design errors.

[0088] By analyzing the initially determined update range, the update region is further derived and expanded. The expansion process not only considers the time sequence of the timing block, but also combines factors such as message passing relationship, event triggering time, timing dependency relationship, etc., to ensure that the update range covers all related timing elements. The specific steps of S1.2 are as follows:

[0089] S1.2.1: Analyze the message passing and event triggering relationship between the timing blocks in the initial update range to obtain timing dependencies and time constraints;

[0090] First, view the message passing path in the timing diagram and analyze how messages pass between timing blocks to confirm the order and timing dependency of messages. For example, if a timing block sends a message that is the trigger condition for another timing block, there is a strong dependency relationship between them;

[0091] Then analyze the triggering time and order of events to confirm which events are triggered synchronously and which events need to wait for the completion of other events. The system maps these triggering relationships into timing dependency chains and performs time constraint calculations based on the triggering time of events;

[0092] Timing dependency refers to the execution of a timing block depending on the completion of other timing blocks. For example, the execution of timing block A may depend on the completion of a certain event triggered by timing block B. This dependency relationship determines the execution order and timing of the timing blocks. In addition to the dependency relationship, time constraints also involve time interval requirements between timing blocks. For example, there may be a time interval constraint between timing blocks A and B, requiring A to execute, and B must execute within a specified time range;

[0093] Identify which timing blocks and their events are interdependent and which timing blocks are independent, and then determine which timing blocks need to be considered together during the update process. The purpose of this step is to ensure that the timing diagram does not miss any key dependency relationships during the update, avoiding design errors due to inaccurate update ranges.

[0094] Specifically, the first step is to analyze the message passing paths in the sequence graph to clarify the message delivery order and dependencies between time-series blocks. Message path analysis reveals which time-series blocks have strong dependencies and which are independent. For example, if the output of time-series block A is the trigger condition for time-series block B, then A and B have a strong dependency, and their updates must be considered simultaneously. The timing relationships of event triggering determine which events must wait for other events to complete before triggering, and which events can be triggered in parallel. These triggering relationships are ultimately mapped to time-series dependency chains, thus forming the basis for time-constrained computation.

[0095] S1.2.2: Based on the time-series dependencies, derive the dynamic dependency chain between time-series blocks, generate message paths, and calculate the synchronization degree and dependency degree of the message paths in the time-series blocks;

[0096] Dependency chains derived from temporal dependencies represent the execution order between temporal blocks. This chain indicates that some temporal blocks can only begin after other temporal blocks have completed execution. For complex temporal graphs, dependency chains may form with multiple branches, determining the direction of update scope expansion.

[0097] A message path refers to the route taken by data or control signals from one timing block to another in a timing diagram. Generating message paths involves more than just identifying their existence; it also requires analyzing their characteristics, including the message delivery order, triggering timing, and delivery interval.

[0098] Synchronization level indicates whether time-series blocks need to execute simultaneously or wait at the same time. Dependency level indicates whether the execution of a time-series block depends on the state of other time-series blocks; the higher the dependency level, the stricter the execution order requirements of the time-series block on the other time-series blocks. By calculating these parameters, it is possible to further determine which time-series blocks must be executed synchronously and which time-series blocks can be executed independently, thereby accurately determining the scope of expansion.

[0099] Specifically, based on temporal dependencies, dynamic dependency chains between temporal blocks are derived. These dependency chains reflect the execution order and mutual influence between temporal blocks, clarifying which temporal blocks cannot be executed before the completion of other temporal blocks. For complex timing graphs, the dependencies between temporal blocks may exhibit multi-level or branching structures, thus requiring precise derivation of dependency chains to clarify the update scope of temporal blocks. Based on this, the generated message paths not only include the message delivery order but also analyze the timing characteristics, triggering moments, and delivery intervals of message delivery. Calculating these parameters helps to further determine which temporal blocks must be executed synchronously and which can be executed independently, thereby accurately expanding the update scope.

[0100] S1.2.3: According to the time constraints, analyze the time window of the time sequence block, and calculate the time sequence delay factor of the time sequence block, wherein the time sequence delay factor refers to the minimum delay time of the time sequence block in the message passing or event triggering process under the time limit of other time sequence blocks;

[0101] The time window represents the maximum time limit of the execution of the time sequence block at a certain time or time period. The size and range of the time window are obtained by analyzing the dependency relationship and constraint conditions between the time sequence blocks. For some time sequence blocks, their time windows may be limited by other time sequence blocks. For example, if time sequence block A requires completion within a certain time after the execution of B, the execution time of A will be limited by the time of B;

[0102] The time sequence delay factor is a measure of the influence of the time constraints of other time sequence blocks on the execution of a time sequence block. It represents the minimum delay time that a time sequence block is subjected to when it starts execution. For example, if time sequence block A depends on the completion of time sequence block B, and the execution time of B is delayed, the start time of A will be delayed accordingly. The calculation of the time sequence delay factor is based on the analysis results of the time window, which can effectively quantify the execution delay of each time sequence block;

[0103] S1.2.4: Aggregate the time sequence delay factors of all time sequence blocks, determine the parallel execution relationship between the time sequence blocks according to the time sequence delay factors, and calculate the time sequence expansion factor of the time sequence block according to the parallel blocks and message paths of the current time sequence block;

[0104] The aggregation of the time sequence delay factor is mainly used to identify the parallel execution relationship between the time sequence blocks in the time sequence diagram. By synthesizing the delay factors of all time sequence blocks, it can be determined which time sequence blocks can be executed in parallel and which time sequence blocks must be executed in series. The time constraints between the time sequence blocks that are executed in parallel are relatively loose, while the time constraints between the time sequence blocks that are executed in series are relatively tight;

[0105] In the time sequence diagram, different time sequence blocks may be executed independently in the same time period, which is called parallel execution. The parallel execution of time sequence blocks can be calculated by aggregating the time sequence delay factors. If the delay factors of multiple time sequence blocks do not affect each other, they can be executed in parallel, thereby reducing the total execution time;

[0106] The time sequence expansion factor is a comprehensive evaluation of the time sequence delay factors of the time sequence blocks in the time sequence diagram, which represents the expansion factor of the entire time sequence update range. It is calculated by considering the order of the parallel blocks, message paths and the sum of the time sequence delays of all time sequence blocks. The larger the time sequence expansion factor, the more complex the time sequence relationship in the expansion range, and the larger the expansion radius;

[0107] Specifically, the time constraints between the parallel executed timing blocks are looser, while the constraints between the serial executed timing blocks are stricter. By aggregating the timing delay factors, the execution relationship of the timing blocks in the timing diagram can be derived, providing a more accurate basis for extending the update range. By analyzing the relationship between parallel and serial execution, the execution efficiency of the timing diagram can be optimized, unnecessary execution delays can be reduced, and all relevant timing blocks can be properly updated.

[0108] S1.2.5: Sort the timing extension factors of all timing blocks, take the maximum timing extension factor as the extension radius, and superimpose it with the radius of the initial update range to obtain the update range, ensuring that the update range can fully cover all timing blocks and related elements that need to be updated, avoiding missing any timing blocks or events.

[0109] The formula for calculating the timing extension factor is:

[0110]

[0111] where A i represents the timing extension factor of timing block i, δ i represents the timing delay factor of timing block i, n represents the number of parallel blocks of timing block i, j represents a single event of timing block i, N represents the total number of events of timing block i, E j represents the trigger time of the jth event, T max represents the maximum delay within timing block i, l represents the single message path of timing block i, M represents the total number of message paths of timing block i, P l represents the load of the lth message path, P max represents the maximum load within timing block i, β l represents the dependency factor of the lth message path, θ l represents the timing synchronization factor of the lth message path.

[0112] Through comprehensive analysis of the dependency relationship between timing blocks, message passing order and time constraints, the initially selected update area can be effectively expanded, ensuring that the update range covers all affected timing blocks, avoiding missing any critical timing blocks or events. At the same time, the calculation of timing delay factor and timing extension factor can accurately quantify the execution relationship and dependency between timing blocks, ensuring that the update process of the timing diagram is more accurate and meets the design requirements.

[0113] By providing an interactive editing interface, users can make detailed modifications to the timing blocks to ensure the accuracy and reasonableness of the timing diagram. The pop-up editing box has multiple functional modules, each of which can fine-tune different aspects of the timing block. The pop-up editing box includes:

[0114] Attribute editing tool for displaying and modifying the attribute information of selected timing blocks, wherein the attribute information includes trigger timing, execution order, time interval and message path;

[0115] Trigger timing refers to the time at which a user can adjust the trigger of an event or timing block through the tool. For example, the trigger timing of a timing block can be delayed or advanced from the current time to ensure that the timing block can be executed according to the designed timing sequence;

[0116] Execution order refers to the execution order of timing blocks with multiple concurrent execution or dependency relationships, which can be adjusted by the user to meet specific business requirements;

[0117] Time interval refers to the minimum time interval between two timing blocks, which controls the time distribution of timing block execution. The tool allows users to manually adjust the time interval to ensure that the time relationship between timing blocks is within the specified constraints.

[0118] Message path is the communication path between timing blocks in a timing diagram, and the editing tool supports users to modify the sending order of messages or reassign the message delivery path to ensure that messages flow between timing blocks in the correct order.

[0119] Event trigger timing adjustment tool for adjusting the trigger timing of events in timing blocks and providing graphical display of the time relationship between event triggers;

[0120] The event trigger timing adjustment tool displays the trigger position of each event on the time axis, and users can adjust the trigger order and time position of events through operations such as dragging. When a user adjusts the trigger timing of an event, the system will automatically adjust the time interval between related events and prompt the user of possible timing constraints. This function helps users ensure that the timing constraints in the timing diagram are not violated, making event adjustment in the timing diagram more intuitive and accurate. Users can intuitively understand the time relationship between events, avoid errors caused by manual input of timing trigger times, and reduce design errors caused by timing conflicts.

[0121] Synchronization and dependency relationship editing tool for modifying the message delivery path between timing blocks and adjusting the dependency relationship between timing blocks;

[0122] The dependency relationship between timing blocks determines the execution order of timing blocks. The synchronization and dependency relationship editing tool allows users to redefine the dependency relationship between timing blocks and change the execution order of timing blocks. For example, some timing blocks may depend on the completion of other timing blocks before they can be executed, and users can adjust the dependency chain through the tool to make the timing diagram meet new business requirements or design requirements.

[0123] A structure preview tool is used to show a preview picture of the editing result during the editing process.

[0124] For the selected timing block and its related attributes, a pop-up editing box is used for detailed editing. Through the graphical operation provided by the interactive interface, the modification of timing blocks, events, message passing paths, etc. is completed, thereby realizing the rapid design and update of the timing diagram. The specific steps of S2 are as follows:

[0125] S2.1: Select the timing block to be edited through the interactive device, and modify the related attributes of the timing block in the pop-up editing box. The attributes include the name of the timing block, the event trigger timing, the time interval of message passing, and the trigger condition;

[0126] The timing block is the basic unit in the timing diagram, which contains information such as events, message paths, and time constraints between them. In the pop-up editing box, the modification of the related attributes is carried out for the selected timing block. The specific modification contents include:

[0127] The name of the timing block. By modifying the name of the timing block, different timing blocks can be clearly identified, helping to better manage the elements in the timing diagram. The timing block name is usually related to the function or module it carries. By modifying the name, the structural changes in the timing diagram design can be reflected.

[0128] Event trigger timing. The trigger timing of an event determines the execution order of events within a timing block. Modifying the trigger timing will directly affect the time point of the event in the timing diagram and its relative order with other events. This modification operation is particularly important when dealing with complex timing dependencies.

[0129] Time interval of message passing. The time interval of message passing represents the time delay of communication between events or timing blocks. By modifying the time interval, the efficiency and latency of message passing can be adjusted, which is particularly important in designing timing diagrams.

[0130] Trigger condition. The trigger condition of each event is usually related to the completion of other events or external signals. Modifying the trigger condition can redefine the activation condition of the event, change the dependency relationship between events, and thus affect the timing structure within the timing block.

[0131] S2.2: Through the graphical interface, drag or select the trigger order between events, and adjust the dependency relationship between events to modify the interaction relationship between timing blocks;

[0132] In the design of timing diagrams, the trigger order and dependency relationship between events are important manifestations of the interaction between timing blocks. Through the graphical interface, the trigger order between events can be intuitively adjusted, and the interaction relationship between timing blocks can be modified. The specific operations include:

[0133] Drag adjustment event trigger order, in the graphical interface, users can rearrange the trigger order of events through drag operation. The order of events determines the order of message passing in the timing diagram. Modifying the trigger order of events will affect the subsequent message path and event synchronization, especially in complex timing diagrams with multiple event triggers, order adjustment is crucial for the correctness and executability of the timing diagram.

[0134] Adjust the dependency between events, the dependency indicates that certain events must be triggered after other events are completed. By adjusting the dependency between events, the execution path of the timing diagram can be changed, and even the parallel execution or sequential execution of certain events can be changed. Changing the dependency is a key means to handle complex business logic and timing rules in the timing diagram.

[0135] Modify the interaction between timing blocks, the interaction between timing blocks is usually embodied through message passing and event triggering. By modifying the interaction, the overall structure of the timing diagram can be affected, especially when there are complex message passing paths and multiple dependencies, the modification of the interaction can effectively optimize the execution efficiency and correctness of the timing diagram.

[0136] S2.3: During editing, display the synchronization factor and delay factor of each event in the timing block in real time, and change the synchronization and delay relationship between events according to the synchronization factor and delay factor;

[0137] Specifically, a key feature of the timing diagram is the synchronization and delay of events. The synchronization factor and delay factor directly determine the execution mode and time relationship of events in the timing diagram. During the editing process of the timing block, the synchronization factor and delay factor are calculated and displayed in real time to ensure that the designed timing diagram meets the timing requirements and provides efficient and accurate time control.

[0138] The synchronization factor indicates the degree of simultaneous occurrence of multiple events. In a multi-event timing block, some events may be triggered simultaneously or need to be executed synchronously under certain conditions. The calculation of the synchronization factor helps to understand the time relationship between events and ensure their synchronization is correctly executed. For example, if the synchronization factor of multiple events is 1, it means that these events are triggered at the same time; if the synchronization factor is less than 1, it means that these events are staggered in time.

[0139] The delay factor indicates the time delay between event triggers. The calculation of the delay factor can accurately control the execution time of events and ensure that events are executed according to the predetermined timing. The delay factor is particularly important for timing diagrams with multiple event dependencies. By adjusting the delay factor, the execution efficiency of the timing diagram can be effectively optimized, avoiding unnecessary waiting or delay.

[0140] S2.4: Logical verification of the timing block and its timing properties, including time dependency, sequence of event trigger timing, and time interval of message passing.

[0141] The design and update of the timing diagram must follow strict timing constraints, otherwise it may lead to timing errors or logical conflicts. After the timing block and its properties are edited, logical verification must be performed on the timing block and its properties to ensure that the timing diagram meets the timing logic and design requirements. The specific verification contents include:

[0142] Time dependency verification, time dependency refers to the execution time of a timing block depends on the completion time of other timing blocks. If there are multiple time dependencies between timing blocks, it must be ensured that these dependencies will not conflict. The verification of time dependency can prevent parallel execution or sequential execution of timing conflicts, ensuring that events in the timing diagram are executed in the correct order.

[0143] Sequence of event trigger timing verification, the sequence of event triggering must meet the design requirements. In the timing block of multiple event triggers, if the sequence of events is improper, it may lead to incorrect message passing or logical execution. By verifying the sequence of trigger timing, it ensures that each event is triggered in the correct time sequence, avoiding logical inconsistencies.

[0144] Time interval verification of message passing, the time interval of message passing is usually related to factors such as event trigger timing, execution sequence, etc. By verifying the time interval of message passing, it can ensure that message passing will not cause errors due to too short or too long time interval. By verifying the time interval, it can effectively avoid timing problems caused by time constraint errors.

[0145] The logic generation block includes:

[0146] Standardized conversion tool, used to convert the modifications made to the timing block and its timing properties during the editing process into standardized timing logic fragments;

[0147] Timing verification tool, used to check the time dependency, event trigger sequence, and message passing path within the logic fragment, and to verify the functionality of the generated timing logic fragment;

[0148] Timing dependency conversion tool, used to analyze and convert the dependency relationship between the edited timing logic fragment and the original timing diagram;

[0149] Timing property synchronization tool, used to verify whether the timing properties of the updated timing block in the entire timing diagram meet the overall consistency and synchronization.

[0150] The S4 specific steps are as follows:

[0151] S4.1: When a new timing block or updated content is introduced, the spatial layout is adjusted according to the timing relationship between the timing blocks in the timing diagram, the event trigger timing, the message transmission path, and the timing attribute;

[0152] S4.2: By analyzing the timing dependency chain of each timing block, the relative order and connection relationship of the timing blocks are adjusted, a new message path is generated according to the dependency degree and timing attribute between the timing blocks, and the updated timing blocks are reconnected according to the dependency relationship;

[0153] S4.3: According to the time constraint of each timing block, the time overlap and parallel execution between the timing blocks are analyzed, and the execution order and spatial distribution between the timing blocks are adjusted.

[0154] Embodiment 2:

[0155] Please refer to Figure 2 The application provides an embodiment: a timing block-based architecture model timing diagram rapid design update verification system, which comprises a selection expansion module, an editing derivation module, a logic verification module, and a layout adjustment module;

[0156] The selection expansion module is configured with an intelligent expansion strategy, which is used to determine an initial update range, and expand the initial update range according to the time sequence of the timing blocks in the initial update range, the message transmission sequence, and the timing block dependency relationship;

[0157] The editing derivation module is used to edit the timing blocks and their timing attributes in a pop-up editing box, and the editing includes attribute modification of the timing blocks.

[0158] The logic verification module is used to convert the editing result into a standardized logic segment through a logic generation box.

[0159] The layout adjustment module is used to fuse the standardized logic segment with the original timing diagram according to a layout algorithm of the timing diagram.

[0160] The selection expansion module comprises:

[0161] An initial circumscription unit is used to determine an initial update range of a to-be-updated area by performing a selection operation in a timing diagram interface through an interactive device.

[0162] An intelligent update unit is used to dynamically expand the initial update range and generate a new to-be-updated area.

[0163] A region display unit is used to display the to-be-updated area in the form of a dynamic box.

[0164] The editing derivation module comprises:

[0165] Timing attribute editing unit: used for selecting and editing the relevant attributes of the timing block through the interactive device, such as event trigger timing, message transmission time interval, trigger condition, etc. The unit provides a graphical interface, and the user can operate through dragging, inputting or selecting.

[0166] Event order adjustment unit: used for adjusting the trigger order and dependency of each event in the timing block. Graphical dragging adjustment is supported, and the timing synchronization factor and delay factor of the event are automatically updated.

[0167] Synchronization dependency derivation unit: used for deriving and displaying the synchronization and dependency between timing blocks based on editing operations, calculating and displaying timing attributes such as synchronization factor and delay factor between events, to help designers evaluate the feasibility and consistency of the edited timing diagram.

[0168] The logic verification module comprises:

[0169] Timing logic generation unit: converts the timing block attribute modification result in the editing derivation module into a timing logic segment that meets the design specification, ensuring that the generated logic segment meets the timing constraint requirements.

[0170] Timing dependency verification unit: verifies whether the dependency of the generated timing logic segment meets the predetermined timing rules, especially the time dependency and message transmission order between timing blocks.

[0171] Timing consistency verification unit: performs timing consistency verification on the generated logic segment to ensure the coordination and consistency of all timing blocks, message paths and event trigger conditions in the global scope.

[0172] The layout adjustment module comprises:

[0173] Timing relationship analysis unit: analyzes the relative position and execution order between timing blocks according to the time order, event trigger timing and message transmission path in the timing diagram, and generates a reasonable spatial layout scheme.

[0174] Dependency adjustment unit: adjusts the relative order and connection mode of the timing blocks according to the dependency and timing attributes between the timing blocks, to ensure that the layout conforms to the actual timing flow and dependency structure.

[0175] Space optimization unit: optimizes the spatial distribution of the timing diagram according to the layout algorithm, avoids overlap and resource conflicts between timing blocks, and improves the readability of the graphical interface and user interaction experience.

[0176] Although the embodiments of the present application have been shown and described above, it is understood that the above-described embodiments are exemplary and are not to be construed as limiting the present application, and that variations, modifications, substitutions and changes can be made by those skilled in the art without departing from the scope of the present application.

Claims

1. A method for updating and verifying a timing diagram of an architecture model based on a timing block, characterized in that, The method comprises: selecting an area to be updated in a timing diagram interface through an interactive device, the area to be updated being displayed in the form of a dynamic box, the dynamic box comprising timing blocks, interaction relationships and timing attributes, the timing attributes comprising time intervals of message transmission, triggering time of events and transmission relationships between timing blocks; generating a pop-up editing box corresponding to the area to be updated according to the area to be updated, editing the timing blocks and their timing attributes in the pop-up editing box, the editing comprising attribute modification of the timing blocks; converting the editing result into a standardized logic segment through a logic generation box, and fusing the standardized logic segment with the original timing diagram according to a layout algorithm of the timing diagram; the selecting the area to be updated comprises: performing a selection operation in the timing diagram interface through the interactive device to determine an initial update range of the area to be updated, the selection operation comprising a frame selection operation, a timing block selection operation and a message path selection operation, wherein the message path selection operation comprises selecting message transmission paths and timing constraint relationships between timing blocks; expanding the initial update range according to time sequences of the timing blocks in the initial update range, message transmission sequences and timing block dependency relationships; highlighting the expanded area to be updated in the timing diagram interface through the dynamic box, performing timing logic verification, and if the verification is passed, marking the area to be updated, and if the verification is not passed, adjusting the update range according to the timing constraint relationships; the expanding the initial update range comprises: analyzing message transmission and event triggering relationships between the timing blocks in the initial update range to obtain timing dependency and time constraints; deriving dynamic dependency chains between the timing blocks according to the timing dependency, generating message paths, and calculating synchronization degrees and dependency degrees of the message paths in the timing blocks; analyzing the timing blocks through a time window according to the time constraints, and calculating timing delay factors of the timing blocks, wherein the timing delay factor refers to a minimum delay time of a timing block in a message transmission or event triggering process, which is limited by other timing blocks; aggregating the timing delay factors of all the timing blocks, determining parallel execution relationships between the timing blocks according to the timing delay factors, calculating timing expansion factors of the timing blocks according to the parallel blocks of the current timing block and the message paths; sorting the timing expansion factors of all the timing blocks, taking the maximum timing expansion factor as an expansion radius, superimposing the expansion radius with a radius of the initial update range, and obtaining the update range.

2. The method of claim 1, wherein the method is characterized by: a calculation formula of the timing expansion factor is: ， wherein, denotes a timing extension factor of timing block i, denotes a timing delay factor of timing block i, n denotes a number of parallel blocks of timing block i, j denotes a single event of timing block i, N denotes a total number of events of timing block i, denotes a triggering timing of the jth event, denotes a maximum latency within timing block i, l denotes a single message path of timing block i, M denotes a total number of message paths of timing block i, denotes a load amount of the lth message path, denotes a maximum load amount within timing block i, denotes a dependency factor of the lth message path, denotes a timing synchronization factor of the lth message path.

3. The method of claim 1, wherein the method is characterized by: the pop-up editing box comprises: an attribute editing tool for displaying and modifying attribute information of a selected timing block, wherein the attribute information comprises triggering time, execution sequence, time interval and message path; an event triggering time adjustment tool for adjusting triggering times of events in the timing block, and providing a graphical display of time relationships between event triggering; a synchronization and dependency relationship editing tool for modifying message transmission paths between the timing blocks, and adjusting dependency relationships between the timing blocks; a structure preview tool for displaying a preview screen of the editing result in the editing process.

4. The method of claim 3, wherein the method is characterized by: editing the time sequence block and its time sequence attributes in the pop-up editing box, including: selecting the time sequence block to be edited through the interactive device, and modifying the related attributes of the time sequence block in the pop-up editing box, the attributes including the name of the time sequence block, the event trigger timing, the time interval of message transmission and the trigger condition; dragging or selecting the trigger sequence between events through the graphical interface, and adjusting the dependency relationship between events to modify the interaction relationship between time sequence blocks; during the editing process, displaying the synchronization factor and the delay factor of each event in the time sequence block in real time, and changing the synchronization and delay relationship between events according to the synchronization factor and the delay factor; performing logical verification on the time sequence block and its time sequence attributes, including time dependency, sequence of event trigger timing and time interval of message transmission.

5. The method of claim 4, wherein the method further comprises: the logic generation box, including: a standardized conversion tool for converting the modifications made to the time sequence block and its time sequence attributes during the editing process into a standardized time sequence logic segment; a time sequence verification tool for checking the time dependency, trigger sequence of events and message transmission path in the logic segment, and performing functional verification on the generated time sequence logic segment; a time sequence dependency relationship conversion tool for analyzing and converting the dependency relationship between the edited time sequence logic segment and the original time sequence diagram; a time sequence attribute synchronization tool for verifying whether the time sequence attributes of the updated time sequence block in the entire time sequence diagram meet the overall consistency and synchronization.

6. The method of claim 5, wherein the method further comprises: the layout algorithm of the time sequence diagram, including: when a new time sequence block or updated content is introduced, adjusting the spatial layout according to the time sequence relationship between the time sequence blocks in the time sequence diagram, the event trigger timing, the message transmission path and the time sequence attributes; by analyzing the time sequence dependency chain of each time sequence block, adjusting the relative order and connection relationship of the time sequence blocks, generating new message paths according to the dependency degree and time sequence attributes between the time sequence blocks, and reconnecting the updated time sequence blocks according to the dependency relationship; according to the time constraints of each time sequence block, analyzing the time overlap and parallel execution between the time sequence blocks, and adjusting the execution order and spatial distribution between the time sequence blocks.

7. A system for updating and verifying the timing diagram of a block-based architecture model, based on a method for updating and verifying the timing diagram of a block-based architecture model according to any one of claims 1 to 6, characterized in that, the system includes a selection expansion module, an editing derivation module, a logic verification module and a layout adjustment module; the selection expansion module is configured with an intelligent expansion strategy, which is used to determine an initial update range, and expand the initial update range according to the time sequence of the time sequence blocks in the initial update range, the message transmission sequence and the time sequence block dependency relationship; the editing derivation module is used to edit the time sequence block and its time sequence attributes in the pop-up editing box, and the editing includes attribute modification of the time sequence block; the logic verification module is used to convert the editing result into a standardized logic segment through the logic generation box; the layout adjustment module is used to fuse the standardized logic segment with the original time sequence diagram according to the layout algorithm of the time sequence diagram.

8. The system of claim 7, wherein the system is configured to: the selection expansion module, including: an initial circumscription unit for performing selection operation in the time sequence diagram interface through the interactive device to determine an initial update range of the to-be-updated area; an intelligent update unit for dynamically expanding the initial update range and generating a new to-be-updated area; A region display unit is configured to display the region to be updated in the form of a dynamic box.

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