Pixel driving circuit and display panel

Abstract

The present application provides a pixel driving circuit and a display panel, comprising a light emitting element, a driving transistor for generating a driving current according to a data signal to drive the light emitting element to emit light, a storage capacitor for storing the data signal, an internal compensation transistor for compensating the threshold voltage of the driving transistor in response to a first write control signal, and an external compensation transistor electrically connected to the source of the light emitting control transistor and the driving transistor (for reading the electrical signal of the source of the driving transistor and compensating the threshold voltage of the driving transistor in response to a read-write control signal). The first write control signal is different from the second write control signal, thereby improving the reliability of data signal writing and the accuracy of the driving current.

Description

Technical Field

[0001] This invention relates to the field of display technology, and more specifically to pixel driving circuits and display panels. Background Technology

[0002] OLED (Organic Light-Emitting Diode) display panels are widely used due to their flexibility and other characteristics.

[0003] Among them, the pixel driving circuit of the OLED display panel is required to realize the functions of the display panel at different times, and in order to improve the reliability of the display panel operation, its timing design has high requirements. Summary of the Invention

[0004] This invention provides a pixel driving circuit and a display panel to improve the reliability of the display panel's function at different times.

[0005] This invention provides a pixel driving circuit, comprising:

[0006] Light-emitting elements;

[0007] A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light.

[0008] A data writing transistor is used to transmit the data signal to the driving transistor in response to a second write control signal;

[0009] A storage capacitor, electrically connected to the driving transistor, is used to store the data signal;

[0010] An internal compensation transistor is electrically connected between the gate and drain of the driving transistor and is used to compensate the threshold voltage of the driving transistor in response to a first write control signal, wherein the first write control signal is different from the second write control signal.

[0011] An external compensation transistor is electrically connected to the source of the light-emitting control transistor and the driving transistor. The external compensation transistor is used to respond to a read / write control signal to read the electrical signal at the source of the driving transistor and to compensate the threshold voltage of the driving transistor.

[0012] In some embodiments, the pixel driving circuit further includes:

[0013] A light-emitting control transistor is electrically connected between the light-emitting element and the driving transistor, and is used to transmit the driving current to the light-emitting element in response to a first light-emitting control signal;

[0014] A reset transistor, electrically connected to the storage capacitor and the data write transistor, is used to respond to a second light-emitting control signal to transmit a first signal to one end of the storage capacitor. The first signal is different from the second signal loaded at the source of the driving transistor.

[0015] In some embodiments, the pixel driving circuit has a data writing period in each frame, during which the first write control signal is different from the second write control signal.

[0016] During the data writing period, the data writing transistor is used to respond to the second write control signal to transmit the data signal to one end of the storage capacitor to turn on the driving transistor. The internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate and drain of the driving transistor.

[0017] In some embodiments, the pixel driving circuit has a light-emitting period in each frame, during which the first light-emitting control signal is different from the second light-emitting control signal, and the first write control signal is the same as the second write control signal.

[0018] During the light-emitting period, the reset transistor is used to respond to the second light-emitting control signal, and the data writing transistor is used to respond to the second write control signal to jointly maintain the voltage at one end of the storage capacitor as the voltage corresponding to the data signal. The internal compensation transistor is used to respond to the first write control signal to maintain the voltage at the other end of the storage capacitor as the voltage during the data writing period, so as to keep the driving transistor turned on. The light-emitting control transistor is used to respond to the first light-emitting control signal to electrically connect the light-emitting element and the driving transistor to transmit the driving current to the light-emitting element.

[0019] In some embodiments, the pixel driving circuit has a first reset period in each frame, during which the first write control signal is different from the second write control signal.

[0020] During the first reset period, the data write transistor is used to respond to the second write control signal to transmit a third signal to one end of the storage capacitor, and / or the reset transistor is used to respond to the second light emission control signal to transmit a first signal to one end of the storage capacitor to turn off the driving transistor, and the internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor.

[0021] In some embodiments, during the first reset period, the first light emission control signal is different from the first write control signal;

[0022] During the first reset period, the external compensation transistor is used to respond to the read / write control signal to transmit a fourth signal to the light-emitting control transistor, the light-emitting control transistor is used to respond to the first light-emitting control signal to transmit a second signal to the light-emitting element to reset the light-emitting element, and the internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor.

[0023] In some embodiments, the pixel driving circuit has a second reset period in each frame, during which the first light emission control signal is different from the first write control signal.

[0024] During the second reset period, the reset transistor is configured to respond to the second light emission control signal to transmit the first signal to one end of the storage capacitor, and / or, the data write transistor is configured to respond to the second write control signal to transmit the third signal to one end of the storage capacitor, the external compensation transistor is configured to respond to the read / write control signal to transmit the fourth signal to the source of the driving transistor, and the internal compensation transistor is configured to respond to the first write control signal to electrically connect the gate of the driving transistor and the source of the driving transistor so that the fourth signal is transmitted to the gate of the driving transistor to reset the driving transistor;

[0025] The light-emitting control transistor is used to electrically disconnect from the driving transistor in response to the first light-emitting control signal.

[0026] In some embodiments, the pixel driving circuit has a threshold voltage external detection period before the first frame, during which the first light emission control signal is different from the first write control signal;

[0027] During the external detection period of the threshold voltage, the reset transistor is used to respond to the second light emission control signal to transmit the first signal to one end of the storage capacitor, and / or, the data write transistor is used to respond to the second write control signal to transmit the third signal to one end of the storage capacitor, the internal compensation transistor is used to respond to the first write control signal to transmit the second signal to one end of the storage capacitor, and the external compensation transistor is used to respond to the read / write control signal to read the threshold voltage of the driving transistor;

[0028] The light-emitting control transistor is used to electrically disconnect from the driving transistor in response to the first light-emitting control signal.

[0029] In some embodiments, the pixel driving circuit has an external emission detection period before the first frame, located after the external detection period of the threshold voltage, during which the first write control signal is different from the second write control signal, and the first emission control signal is different from the second emission control signal.

[0030] During the external detection period of light emission, the data writing transistor is used to respond to the second write control signal to transmit the target data signal to the storage capacitor to turn on the driving transistor. The light emission control transistor is used to respond to the first light emission control signal to electrically connect the light emission element and the driving transistor. The external compensation transistor is used to respond to the read / write control signal to read the electrical signal of the light emission element. The target data signal is determined based on the data signal and the threshold voltage.

[0031] The internal compensation transistor is used to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor in response to the first write control signal, and the reset transistor is used to electrically disconnect the storage capacitor in response to the second light emission control signal.

[0032] In some embodiments, the pixel driving circuit has an external emission detection period before the first frame, during which the first write control signal is different from the second write control signal, and the first emission control signal is different from the second emission control signal.

[0033] During the external detection period of light emission, the data write transistor is used to respond to the second write control signal to transmit a third signal to one end of the storage capacitor to turn off the driving transistor. The external compensation transistor is used to respond to the read / write control signal to transmit a fourth signal to the light emission control transistor. The light emission control transistor is used to respond to the first light emission control signal to electrically connect the light emission element and the driving transistor so that the fourth signal is transmitted to the light emission element. The external compensation transistor is also used to respond to the read / write control signal to read the threshold voltage of the light emission element and to compensate the threshold voltage of the driving transistor.

[0034] The internal compensation transistor is used to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor in response to the first write control signal, and the reset transistor is used to electrically disconnect the storage capacitor in response to the second light emission control signal.

[0035] In some embodiments, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor.

[0036] In this configuration, the first write control pulse in the first write control signal overlaps with the read write control pulse in the read write control signal, and the start point of the first write control pulse is earlier than the start point of the corresponding read write control pulse.

[0037] In some embodiments, the second write control pulse of the second write control signal is used to turn on the data write transistor, and the second light emission control pulse of the second light emission control signal is used to turn on the reset transistor;

[0038] In this configuration, one of the second write control pulses in the second write control signal is staggered from one of the second light emission control pulses in the second light emission control signal that is close to the corresponding second write control pulse.

[0039] In some embodiments, the first light emission control pulse of the first light emission control signal is used to turn on the light emission control transistor, the read / write control pulse of the read / write control signal is used to turn on the external compensation transistor, and the first write control pulse of the first write control signal is used to turn on the internal compensation transistor.

[0040] Wherein, one of the first light emission control pulses in the first light emission control signal overlaps with one of the read / write control pulses in the read / write control signal, and is offset from one of the first write control pulses in the first write control signal that is close to the corresponding first light emission control pulse.

[0041] In some embodiments, the second write control pulse of the second write control signal is used to turn on the data write transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor.

[0042] In this configuration, one of the second write control pulses in the second write control signal is staggered from one of the read write control pulses in the read write control signal that is close to the corresponding second write control pulse, and the second write control pulse is located before the corresponding read write control pulse.

[0043] In some embodiments, the first light-emitting control pulse of the first light-emitting control signal is used to turn on the light-emitting control transistor;

[0044] Wherein, the first light emission control pulse in the first light emission control signal and the second write control pulse in the second write control signal are overlapped, and the starting point of the first light emission control pulse is earlier than or equal to the starting point of the corresponding second write control pulse, and the ending point of the first light emission control pulse is later than the ending point of the corresponding second write control pulse.

[0045] In some embodiments, the second light emission control pulse of the second light emission control signal is used to turn on the reset transistor, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor.

[0046] Wherein, a second light emission control pulse in the second light emission control signal overlaps with a first write control pulse in the first write control signal.

[0047] In some embodiments, the second write control pulse of the second write control signal is used to turn on the data write transistor, and the first write control pulse of the first write control signal is used to turn on the internal compensation transistor.

[0048] In this configuration, a second write control pulse in the second write control signal is interleaved with a first write control pulse in the first write control signal that is close to the corresponding second write control pulse, and the first write control pulse is located before the corresponding second write control pulse.

[0049] In some embodiments, the first light emission control pulse of the first light emission control signal is used to turn on the light emission control transistor, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read / write control pulse of the read / write control signal is used to turn on the external compensation transistor.

[0050] In the first light emission control signal, the first light emission control pulse is staggered from the first write control pulse that is close to the corresponding first light emission control pulse in the first write control signal, and is also staggered from the read / write control pulse that is close to the corresponding first light emission control pulse in the read / write control signal. The first light emission control pulse is located after the corresponding first write control pulse and the corresponding read / write control pulse.

[0051] Embodiments of the present invention also provide a display panel, including:

[0052] The panel body includes any of the pixel driving circuits described above;

[0053] A driver chip is electrically connected to the pixel driver circuit to drive the pixel driver circuit to operate.

[0054] In some embodiments, the panel body further includes a multi-stage gate driving circuit arranged in cascades;

[0055] The driver chip includes:

[0056] A timing controller, wherein each of the gate driving circuits is electrically connected between the timing controller and the corresponding plurality of pixel driving circuits, and is used to respond to a first control signal output by the timing controller to output a first light emission control signal, a second light emission control signal, a first write control signal or a second write control signal;

[0057] At least one source driver is electrically connected between the timing controller and the corresponding plurality of pixel driving circuits, for responding to a second control signal output by the timing controller to output the data signal.

[0058] This invention provides a pixel driving circuit and a display panel, based on a light-emitting element, a driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light, a storage capacitor for storing the data signal, an internal compensation transistor for responding to a first write control signal to compensate for the threshold voltage of the driving transistor, an electrical signal for responding to a read / write control signal to read the source of the driving transistor, and an external compensation transistor (electrically connected to the light-emitting control transistor and the source of the driving transistor) for compensating for the threshold voltage of the driving transistor. The first write control signal is set to be different from the second write control signal so that during the data writing period of each frame, the data signal is transmitted to one end of the storage capacitor to turn on the driving transistor, and the gate and drain of the driving transistor are electrically disconnected, thereby improving the reliability of data signal writing and the accuracy of the driving current. Attached Figure Description

[0059] To more clearly illustrate the technical solutions in the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0060] Figure 1 This is a schematic diagram of the structure of a display panel provided in an embodiment of the present invention.

[0061] Figure 2 This is a schematic diagram of the pixel driving circuit provided in an embodiment of the present invention.

[0062] Figure 3 , Figure 5 , Figure 8 , Figure 10 , Figure 12 These are waveform diagrams of some signals in the pixel driving circuit provided in the embodiments of the present invention.

[0063] Figure 4 , Figure 7 , Figure 9 , Figure 11 , Figures 13 to 18 These are schematic diagrams of the signal flow at certain stages of the pixel driving circuit provided in the embodiments of the present invention.

[0064] Figure 6 The potential V of the third node B in the pixel driving circuit B The curve showing the change at t1. Detailed Implementation

[0065] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0066] In the description of this invention, the terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In this document, the source and drain of a transistor are not distinguished and can be interchanged. Furthermore, it should be noted that the accompanying drawings only provide structures closely related to the invention, omitting some details less relevant to the invention. The purpose is to simplify the drawings and make the inventive points clear at a glance, not to indicate that the actual device is identical to the attached drawings. Figure 1 It is identical, but this is not a limitation of the actual device.

[0067] In this document, the term "embodiment" means that a particular feature, structure, or characteristic described in connection with an embodiment may be included in at least one embodiment of the invention. The appearance of this phrase at various points in the specification does not necessarily refer to the same embodiment, nor is it a separate or alternative embodiment mutually exclusive with other embodiments. It will be explicitly and implicitly understood by those skilled in the art that the embodiments described herein can be combined with other embodiments.

[0068] The present invention provides a pixel driving circuit and a display panel including the pixel circuit, wherein the display panel and the pixel driving circuit include, but are not limited to, the following embodiments and combinations thereof.

[0069] In some embodiments, such as Figure 1As shown, the display panel 100 includes: a panel body 10, including a pixel driving circuit 101 as described below; and a driving chip 20, electrically connected to the pixel driving circuit 101 to drive the pixel driving circuit 101 to operate. It can be understood that the driving chip 20 stores multiple instructions and multiple data, and the multiple instructions can control the transmission of multiple data to control the communication within the driving chip 20 and between the driving chip 20 and the panel body 10, thereby realizing the display of the image.

[0070] Specifically, such as Figure 1 As shown, the panel body 10 also includes a cascaded multi-stage gate driving circuit (included in the gate driving module 102). The driving chip 20 includes: a timing controller 201, each of the gate driving circuits being electrically connected between the timing controller 201 and the corresponding plurality of pixel driving circuits 101, for responding to a first control signal output by the timing controller 201 to output a gate signal (including the first light emission control signal EM1, the second light emission control signal EM2, the first write control signal WR1 or the second write control signal WR2 hereinafter); and at least one source driver 202, electrically connected between the timing controller 201 and the corresponding plurality of pixel driving circuits 101, for responding to a second control signal output by the timing controller 201 to output the data signal VDATA.

[0071] For ease of description, this example uses an array of multiple pixel driving circuits 101 arranged in n rows and m columns (n ​​and m are both positive integers). The gate driving module 102 can include at least n levels of gate driving circuits, such as... Figure 1 As shown, each gate driving circuit outputs a corresponding gate signal according to the first control signal. The n-level gate signals are transmitted to the n-row pixel driving circuit 101 through n gate lines (GL1 to GLn). The first control signal controls the gate driving module 102 so that the effective gate pulses in the n-level gate signals used to turn on the pixel driving circuit 101 can be arranged sequentially on the time axis to turn on the multiple rows of pixel driving circuits 101 in sequence. The source driver 202 can transmit multiple sets of data signals VDATA to the multiple columns of pixel driving circuits 101 through m data lines (DL1 to DLm). The data signal VDATA can include multiple data signals VDATA corresponding to multiple pixel driving circuits 101 in the same column. When the second control signal controls the source driver 202 to turn on each row of pixel driving circuits 101, the multiple data lines respectively receive multiple data voltages from the multiple pixel driving circuits 101 in that row. This causes the multiple data voltages to act on the multiple pixel driving circuits 101 in that row, so as to realize the light emission of multiple light-emitting elements in the multiple pixel driving circuits 101 in that row. By analogy, the light emission of all row light-emitting elements can be controlled in sequence to present a complete picture.

[0072] In some embodiments, such as Figure 2 As shown, the pixel driving circuit 101 includes: a light-emitting element (including a light-emitting element body and a light-emitting element capacitor Coled connected in parallel therewith; the light emission referred to below can be understood as light emission by the "light-emitting element body"); a driving transistor T1, used to generate a driving current according to the data signal VDATA to drive the light-emitting element to emit light; a data writing transistor T3, used to transmit the data signal VDATA to the driving transistor T1 in response to a second write control signal WR2; a storage capacitor Cs, electrically connected to the driving transistor T1, used to store the data signal VDATA; and an internal compensation transistor T2, electrically connected between the gate and the drain of the driving transistor T1, used to compensate the threshold voltage of the driving transistor T1 in response to a first write control signal WR1.

[0073] Furthermore, such as Figure 2 As shown, the pixel driving circuit 101 further includes an external compensation transistor T4, which is electrically connected to the source of the light-emitting control transistor T5 and the driving transistor T1. The external compensation transistor T4 is used to respond to the read / write control signal RD to read the electrical signal at the source of the driving transistor T1 and to compensate the threshold voltage of the driving transistor T1. Specifically, the gate of the external compensation transistor T4 is loaded with the read / write control signal RD, the source of the external compensation transistor T4 can be connected to the drain of the driving transistor T1, and the drain of the external compensation transistor T4 can be loaded with a fourth signal VMON.

[0074] When the driving transistor T1 is in the off state, the potential of the source of the driving transistor T1 is detected. The drain of the external compensation transistor T4 can be connected to an external compensation module. The external compensation module can combine the potential of the source of the driving transistor T1 and the magnitude of the second signal ELVDD loaded on the source of the driving transistor T1 to calculate the threshold voltage of the driving transistor T1 and perform corresponding compensation value calculation to react on the pixel driving circuit 101 to compensate the threshold voltage of the driving transistor T1.

[0075] The light-emitting element can be an electroluminescent element, including at least one of OLED and LED (Light-Emitting Diode). The multiple transistors in the pixel driving circuit 101 can be of the same or different types. For example, they can all be P-type transistors (their constituent material can be, but is not limited to, LTPS (Low Temperature Poly-Silicon)), all can be N-type transistors (their constituent material can be, but is not limited to, IGZO (Indium Gallium Zinc Oxide)), or some (e.g., including driving transistor T1 and light-emitting control transistor T5) can be P-type transistors, and the other part (e.g., including internal compensation transistor T2, data writing transistor T3, external compensation transistor T4, and reset transistor T6) can be N-type transistors. It should be noted that the type of each transistor is not limited in this invention; the purpose is to illustrate that it has a corresponding function, and the signals acting on it can be set according to the type and functional requirements of the transistor.

[0076] Furthermore, such as Figure 2 As shown, the pixel driving circuit 101 further includes: a light-emitting control transistor T5, electrically connected between the light-emitting element and the driving transistor T1, for responding to a first light-emitting control signal EM1 to transmit the driving current to the light-emitting element; and a reset transistor T6, electrically connected to the storage capacitor Cs and the data writing transistor T3, for responding to a second light-emitting control signal EM2 to transmit a first signal VREF to one end of the storage capacitor Cs, wherein the first signal VREF is different from the second signal ELVDD loaded at the source of the driving transistor T1.

[0077] like Figure 3 As shown, the pixel driving circuit 101 has a data writing period S2 in each frame. During the data writing period S2, the first write control signal WR1 is different from the second write control signal WR2. During the data writing period S2, the data writing transistor T3 is used to respond to the second write control signal WR2 to transmit the data signal VDATA to one end of the storage capacitor Cs to turn on the driving transistor T1. The internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate and drain of the driving transistor T1.

[0078] Specifically, such as Figure 2As shown, the source of data writing transistor T3 can be loaded with the data signal VDATA, the source of reset transistor T6 can be loaded with the first signal VREF, the gate of data writing transistor T3 is loaded with the second write control signal WR2, the gate of reset transistor T6 is loaded with the second light emission control signal EM2, the drain of data writing transistor T3 and the drain of reset transistor T6 can be connected to the first terminal of storage capacitor Cs through the first node N, the gate of driving transistor T1 and the drain of internal compensation transistor T2 can be connected to the second terminal of storage capacitor Cs through the second node Q; the gate of internal compensation transistor T2 is loaded with the first write control signal WR1; the source of driving transistor T1 is loaded with the second signal ELVDD, the gate of light emission control transistor T5 is loaded with the first light emission control signal EM1, the source of light emission control transistor T5 is connected to the drain of driving transistor T1 and the source of internal compensation transistor T2 through the third node B, the drain of light emission control transistor T5 can be connected to the anode of light emission element, and the cathode of light emission element can be grounded (i.e., ground voltage ELVSS is applied).

[0079] Among them, the reset transistor T6 can be used to reset the potential VN of the first node N, the data writing transistor T3 can be used to transmit the data signal VDATA to the storage capacitor Cs, the internal compensation transistor T2 can be used to store the threshold voltage of the driving transistor T1 in the storage capacitor Cs, the driving transistor T1 can generate a driving current under the action of the data signal VDATA, and the light-emitting control transistor T5 is used to turn on to transmit the driving current to the light-emitting element in order to control the light-emitting element to emit light.

[0080] To better illustrate the above-mentioned functions of the pixel driving circuit 101 of the present invention, it is assumed here that all transistors in the pixel driving circuit 101 are P-type transistors (it can be considered that if the signal loaded on its gate is at the corresponding low potential, it can be used to control its turn-on, and if it is at the corresponding high potential, it can be used to control its turn-off; the high potentials of multiple signals can be equal or unequal, and the low potentials of multiple signals can be equal or unequal). The values ​​of the first signal VREF, the second signal ELVDD, the third signal VGMP, and the fourth signal VMON can also be represented by VREF, ELVDD, VGMP, and VMON, respectively, and VREF, ELVDD, and VGMP are at high potentials (used to control the P-type transistor to turn off), and VMON is at low potentials (used to control the P-type transistor to turn on). The working period of the pixel driving circuit 101 is described as follows.

[0081] (1) Threshold voltage external detection time period t1: combined with Figure 4 and Figure 5As shown, the first light-emitting control signal EM1 and the second write control signal WR2 are both at high potentials, controlling the light-emitting control transistor T5 and the data writing transistor T3 to be turned off. The first write control signal WR1, the second light-emitting control signal EM2, and the read / write control signal RD are all at low potentials, controlling the internal compensation transistor T2, the reset transistor T6, and the external compensation transistor T4 to be turned on. The first signal VREF is transmitted to the first node N through the reset transistor T6 to maintain the potential VN of the first node N. Before this, the second node Q can be reset to a low potential (for example, by turning on the internal compensation transistor T2 and the external compensation transistor T4, the first node Q, which is at a low potential, can be reset to a low potential). The four signals VMON are transmitted to the second node Q, so it can be considered that the driving transistor T1 is turned on. The second signal ELVDD is transmitted to the second node Q through the driving transistor T1 and the internal compensation transistor T2 to charge the storage capacitor Cs. The potential VQ of the second node Q gradually rises until the difference between it and the potential of the source of the driving transistor T1 (equal to ELVDD) is equal to the first threshold voltage Vth1 of the driving transistor T1, that is, "VQ-ELVDD=Vth1". At this time, the driving transistor T1 is turned off. Therefore, the potential VQ of the second node Q can gradually approach ELVDD+Vth1 (Vth1<0) from its initial potential (which can be close to VMON). Figure 6 As shown, the curve of the potential VB of the third node B during this period can be represented. Since the internal compensation transistor T2 is turned on, the external compensation module can obtain VB, i.e., VQ, through the external compensation transistor T4.

[0082] Furthermore, the threshold voltage external detection period t1 can be divided into a first sub-period t11 and a second sub-period t12 following the first sub-period t11, such as... Figure 6 As shown, the first sub-period t11 can be understood as the period when VQ changes significantly. At this time, the driving transistor T1 is still far from reaching the cutoff state. The second sub-period t12 can be understood as the period when VQ is relatively stable (close to ELVDD-|Vth1|). Therefore, the duration of the first write control signal WR1 at the corresponding low potential (unknown, which can be set according to multiple experimental values ​​or empirical values) needs to be long enough to ensure that it can reach the second sub-period t12. In order to reduce the power consumption of the external compensation module in detecting Vth1, the read / write control signal RD can be set to the corresponding low potential only in the second sub-period t12 to turn on the external compensation transistor T4 and enable the external compensation module to work.

[0083] Therefore, it can be seen that a first write control pulse p1 in the first write control signal WR1 overlaps with a read / write control pulse p2 in the read / write control signal RD, and the starting point of the first write control pulse p1 is earlier than the starting point of the corresponding read / write control pulse p2; for example Figure 5As shown, during the detection period t1 outside the threshold voltage, the first write control pulse p1 can cover the first sub-period t11, but the read / write control pulse p2 can only cover the second sub-period t12.

[0084] Specifically, the pixel driving circuit 101 has a threshold voltage external detection period t1 before the first frame (which can be understood as the first frame displayed after the display panel 100 is powered on). In conjunction with the above discussion, during the threshold voltage external detection period t1, the first light emission control signal EM1 is different from the first write control signal WR1. Specifically, the reset transistor T6 is used to respond to the second light emission control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs, and / or, the data write transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to one end of the storage capacitor Cs, the internal compensation transistor T2 is used to respond to the first write control signal WR1 to transmit the second signal ELVDD to one end of the storage capacitor Cs, and the external compensation transistor T4 is used to respond to the read / write control signal RD to read the threshold voltage (the aforementioned first threshold voltage Vth1) of the driving transistor T1; wherein, the light emission control transistor T5 is used to respond to the first light emission control signal EM1 to electrically disconnect from the driving transistor T1.

[0085] Understandable. Figure 4 and Figure 5 The illustration uses the reset transistor T6 responding to the second light-emitting control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs (the first node N, i.e., the first end of the storage capacitor Cs) as an example. Its function is to maintain the potential of the first end of the storage capacitor Cs, allowing for stable charging of the storage capacitor Cs. Similarly, ... Figure 4 and Figure 5 Alternatively, this method can be replaced by setting the second write control signal WR2 to a corresponding low potential to transmit the third signal VGMP to the first terminal of the storage capacitor Cs.

[0086] Therefore, during this period, either the second write control signal WR2 or the second light emission control signal EM2 can be set to the corresponding low potential; however, the first light emission control signal EM1 should be different from the first write control signal WR1. For example, the former can be set to the corresponding high potential to turn off the light emission control transistor T5 to prevent the light emission element from emitting light, while the latter can be set to the corresponding low potential to turn on the internal compensation transistor T2 to charge the second node Q.

[0087] Specifically, the threshold voltage external detection period t1 after the i1th power-on (i1 is a positive integer) can be used to detect the threshold voltage to obtain the i1th VQ (referred to as VQ1, close to ELVDD-|Vth1|), and the threshold voltage external detection period t1 after the i2th power-on (i2 is a positive integer greater than i1) can be used to detect the i2th VQ (referred to as VQ2, close to ELVDD-|Vth2|), where Vth2 is the driving crystal at the i2th power-on. The threshold voltage of transistor T1 is called the second threshold voltage Vth2. Then, for the i2th power-on compared to the i1th power-on, the absolute value of the offset ΔVth of the threshold voltage of the driving transistor T1 is approximately equal to |VQ1-VQ2|. Therefore, for the i2th power-on compared to the i1th power-on, the absolute value of the compensation value ΔVDATA of the data signal VDATA can be positively correlated with ΔVth. Considering the influence of detection accuracy, the absolute value of ΔVDATA can be equal to k1*|ΔVth|, where k1 is greater than 0.

[0088] It should be noted that, in order to improve the consistency of detection standards, VQ can be measured at a time when VQ is relatively stable during the external detection period t1 of the threshold voltage after the i1th and i2th power-on.

[0089] (2) External luminescence detection period t2: combined with Figure 7 and Figure 8As shown, the first write control signal WR1 and the second light emission control signal EM2 are both at high potentials to control the internal compensation transistor T2 and the reset transistor T6 to be turned off. The second write control signal WR2, the first light emission control signal EM1, and the read / write control signal RD are all at low potentials to control the reset transistor T6, the light emission control transistor T5, and the external compensation transistor T4 to be turned on. Since the corresponding ΔVDATA can be determined after the threshold voltage external detection period t1 after this (second and subsequent) power-on, in order to avoid the influence of the threshold voltage deviation of the driving transistor T1 on the brightness of the light emission element, a new data voltage "VDATA+ΔVDATA" can be superimposed on the theoretical data voltage as the data voltage and loaded into the data. The source of the write transistor T3 is used to transmit data to the first node N through the write transistor T3, so that the change in the potential VN of the first node N is "(VDATA+△VDATA)-VREF". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q will also have the same change, so the potential of the second node Q "ELVDD-|Vth2|+(VDATA+△VDATA)-VREF" is also related to the new data voltage. At this time, the drive transistor T1 is also turned on, which can be considered to be working in the saturation region. After the light-emitting control transistor T5 is turned on, the new drive current generated by the drive transistor T1 (related to the new data voltage) flows into the light-emitting element. At this time, the potential of the third node B can be detected by the external compensation module.

[0090] Specifically, this can be understood as the pixel driving circuit 101 having a light emission external detection period t2 before the first frame, located after the threshold voltage external detection period t1. During this light emission external detection period t2, as discussed above, the first write control signal WR1 is different from the second write control signal WR2, and the first light emission control signal EM1 is different from the second light emission control signal EM2. Specifically, the data writing transistor T3 responds to the second write control signal WR2 to transmit the target data signal VDATA (i.e., "VDATA+ΔVDATA") to the storage capacitor Cs, thereby turning on the driving transistor T1. The body transistor T5 is used to respond to the first light-emitting control signal EM1 to electrically connect the light-emitting element and the driving transistor T1. The external compensation transistor T4 is used to respond to the read / write control signal RD to read the electrical signal of the light-emitting element (i.e., the potential of the third node B). The target data signal VDATA is determined based on the data signal VDATA and the threshold voltage. The internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 from the output terminal of the driving transistor T1. The reset transistor T6 is used to respond to the second light-emitting control signal EM2 to electrically disconnect from the storage capacitor Cs.

[0091] During this period, turning off the reset transistor T6 can prevent the first signal VREF from being transmitted to the first node N and affecting its potential, and turning off the internal compensation transistor T2 can prevent the potential of the second node Q from affecting the potential of the third node B.

[0092] Therefore, it can be seen that a second write control pulse p3 in the second write control signal WR2 is staggered from a second light emission control pulse p4 in the second light emission control signal EM2 that is close to the corresponding second write control pulse p3; for example... Figure 5 As shown, the second light-emitting control pulse p4 covers the external detection period t1 of the threshold voltage, while the second write control pulse p3 is not set during the external detection period t1 of the threshold voltage; for example... Figure 8 As shown, the second write control pulse p3 covers the external emission detection period t2, while the second emission control pulse p4 is not set during the external emission detection period t2; or, for example, Figure 9 As shown, the second light emission control pulse p4 covers the light emission external detection period t2, while the second write control pulse p3 is not set during the light emission external detection period t2.

[0093] Specifically, in this embodiment, the external light emission detection period t2 after the j1st power-on (j1 is a positive integer) (which must be preceded by a corresponding threshold voltage external detection period t1) can be used to detect and obtain the VB of the j1st power-on (referred to as VB1, which is close to the anode potential of the light-emitting element during the j1st light emission). Similarly, the external light emission detection period t2 after the j2th power-on (j2 is a positive integer greater than j1) can be used to detect and obtain the VB of the j2nd power-on (referred to as VB2, which is close to the anode potential of the light-emitting element during the j2nd light emission). j1 and j2 can be compared... The terms j2 and j2 can be the same or different. That is, in this embodiment, there must be a corresponding threshold voltage external detection period t1 before the external detection period t2 of light emission. However, there is not a corresponding external detection period t2 of light emission after every external detection period t1 of threshold voltage. That is, the frequency of external detection of light emission can be less than the frequency of external detection of threshold voltage. Therefore, compared with the j1st power-on, the absolute value of the change in anode potential of the light-emitting element when it emits light under the same "VDATA+△VDATA" action can be positively correlated with the absolute value of the offset of VB △VB. If other factors are not considered, the two can be considered equal.

[0094] It should be noted that due to the leakage current of the internal compensation transistor T2, the brightness of the light-emitting element will continuously decrease during the process of the external compensation module detecting the potential of the third node B, and the detected potential of the third node B will also continuously decrease. Based on this, the internal compensation transistor T2 can be set to include two transistors connected in series, and the gates of the two transistors are shorted to serve as the gate of the internal compensation transistor T2. The drain of one transistor is connected to the second node Q, and the source of the other transistor is connected to the third node B. Similarly, in order to improve the consistency of the detection standard, VB can be measured at the time corresponding to the same leakage current level of VB during the external detection period t2 after the j1st and j2th power-on.

[0095] Of course, in other embodiments, combined with Figure 9 and Figure 10As shown, the pixel driving circuit 101 may also have an external emission detection period t2 before the first frame (the aforementioned threshold voltage external detection period t1 may not be set before it). During the external emission detection period, the first write control signal WR1 is different from the second write control signal WR2, and the first emission control signal EM1 is different from the second emission control signal EM2. Specifically, the data writing transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to one end of the storage capacitor Cs (i.e., the first node N) to turn off the driving transistor T1. The external compensation transistor T4 is used to respond to the read / write control signal RD to transmit the fourth signal VMON to the storage capacitor Cs. The light-emitting control transistor T5 is used to respond to the first light-emitting control signal EM1 to electrically connect the light-emitting element and the driving transistor T1 so that the fourth signal VMON is transmitted to the light-emitting element. The external compensation transistor T4 is also used to respond to the read / write control signal RD to read the threshold voltage of the light-emitting element and to compensate the threshold voltage of the driving transistor T1. The internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate and output terminal of the driving transistor T1. The reset transistor T6 is used to respond to the second light-emitting control signal EM2 to electrically disconnect from the storage capacitor Cs.

[0096] The difference between this embodiment and the previous embodiment's external light emission detection period t2 is that here, the high-potential third signal VGMP, instead of the data signal VDATA, is transmitted to the first node N through the activated data writing transistor T3. Similarly, the change in the potential VN of the first node N at this time is "VGMP-VREF". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q will also have the same change, making the potential of the second node Q higher at this time, causing the driving transistor T1 to turn off, making the driving current close to 0. At this time, the external detection module can transmit the fourth signal VMON to the anode of the light-emitting element through the activated external compensation transistor T4 and the light emission control transistor T5. It can be considered that the potential of the fourth signal VMON is still higher than the ground voltage ELVSS, so that the light-emitting element is still turned on, and the external detection module can still measure the anode potential of the light-emitting element when it emits light.

[0097] In this embodiment, turning off the reset transistor T6 can prevent the first signal VREF from being transmitted to the first node N and affecting its potential, and turning off the internal compensation transistor T2 can prevent the potential of the second node Q from affecting the potential of the third node B.

[0098] In this embodiment, the change in anode potential of the light-emitting element when it emits light under the same fourth signal VMON can be measured by referring to the absolute value of the change in anode potential of the light-emitting element when it emits light under the same "VDATA+△VDATA" signal in the previous embodiment.

[0099] Therefore, it can be seen that a first light-emitting control pulse p5 in the first light-emitting control signal EM1 overlaps with a read-write control pulse p2 in the read-write control signal RD, and is offset from a first write control pulse p1 in the first write control signal WR1 that is close to the corresponding first light-emitting control pulse p5; for example Figure 8 and Figure 10 As shown, the first light emission control pulse p5 and the read / write control pulse p2 both cover the light emission external detection period t2, while the first write control pulse p1 is not set during the light emission external detection period t2.

[0100] It should be noted that the pixel driving circuits 101 located in the same row can be controlled by the same read / write control signal RD. Each read / write control signal RD can control the opening and closing of the corresponding multiple external compensation transistors T4, which is positively correlated with the row scanning period. In this case, if the above-mentioned threshold voltage external detection period t1 and light emission external detection period t2 are also set before multiple frames (not the first frame), in order to improve the detection accuracy of the external detection module in at least one of the above-mentioned threshold voltage external detection period t1 and light emission external detection period t2, the period of the read / write control signal RD can be set to be longer. This can be achieved by frequency reduction.

[0101] (3) First reset time period t3 (including first sub-time period S0-1 and second sub-time period S0-2): combined with Figure 11 and Figure 12 As shown, in the first sub-time period S0-1, the second light emission control signal EM2, the first write control signal WR1, and the read / write control signal RD are all at high potentials to control the reset transistor T6, the internal compensation transistor T2, and the external compensation transistor T4 to be turned off. The first light emission control signal EM1 and the second write control signal WR2 are at low potentials to control the internal compensation transistor T2 and the data write transistor T3 to be turned on. For ease of description, this is based on... Figure 7The above-described embodiment is used as a premise for discussion. At this time, the third signal VGMP is transmitted to the first node N through the data writing transistor T3. At this time, the change in the potential VN of the first node N is "VGMP-(VDATA+△VDATA)". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q will also have the same change, making the potential of the second node Q become "ELVDD-|Vth2|+(VDATA+△VDATA)-VREF+VGMP-(VDATA+△VDATA)", that is, "ELVDD-|Vth2|-VREF+VGMP". Since the second signal ELVDD and the third signal VGMP are at high potentials, the potential of the gate of the driving transistor T1 can be considered to be close to the dark state voltage. The driving transistor T1 is close to the off state. At this time, there is a very small dark state current flowing through the light-emitting element.

[0102] In the second sub-time period S0-2, combined Figure 13 and Figure 12 As shown, the second light-emitting control signal EM2, the first write control signal WR1, and the second write control signal WR2 are all at high potentials to control the reset transistor T6, the internal compensation transistor T2, and the data write transistor T3 to be turned off. The first light-emitting control signal EM1 and the read / write control signal RD are both at low potentials to control the internal compensation transistor T2 and the external compensation transistor T4 to be turned on. At this time, the first node N and the second node Q can be maintained at their previous potentials respectively. The driving transistor T1 is still turned off. The fourth signal VMON, which is at a low potential, is transmitted to the anode of the light-emitting element (i.e., the fourth node C) through the turned-on external compensation transistor T4 and light-emitting control transistor T5 to reset the potential.

[0103] Among them, combined Figure 11 and Figure 12 As shown, this can be understood as the pixel driving circuit 101 having the aforementioned first reset period t3 in each frame. The first sub-period S0-1 in the first reset period t3 is specifically manifested as follows: the data writing transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to one end of the storage capacitor Cs, and / or, the reset transistor T6 is used to respond to the second light emission control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs to turn off the driving transistor T1, and the internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the output terminal of the driving transistor T1.

[0104] This stage involves applying a high-potential third signal VGMP to the driving transistor T1 to control its shutdown, thereby avoiding a large drive current. Furthermore, the internal compensation transistor T2 disconnects the gate and drain of the driving transistor T1 to prevent the potentials of the third node B and the fourth node C from being affected by the potential of the second node Q. As discussed above, this differs from... Figure 11 In the embodiment shown, the reset transistor T6 can also be turned on to transmit the first signal VREF, which is at a high potential, to the first node N. That is, at least one of the data writing transistor T3 and the reset transistor T6 can be turned on, which can raise the second node Q to a higher potential to turn off the driving transistor T1.

[0105] Following the first sub-period S0-1, combined with Figure 13 and Figure 12 As shown, in the second sub-period S0-2 of the first reset period t3, the first light emission control signal EM1 is different from the first write control signal WR1. Specifically, the external compensation transistor T4 is used to respond to the read / write control signal RD to transmit the fourth signal VMON to the light emission control transistor T5. The light emission control transistor T5 is used to respond to the first light emission control signal EM1 to transmit the second signal ELVDD to the light emission element to reset the light emission element. The internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically disconnect the gate of the driving transistor T1 and the output terminal of the driving transistor T1.

[0106] This stage involves resetting the fourth node C (i.e., the anode of the light-emitting element) by transmitting the low-potential fourth signal VMON. Similarly, the data writing transistor T3, the reset transistor T6, and the internal compensation transistor T2 are all turned off to avoid affecting the reset of the potential of the fourth node C.

[0107] Therefore, it can be seen that a second write control pulse p3 in the second write control signal WR2 is staggered from a read / write control pulse p2 in the read / write control signal RD that is close to the corresponding second write control pulse p3, and the second write control pulse p3 is located before the corresponding read / write control pulse p2; for example Figure 12 As shown, the second write control pulse p3 is located in the first sub-period S0-1 of the first reset period t3, and the read / write control pulse p2 is located in the first sub-period S0-1 of the corresponding first reset period t3.

[0108] Furthermore, a first light-emitting control pulse p5 in the first light-emitting control signal EM1 overlaps with a second write control pulse p3 in the second write control signal WR2, and the start point of the first light-emitting control pulse p5 is earlier than or equal to the start point of the corresponding second write control pulse p3, and the end point of the first light-emitting control pulse p5 is later than the end point of the corresponding second write control pulse p3; for example Figure 12 As shown, the second write control pulse p3 is located in the first sub-period S0-1 of the first reset period t3, and the first light emission control pulse p5 covers the entire first reset period t3.

[0109] (4) Second reset period S0-3: combined with Figure 14 and Figure 12 As shown, the first light-emitting control signal EM1 and the second write control signal WR2 are both at high potentials, which control the light-emitting control transistor T5 and the data writing transistor T3 to be turned off. The second light-emitting control signal EM2, the first write control signal WR1, and the read / write control signal RD are all at low potentials, which control the reset transistor T6, the internal compensation transistor T2, and the external compensation transistor T4 to be turned on. At this time, the fourth signal VMON, which is at a low potential, is transmitted to the second node Q through the turned-on external compensation transistor T4 and internal compensation transistor T2, driving transistor T1 to turn on. At the same time, the first signal VREF, which is at a high potential, is transmitted to the first node N through the turned-on reset transistor T6 to maintain the potential of the first end of the storage capacitor Cs, which is conducive to the charging of the storage capacitor Cs. This allows the potential of the second end of the storage capacitor Cs (the second node Q) to be charged and stabilized, thereby realizing the reset.

[0110] This can be understood as the pixel driving circuit 101 having the aforementioned second reset period S0-3 in each frame (which may be located after the corresponding first reset period t3). During the second reset period S0-3, the first light emission control signal EM1 is different from the first write control signal WR1. During the second reset period S0-3, the reset transistor T6 is used to respond to the second light emission control signal EM2 to transmit the first signal VREF to one end of the storage capacitor Cs. Figure 14 (This is only an example for illustration only), and / or, the data write transistor T3 is used to respond to the second write control signal WR2 to transmit the third signal VGMP to the storage capacitor Cs ( Figure 14(Not shown in the diagram) At one end, the external compensation transistor T4 is used to respond to the read / write control signal RD to transmit the fourth signal VMON to the source of the driving transistor T1. The internal compensation transistor T2 is used to respond to the first write control signal WR1 to electrically connect the gate of the driving transistor T1 and the source of the driving transistor T1, so that the fourth signal VMON is transmitted to the gate of the driving transistor T1 to reset the driving transistor T1. The light-emitting control transistor T5 is used to respond to the first light-emitting control signal EM1 to electrically disconnect from the driving transistor T1.

[0111] This stage involves resetting the second node Q by transmitting the fourth signal VMON to it, and requires either the reset transistor T6 or the data writing transistor T3 to be turned on in order to maintain the potential of the first node N, which is beneficial for resetting the potential of the second node Q.

[0112] Specifically, the third signal VGMP discussed throughout the text can be understood as a signal independent of the data signal VDATA; it can also be understood as a part of the first signal VREF, that is, the signal loaded at the source of the data writing transistor T3 can always be the first signal VREF, and as... Figure 3 and Figure 12 As shown, the first signal VREF is equal to the third signal VGMP in the corresponding time period. This is consistent with the circuit diagrams for S0-1, S0-2, and S0-3 above. Figure 12 As shown in the timing diagram, since the source of the data transistor in S0-1 and S0-2 needs to be loaded with the third signal VGMP, the first signal VREF can be set to be equal to the value of the third signal VGMP in S0-1 and S0-2. In S0-3, the data writing transistor T3 can be turned off, so the specific value of the first signal VREF is not limited. For example, it can be equal to the value of the first signal VREF. Combining the above discussion, in t1, the first signal VREF can be set to be equal to the third signal VGMP or to be a valid data signal.

[0113] (5) Threshold voltage internal detection period S1: combined with Figure 15 and Figure 12As shown, the first light-emitting control signal EM1, the second write control signal WR2, and the read / write control signal RD are all at high potentials to control the light-emitting control transistor T5, the data writing transistor T3, and the external compensation transistor T4 to be turned off. The second light-emitting control signal EM2 and the first write control signal WR1 are both at low potentials to control the reset transistor T6 and the internal compensation transistor T2 to be turned on. At this time, the first signal VREF, which is at a high potential, is transmitted to the first node N through the turned-on reset transistor T6. The driving transistor T1 remains on. The second signal ELVDD, which is at a high potential, charges the second node Q through the driving transistor T1 and the turned-on internal compensation transistor T2. When the potential VQ of the second node Q gradually rises to the point where the difference between it and the potential of the source of the driving transistor T1 (equal to ELVDD) is equal to the third threshold voltage Vth3 of the driving transistor T1 at this time (which can be equal to Vth2), that is, "VQ-ELVDD=Vth3", the driving transistor T1 is turned off. Therefore, the potential VQ of the second node Q gradually approaches ELVDD+Vth3 (Vth3<0).

[0114] Unlike T1, S1 only stores the current third threshold voltage Vth3 of the driving transistor T1 at the second node Q, without turning on the external compensation transistor T4 to detect it; each frame can include the above S0-1, S0-2, and S0-3, and S1 can be performed after S0-3 of each frame to "detect" the threshold voltage of the driving transistor T1 in this frame.

[0115] Therefore, it can be seen that the second light emission control pulse p4 in the second light emission control signal EM2 overlaps with the first write control pulse p1 in the first write control signal WR1; for example... Figure 12 As shown, the second light emission control pulse p4 and the first write control pulse p1 both cover the detection period S1 within the threshold voltage.

[0116] (6) Data writing period S2: combined with Figure 16 and Figure 12As shown, the first light-emitting control signal EM1, the second light-emitting control signal EM2, the first write control signal WR1, and the read / write control signal RD are all at high potentials to control the light-emitting control transistor T5, the reset transistor T6, the internal compensation transistor T2, and the external compensation transistor T4 to be turned off. The second write control signal WR2 is at a low potential to control the data writing transistor T3 to be turned on. At this time, the low-potential data signal VDATA (which is the valid data signal VDATA at this time) is transmitted to the first node N through the turned-on data writing transistor T3, so that the change in the potential VN of the first node N is "VDATA-VREF". Due to the coupling effect of the storage capacitor Cs, the potential of the second node Q will also have the same change. Therefore, the potential VQ of the second node Q is "ELVDD-|Vth3|+VDATA-VREF". It can be seen that the potential of the second node Q includes the valid data signal VDATA in the data signal VDATA and the third threshold voltage of the driving transistor T1 at this time. At this time, the driving transistor T1 is turned on.

[0117] Specifically, as discussed above, during the data writing period S2, the first write control signal WR1 is different from the second write control signal WR2. Specifically, the data writing transistor T3 responds to the second write control signal WR2 to transmit the data signal VDATA to one end of the storage capacitor Cs to turn on the driving transistor T1. The internal compensation transistor T2 responds to the first write control signal WR1 to electrically disconnect the gate and drain of the driving transistor T1, preventing the high-potential second signal ELVDD from charging the second node Q through the driving transistor T1 and the internal transistor, thus preventing the potential of the second node Q from retaining the data signal VDATA and the third threshold voltage of the driving transistor T1 at this time.

[0118] Therefore, it can be seen that a second write control pulse p3 in the second write control signal WR2 is interleaved with a first write control pulse p1 in the first write control signal WR1 that is close to the corresponding second write control pulse p3, and the first write control pulse p1 is located before the corresponding second write control pulse p3; for example Figure 12 As shown, the second write control pulse p3 can be located in the data write period S2, but the first write control pulse p1 is not set during the data write period S2.

[0119] (7) Emission period S3: Combination Figure 17 and Figure 12As shown, the second light-emitting control signal EM2, the first write control signal WR1, the read-write control signal RD, and the second write control signal WR2 are all at high potentials to control the reset transistor T6, the internal compensation transistor T2, the external compensation transistor T4, and the data write transistor T3 to be turned off. The first light-emitting control signal EM1 is at a low potential to control the light-emitting control transistor T5 to be turned on. At this time, the storage capacitor Cs maintains the potentials of the first node N and the second node Q at its two ends unchanged. The driving current generated by the turn-on transistor T1 is transmitted to the light-emitting element through the turned-on light-emitting control transistor T5, and the light-emitting element emits light.

[0120] Among them, such as Figure 17 In the illustrated embodiment, the potential VQ of the second node Q is maintained at "ELVDD-|Vth3|+VDATA-VREF", therefore the voltage difference between the gate and source of the driving transistor T1 is "VQ-ELVDD", and the driving current is equal to k2*((VQ-ELVDD)-Vth3)2. Substituting this into the expression for VQ, we get that the driving current is equal to k2*(VDATA-VREF)2. Therefore, through the above S1 and S2, the threshold voltage of the driving transistor T1 in this frame is compensated through internal compensation.

[0121] Therefore, it can be seen that a first light-emitting control pulse p5 in the first light-emitting control signal EM1 is staggered from the first write control pulse p1 in the first write control signal WR1 that is close to the corresponding first light-emitting control pulse p5, and is also staggered from the read / write control pulse p2 in the read / write control signal RD that is close to the corresponding first light-emitting control pulse p5. The first light-emitting control pulse p5 is located after the corresponding first write control pulse p1 and the corresponding read / write control pulse p2; for example Figure 12 As shown, the first light emission control pulse p5 covers the light emission period S3, but the first write control pulse p1 and the read / write control pulse p2 are not set within the light emission period S3, and both the first write control pulse p1 and the read / write control pulse p2 are located before the light emission period S3.

[0122] Of course, such as Figure 18 In the illustrated embodiment, with Figure 12Different from the timing diagram of S3 shown, at this time the second emission control potential can also be the corresponding low potential to turn on the reset transistor T6. At this time, the first signal VREF is transmitted to the first node N, that is, VN in S3 is equal to VREF, while VN in S2 is "VREF+(VDATA-VREF)", that is, equal to VDATA. Therefore, the change amount of the potential of the first node N in S3 is "VREF-VDATA". Correspondingly, the potential of the second node Q also has the same change amount. However, in this case, it needs to be considered that VQ in S1 gradually approaches "ELVDD+Vth3" but is not equal. It can be considered that VQ in S1 is equal to a*(ELVDD+Vth3), where 0 < a < 1. In S2, it needs to consider all the capacitances CN coupled between the first node N and other signals and all the capacitances CQ coupled between the second node Q and other signals. Therefore, there is an equation of "△VN*CN = △VQ*CQ". Therefore, VQ in S2 is equal to "(CN / CQ)*(VDATA-VREF)+a*(ELVDD+Vth3)". Let "CN / CQ" be equal to b, then VQ in S2 is equal to a*(ELVDD+Vth3)+b*(VDATA-VREF). In S3, VQ is equal to the sum of VQ in S2 and "VREF-VDATA", that is, equal to a*(ELVDD+Vth3)+(b-1)*(VDATA-VREF). And the drive current is equal to k2*((VQ-ELVDD)-Vth3)^2. Substituting the expression of VQ, the drive current is equal to k2*((a-1)*(ELVDD+Vth3)+(b-1)*(VDATA-VREF))^2.

[0123] Of course, different from Figure 17 and Figure 18 the embodiment shown, different from the timing diagram of S3 shown in Figure 12 at this time, the second write control signal potential can also be the corresponding low potential to turn on the data writing transistor T3 to still write VDATA to the first node N. Since the potential of the first node N in S3 is the same as that of the first node N in S2, the potential VQ of the second node Q is maintained as "ELVDD-|Vth3|+VDATA-VREF" and the drive current is also equal to k2*(VDATA-VREF)^2, just like the embodiment shown in Figure 17 above.

[0124] It is important to note that if a threshold voltage external detection period t1 was performed before the first frame following at least one previous power-on to determine the compensation value ΔVDATA of the data signal VDATA, the data signal VDATA loaded during the data writing period S2 can be a new data signal VDATA superimposed with ΔVDATA. That is, the change in VN in S2 can be "VDATA + ΔVDATA - VREF", and VQ is "ELVDD - |Vth3| + VDATA + ΔVDATA - VREF". Correspondingly, the drive current in S3 is equal to k2 * (VDATA + ΔVDATA - VREF). 2 .

[0125] Therefore, in this invention, the threshold voltage external detection period t1 can be set after two power-on intervals to obtain the ΔVth of the driving transistor T1 at the later power-on, so as to obtain the compensation value ΔVDATA1 of the data voltage corresponding to the entire screen display after the later power-on. Thus, in the data writing period S2 of each frame, the driving transistor T1 is turned on according to the voltage related to ΔVDATA1 to realize the external compensation of the threshold voltage. At the same time, in the threshold voltage internal detection period S1, data writing period S2, and light emission period S3 of each frame, the internal compensation of the threshold voltage can be realized through the above timing settings.

[0126] Similarly, the present invention can also set an external light emission detection period t2 after two power-on intervals to obtain the potential offset of the anode of the light emission element ΔVth at the later power-on. Alternatively, it can obtain the compensation value ΔVDATA2 of the data voltage corresponding to the entire screen display after the later power-on according to the corresponding algorithm. Thus, in the data writing period S2 of each frame, the driving transistor T1 is turned on according to the voltage related to ΔVDATA2 to realize the external compensation of the light emission element. At the same time, in the threshold voltage internal detection period S1, data writing period S2, and light emission period S3 of each frame, the internal compensation of the threshold voltage can be realized through the above timing settings.

[0127] The external detection period t2 for light emission can be set to correspond to the external detection period t1 for threshold voltage, or only the external detection period t2 for light emission or only the external detection period t1 for threshold voltage can be set. Please refer to the above discussion for details.

[0128] This invention provides a pixel driving circuit and a display panel, based on a light-emitting element, a driving transistor for generating a driving current according to a data signal to drive the light-emitting element to emit light, a storage capacitor for storing the data signal, an internal compensation transistor for responding to a first write control signal to compensate for the threshold voltage of the driving transistor, an electrical signal for responding to a read / write control signal to read the source of the driving transistor, and an external compensation transistor (electrically connected to the light-emitting control transistor and the source of the driving transistor) for compensating for the threshold voltage of the driving transistor. The first write control signal is set to be different from the second write control signal so that during the data writing period of each frame, the data signal is transmitted to one end of the storage capacitor to turn on the driving transistor, and the gate and drain of the driving transistor are electrically disconnected, thereby improving the reliability of data signal writing and the accuracy of the driving current.

[0129] This document uses specific examples to illustrate the principles and implementation methods of the present invention. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of the present invention. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of the present invention. Therefore, the content of this specification should not be construed as a limitation of the present invention.

Claims

1. A pixel driving circuit, characterized in that, include: Light-emitting elements; A driving transistor is used to generate a driving current based on a data signal to drive the light-emitting element to emit light. A data writing transistor is used to transmit the data signal to the driving transistor in response to a second write control signal; A storage capacitor, electrically connected to the driving transistor, is used to store the data signal; An internal compensation transistor is electrically connected between the gate and drain of the driving transistor and is used to compensate the threshold voltage of the driving transistor in response to a first write control signal, wherein the first write control signal is different from the second write control signal. A light-emitting control transistor is electrically connected between the light-emitting element and the driving transistor, and is used to transmit the driving current to the light-emitting element in response to a first light-emitting control signal; An external compensation transistor is electrically connected to the drain of the light-emitting control transistor and the driving transistor, and the source of the external compensation transistor is electrically connected to the drain of the driving transistor. The drain of the external compensation transistor is time-divisionally loaded with a fourth signal and electrically connected to the external compensation module. The external compensation transistor is used to respond to the read / write control signal to read the electrical signal at the drain of the driving transistor, to respond to the read / write control signal to read the threshold voltage of the driving transistor, to respond to the read / write control signal to transmit the fourth signal to the drain of the light-emitting control transistor and the driving transistor, and to compensate the threshold voltage of the driving transistor.

2. The pixel driving circuit according to claim 1, characterized in that, Also includes: A reset transistor, electrically connected to the storage capacitor and the data write transistor, is used to respond to a second light-emitting control signal to transmit a first signal to one end of the storage capacitor. The first signal is different from the second signal loaded at the source of the driving transistor.

3. The pixel driving circuit according to claim 2, characterized in that, The pixel driving circuit has a data writing period in each frame, during which the first write control signal and the second write control signal are different. During the data writing period, the data writing transistor is used to respond to the second write control signal to transmit the data signal to one end of the storage capacitor to turn on the driving transistor. The internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate and drain of the driving transistor.

4. The pixel driving circuit according to claim 3, characterized in that, The pixel driving circuit has a light-emitting period in each frame. During the light-emitting period, the first light-emitting control signal is different from the second light-emitting control signal, and the first write control signal is the same as the second write control signal. During the light-emitting period, the reset transistor is used to respond to the second light-emitting control signal, and the data writing transistor is used to respond to the second write control signal to jointly maintain the voltage at one end of the storage capacitor as the voltage corresponding to the data signal. The internal compensation transistor is used to respond to the first write control signal to maintain the voltage at the other end of the storage capacitor as the voltage during the data writing period, so as to keep the driving transistor turned on. The light-emitting control transistor is used to respond to the first light-emitting control signal to electrically connect the light-emitting element and the driving transistor to transmit the driving current to the light-emitting element.

5. The pixel driving circuit according to claim 2, characterized in that, The pixel driving circuit has a first reset period in each frame, during which the first write control signal is different from the second write control signal. During the first reset period, the data write transistor is used to respond to the second write control signal to transmit a third signal to one end of the storage capacitor, and / or the reset transistor is used to respond to the second light emission control signal to transmit a first signal to one end of the storage capacitor to turn off the driving transistor, and the internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor.

6. The pixel driving circuit according to claim 5, characterized in that, During the first reset period, the first light emission control signal is different from the first write control signal; During the first reset period, the external compensation transistor is used to respond to the read / write control signal to transmit the fourth signal to the light-emitting control transistor. The light-emitting control transistor is used to respond to the first light-emitting control signal to transmit the second signal to the light-emitting element to reset the light-emitting element. The internal compensation transistor is used to respond to the first write control signal to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor.

7. The pixel driving circuit according to claim 2, characterized in that, The pixel driving circuit has a second reset period in each frame. During the second reset period, the first light emission control signal is different from the first write control signal. During the second reset period, the reset transistor is configured to respond to the second light emission control signal to transmit the first signal to one end of the storage capacitor, and / or, the data write transistor is configured to respond to the second write control signal to transmit the third signal to one end of the storage capacitor, the external compensation transistor is configured to respond to the read / write control signal to transmit the fourth signal to the drain of the driving transistor, and the internal compensation transistor is configured to respond to the first write control signal to electrically connect the gate of the driving transistor and the drain of the driving transistor so that the fourth signal is transmitted to the gate of the driving transistor to reset the driving transistor; The light-emitting control transistor is used to electrically disconnect from the driving transistor in response to the first light-emitting control signal.

8. The pixel driving circuit according to claim 2, characterized in that, The pixel driving circuit has a threshold voltage external detection period before the first frame, during which the first light emission control signal is different from the first write control signal. During the external detection period of the threshold voltage, the reset transistor is used to respond to the second light emission control signal to transmit the first signal to one end of the storage capacitor, and / or, the data write transistor is used to respond to the second write control signal to transmit the third signal to one end of the storage capacitor, the internal compensation transistor is used to respond to the first write control signal to transmit the second signal to the other end of the storage capacitor, and the external compensation transistor is used to respond to the read / write control signal to read the threshold voltage of the driving transistor; The light-emitting control transistor is used to electrically disconnect from the driving transistor in response to the first light-emitting control signal.

9. The pixel driving circuit according to claim 8, characterized in that, The pixel driving circuit has a light emission external detection period before the first frame, which is located after the threshold voltage external detection period. During the light emission external detection period, the first write control signal is different from the second write control signal, and the first light emission control signal is different from the second light emission control signal. During the external detection period of light emission, the data writing transistor is used to respond to the second write control signal to transmit the target data signal to the storage capacitor to turn on the driving transistor. The light emission control transistor is used to respond to the first light emission control signal to electrically connect the light emission element and the driving transistor. The external compensation transistor is used to respond to the read / write control signal to read the electrical signal of the light emission element. The target data signal is determined based on the data signal and the threshold voltage. The internal compensation transistor is used to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor in response to the first write control signal, and the reset transistor is used to electrically disconnect the storage capacitor in response to the second light emission control signal.

10. The pixel driving circuit according to claim 2, characterized in that, The pixel driving circuit has an external light emission detection period before the first frame. During the external light emission detection period, the first write control signal is different from the second write control signal, and the first light emission control signal is different from the second light emission control signal. During the external detection period of light emission, the data write transistor is used to respond to the second write control signal to transmit a third signal to one end of the storage capacitor to turn off the driving transistor. The external compensation transistor is used to respond to the read / write control signal to transmit a fourth signal to the light emission control transistor. The light emission control transistor is used to respond to the first light emission control signal to electrically connect the light emission element and the driving transistor so that the fourth signal is transmitted to the light emission element. The external compensation transistor is also used to respond to the read / write control signal to read the threshold voltage of the light emission element and to compensate the threshold voltage of the driving transistor. The internal compensation transistor is used to electrically disconnect the gate of the driving transistor and the output terminal of the driving transistor in response to the first write control signal, and the reset transistor is used to electrically disconnect the storage capacitor in response to the second light emission control signal.

11. The pixel driving circuit according to claim 2, characterized in that, The first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor. In this configuration, the first write control pulse in the first write control signal overlaps with the read write control pulse in the read write control signal, and the start point of the first write control pulse is earlier than the start point of the corresponding read write control pulse.

12. The pixel driving circuit according to claim 2, characterized in that, The second write control pulse of the second write control signal is used to turn on the data write transistor, and the second light emission control pulse of the second light emission control signal is used to turn on the reset transistor; In this configuration, one of the second write control pulses in the second write control signal is staggered from one of the second light emission control pulses in the second light emission control signal that is close to the corresponding second write control pulse.

13. The pixel driving circuit according to claim 2, characterized in that, The first light emission control pulse of the first light emission control signal is used to turn on the light emission control transistor, the read / write control pulse of the read / write control signal is used to turn on the external compensation transistor, and the first write control pulse of the first write control signal is used to turn on the internal compensation transistor. Wherein, one of the first light emission control pulses in the first light emission control signal overlaps with one of the read / write control pulses in the read / write control signal, and is offset from one of the first write control pulses in the first write control signal that is close to the corresponding first light emission control pulse.

14. The pixel driving circuit according to claim 2, characterized in that, The second write control pulse of the second write control signal is used to turn on the data write transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor. In this configuration, one of the second write control pulses in the second write control signal is staggered from one of the read write control pulses in the read write control signal that is close to the corresponding second write control pulse, and the second write control pulse is located before the corresponding read write control pulse.

15. The pixel driving circuit according to claim 14, characterized in that, The first light-emitting control pulse of the first light-emitting control signal is used to turn on the light-emitting control transistor; Wherein, the first light emission control pulse in the first light emission control signal and the second write control pulse in the second write control signal are overlapped, and the starting point of the first light emission control pulse is earlier than or equal to the starting point of the corresponding second write control pulse, and the ending point of the first light emission control pulse is later than the ending point of the corresponding second write control pulse.

16. The pixel driving circuit according to claim 2, characterized in that, The second light emission control pulse of the second light emission control signal is used to turn on the reset transistor, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor. Wherein, a second light emission control pulse in the second light emission control signal overlaps with a first write control pulse in the first write control signal.

17. The pixel driving circuit according to claim 2, characterized in that, The second write control pulse of the second write control signal is used to turn on the data write transistor, and the first write control pulse of the first write control signal is used to turn on the internal compensation transistor. In this configuration, a second write control pulse in the second write control signal is interleaved with a first write control pulse in the first write control signal that is close to the corresponding second write control pulse, and the first write control pulse is located before the corresponding second write control pulse.

18. The pixel driving circuit according to claim 2, characterized in that, The first light emission control pulse of the first light emission control signal is used to turn on the light emission control transistor, the first write control pulse of the first write control signal is used to turn on the internal compensation transistor, and the read write control pulse of the read write control signal is used to turn on the external compensation transistor. In the first light emission control signal, the first light emission control pulse is staggered from the first write control pulse that is close to the corresponding first light emission control pulse in the first write control signal, and is also staggered from the read / write control pulse that is close to the corresponding first light emission control pulse in the read / write control signal. The first light emission control pulse is located after the corresponding first write control pulse and the corresponding read / write control pulse.

19. A display panel, characterized in that, include: The panel body includes the pixel driving circuit as described in any one of claims 2 to 18; A driver chip is electrically connected to the pixel driver circuit to drive the pixel driver circuit to operate.

20. The display panel according to claim 19, characterized in that, The panel body also includes a cascaded multi-stage gate drive circuit; The driver chip includes: A timing controller, wherein each of the gate driving circuits is electrically connected between the timing controller and the corresponding plurality of pixel driving circuits, and is used to respond to a first control signal output by the timing controller to output a first light emission control signal, a second light emission control signal, a first write control signal or a second write control signal; At least one source driver is electrically connected between the timing controller and the corresponding plurality of pixel driving circuits, for responding to a second control signal output by the timing controller to output the data signal.

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