Signal jitter elimination method in single-wire serial communication and LED backlight driving system

Abstract

The invention discloses a signal jitter elimination method in single-line serial communication and an LED backlight system. The LED backlight driving system comprises an upper computer and a plurality of LED driving chips, a data input port Din and a data output port Dout are arranged on each LED driving chip; a data input port of each LED driving chip is provided with an edge anti-shake circuit, and the edge anti-shake circuit comprises a D trigger unit, a counter unit and a selector unit; an input signal In which is input from a data input port Din and is sent by an upper computer or a preceding-stage LED driving chip is simultaneously input into the D trigger unit, the counter unit and the selector unit; and a driving chip clock Clk in the LED driving chip is simultaneously input to the D trigger unit and the counter unit.

Description

Technical Field

[0001] The present invention relates to the technical field of LED backlight driving, and particularly to a method for eliminating signal jitter in single-line serial communication and an LED backlight system. Background Art

[0002] With the continuous development of display technology, the number of channels and driving capabilities of Mini LED driving chips are also constantly improving. Some driving chips can drive thousands or even tens of thousands of Mini LED lamp beads by cascading multiple chips, so it is particularly important to ensure the correctness of data transmission. Since there are a large number of Mini LED lamp beads, in order to reduce the cost and complexity of control logic, a cascading method is usually selected to transmit data. Generally, standard protocols such as SPI / IIC are adopted, and standard protocols have strong anti-interference capabilities. However, considering the actual application situation, the AM chips launched by major manufacturers are very small in size because the MiniLED lamp beads and chips are co-packaged in the lamp board, and a too large chip will affect the light-emitting efficiency of the lamp board. Therefore, a single-line transmission protocol is mostly used to receive and send data, and the anti-interference ability is poor. In the prior art, from the hardware aspect, necessary capacitors need to be added at the board level to ensure the stability of the power supply voltage, and amplifiers and filters are added to ensure the correctness of signal transmission and improve the anti-interference ability. From the software aspect, a data transmission method with error correction function and retransmission mechanism is adopted, and data verification and other methods are carried out to ensure that data can be correctly sent to the driving chip. From the hardware aspect, high-quality transmission media can be selected or the circuit design can be optimized to reduce signal distortion and delay, but the cost is high. From the software aspect, it will increase the complexity of software control.

[0003] It can be seen that when the driving chip is affected by board-level parasitic parameters, the signal at the communication interface of the driving chip will oscillate to form a glitch when changing, as Figure 1 shown, resulting in the driving chip sampling incorrect data information, thus causing communication errors. Edge jitter refers to the appearance of glitches at the upper and lower edges of the signal. The size of the glitches is affected by parasitic parameters. Since the high and low peaks of the glitches exceed the threshold of the interface I / O design, two rising edges or falling edges will be judged, and it is considered to be two bits, which will lead to incorrect parsing of communication data. Full-time jitter means that the input signal is subject to external interference (crosstalk of other signals) at any time. Therefore, the present invention proposes to implement edge debouncing and full-time debouncing in the driving chip to remove the glitches of the signal and ensure the correctness of data communication. Summary of the Invention

[0004] The technical object to be achieved by the present invention is to provide a method for eliminating signal jitter in single-line serial communication, which removes the glitches of the signal by implementing edge debouncing and full-time debouncing on the driving chip side to ensure the correctness of data communication.

[0005] Based on the above technical objectives, the present invention provides an LED backlight driving system, and the LED backlight driving system includes:

[0006] a host computer and multiple LED driving chips; the host computer and the multiple LED driving chips form a serial communication link, and the host computer sends instruction data to the multiple LED driving chips as slaves.

[0007] Each of the LED driving chips is provided with a data input port Din and a data output port Dout;

[0008] An edge anti-shake circuit is provided on the data input port of each of the LED driving chips, and the edge anti-shake circuit includes a D flip-flop unit, a counter unit, and a selector unit;

[0009] An input signal In sent by the host computer or a previous-stage LED driving chip and input from the data input port Din is simultaneously input to the D flip-flop unit, the counter unit, and the selector unit; a driving chip clock Clk inside the LED driving chip is simultaneously input to the D flip-flop unit and the counter unit;

[0010] The D flip-flop unit outputs the stored signal In_r; the counter unit compares the input signal In and the stored signal In_r, and when the two are in different level states, the counter unit starts to count the driving chip clock Clk and generates a count value Ct;

[0011] The count value Ct is input to the D flip-flop unit and the selector unit. The counter unit receives a configuration signal Dg_set, and when the count value Ct reaches the configuration signal Dg_set, the count value Ct of the counter unit is reset to zero;

[0012] The D flip-flop unit is configured to input the input signal In to the Q end of the D flip-flop only when the count value Ct is zero;

[0013] The selector unit is a two-to-one selector. The selector unit receives the count value Ct. When the count value Ct is zero, the selector unit uses the input signal In as the output signal Out; when the count value Ct is not zero, the selector unit uses the stored signal In_r as the output signal Out.

[0014] In one embodiment, the D flip-flop unit includes a D flip-flop, the input signal In is input to the D end of the D flip-flop, and the stored signal In_r is output from the Q end of the D flip-flop.

[0015] In one embodiment, the configuration signal Dg_set is configured with different values to achieve full coverage of signal jitter at the rising and falling edges.

[0016] The present invention also provides another LED backlight driving system, which includes:

[0017] A host computer and multiple LED driving chips; the host computer and the multiple LED driving chips form a serial communication link, and the host computer sends command data to the multiple LED driving chips as slaves.

[0018] Each of the LED driving chips is provided with a data input port Din and a data output port Dout;

[0019] A full-time anti-jitter circuit is provided on the data input port of each of the LED driving chips, and the full-time anti-jitter circuit includes a count reset unit, a selector unit, and a D flip-flop;

[0020] The input signal In sent by the host computer or the previous-stage LED driving chip input from the data input port Din is simultaneously input to the count reset unit, the counter unit, and the selector unit; the driving chip clock Clk inside the LED driving chip is simultaneously input to the D flip-flop and the counter unit; the configuration signal Dg_set is input to the count reset unit;

[0021] The count reset unit is used to generate a count reset signal Ct_clr; the counter unit receives the count reset signal Ct_clr. When the count reset signal Ct_clr is 0, the counter unit starts to count the driving chip clock Clk and generates a count value Ct; when the count reset signal Ct_clr is 1, the count value Ct of the counter unit is reset to 0; at the same time, the counter unit outputs the count value Ct to the count reset unit and the selector unit.

[0022] The selector unit is used to generate an output signal Out after anti-jitter processing of the input signal In; the D terminal of the D flip-flop inputs the output signal Out, and the Q output terminal outputs a delayed signal Out_dl; the delayed signal Out_dl is simultaneously input to the count reset unit and the selector unit;

[0023] The counting reset unit compares the configuration signal Dg_set with the count value Ct. When the count value Ct is greater than the configuration signal Dg_set, the counting reset signal Ct_clr is set to 1. At the same time, the counting reset unit compares the level states of the input signal In and the delayed signal Out_dl. When their level states are the same, the counting reset signal Ct_clr is also set to 1. Otherwise, the counting reset signal Ct_clr is set to 0.

[0024] The selector unit compares the configuration signal Dg_set with the count value Ct. When the count value Ct is greater than the configuration signal Dg_set, the selector unit selects the input signal In as the output signal Out. Otherwise, the selector unit selects the delayed signal Out_dl as the output signal Out.

[0025] In one embodiment, the configuration signal Dg_set is configured with different values to fully cover the signal jitter within the entire time domain of the signal.

[0026] Other features and advantages of the present invention will be described in the following specification, and will, in part, be obvious from the specification, or will be learned by practicing the present invention. The objectives and other advantages of the present invention can be realized and obtained by the structures particularly pointed out in the specification, claims, and drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The drawings are used to provide a further understanding of the present invention, and constitute a part of the specification. They are used together with the embodiments of the present invention to explain the present invention, and do not constitute a limitation to the present invention. In the drawings:

[0028] Figure 1 is a schematic diagram of the input signal jitter of an LED driver chip interface in the prior art;

[0029] Figure 2 is a schematic diagram of the structure of the LED backlight driving system of the present invention;

[0030] Figure 3 is a schematic diagram of the structure of the edge jitter elimination circuit of the present invention;

[0031] Figure 4 is a timing diagram of the edge jitter elimination circuit of the present invention;

[0032] Figure 5 is a schematic diagram of the structure of the full-time jitter elimination circuit of the present invention;

[0033] Figure 6 is a timing diagram of the full-time jitter elimination circuit of the present invention. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0034] To make the objectives, technical solutions and advantages of the present invention clearer, the present invention will be further described in detail below with reference to the accompanying drawings.

[0035] It should be understood that when an element or layer is referred to as "on", "adjacent to", "connected to" or "coupled to" another element or layer, it can be directly on, adjacent to, connected or coupled to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers and / or parts, these elements, components, regions, layers and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or part from another element, component, region, layer or part. Thus, without departing from the teachings of the present invention, the first element, component, region, layer or part discussed below may be referred to as the second element, component, region, layer or part. And when discussing the second element, component, region, layer or part, it does not imply that the present invention necessarily has a first element, component, region, layer or part.

[0036] Spatial relationship terms such as "under", "below", "lower", "beneath", "above", "upper", etc. are used herein for convenience in describing the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figures is flipped, then an element or feature described as "under" or "beneath" or "below" other elements or features will be oriented "above" the other elements or features. Thus, the exemplary terms "under" and "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatial descriptors used herein are to be interpreted accordingly.

[0037] The purpose of the terms used herein is only to describe specific embodiments and is not a limitation of the present invention. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "including", when used in this specification, specify the presence of the stated features, integers, steps, operations, elements and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups. As used herein, the term "and / or" includes any and all combinations of the related listed items.

[0038] Example 1

[0039] As Figure 2 shown in the LED driving system of the present invention, the LED driving system includes: a host computer and a plurality of LED driving chips Chip1 to Chip4; the host computer and the plurality of LED driving chips Chip1 to Chip4 form a serial communication link, and the host computer sends command data to the plurality of LED driving chips Chip1 to Chip4 as slaves.

[0040] Each of the LED driving chips has a plurality of LED driving channel pins LED1 to LED4, and the LED driving channel pins are used to connect to an LED string to directly control the light emission of the LED string.

[0041] Each of the LED driving chips is provided with a data input port Din and a data output port Dout. The serial communication link means that the data input port Din of each LED driving chip is connected to the data output port Dout of the previous-stage LED driving chip adjacent to this LED driving chip, and the data output port Dout of each LED driving chip is connected to the data input port Din of the next-stage LED driving chip adjacent to this LED driving chip. The data input port Din of the first LED driving chip in the serial communication link is connected to the signal output port of the host computer.

[0042] As Figure 3 shown, in this embodiment, an edge anti-shake circuit is provided on the data input port of each LED driving chip. The edge anti-shake circuit includes a D flip-flop unit, a counter unit, and a selector unit. The input signal In sent by the host computer or the previous-stage LED driving chip and input from the data input port Din is simultaneously input to the D flip-flop unit, the counter unit, and the selector unit. The driving chip clock Clk inside the LED driving chip is simultaneously input to the D flip-flop unit and the counter unit.

[0043] The D flip-flop unit includes a D flip-flop, and the D flip-flop delays the input of the input signal In to generate a registered signal In_r of the input signal In. That is, the input signal In is input to the D terminal of the D flip-flop, and the registered signal In_r is output from the Q terminal of the D flip-flop.

[0044] The counter unit compares the input signal In and the registered signal In_r. When they are in different level states, the counter unit starts counting the driving chip clock Clk and generates a count value Ct. And the count value Ct is input to the D flip-flop unit and the selector unit. The counter unit receives the configuration signal Dg_set. When the count value Ct reaches the configuration signal Dg_set, the count value Ct of the counter unit is reset to zero.

[0045] The D flip-flop unit receives the count value Ct, and the D flip-flop unit is configured to input the input signal In to the Q end of the D flip-flop only when the count value Ct is zero. If the count value Ct is not zero, the input signal In will not be input to the Q end of the D flip-flop.

[0046] The selector unit is a two-to-one selector. The selector unit receives the count value Ct. When the count value Ct is zero, the selector unit outputs the input signal In as the output signal Out after anti-shake processing; when the count value Ct is not zero, the selector unit outputs the registered signal In_r as the output signal Out after anti-shake processing.

[0047] As Figure 4 shown in the timing diagram of each signal in this embodiment, it can be seen that through the above-mentioned edge anti-shake circuit, the signal jitter or signal glitch at the rising edge or falling edge of the input signal In can be filtered out, and the signal jitter is included in the signal bit duration. When the input signal In judges the binary value of the bit data as 0 or 1 based on the high-level duration or low-level duration, the signal jitter will no longer affect the recognition of the bit data.

[0048] At the same time, in this embodiment, the length of the clock delay can be controlled by adjusting the configuration signal Dg_set, so as to ensure that the signal jitter can be accurately filtered out.

[0049] Example 2

[0050] Similarly, the LED backlight driving system based on this embodiment is as Figure 2 shown. The LED driving system includes: a host computer and multiple LED driving chips Chip1 to Chip4; the host computer and the multiple LED driving chips Chip1 to Chip4 form a serial communication link, and the host computer sends command data to the multiple LED driving chips Chip1 to Chip4 as slaves.

[0051] Each of the LED driving chips has a plurality of LED driving channel pins LED1 to LED4, and the LED driving channel pins are used to connect to an LED string to directly control the light emission of the LED string.

[0052] Each of the LED driving chips is provided with a data input port Din and a data output port Dout. The serial communication link means that the data input port Din of each LED driving chip is connected to the data output port Dout of the previous-stage LED driving chip adjacent to this LED driving chip, and the data output port Dout of each LED driving chip is connected to the data input port Din of the next-stage LED driving chip adjacent to this LED driving chip. The data input port Din of the first LED driving chip in the serial communication link is connected to the signal output port of the host computer.

[0053] As Figure 5 shown, in this embodiment, a full-time anti-shake circuit is provided on the data input port of each LED driving chip. The full-time anti-shake circuit includes a counting reset unit, a selector unit, and a D flip-flop. The input signal In sent by the host computer or the previous-stage LED driving chip and input through the data input port Din is simultaneously input to the counting reset unit, the counter unit, and the selector unit. The driving chip clock Clk inside the LED driving chip is simultaneously input to the D flip-flop and the counter unit. The configuration signal Dg_set is input to the counting reset unit.

[0054] The counting reset unit is used to generate a counting reset signal Ct_clr;

[0055] The counter unit receives the counting reset signal Ct_clr. When the counting reset signal Ct_clr is 0, the counter unit starts to count the driving chip clock Clk and generates a count value Ct. When the counting reset signal Ct_clr is 1, the count value Ct of the counter unit is reset to 0. At the same time, the counter unit outputs the count value Ct to the counting reset unit and the selector unit.

[0056] The selector unit is used to generate an output signal Out after anti-shake processing of the input signal In.

[0057] The D terminal of the D flip-flop inputs the output signal Out, and the Q output terminal outputs a delayed signal Out_dl.

[0058] The delayed signal Out_dl is simultaneously input to the counting reset unit and the selector unit.

[0059] In this embodiment, the counting reset unit compares the configuration signal Dg_set with the count value Ct. When the count value Ct is greater than the configuration signal Dg_set, the counting reset signal Ct_clr is set to 1. At the same time, the counting reset unit compares the level states of the input signal In and the delayed signal Out_dl. When their level states are the same, the counting reset signal Ct_clr is also set to 1. Otherwise, the counting reset signal Ct_clr is set to 0.

[0060] In this embodiment, the selector unit compares the configuration signal Dg_set with the count value Ct. When the count value Ct is greater than the configuration signal Dg_set, the selector unit selects the input signal In as the output signal Out. Otherwise, the selector unit selects the delayed signal Out_dl as the output signal Out.

[0061] As Figure 6 shown in the timing diagram of each signal in this embodiment, it can be seen that through the above full-time anti-shake circuit, signal jitter or signal glitches within the entire signal time domain of the input signal In can be filtered out.

[0062] As described above, the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features. And these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. An LED backlight driving system, the LED backlight driving system comprising: Host computer and multiple LED driver chips; The host computer and the plurality of LED driver chips form a serial communication link, and the host computer acts as a host to send command data to the plurality of LED driver chips acting as slaves; Each of the LED driver chips is provided with a data input port Din and a data output port Dout; the characteristics are: An edge anti-shake circuit is provided on the data input port of each LED driver chip, and the edge anti-shake circuit includes a D trigger unit, a counter unit and a selector unit; The input signal In sent by the host computer or the previous LED driver chip input from the data input port Din is simultaneously input to the D flip-flop unit, the counter unit and the selector unit; the driver chip clock Clk inside the LED driver chip is simultaneously input to the D flip-flop unit and the counter unit; The D flip-flop unit outputs the register signal In_r; the counter unit compares the input signal In and the register signal In_r, and when the two are in different level states, the counter unit starts counting the driving chip clock Clk and generates a count value Ct; The count value Ct is input to the D flip-flop unit and the selector unit. The counter unit receives a configuration signal Dg_set, and when the count value Ct reaches the configuration signal Dg_set, the count value Ct of the counter unit is reset to zero; The D flip-flop unit is configured to input the input signal In to the Q terminal of the D flip-flop only when the count value Ct is zero; The selector unit is a two-to-one selector, which receives the count value Ct. When the count value Ct is zero, the selector unit uses the input signal In as the output signal Out; and when the count value Ct is zero but not zero, the selector unit uses the registered signal In_r as the output signal Out.

2. The LED backlight driving system according to claim 1, characterized in that: The D flip-flop unit includes a D flip-flop, an input signal In is input to a D terminal of the D flip-flop, and the register signal In_r is output from a Q terminal of the D flip-flop.

3. The LED backlight driving system according to claim 1, characterized in that: The configuration signal Dg_set is configured to have different values ​​to achieve full coverage of signal jitter at the rising edge and the falling edge.

4. An LED backlight driving system, the LED backlight driving system comprising: Host computer and multiple LED driver chips; The host computer and the plurality of LED driver chips form a serial communication link, and the host computer acts as a host to send command data to the plurality of LED driver chips acting as slaves; Each of the LED driver chips is provided with a data input port Din and a data output port Dout; A full-time anti-shake circuit is provided on the data input port of each LED driver chip, and the full-time anti-shake circuit includes a count reset unit, a selector unit and a D flip-flop; The input signal In sent by the host computer or the previous LED driver chip input from the data input port Din is simultaneously input to the count reset unit, the counter unit and the selector unit; the driver chip clock Clk inside the LED driver chip is simultaneously input to the D flip-flop and the counter unit; the configuration signal Dg_set is input to the count reset unit; The counting reset unit is used to generate a counting reset signal Ct_clr; the counter unit receives the counting reset signal Ct_clr, and when the counting reset signal Ct_clr is 0, the counter unit starts to count the driving chip clock Clk and generates a counting value Ct; when the counting reset signal Ct_clr is 1, the counting value Ct of the counter unit is reset to 0; and at the same time, the counter unit outputs the counting value Ct to the counting reset unit and the selector unit; The selector unit is used to generate an output signal Out after the input signal In is de-shaked; the D terminal of the D flip-flop inputs the output signal Out, and the Q output terminal outputs a delay signal Out_dl; the delay signal Out_dl is simultaneously input to the count reset unit and the selector unit; The counting reset unit compares the configuration signal Dg_set and the count value Ct. When the count value Ct is greater than the configuration signal Dg_set, the counting reset signal Ct_clr is set to 1. At the same time, the counting reset unit compares the level states of the input signal In and the delay signal Out_dl. When the level states of the two are the same, the counting reset signal Ct_clr is also set to 1. Otherwise, the counting reset signal Ct_clr is set to 0. The selector unit compares the configuration signal Dg_set and the count value Ct. When the count value Ct is greater than the configuration signal Dg_set, the selector unit selects the input signal In to output as the output signal Out; otherwise, the selector unit selects the delay signal Out_dl to output as the output signal Out.

5. The LED backlight driving system according to claim 4, characterized in that: The configuration signal Dg_set is configured to have different values ​​to achieve complete coverage of signal jitter in the entire time domain of the signal.

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