A Time-Triggered DMA Transmission Start Control Method and Device

Abstract

The present invention discloses a time-triggered DMA transmission start control method and device. The method steps include: Step S01. Obtain the static scheduling time table of time-sensitive traffic, calculate the offset time, generate a TX ring scheduling time table, and configure it into the DMA transmission start control module; Step S02. Run the DMA transmission start control module, poll the TX ring scheduling time table, and each time when polling, determine whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, and when it is determined that the time-sensitive flow mounting offset is reached, mount the corresponding offset address and message length onto the TX descriptor ring, and send a signal to the DMA controller; Step S03. The DMA controller starts the DMA read process according to the received signal, and sends the time-sensitive messages in the deterministic transmission buffer to the network. The present invention has the advantages of simple implementation method, low cost, high efficiency, and strong flexibility, etc.

Description

Technical Field

[0001] The present invention relates to the technical field of Time Sensitive Networking (TSN), and in particular, to a time-triggered DMA transmission start control method and apparatus. Background Art

[0002] In distributed real-time systems such as industrial control systems, automotive electronic systems, and aerospace systems, there are a large number of "sensing - computing - execution" control loops that have strict requirements for end-to-end real-time performance. The control loop consists of sensors, computing nodes, actuators, and sensing data streams and control data streams. Sensors generate sensing data streams and send them to computing nodes through the network. The computing nodes run computing tasks, and the tasks use the sensing data streams to calculate control data streams and send the control data streams to the actuators through the network. The actuators perform corresponding actions according to the control data streams to complete the "sensing - computing - execution" control loop. Since the control loop has high real-time requirements, the involved sensing data streams and control data streams are also time-sensitive streams or time-critical streams. Time-sensitive streams have extremely strict requirements for end-to-end real-time performance. For example, in an autonomous driving system, it is required that the end-to-end delay of time-sensitive streams is between 100 microseconds and 250 microseconds, and the end-to-end jitter is below dozens of microseconds. Time-sensitive streams have end-to-end determinism. Especially in a distributed system, it is a system-level attribute that requires the joint guarantee of determinism on the end system and determinism in the network.

[0003] Time Sensitive Networking (TSN) can provide deterministic services for Ethernet, ensuring the transmission determinism of time-sensitive traffic in the network. It introduces functions such as time synchronization, deterministic packet forwarding, frame replication and redundancy elimination technology, and resource reservation on the basis of standard Ethernet. TSN upgrades Ethernet from an event-triggered type to a time-triggered type by adding a time reference to the standard Ethernet. Through time synchronization technology, each node in the network has a common time reference, and the global time is divided into equal-length time slots.

[0004] In the prior art, the DMA (Direct Memory Access) engine in TSN (Time-Sensitive Networking) adopts an "event-triggered" working mode, that is, the skb (Socket Buffer) associated with the packet is mounted on the descriptor, and the DMA engine reads the packet from the memory are all event-triggered, resulting in the packet sending not being able to be carried out according to the planned time. As a result, the network card needs to additionally implement the injection control of time-sensitive packets, and an additional buffer is required to store the time-sensitive packets that arrive in advance but cannot be scheduled for sending. Moreover, during the operation of the current TSN DMA engine, it is impossible to distinguish between time-sensitive packets and non-time-sensitive packets, and the number of descriptors in the TX descriptor ring is limited. The time for the hardware to write back the descriptors is also affected by the number of packets processed in each round and there is uncertainty, resulting in the processing of time-sensitive packets being extremely vulnerable to the impact of sudden non-time-sensitive packets. Based on the above event-triggered characteristics and the mixed processing of non-time-sensitive packets, the determinacy of time-sensitive packets is reduced, making the DMA transmission engine on the end-system network card actually not have the ability to transmit deterministic packets. Summary of the Invention

[0005] The technical problem to be solved by the present invention lies in: aiming at the technical problems existing in the prior art, the present invention provides a time-triggered DMA transmission start control method and device with simple implementation method, low cost, high efficiency and strong flexibility.

[0006] To solve the above technical problems, the technical solution proposed by the present invention is as follows:

[0007] A time-triggered DMA transmission start control method, the steps include:

[0008] Step S01. Obtain the static scheduling time table of time-sensitive traffic, calculate the mounting offset time and the ring clearing offset time according to the triggering time of the time-sensitive packets in the obtained static scheduling time table, generate a TX ring scheduling time table and configure it into the DMA transmission start control module. The mounting offset time is the offset of the time-sensitive packet information mounting time within the scheduling period, and the ring clearing offset time is the offset of clearing the non-time-sensitive packet information in the TX descriptor ring within the scheduling period;

[0009] Step S02. Run the DMA transmission start control module, poll the TX ring scheduling time table, and each time when polling, judge whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring according to the offset time in the TX ring scheduling time table, and when it is judged that the mounting offset time of the time-sensitive flow is reached, after mounting the offset address and packet length corresponding to the time-sensitive packet information on the TX descriptor ring, send a doorbell signal to the DMA transmission start register of the DMA controller;

[0010] Step S03. The DMA controller starts the DMA read process according to the received doorbell signal, and sends the time-sensitive packets in the deterministic transmission buffer to the network.

[0011] Furthermore, the fields in the TX ring scheduling time table further include an operation, an offset address, and a packet length. The operation is the operation that the DMA transmission start control module needs to execute at the operation offset time, including clearing the descriptor information of non-time-sensitive packets, mounting the time-sensitive packet information to the TX transmission descriptor ring, and sending a doorbell signal to notify the hardware to perform DMA read processing; the offset address is the offset address of the time-sensitive packet in the deterministic transmission buffer, and the time-sensitive flow is stored in a continuous memory area; the packet length is the length of the time-sensitive packet.

[0012] Furthermore, in step S01, the TX ring scheduling time table is generated by adopting a preset scheduling algorithm. The input parameters of the preset scheduling algorithm include the static scheduling time table of time-sensitive traffic, the DMA channel bandwidth, the processing time of the network card, the time consumed to clear the descriptor information of other non-time-sensitive flows on the TX ring, the time consumed to mount the descriptor information of the current time-sensitive flow, and the time consumed to refresh the tail pointer. The content of the table entries in the static scheduling time table includes any one or more of the source end, the destination end, the period, the packet length, and the deadline. The output parameters of the preset scheduling algorithm include an array of transmission buffer offset amounts of critical flows for marking the positions of critical flows in the transmission buffer and a scheduling time table. The scheduling time table includes any one or more fields such as the scheduling time of the operation, the specific operation type, the buffer offset amount for mounting time-sensitive traffic, and the packet length of each time-sensitive traffic.

[0013] Furthermore, step S01 includes:

[0014] Step S101. Initialize the transmission buffer offset amount array and the TX ring scheduling time table according to the size of the static scheduling time table;

[0015] Step S102. Poll the static scheduling time table, and calculate the storage offset address and the delayed mounting time of the time-sensitive packet in the deterministic buffer item by item according to the information of each time-sensitive packet;

[0016] Step S103. Determine the mounting offset time of the time-sensitive packet according to the transmission time in the static scheduling time table and the delayed mounting time, and store them in a temporary array in sequence;

[0017] Step S104. Calculate the TX descriptor ring clear time according to the temporary array, and generate a schedule entry for the TX ring schedule time table. Specifically, calculate the clear time of the TX descriptor ring based on the current time-sensitive flow information mounting time and the clear ring time consumption. Add the clear time corresponding to the current time-sensitive traffic, the mounting offset time, the corresponding operation, the offset address, and the message length as a schedule entry to the TX ring schedule time table. The clear ring time consumption is the time required to clear all non-time-sensitive message information on the ring before mounting the time-sensitive message information.

[0018] Step S105. Output the complete TX ring schedule time table for use by the DMA transmission start control module.

[0019] Furthermore, the delay mounting time includes the descriptor dma processing time t_dma_desc, the data dma processing time t_dma_data, the time consumption t_mount for mounting the current time-sensitive flow descriptor information, the time consumption t_tail for refreshing the tail pointer, and the processing time t_nic of the network card.

[0020] Furthermore, in step S103, by calculating the time consumption from the mounting of the time-sensitive message to the descriptor until the network card actually sends the message, the mounting offset time of the time-sensitive message is corrected.

[0021] Furthermore, the TX ring schedule time table also includes a pointer for polling each item in the TX ring schedule time table. The DMA transmission start control module compares the current global time with the table entry pointed to by the pointer of the TX ring schedule time table to perform corresponding operations, that is, to determine whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, or when it is determined that the time-sensitive flow mounting offset is satisfied, mount the offset address and message length corresponding to the time-sensitive flow information to the TX descriptor ring and send a doorbell signal to the DMA transmission start register of the DMA controller.

[0022] Furthermore, step S02 includes:

[0023] Step S201. After the DMA transmission start control module starts running, continuously obtain the global time and compare it with the current table entry pointer offset time of the TX ring schedule time table.

[0024] Step S202. Determine whether the current time is the TX ring schedule time table offset time. If so, jump to step S203; otherwise, jump to step S205.

[0025] Step S203. Determine whether the offset time corresponding to the current moment is the mounting offset of the time-sensitive message. If so, it is determined that the mounting offset time of the time-sensitive message is reached, and the process jumps to Step S204. Otherwise, it is determined that the clearing ring offset time is reached and the process jumps to Step S206;

[0026] Step S204. Write the storage offset address and message length of the current time-sensitive message into the descriptor ring, and then transfer to Step S207;

[0027] Step S205. Determine whether the number of messages in the current ring reaches the threshold or whether the timer expires. If so, transfer to Step S207. Otherwise, return to Step S201;

[0028] Step S206. Directly clear the descriptor information of the non-critical messages in the TX transmission descriptor ring, that is, release the correspondence between the descriptor and the corresponding non-critical message, and set the message value in the ring to 0, and then transfer to Step S208;

[0029] Step S207. Send a doorbell signal to the DMA send start register of the DMA controller;

[0030] Step S208. Move the entry pointer to the next entry in the TX ring scheduling time table, jump to Step S201, and continue to wait for triggering.

[0031] A time-triggered DMA send start control device includes a processor and a memory. The memory is used to store a computer program, and the processor is used to execute the computer program to perform the method as described above.

[0032] A computer-readable storage medium storing a computer program, where the computer program, when executed by a processor, implements the method as described above.

[0033] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0034] 1. The present invention introduces a time scale on the basis of a standard DMA engine, uses the TX ring scheduling time table to control the time when time-sensitive packet information is mounted on the TX descriptor ring, and then controls the time when the DMA engine reads the time-sensitive packets in the memory, enabling the "event-triggered" standard DMA engine to have the characteristics of "time-triggered". By planning the transmission offset time of time-sensitive packets and controlling the packets to be sent according to time, the consumption of hardware storage resources can be reduced. At the same time, in cooperation with the deterministic transmission buffer, the polling DMA transmission start control module is used instead of the interrupt method to send the doorbell signal, so that the transmission of packets is only related to the time when the descriptors are mounted, which can improve the determinacy of the packet transmission time, effectively reduce the jitter of the network card when sending time-sensitive flows, improve the delay determinacy of packet transmission, and thus improve the end-to-end determinacy of time-sensitive flows.

[0035] 2. The present invention corrects the offset time of mounting time-sensitive packet information and packet transmission, so that the underlying hardware does not need to allocate too much storage space to accommodate the time-sensitive packets that arrive too early, which can save the storage resources of the underlying hardware and is especially suitable for the application of on-chip embedded end systems.

[0036] 3. The present invention realizes the deterministic scheduling of time-sensitive traffic in mixed traffic through software, and can also improve the implementation flexibility, reduce the hardware design cost, thus simplifying the hardware design and having better portability. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] Figure 1 It is a schematic diagram of the principle of the time-triggered DMA transmission start control method based on this embodiment.

[0038] Figure 2 It is a schematic diagram of the implementation process of the time-triggered DMA transmission start control method based on this embodiment.

[0039] Figure 3 It is a schematic diagram of the configuration of the TX ring scheduling time table obtained in the specific application embodiment of the present invention.

[0040] Figure 4 It is a flowchart of the implementation of the time-triggered DMA transmission start control based on this embodiment. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0041] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific preferred embodiments, but the protection scope of the present invention is not limited thereby.

[0042] For ease of understanding, first, an introduction to the relevant technical background related to the present invention is given by way of example.

[0043] On the end system in the TSN network, for a packet to go from the application task to the physical link, it needs to pass through the application, Socket API, protocol stack, network card driver, DMA engine, and network card switch in sequence. Among them, the application copies the message Msg constructed for sending to the kernel space through system calls such as the sendto() function, constructs an skb based on the content of Msg, and performs an enqueue operation; in the protocol stack, the skb will go through the processing of the transport layer and network layer, such as filling in the header fields; then it enters the traffic control subsystem. If there are no queue rules restricting packet sending, the packet is immediately mounted to the transmit (TX) descriptor ring in the driver; if there are restrictions, it selects an appropriate queue for enqueue processing and decides when to send it to the driver according to the queue rules and queue quotas; the driver maintains the mapping relationship between the TX descriptor ring address and the DMA address. The network card reads the skb mounted by the descriptor through DMA, finds the packet at the memory location pointed to by the skb, and DMA it to the packet buffer of the network card. Finally, the network card sends the packet to the network. Among them, the DMA engine is an important part to ensure the determinism of the end system. The DMA engine uses DMA technology to write the packets in memory to the network card. DMA is a data transfer method in which the I / O device directly exchanges data with the memory without the intervention of the CPU.

[0044] In the prior art, the standard DMA engine and the network card driver exchange data through the descriptor mechanism and the interrupt mechanism. The specific process is as follows:

[0045] 1. First, the network card driver initializes the descriptor ring in memory. The descriptor ring is a key data structure for the DMA engine and the network card driver to exchange packets. It is organized into a circular structure by individual descriptors. A descriptor includes a pointer to the packet buffer, that is, the physical address of the packet buffer. The descriptor can be regarded as a summary of the packet buffer, and the packet buffer is the area where the packet is actually stored. The specific data structure of the descriptor is related to the network card, but its key fields are roughly the same, including the address of the packet buffer, the packet length, and the status bit. The status bit is used to indicate whether there is a packet in the packet buffer pointed to by this descriptor.

[0046] 2. After the skb representing the packet passes through the processing of the protocol stack, neighbor subsystem, and network device subsystem, it reaches the network card driver. In the driver function, an element is taken from the transmit descriptor ring, and the skb is hung on the element, and a memory mapping is constructed for the data corresponding to the skb to allow the device to read data from the RAM through DMA. It is necessary to traverse all the fragments of the packet, generate a valid mapping for each fragment of the skb, and update the head pointer of the descriptor ring. The head pointer is the pointer pointing to the next available transmit descriptor.

[0047] 3. When the transmission queue is driven, or the protocol stack pauses transmission, or the number of written descriptors reaches a preset threshold, i.e., the flag indicating that there is no more data to send is set, the driver will write the current descriptor position into the tail pointer register of the hardware to notify the hardware for processing. That is, the DMA engine obtains the number and position of the descriptors of the currently written packets, and the DMA processes the descriptors by polling, retrieves the packets from the memory and writes them into the buffer of the network card. Every time the hardware finishes sending a data packet, it will write back the flag bit to the descriptor so that the driver can recycle the transmission descriptor during subsequent interrupt processing.

[0048] The working process of the above standard DMA engine belongs to the "event-triggered" type. The occurrence of the skb associated with the packet being mounted on the descriptor and the occurrence of the DMA engine reading the packet from the memory are both event-triggered, resulting in the packet transmission not being able to occur according to the planned time. As a result, the network card needs to additionally implement the injection control of time-sensitive packets, and an additional buffer is required to store the time-sensitive packets that arrive in advance but cannot be scheduled for transmission. Moreover, during the working process of the above standard DMA engine, it cannot distinguish between time-sensitive packets and non-time-sensitive packets, leading to the problem of mixed processing of non-time-sensitive packets. The processing of time-sensitive packets is extremely vulnerable to the impact of sudden non-time-sensitive packets, thus reducing the determinacy of time-sensitive packets and making the standard DMA transmission engine on the end-system network card not have the ability to transmit deterministic packets.

[0049] In view of the above problems existing in the prior art, the present invention provides a time-triggered DMA transmission start control method and device with simple implementation, low cost, high efficiency and strong flexibility. By introducing a time scale on the basis of the standard DMA engine and using the TX ring scheduling time table to control the time when the time-sensitive packet information is mounted on the TX descriptor ring, and further controlling the time when the DMA engine reads the time-sensitive packets from the memory, the "event-triggered" standard DMA engine is made to have the characteristics of "time-triggered". By planning the transmission offset time of the time-sensitive packets and controlling the packets to be sent according to time, the consumption of hardware storage resources can be reduced. At the same time, in cooperation with the deterministic transmission buffer, the doorbell signal is sent in a polling DMA transmission start control module rather than in an interrupt manner, so that the packet transmission is only related to the time when the descriptor is mounted, which can improve the determinacy of the packet transmission moment, effectively reduce the jitter of the network card sending time-sensitive flows, improve the delay determinacy of packet transmission, and thus improve the end-to-end determinacy of time-sensitive flows.

[0050] The present invention will be further described below in conjunction with specific embodiments.

[0051] Such as Figure 1As shown in the figure, the principle of the time-triggered DMA transmission start control method in this embodiment is to generate and configure a TX ring scheduling time table for the DMA transmission start control module. The DMA transmission start control module obtains the global time and then compares it with the offset time of the TX ring scheduling time table entry. When the ring clearing offset is satisfied, the information of non-time-sensitive flows on the TX descriptor ring is cleared to prepare for the mounting of time-sensitive flows; when the time-sensitive flow mounting offset is satisfied, the corresponding offset address and message length are mounted on the TX descriptor ring and a doorbell signal is sent to notify the hardware to perform DMA read processing.

[0052] As Figure 2 shown in the figure, the steps of the time-triggered DMA transmission start control method in this embodiment include:

[0053] Step S01. Obtain the static scheduling time table of time-sensitive traffic, calculate the mounting offset time and the ring clearing offset time according to the trigger time of the time-sensitive message in the obtained static scheduling time table, generate a TX ring scheduling time table and configure it into the DMA transmission start control module. The mounting offset time is the offset of the time-sensitive message information mounting time within the scheduling period, and the ring clearing offset time is the offset of the TX descriptor ring clearing non-time-sensitive message information within the scheduling period;

[0054] Step S02. Run the DMA transmission start control module, poll the TX ring scheduling time table, and each time when polling, judge whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring according to the ring clearing offset time in the TX ring scheduling time table, and when it is judged that the mounting offset time of the time-sensitive message information is reached, mount the offset address and message length corresponding to the time-sensitive message information on the TX descriptor ring, and send a doorbell signal to the DMA transmission start register of the DMA controller;

[0055] Step S03. The DMA controller starts the DMA read processing according to the received doorbell signal, and sends the time-sensitive message in the deterministic transmission buffer to the network.

[0056] Since time-sensitive flows are periodic and static, a time-sensitive flow can be described by a five-tuple of source, destination, period, packet length, and deadline. Therefore, each time-sensitive traffic flow can be pre-planned to obtain a static scheduling time table that can be known in advance for TSN traffic planning and scheduling. In this embodiment, first, according to the static scheduling time table of the time-sensitive traffic known a priori, combined with the DMA transfer time consumption of the system, etc., a TX ring scheduling time table is generated. Then, the DMA send start control module is run, and by polling the TX ring scheduling time table, it is determined when to clear the non-time-sensitive flow information in the current TX descriptor ring, or when to mount the time-sensitive flow information to the TX descriptor ring, and a doorbell signal is sent to the DMA send start register of the underlying hardware. The DMA controller starts DMA read according to the doorbell signal, and sends the time-sensitive packets in the deterministic send buffer to the network on time. By the above method, using the TX ring scheduling time table to control the time when the time-sensitive packet information is mounted to the TX descriptor ring, and then controlling the time when the DMA engine reads the time-sensitive packets in the memory, the "event-triggered" standard DMA engine can have the characteristics of "time-triggered". By controlling the mounting time of the time-sensitive packet information and the time when the packet is submitted to the underlying hardware, the transmission of the time-sensitive traffic conforms to the network scheduling plan, and the "last mile" problem of the time-delay determinism of the time-sensitive flow on the sending side can be solved. At the same time, using the polling DMA send start control module instead of the interrupt method to send the doorbell signal makes the packet transmission only related to the time when the descriptor is mounted, and has nothing to do with other factors such as the number, length of non-time-sensitive packets, and the processing queue of the protocol stack, making the packet transmission time more deterministic. Thus, the jitter of the network card sending time-sensitive flows can be reduced, the time-delay determinism of packet transmission can be improved, and the end-to-end determinism of time-sensitive flows can be improved.

[0057] In this embodiment, each field in the TX ring scheduling time table includes an offset time, an operation, an offset address, and a packet length. The offset time is the mounting offset time and the ring clearing offset time. Among them, the mounting offset time is the offset of the time when the time-sensitive packet information is mounted within the scheduling period, and the ring clearing offset time is the offset of clearing the non-time-sensitive packet information in the TX descriptor ring within the scheduling period; the operation is the operation that the DMA send start control module needs to execute when reaching the operation offset time, including clearing the descriptor information of non-time-sensitive packets, mounting the time-sensitive packet information to the TX send descriptor ring, and sending a doorbell signal to notify the hardware for DMA read processing; the offset address is the offset address of the time-sensitive packet in the deterministic send buffer, and the time-sensitive flows are stored in a continuous memory area; the packet length is the length of the time-sensitive packet.

[0058] Specifically, the specific definitions of each field in the TX ring scheduling time table are as follows:

[0059] (1) Offset time: The offset time represents the offset of the time-sensitive packet information mounting time within the scheduling period, that is, the mounting offset time. The mounting time of the corresponding information of this stream is obtained by adding this offset time to the start time of the scheduling period; or it is the offset of the TX descriptor ring clearing non-time-sensitive packet information within the scheduling period, that is, the ring clearing offset time. The ring clearing offset time plus the start time of the scheduling period is the non-time-sensitive packet information clearing time of the TX descriptor ring. The entries in the static scheduling time table are sorted in ascending order of the offset time. The mounting offset time and the ring clearing offset time of the time-sensitive packet information can also be configured to be sorted in ascending order.

[0060] (2) Operation: It represents the operation that the DMA transmission start control module will execute when reaching the operation offset time, including clearing the descriptor information of non-time-sensitive packets, or mounting the time-sensitive packet information to the TX transmission descriptor ring and sending a doorbell signal to notify the hardware for DMA read processing.

[0061] (3) Offset address: It represents the offset address of the time-sensitive packet in the deterministic transmission buffer.

[0062] In this embodiment, a continuous memory area is pre-applied for all time-sensitive streams for storage. Each stream corresponds to a static scheduling time table with a priori known specific offset address. In this way, after the DMA engine receives the doorbell signal sent by the transmission start control module, it can obtain the correct time-sensitive packet at the specified offset address.

[0063] (4) Packet length: It represents the length of the time-sensitive packet.

[0064] In this embodiment, step S01 uses a preset scheduling algorithm to generate a TX ring scheduling time table according to the static scheduling time table of the a priori known time-sensitive streams and the deterministic transmission buffer address, and configures it into the DMA transmission start control module. The specific steps include:

[0065] Step S101. Initialize the transmission buffer offset array and the TX ring scheduling time table according to the size of the static scheduling time table;

[0066] Step S102. Poll the static scheduling time table, and calculate the storage offset address and the delayed mounting time of the time-sensitive packet in the deterministic buffer item by item according to the information of each time-sensitive packet;

[0067] Step S103. Determine the mounting offset time of the time-sensitive packet according to the transmission time and the delayed mounting time in the static scheduling time table, and store it in the temporary array in turn;

[0068] Step S104. Calculate the TX descriptor ring clear time based on the temporary array, and generate a schedule entry for the TX ring scheduling time table. Among them, calculate the clear time of the TX descriptor ring according to the current time-sensitive flow information mounting time and the clear ring time consumption. Add the clear time corresponding to the current time-sensitive traffic, the mounting offset time, the corresponding operation, the offset address, and the message length as a schedule entry to the TX ring scheduling time table. The clear ring time consumption is the time required to clear all non-time-sensitive message information on the ring before mounting the time-sensitive message information.

[0069] Step S105. Output the complete TX ring scheduling time table for use by the DMA transmission start control module.

[0070] In the above step S103, by calculating the time consumption from the time-sensitive message being mounted to the descriptor until the network card actually sends the message, the mounting offset time of the time-sensitive message is corrected. The time-sensitive flow information needs to be mounted on the TX descriptor ring at a specified time.

[0071] Since the application may generate time-sensitive messages prematurely, if the message information is mounted as soon as a time-sensitive message is generated, it may cause transmission failure due to insufficient descriptor quantity or message discard due to insufficient hardware storage resources. In this embodiment, by correcting the offset time of mounting the time-sensitive message information and message transmission, when the application generates a time-sensitive message, the time-sensitive message will be directly stored in the pre-applied deterministic transmission buffer first. The DMA transmission start control module polls the TX ring scheduling time table and mounts its information, that is, the offset address and the message length, on the TX descriptor ring when the mounting offset time of the time-sensitive message is satisfied, and immediately sends a doorbell signal to the DMA transmission start register of the underlying hardware to notify the hardware network card to process the descriptor and send the time-sensitive message. Since it enables the underlying hardware not to allocate too much storage space to accommodate prematurely arrived time-sensitive messages, it can effectively save the storage resources of the underlying hardware and simplify the design of the underlying hardware, especially suitable for the application of on-chip embedded end systems.

[0072] In step S01 of this embodiment, when generating the TX ring scheduling time table by using a preset scheduling algorithm, the input parameters of the preset scheduling algorithm include the static scheduling time table of time-sensitive traffic, the DMA channel bandwidth, the processing time of the network card, the time consumed to clear the descriptor information of other non-time-sensitive flows on the TX ring, the time consumed to mount the descriptor information of the current time-sensitive flow, and the time consumed to refresh the tail pointer. The content of the table entries of the static scheduling time table includes any one or more of the source end, the destination end, the period, the message length, and the deadline. The output parameters of the preset scheduling algorithm include the transmission buffer offset array of the critical flow for marking the position of the critical flow in the transmission buffer and the scheduling time table. The scheduling time table includes any one or more fields of the scheduling time of the operation, the specific operation type, the buffer offset for mounting the time-sensitive traffic, and the message length of each time-sensitive traffic.

[0073] Specifically, the input parameters required by the scheduling algorithm include:

[0074] critical_flow_schedule: The static scheduling time table of time-sensitive traffic that is known a priori. The content of the table entries includes the five-tuple of the source end, the destination end, the period, the message length, and the deadline;

[0075] dma_bandwidth: The DMA channel bandwidth;

[0076] t_nic: The processing time of the network card, such as the queuing time, etc.;

[0077] t_clear: The time consumed to clear the descriptor information of other non-time-sensitive flows on the TX ring.

[0078] t_mount: The time consumed to mount the descriptor information of the current time-sensitive flow.

[0079] t_tail: The time consumed to refresh the tail pointer, that is, the hardware time consumed through MMIO.

[0080] The above t_clear, t_mount, and t_tail can all obtain empirical values through experiments.

[0081] The output parameters of the scheduling algorithm include:

[0082] buffer_offset_array: The transmission buffer offset array of the critical flow, used to mark the position of the critical flow in the transmission buffer, and can be used as an intermediate output parameter for schedule_table. Among them, each offset of buffer_offset_array can be determined by the message size of each time-sensitive flow in critical_flow_schedule.

[0083] schedule_table: Scheduling time table. It includes the following fields: the scheduling time offset_time of the operation, the specific operation type operation (clear_ring or mount_critical_flow), the buffer offset offset_arr for mounting time-sensitive traffic (this value is NULL during the clear_ring operation), and the packet length pkt_len of each time-sensitive traffic.

[0084] In a specific application embodiment, the scheduling algorithm can be configured as the following steps:

[0085] (1) Initialize the send buffer offset array and the TX ring scheduling time table according to the size of the input static scheduling time table.

[0086] (2) Poll the static scheduling time table and calculate the storage offset address of the send buffer offset array (buffer_offset_array) and the delayed mounting time of the time-sensitive packet item by item. For each time-sensitive packet, that is, the critical flow, calculate its storage offset address in the deterministic buffer according to the packet size; calculate the delay time (latency_offset) according to the packet size, DMA bandwidth, network card processing rate, etc.

[0087] Specifically, the delayed mounting time includes the descriptor dma processing time t_dma_desc, the data dma processing time t_dma_data, the time consumed for mounting the current time-sensitive flow descriptor information t_mount, the time consumed for refreshing the tail pointer t_tail, and the processing time of the network card t_nic. For example, the descriptor dma processing time: t_dma_desc = descriptor_size / dma_bandwidth;

[0088] The data dma processing time: t_dma_data = packet_size / dma_bandwidth; the delay time latency_offset = t_mount + t_tail + t_dma_desc + t_dma_data + t_nic.

[0089] (3) Determine the mounting offset time of the time-sensitive packet according to the sending time of the static scheduling time table and latency_offset, and store them into the temporary array in sequence. Among them, the mounting time = the sending time of the time-sensitive flow - latency_offset.

[0090] (4)Calculate the TX descriptor ring clear time based on the temporary array and generate a schedule table entry. When calculating a clear time, add the corresponding clear and mount offset times, corresponding operations, offset addresses, and packet lengths of the time-sensitive traffic to the schedule table. Among them, the clear time = the current time-sensitive flow information mount time - the clear time consumption.

[0091] Before mounting the time-sensitive packet information, it is necessary to first clear all non-time-sensitive packet information on the ring to prevent a large number of unprocessed non-time-sensitive packets from occupying limited descriptors and prevent the time-sensitive packets from missing the processing time due to processing too many non-time-sensitive packets.

[0092] (5)Return the schedule table. Output the complete TX ring schedule table shcedule_table for the DMA transmission start control module to use.

[0093] In a specific application embodiment, the TX ring schedule table generated by calling the above scheduling algorithm is configured as Figure 3 shown.

[0094] In this embodiment, the ring schedule table is a circular structure generated according to the static schedule table to control the mounting of time-sensitive traffic information to the TX descriptor ring or clear the TX descriptor ring information. The TX ring schedule table also includes a pointer for polling each item in the TX ring schedule table; the DMA transmission start control module compares the current global time with the item pointed to by the pointer of the TX ring schedule table to perform corresponding operations, that is, to determine whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, or when it is determined that the time-sensitive flow mount offset is met, mount the offset address and packet length corresponding to the time-sensitive flow information to the TX descriptor ring and send a doorbell signal to the DMA transmit start register of the DMA controller.

[0095] Step S1 generates a TX ring schedule table according to the static schedule table of the priori known time-sensitive flows and the deterministic transmit buffer address and configures it into the DMA transmission start control module; then step S02 realizes the DMA transmission start control based on time triggering. As Figure 4 shown, in this embodiment, the detailed steps of step S02 include:

[0096] Step S201. After the DMA transmission start control module starts running, continuously obtain the global time and compare it with the current table item pointer offset time of the TX ring schedule table;

[0097] Step S202. Determine whether the current time is the TX ring schedule table offset time. If so, jump to step S203; otherwise, jump to step S205;

[0098] Step S203. Determine whether the offset time corresponding to the current time is the time-sensitive message mounting offset. If so, determine that the time-sensitive message mounting offset time has been reached, and jump to step S204. Otherwise, determine that the ring clearing offset time has been reached and jump to step S206.

[0099] Step S204. Write the storage offset address and message length of the current time-sensitive message into the descriptor ring, and proceed to step S207;

[0100] Step S205. Determine whether the number of messages on the current ring has reached a threshold or whether the timer has expired. If so, proceed to step S207, otherwise return to step S201;

[0101] Step S206. directly send the descriptor information of the non-critical message of the descriptor ring to TX to perform a clearing operation, that is, cancel the corresponding relationship between the descriptor and the corresponding non-critical message, and set the message value on the ring to 0, and then go to step S208;

[0102] Step S207: Send a doorbell signal to the DMA send start register of the DMA controller to notify the hardware that it can send a data packet;

[0103] Step S208: Move the entry pointer to the next entry in the TX ring scheduling schedule, jump to step S201, and continue to wait for triggering.

[0104] The threshold and timer used in the above step S205 can be customized by the user according to the scheduling of time-sensitive messages. For example, each time a message is mounted, the counter is increased by 1. When the hardware processes the message, the number is reduced by the corresponding number. When the ring clearing operation is performed, the counter is set to 0; the timer increases with the system clock and is cleared after expiration. When the threshold is met or the timer expires, jump to step S207 and then jump to step S201, otherwise jump directly to step S207.

[0105] The present invention introduces a time scale on the basis of a standard DMA engine, uses a TX ring scheduling time table to control the time when time-sensitive packet information is mounted on the TX descriptor ring, and further controls the time when the DMA engine reads the time-sensitive packets in the memory, so that the standard "event-triggered" DMA engine has the characteristics of "time-triggered". By controlling the mounting time of the time-sensitive packet information, the time when the packet is submitted to the underlying hardware is controlled, so that the transmission of time-sensitive traffic conforms to the network scheduling plan, and the "last mile" problem of the time delay determinacy of time-sensitive flows on the sending side can be solved. At the same time, the present invention corrects the offset time of the mounting of time-sensitive packet information and the packet sending, so that the underlying hardware does not need to allocate too much storage space to accommodate the time-sensitive packets that arrive too early, which can save the storage resources of the underlying hardware and simplify the design of the underlying hardware. The present invention realizes the deterministic scheduling of time-sensitive traffic in mixed traffic through software, and can also improve the implementation flexibility, reduce the hardware design cost, thereby simplifying the hardware design and having better portability.

[0106] This embodiment further provides a DMA transmission start control device based on time-triggering, including a processor and a memory. The memory is used to store a computer program, and the processor is used to execute the computer program to execute the method as described above.

[0107] It can be understood that the above method of this embodiment can be executed by a single device, such as a computer or a server, etc., or can also be applied to a distributed scenario where multiple devices cooperate with each other to complete. In the case of a distributed scenario, one of the multiple devices can only execute one or more steps of the above method of this embodiment, and the multiple devices interact with each other to complete the above method. The processor can be implemented in ways such as a general-purpose CPU, a microprocessor, an application-specific integrated circuit, or one or more integrated circuits, and is used to execute relevant programs to implement the above method of this embodiment. The memory can be implemented in forms such as a read-only memory ROM, a random access memory RAM, a static storage device, and a dynamic storage device. The memory can store an operating system and other application programs. When implementing the above method of this embodiment through software or firmware, the relevant program codes are stored in the memory and are called and executed by the processor.

[0108] This embodiment further provides a computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, the method as described above is realized.

[0109] Those skilled in the art should understand that the above embodiments of the present invention can be provided as a method, a system, or a computer program product. Therefore, the present invention can take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware aspects. Moreover, the present invention can take the form of a computer program product implemented on one or more computer-readable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that contain computer-usable program code. The present invention is described with reference to the flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to the embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram can be realized by computer program instructions, and the combination of processes and / or blocks in the flowchart and / or block diagram can also be realized. These computer program instructions can be provided to the processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing devices to generate a machine, so that the instructions executed by the processor of the computer or other programmable data processing devices generate a device for realizing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks. These computer program instructions can also be stored in a computer-readable memory that can direct a computer or other programmable data processing devices to work in a specific manner, so that the instructions stored in the computer-readable memory generate a manufactured product including an instruction device, and the instruction device realizes the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks. These computer program instructions can also be loaded onto a computer or other programmable data processing devices, so that a series of operation steps are executed on the computer or other programmable devices to generate a computer-implemented process. Therefore, the instructions executed on the computer or other programmable devices provide steps for realizing the functions specified in the process Figure 1 one process or multiple processes and / or blocks Figure 1 one block or multiple blocks.

[0110] The above are only the preferred embodiments of the present invention and do not impose any form of limitation on the present invention. Although the present invention has been disclosed above with the preferred embodiments, it is not intended to limit the present invention. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the technical solution of the present invention should fall within the scope of the protection of the technical solution of the present invention.

Claims

1. A time-triggered DMA transmission start control method, characterized in that the steps Including: Step S01. Obtain the static scheduling timetable of time-sensitive traffic, calculate the mounting offset time and the ring clearing offset time according to the triggering time of the time-sensitive packets in the obtained static scheduling timetable, generate a TX ring scheduling timetable and configure it into the DMA transmission start control module. The mounting offset time is the offset of the time-sensitive packet information mounting time within the scheduling period, and the ring clearing offset time is the offset of clearing non-time-sensitive packet information in the TX descriptor ring within the scheduling period; Step S02. Run the DMA transmission start control module, poll the TX ring scheduling timetable, and each time when polling, judge whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring according to the ring clearing offset time in the TX ring scheduling timetable, and when it is judged that the mounting offset time of the time-sensitive packet information is reached, after mounting the offset address and the packet length corresponding to the time-sensitive packet information onto the TX descriptor ring, send a doorbell signal to the DMA transmission start register of the DMA controller; Step S03. The DMA controller starts the DMA read process according to the received doorbell signal, and sends the time-sensitive packets in the deterministic transmission buffer to the network.

2. The time-triggered DMA transmission start control method according to claim 1, wherein The fields in the TX ring scheduling timetable further include operations, offset addresses, and packet lengths. The operation is the operation that the DMA transmission start control module needs to execute when reaching the operation offset time, including clearing the descriptor information of non-time-sensitive packets, mounting the time-sensitive packet information onto the TX transmission descriptor ring, and sending a doorbell signal to notify the hardware to perform the DMA read process; the offset address is the offset address of the time-sensitive packet in the deterministic transmission buffer, and the time-sensitive flow is stored in a continuous memory area; the packet length is the length of the time-sensitive packet.

3. The time-triggered DMA transmission start control method according to claim 1, wherein In the step S01, the TX ring scheduling timetable is generated by adopting a preset scheduling algorithm. The input parameters of the preset scheduling algorithm include the static scheduling timetable of time-sensitive traffic, the DMA channel bandwidth, the processing time of the network card, the time consumed for clearing the descriptor information of other non-time-sensitive flows on the TX ring, the time consumed for mounting the descriptor information of the current time-sensitive flow, and the time consumed for refreshing the tail pointer. The content of the table entry of the static scheduling timetable includes any one or more of the source end, the destination end, the period, the packet length, and the deadline. The output parameters of the preset scheduling algorithm include an array of transmission buffer offset amounts of critical flows for marking the positions of critical flows in the transmission buffer and a scheduling timetable. The scheduling timetable includes any one or more fields such as the scheduling time of the operation, the specific operation type, the buffer offset amount for mounting the time-sensitive traffic, and the packet length of each time-sensitive traffic.

4. The time-triggered DMA transmission start control method according to claim 1, characterized in that Step S01 includes: Step S101. Initialize the transmission buffer offset amount array and the TX ring scheduling timetable according to the size of the static scheduling timetable; Step S102. Poll the static scheduling timetable, and calculate the storage offset address and the delayed mounting time of the time-sensitive packets in the deterministic buffer item by item according to the information of each time-sensitive packet; Step S103. Determine the mounting offset time of the time-sensitive message according to the sending time in the static scheduling time table and the delayed mounting time, and store them in the temporary array in sequence; Step S104. Calculate the ring clearing offset time according to the temporary array, and generate a schedule entry for the TX ring scheduling time table. The ring clearing offset time is calculated according to the mounting time of the current time-sensitive message information and the time consumed for ring clearing. The ring clearing offset time, the mounting offset time, the corresponding operation, the offset address, and the message length corresponding to the current time-sensitive traffic are added as a schedule entry to the TX ring scheduling time table. The time consumed for ring clearing is the time required to clear all non-time-sensitive message information on the ring before the time-sensitive message information is mounted; Step S105. Output the complete TX ring scheduling time table for use by the DMA transmission start control module.

5. The time-triggered DMA transmission start control method according to claim 4, characterized in that The delayed mounting time includes the descriptor dma processing time t_dma_desc, the data dma processing time t_dma_data, the time consumed for mounting the current time-sensitive flow descriptor information t_mount, the time consumed for refreshing the tail pointer t_tail, and the processing time of the network card t_nic.

6. The time-triggered DMA transmission start control method according to claim 4, wherein In step S103, the mounting offset time of the time-sensitive message is corrected by calculating the time consumed from the mounting of the time-sensitive message to the descriptor to the actual sending of the message by the network card.

7. The time-triggered DMA transmission start control method according to any one of claims 1 to 6, characterized in that The TX ring scheduling time table also includes a pointer for polling each item in the TX ring scheduling time table; the DMA transmission start control module compares the current global time with the item pointed to by the pointer of the TX ring scheduling time table to perform corresponding operations, that is, to determine whether it is necessary to clear the non-time-sensitive flow information in the current TX descriptor ring, or when it is determined that the mounting offset time of the time-sensitive message is reached, the offset address and message length corresponding to the time-sensitive message information are mounted on the TX descriptor ring, and a doorbell signal is sent to the DMA transmission start register of the DMA controller.

8. The time-triggered DMA transmission start control method according to any one of claims 1 to 6, characterized in that Step S02 includes: Step S201. After the DMA transmission start control module starts running, continuously obtain the global time and compare it with the current entry pointer offset time of the TX ring scheduling time table; Step S202. Determine whether the current time is the offset time of the TX ring scheduling time table. If so, jump to step S203; otherwise, jump to step S205; Step S203. Determine whether the offset time corresponding to the current time is the mounting offset of the time-sensitive message. If so, it is determined that the mounting offset time of the time-sensitive message is reached, and jump to step S204; otherwise, it is determined that the ring clearing offset time is reached and jump to step S206; Step S204. Write the storage offset address and message length of the current time-sensitive message into the descriptor ring, and transfer to step S207; Step S205. Determine whether the number of messages on the current ring reaches the threshold or the timer expires. If so, transfer to step S207; otherwise, return to step S201; Step S206. directly send the descriptor information of the non-critical message of the descriptor ring to TX to perform a clearing operation, that is, cancel the corresponding relationship between the descriptor and the corresponding non-critical message, and set the message value on the ring to 0, and then go to step S208; Step S207: Send a doorbell signal to the DMA send start register of the DMA controller; Step S208: Move the entry pointer to the next entry in the TX ring scheduling schedule, jump to step S201, and continue to wait for triggering.

9. A time-triggered DMA transmission start control device, comprising a processor and a memory, wherein the memory is used for storing a computer program, characterized in that The processor is configured to execute the computer program to perform the method according to any one of claims 1 to 8.

10. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, the method according to any one of claims 1 to 8 is implemented.

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