Micro-LED Display Chip and Its Preparation Method

Abstract

The present application relates to the field of semiconductor device technology, and discloses a Micro-LED display chip and a preparation method thereof. The Micro-LED display chip includes a substrate, at least two layers of LED unit layers and a conductive column. The substrate includes a plurality of first contacts. At least two layers of LED unit layers are stacked on top of the substrate, and each layer of LED unit layers includes a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units. The vertical projections of the plurality of LED units and the plurality of first contacts on the substrate do not overlap. The conductive reflective cup is electrically connected to the first doped semiconductor layer of the corresponding LED unit. The conductive reflective cup includes an extension extending to the outside of the side of the corresponding LED unit. The conductive column is used to electrically connect the extension to the corresponding first contact so that each LED unit can be driven separately. The present application can reduce the alignment accuracy requirements during processing, thereby reducing the difficulty of the processing technology and improving the yield of the device.

Description

Technical Field

[0001] The present application belongs to the field of semiconductor device technology, and specifically relates to a Micro-LED display chip and a method for preparing the same. Background Art

[0002] Micro-LED (micro light-emitting diode) display chips can be used in wearable devices, virtual reality (VR) / augmented reality (AR) and other devices to achieve self-luminescence.

[0003] In related technologies, the LED unit of the Micro-LED display chip is located directly above the corresponding contact and is vertically connected to the corresponding contact. For example, vertical connection is achieved through hybrid bonding. This places extremely high demands on positioning accuracy during processing, resulting in great processing difficulty and reduced yield. Summary of the Invention

[0004] This application aims to solve at least one of the technical problems existing in the related art.

[0005] Therefore, the first aspect of the present application provides a Micro-LED display chip.

[0006] The second aspect of the present application provides a method for preparing a Micro-LED display chip.

[0007] In view of this, according to the first aspect of the embodiment of the present application, a Micro-LED display chip is proposed, comprising: a substrate, the substrate including a plurality of first contacts; at least two LED unit layers stacked above the substrate, each of the LED unit layers comprising a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding one-to-one to the plurality of the LED units, the vertical projections of the plurality of LED units and the plurality of the first contacts on the substrate not overlapping, the LED units comprising a first doped semiconductor layer, an active layer and a second doped semiconductor layer arranged in a stacked manner, the conductive reflective cup being electrically connected to the first doped semiconductor layer of the corresponding LED unit, the conductive reflective cup comprising an extension extending to the outside of the side of the corresponding LED unit; a conductive column for electrically connecting the extension to the corresponding first contact so that each of the LED units can be driven individually.

[0008] In one possible implementation, at least two layers of LED unit layers include: a first LED unit layer, including a plurality of first LED units arranged at intervals and a first filling layer located between adjacent first LED units, the first filling layer being melt-bonded to the top of the substrate and forming a gap between the first LED units and the substrate; a second LED unit layer, disposed above the first LED unit layer, including a plurality of second LED units arranged at intervals.

[0009] In one possible implementation, the display chip also includes: a first planarization layer formed above the first LED unit layer; the second LED unit layer also includes a second filling layer located between adjacent second LED units, the second filling layer is melt-bonded to the top of the first planarization layer and forms a gap between the second LED unit and the first planarization layer.

[0010] In one possible implementation, the display chip also includes: a second planarization layer formed above the second LED unit layer; a third LED unit layer, including a plurality of third LED units arranged at intervals and a third filling layer located between adjacent third LED units, the third filling layer being melt-bonded to the top of the second planarization layer and forming a gap between the third LED unit and the second planarization layer; wherein, at least one of the first LED units and at least one adjacent second LED unit and at least one adjacent third LED unit constitute a full-color pixel point.

[0011] In a possible implementation, vertical projections of the plurality of LED units located in different LED unit layers on the substrate do not overlap.

[0012] In a possible implementation, the conductive reflective cup is disposed around a side surface and / or a bottom surface of the corresponding LED unit.

[0013] In one possible implementation, the display chip also includes: a transparent conductive layer, which is arranged on the upper surface of each of the LED units and electrically connected to the second doped semiconductor layer of the LED unit, and the transparent conductive layer includes an extended area located on the upper side of the LED unit; a common conductive column, which is electrically connected to multiple adjacent extended areas, and the multiple extended areas are located in different LED unit layers, so that the common conductive column is electrically connected to the second doped semiconductor layers of multiple adjacent LED units.

[0014] In a possible implementation, each layer of the LED unit further includes: a passivation layer, which is arranged between the LED unit and the corresponding conductive reflective cup, and the passivation layer at least covers the side surfaces of the LED unit and extends to the outside of the LED unit, so that the upper surface of the passivation layer is flush with the upper surface of the LED unit.

[0015] According to a second aspect of the embodiments of the present application, a method for preparing a Micro-LED display chip is proposed, comprising the following steps:

[0016] providing a substrate comprising a plurality of first contacts;

[0017] Prepare an LED unit layer, the LED unit layer comprising a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units, the LED units comprising a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked in layers, the conductive reflective cups being electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cups comprising protruding portions extending to the outside of the side surfaces of the corresponding LED units;

[0018] At least two layers of the LED units are stacked on top of the substrate, wherein vertical projections of the multiple LED units and the multiple first contacts on the substrate do not overlap, and the protruding portion of the conductive reflective cup is electrically connected to the corresponding first contact through a conductive column, so that each LED unit can be driven individually.

[0019] In one possible implementation, the steps of preparing the LED unit layer include:

[0020] Providing a substrate, wherein one side of the substrate is provided with an LED epitaxial layer;

[0021] Etching a side of the LED epitaxial layer away from the substrate to form a plurality of LED units;

[0022] forming a passivation layer, wherein the passivation layer at least covers the side surfaces of the LED units and the LED epitaxial layers between adjacent LED units;

[0023] forming a plurality of the conductive reflective cups, wherein the plurality of the conductive reflective cups correspond one-to-one to the plurality of the LED units and are electrically connected to the first doped semiconductor layers of the plurality of the LED units;

[0024] A filling layer is formed, where the filling layer covers the passivation layer and the plurality of conductive reflective cups.

[0025] In a possible implementation, the at least two LED unit layers include a first LED unit layer and a second LED unit layer, and the step of stacking the at least two LED unit layers on the substrate includes:

[0026] Melting and bonding the first LED unit layer onto the substrate, and forming a gap between the LED units of the first LED unit layer and the substrate;

[0027] The substrate and part of the LED epitaxial layer of the first LED unit layer are removed to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

[0028] In a possible implementation, the step of stacking at least two layers of LED units on the substrate further includes:

[0029] forming a transparent conductive layer, the transparent conductive layer covering at least the upper surface of each LED unit of the first LED unit layer and electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covering at least a portion of the upper surface of the passivation layer of the first LED unit layer to form an extended region;

[0030] forming a first planarization layer, wherein the first planarization layer covers the first LED unit layer and the transparent conductive layer formed on the first LED unit layer;

[0031] The second LED unit layer is melt-bonded on top of the first planarization layer.

[0032] In one possible implementation, the step of forming the first planarization layer includes:

[0033] forming a first transition layer, wherein the first transition layer covers the passivation layer of the first LED unit layer and the transparent conductive layer formed on the first LED unit layer;

[0034] Etching the first transition layer and the first LED unit layer to form a plurality of first through holes exposing a plurality of the first contacts, wherein some of the first through holes penetrate the protruding portion of the conductive reflective cup of the first LED unit layer;

[0035] forming a plurality of conductive pillars in the plurality of the first through holes, wherein some of the conductive pillars are electrically connected to the first contacts and the protruding portions of the conductive reflective cups of the corresponding first LED unit layers respectively;

[0036] A portion of the first transition layer is removed to form a first planarization layer.

[0037] In a possible implementation, the step of melt-bonding the second LED unit layer onto the first planarization layer includes:

[0038] Melting and bonding the filling layer of the second LED unit layer onto the first planarization layer, and forming a gap between the LED units of the second LED unit layer and the first planarization layer;

[0039] The substrate and part of the LED epitaxial layer of the second LED unit layer are removed to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

[0040] In a possible implementation, after the step of melt-bonding the second LED unit layer onto the first planarization layer, the preparation method further includes:

[0041] forming a transparent conductive layer, the transparent conductive layer covering at least the upper surface of each LED unit of the second LED unit layer and being electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covering at least a portion of the upper surface of the passivation layer of the second LED unit layer to form an extended region;

[0042] forming a second transition layer, wherein the second transition layer covers the passivation layer of the second LED unit layer and the transparent conductive layer formed on the second LED unit layer;

[0043] A portion of the second transition layer is removed to form a second planarization layer.

[0044] In a possible implementation, before the step of removing a portion of the second transition layer, the preparation method further includes:

[0045] Etching the second transition layer and the second LED unit layer to form a second through hole, wherein the second through hole passes through the extended portion of the conductive reflector cup of the second LED unit layer and exposes a portion of the conductive column formed in the first through hole;

[0046] The second through hole is filled and a conductive column is formed in the second through hole. The conductive column formed in the second through hole is electrically connected to the corresponding conductive column formed in the first through hole, so as to electrically connect the extended portion of the conductive reflector cup of the second LED unit layer and the corresponding first contact.

[0047] In one possible implementation, a third through hole is formed while etching the second transition layer and the second LED unit layer to form the second through hole, and the third through hole passes through an extended region of the transparent conductive layer formed on the first LED unit layer and an extended region of the transparent conductive layer formed on the second LED unit layer.

[0048] A common conductive column is formed in the third through hole, wherein the common conductive column is electrically connected to the extended region formed on the transparent conductive layer of the first LED unit layer and the extended region formed on the transparent conductive layer of the second LED unit layer, respectively.

[0049] The Micro-LED display chip and its manufacturing method provided in this application can achieve at least the following technical effects:

[0050] The vertical projections of the multiple LED units and the multiple first contacts on the substrate do not overlap, so the LED units and the corresponding first contacts are not aligned in the same vertical direction, eliminating the need for vertical connection. For example, the first contacts can be located below and to the side of the corresponding LED unit to be connected. This increases the operating space for connection processing, avoids or reduces damage to the LED units during processing, and reduces the alignment accuracy requirements during processing.

[0051] Multiple conductive reflector cups correspond one-to-one with multiple LED units. The conductive reflector cups are electrically connected to the first doped semiconductor layer of the corresponding LED unit, thereby achieving electrical connection between the conductive reflector cups and the corresponding LED unit. The conductive reflector cups include extensions extending to the exterior of the side of the corresponding LED unit. The extensions are electrically connected to the corresponding first contacts via conductive pillars, thereby achieving electrical connection between the first doped semiconductor layer of the LED unit and the corresponding first contacts. This allows each LED unit to be driven individually, reduces alignment accuracy requirements during processing, and thus reduces processing difficulty and improves device yield. It also extends the current path, dissipates thermal and mechanical stresses, and further improves device performance.

[0052] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0053] One or more embodiments are exemplarily described by corresponding drawings. These exemplary descriptions and drawings do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements. The drawings do not constitute a scale limitation. In addition,

[0054] Figure 1 A schematic diagram of the structure of a display chip provided in an embodiment of the present disclosure;

[0055] Figure 2 Schematic diagram of the structure in the process of preparing the first LED unit layer provided in the embodiment of the present disclosure Figure 1 ;

[0056] Figure 3 Schematic diagram of the structure in the process of preparing the first LED unit layer provided in the embodiment of the present disclosure Figure 2 ;

[0057] Figure 4 Schematic diagram of the structure in the process of preparing the first LED unit layer provided in the embodiment of the present disclosure Figure 3 ;

[0058] Figure 5 Schematic diagram of the structure in the process of preparing the first LED unit layer provided in the embodiment of the present disclosure Figure 4 ;

[0059] Figure 6 Schematic diagram of the structure in the process of preparing the first LED unit layer provided in the embodiment of the present disclosure Figure 5 ;

[0060] Figure 7 Schematic diagram of the structure in the process of preparing the second LED unit layer provided in the embodiment of the present disclosure Figure 1 ;

[0061] Figure 8 Schematic diagram of the structure in the process of preparing the second LED unit layer provided in the embodiment of the present disclosure Figure 2 ;

[0062] Figure 9 Schematic diagram of the structure in the process of preparing the second LED unit layer provided in the embodiment of the present disclosure Figure 3 ;

[0063] Figure 10 Schematic diagram of the structure in the process of preparing the second LED unit layer provided in the embodiment of the present disclosure Figure 4 ;

[0064] Figure 11 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 1 ;

[0065] Figure 12 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 2 ;

[0066] Figure 13 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 3 ;

[0067] Figure 14 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 4 ;

[0068] Figure 15 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 5 ;

[0069] Figure 16 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 6 ;

[0070] Figure 17 Schematic diagram of the structure in the process of preparing a display chip provided in the embodiment of the present disclosure Figure 7 ;

[0071] Figure 18 A flow chart of a method for manufacturing a display chip provided in one embodiment of the present disclosure;

[0072] Figure 19 A flow chart for preparing an LED unit layer provided in an embodiment of the present disclosure;

[0073] Figure 20 A flow chart of a method for manufacturing a display chip provided in another embodiment of the present disclosure;

[0074] Figure 21A flowchart of a method for manufacturing a display chip provided in yet another embodiment of the present disclosure;

[0075] Figure 22 A flowchart of a method for manufacturing a display chip provided in yet another embodiment of the present disclosure.

[0076] The reference numerals indicate:

[0077] 1: Display chip;

[0078] 10: substrate; 11: first contact;

[0079] 20: first LED unit layer; 21: first LED unit; 22: first conductive reflector cup; 221: first extension; 23: first fill layer; 24: first passivation layer; 25: first LED epitaxial layer; 26: first substrate; 27: first through hole;

[0080] 30: second LED unit layer; 31: second LED unit; 32: second conductive reflector cup; 321: second extension; 33: second fill layer; 34: second passivation layer; 35: second LED epitaxial layer; 36: second substrate; 37: second through hole; 38: third through hole;

[0081] 40: conductive pillar; 50: first planarization layer; 51: first transition layer; 60: second planarization layer; 61: second transition layer; 70: transparent conductive layer; 71: extension region; 80: common conductive pillar. DETAILED DESCRIPTION

[0082] In order to be able to understand the features and technical content of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The accompanying drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the sake of convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0083] In the description and claims of the embodiments of the present disclosure, as well as in the accompanying drawings, the terms "first," "second," and the like are used to distinguish similar items and are not necessarily used to describe a particular order or precedence. It should be understood that the terms used in this manner are interchangeable where appropriate to describe the embodiments of the present disclosure herein. In addition, the terms "including," "having," and any variations thereof are intended to cover non-exclusive inclusions.

[0084] In the embodiments of the present disclosure, the terms "upper", "lower", "inside", "middle", "outside", "front", "back" and the like indicate directions or positional relationships based on the directions or positional relationships shown in the accompanying drawings. These terms are mainly intended to better describe the embodiments of the present disclosure and their embodiments, and are not intended to limit the indicated devices, elements or components to having a specific direction, or to be constructed and operated in a specific direction. Moreover, in addition to being used to indicate directions or positional relationships, some of the above terms may also be used to indicate other meanings. For example, the term "upper" may also be used to indicate a certain dependency or connection relationship in certain circumstances. For those of ordinary skill in the art, the specific meanings of these terms in the embodiments of the present disclosure can be understood according to specific circumstances.

[0085] Furthermore, the terms "disposed," "connected," and "fixed" should be interpreted broadly. For example, "connected" can mean a fixed connection, a removable connection, or an integral structure; it can be a mechanical connection or an electrical connection; it can be a direct connection, an indirect connection through an intermediary, or an internal connection between two devices, elements, or components. Those skilled in the art will understand the specific meanings of these terms in the embodiments of this disclosure based on the specific circumstances.

[0086] Unless otherwise stated, the term "plurality" means two or more.

[0087] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B means: A or B.

[0088] The term "and / or" describes an association between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or A and B.

[0089] It should be noted that, in the absence of conflict, the embodiments and features in the embodiments of the present disclosure can be combined with each other.

[0090] As used in the present disclosure, the term "layer" refers to a portion of a material comprising an area having a certain thickness. A layer may extend over the entire underlying or superstructure, or may have an extent less than that of the underlying or superstructure. A layer may extend horizontally, vertically, and / or along a tapered surface.

[0091] The term "micro" LED is used in the embodiments of this disclosure to refer to the descriptive size of certain devices or structures according to embodiments of the present application. The term "micro" device or structure as used herein is intended to refer to a scale of 0.1 μm to 100 μm. However, it should be understood that embodiments of the present application are not necessarily limited thereto, and certain aspects of the embodiments may be applicable to larger and potentially smaller scales.

[0092] The term "substrate" as used in the embodiments of the present disclosure refers to the material onto which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a variety of semiconductor materials, such as silicon, silicon carbide, gallium nitride, germanium, gallium arsenide, and indium phosphide. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or sapphire wafer. Further alternatively, the substrate can have semiconductor devices or circuits formed therein.

[0093] Combine Figures 1 to 17 As shown, according to the first aspect of the embodiment of the present application, a Micro-LED display chip 1 is proposed, comprising a substrate 10 and at least two layers of LED unit layers. The substrate 10 includes a plurality of first contacts 11. At least two layers of LED unit layers are stacked on top of the substrate 10. Each layer of LED unit layer includes a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units one by one. The vertical projections of the plurality of LED units and the plurality of first contacts 11 on the substrate 10 do not overlap. The LED unit includes a first doped semiconductor layer, an active layer, and a second doped semiconductor layer arranged in a stacked manner. The conductive reflective cup is electrically connected to the first doped semiconductor layer of the corresponding LED unit. The conductive reflective cup includes an extension extending to the outside of the side of the corresponding LED unit. The conductive column 40 is used to electrically connect the extension to the corresponding first contact 11 so that each LED unit can be driven individually.

[0094] At least two layers of LED units are stacked on the substrate 10, and each layer of LED units includes a plurality of LED units arranged at intervals to achieve a multi-color or full-color display of the display chip 1. In the description of the embodiment of the present disclosure, the terms "upper" and "lower" indicating the orientation or position relationship are based on the attached Figure 1 The orientation or position relationship shown will not be described in detail below.

[0095] Multiple conductive reflector cups correspond one-to-one with multiple LED units. The conductive reflector cups are electrically connected to the first doped semiconductor layer of the corresponding LED unit, thereby electrically connecting the conductive reflector cups to the corresponding LED unit. The conductive reflector cups include an extension extending to the outside of the side of the corresponding LED unit. The extension allows the LED unit to be electrically connected to the corresponding first contact 11 without requiring a vertical connection. The extension is electrically connected to the corresponding first contact 11 via a conductive column 40, thereby electrically connecting the first doped semiconductor layer of the LED unit to the corresponding first contact 11. This allows each LED unit to be driven individually, reduces the alignment accuracy requirements during processing, and thus reduces the difficulty of the processing process and improves the yield of the device. It can also extend the current path, disperse thermal and mechanical stress, and further improve device performance. The material of the conductive reflector cups is not limited, for example, it can be aluminum or silver. The material of the conductive column 40 is not limited, for example, it can be copper or tungsten. In the description of the embodiments of the present disclosure, "corresponding" refers to the relationship between two structures that need to be connected to each other or are positionally related, and will not be further described below.

[0096] The vertical projections of the plurality of LED units and the plurality of first contacts 11 on the substrate 10 do not overlap, so that the LED units and the corresponding first contacts 11 are not in the same vertical direction and do not need to be vertically connected. Figure 1 As shown, the first contact 11 is located on the side below the corresponding connected LED unit, which can increase the operating space for connection processing, avoid or reduce damage to the LED unit during processing, and reduce the alignment accuracy requirements during processing. In the description of the disclosed embodiment, the vertical projection on the substrate 10 refers to the direction perpendicular to the upper surface of the substrate 10 (i.e., along the Figure 1 The projection in the upper and lower directions will not be described in detail below.

[0097] The substrate 10 may be provided with a circuit layer including complementary metal oxide semiconductor (CMOS) devices or thin film transistor (TFT) devices, etc. These CMOS devices or TFT devices may constitute a driving circuit.

[0098] The substrate 10 includes multiple first contacts 11, which can be anode metal contacts. The substrate 10 also includes at least one second contact (not shown), which can be a cathode metal contact. The LED unit includes a stacked first doped semiconductor layer, an active layer, and a second doped semiconductor layer. The first doped semiconductor layer is located closer to the substrate 10. The first doped semiconductor layer can be a p-type semiconductor layer, such as p-type gallium nitride (GaN) or p-type aluminum indium gallium nitride (AlInGaN). The second doped semiconductor layer can be an n-type semiconductor layer, such as n-type gallium nitride (GaN) or n-type aluminum indium gallium nitride (AlInGaN). The first doped semiconductor layer of each LED unit is electrically connected to a corresponding first contact 11. The second doped semiconductor layers of multiple LED units can be electrically connected to the second contact together, forming a common cathode structure. This allows each LED unit to be driven individually, thereby driving the active layer of each LED unit to emit light (for example, green, blue, or red light).

[0099] In a possible implementation, the size of the LED unit is 0.1 μm to 10 μm. The size in this embodiment may refer to a planar size such as length, width or diameter of the LED unit.

[0100] In some embodiments, combined Figure 1 As shown, at least two LED unit layers include a first LED unit layer 20 and a second LED unit layer 30. The first LED unit layer 20 includes a plurality of first LED units 21 arranged at intervals and a first fill layer 23 located between adjacent first LED units 21. The first fill layer 23 is fusion-bonded to the top of the substrate 10 and forms a gap between the first LED units 21 and the substrate 10. The second LED unit layer 30 is disposed above the first LED unit layer 20 and includes a plurality of second LED units 31 arranged at intervals.

[0101] Specifically, the first LED unit layer 20 and the second LED unit layer 30 are stacked on the substrate 10 .

[0102] The first LED unit layer 20 includes a plurality of first LED units 21 arranged in a spaced relationship and a first leveling layer 23 positioned between adjacent first LED units 21. The first leveling layer 23 is fusion bonded to the substrate 10, allowing the first LED unit layer 20 to be positioned above the substrate 10, thereby enabling the plurality of first LED units 21 to be positioned above the substrate 10. This simplifies the manufacturing process and reduces the difficulty of fabrication. The first leveling layer 23 creates a gap between the first LED units 21 and the substrate 10, improving the reliability of the fusion bonding and, consequently, the reliability and performance of the device. The material of the first leveling layer 23 is not limited, and can be, for example, silicon dioxide.

[0103] By melt-bonding the first filling layer 23 to the substrate 10 and electrically connecting the LED unit to the corresponding first contact 11 through the conductive reflective cup and the conductive column, the alignment accuracy requirement is reduced and the processing difficulty is reduced.

[0104] The vertical projections of the multiple first LED units 21 and the multiple first contacts 11 on the substrate 10 do not overlap, which can increase the operating space when the first LED units 21 are connected to the corresponding first contacts 11, avoid or reduce damage to the first LED units 21 during processing, and reduce the positioning accuracy requirements during processing, thereby improving the device yield.

[0105] The first LED unit layer 20 further includes a plurality of first conductive reflective cups 22 corresponding one-to-one to the plurality of first LED units 21 . Each first conductive reflective cup 22 is electrically connected to the first doped semiconductor layer of the corresponding first LED unit 21 .

[0106] Furthermore, by disposing the second LED unit layer 30 above the first LED unit layer 20, the first LED unit layer 20 and the second LED unit layer 30 are stacked above the substrate 10. The second LED unit layer 30 includes a plurality of second LED units 31 arranged at intervals. The vertical projections of the plurality of second LED units 31 and the plurality of first contacts 11 on the substrate 10 do not overlap. This can increase the operating space when connecting the second LED units 31 to the corresponding first contacts 11, avoid or reduce damage to the second LED units 31 during processing, reduce the alignment accuracy requirements during processing, and improve the device yield.

[0107] The second LED unit layer 30 further includes a plurality of second conductive reflective cups 32 corresponding one-to-one to the plurality of second LED units 31 . Each second conductive reflective cup 32 is electrically connected to the first doped semiconductor layer of the corresponding second LED unit 31 .

[0108] During actual processing, the first filler layer 23 can be directly melt-bonded to the substrate 10. The surface material of the substrate 10 on the side where the first filler layer 23 is melt-bonded can include silicon dioxide. Alternatively, a material layer (e.g., a silicon dioxide layer) can be provided on the upper surface of the substrate 10, and the first filler layer 23 can be melt-bonded to the silicon dioxide layer to achieve placement of the plurality of second LED units 31 above the substrate 10.

[0109] In the embodiment of the present disclosure, the first LED unit 21 refers to the LED unit of the first LED unit layer 20, the first passivation layer 24 refers to the passivation layer of the first LED unit layer 20, the first conductive reflective cup 22 refers to the conductive reflective cup of the first LED unit layer 20, the first conductive reflective cup 22 includes a first protruding portion 221, and the first leveling layer 23 refers to the leveling layer of the first LED unit layer 20, which will not be repeated below.

[0110] In the embodiment of the present disclosure, the second LED unit 31 refers to the LED unit of the second LED unit layer 30, the second passivation layer 34 refers to the passivation layer of the second LED unit layer 30, the second conductive reflector cup 32 refers to the conductive reflector cup of the second LED unit layer 30, the second conductive reflector cup 32 includes a second protruding portion 321, and the second leveling layer 33 refers to the leveling layer of the second LED unit layer 30, which will not be repeated below.

[0111] In some embodiments, combined Figure 1 and Figures 14 to 17 As shown, the display chip 1 further includes a first planarization layer 50. The first planarization layer 50 is formed above the first LED unit layer 20. The second LED unit layer 30 further includes a second fill layer 33 located between adjacent second LED units 31. The second fill layer 33 is fusion-bonded to the first planarization layer 50 and forms a gap between the second LED units 31 and the first planarization layer 50.

[0112] The first planarization layer 50 is formed above the first LED unit layer 20 to protect the first LED unit 21 and prepare for the fusion bonding process of the second LED unit layer 30. The material of the first planarization layer 50 is not limited, for example, it can be silicon dioxide.

[0113] The second LED unit layer 30 also includes a second fill layer 33 positioned between adjacent second LED units 31. By fusion bonding the second fill layer 33 to the first planarizing layer 50, the second LED unit layer 30 is positioned above the first LED unit layer 20, thereby enabling multiple second LED units 31 to be positioned above the substrate 10. This simplifies the manufacturing process and reduces the difficulty of fabrication. The second fill layer 33 creates a gap between the second LED units 31 and the first planarizing layer 50, improving the reliability of the fusion bonding and, consequently, the reliability and performance of the device. The material of the second fill layer 33 is not limited, and can be, for example, silicon dioxide.

[0114] By fusion bonding the second fill layer 33 to the first planarization layer 50, and electrically connecting the LED units to the corresponding first contacts 11 via the conductive reflector cups and conductive pillars, alignment accuracy requirements are reduced, thereby lowering processing difficulty. In other words, the LED unit layer of the disclosed embodiment is stacked on top of the substrate 10 via fusion bonding, and the LED units of the LED unit layer are electrically connected to the corresponding first contacts 11 via the conductive pillars. Compared to hybrid bonding, this embodiment reduces alignment accuracy requirements during processing, reduces processing difficulty, and improves device yield.

[0115] In some embodiments, the display chip 1 further includes a second planarization layer 60 and a third LED unit layer. The second planarization layer 60 is formed above the second LED unit layer 30. The third LED unit layer includes a plurality of third LED units arranged in a spaced relationship and a third fill layer located between adjacent third LED units. The third fill layer is fusion-bonded to the second planarization layer 60 to create a space between the third LED units and the second planarization layer 60. At least one first LED unit 21, at least one adjacent second LED unit 31, and at least one adjacent third LED unit constitute a full-color pixel.

[0116] The second planarization layer 60 is formed above the second LED unit layer 30 to protect the second LED unit 31 and prepare for the fusion bonding process of the third LED unit layer. The material of the second planarization layer 60 is not limited, for example, it can be silicon dioxide.

[0117] The third LED unit layer includes multiple third LED units arranged in a spaced-apart pattern and a third fill layer positioned between adjacent third LED units. The third fill layer is fused and bonded to the second planarizing layer 60, allowing the third LED unit layer to be positioned above the second LED unit layer 30. This allows multiple third LED units to be positioned above the substrate 10, simplifying the manufacturing process and reducing manufacturing difficulty. The third fill layer creates a gap between the third LED units and the second planarizing layer 60, improving the reliability of the fusion bonding and, consequently, the reliability and performance of the device. The third fill layer can be made of any material, such as silicon dioxide.

[0118] The first LED unit 21 emits a first color (e.g., blue light), the second LED unit 31 emits a second color (e.g., green light), and the third LED unit emits a third color (e.g., red light). The first, second, and third colors are different. At least one first LED unit 21, at least one adjacent second LED unit 31, and at least one adjacent third LED unit form a full-color pixel, achieving full-color display.

[0119] The vertical projections of the multiple third LED units and the multiple first contacts 11 on the substrate 10 do not overlap, which can increase the operating space when the third LED units are connected to the corresponding first contacts 11, avoid or reduce damage to the first LED units 21 during processing, and reduce the positioning accuracy requirements during processing, thereby improving the device yield.

[0120] The third LED unit layer further includes a plurality of third conductive reflective cups corresponding one-to-one to the plurality of third LED units, and each third conductive reflective cup is electrically connected to the first doped semiconductor layer of the corresponding third LED unit.

[0121] In the embodiment of the present disclosure, the third LED unit refers to the LED unit of the third LED unit layer, the third conductive reflector cup refers to the conductive reflector cup of the third LED unit layer, the third conductive reflector cup includes a third protruding portion, and the third leveling layer refers to the leveling layer of the third LED unit layer, which will not be repeated below.

[0122] In some embodiments, vertical projections of multiple LED units located in different LED unit layers on the substrate 10 do not overlap.

[0123] Specifically, if Figure 1 As shown, the vertical projections of the plurality of first LED units 21 and the plurality of second LED units 31 on the substrate 10 do not overlap, thereby reducing optical crosstalk and improving the display effect. Alternatively, the vertical projections of the plurality of first LED units 21, the plurality of second LED units 31, and the plurality of third LED units on the substrate 10 do not overlap.

[0124] Of course, the vertical projections of the first LED unit 21 and the second LED unit 31 on the substrate 10 may also overlap to improve brightness and color uniformity.

[0125] In some embodiments, the conductive reflective cup is disposed around the side and / or bottom of the corresponding LED unit.

[0126] By surrounding the conductive reflective cup on the side or bottom of the corresponding LED unit, the light emitted by the corresponding LED unit can be reflected, thereby improving the light extraction efficiency and preventing or reducing optical crosstalk.

[0127] like Figure 1 and Figures 11 to 17 As shown, by surrounding the conductive reflective cup on the side and bottom of the corresponding LED unit, the light emitted by the corresponding LED unit can be effectively reflected, reducing the light hitting the adjacent pixels, improving the light output efficiency, preventing or reducing optical crosstalk, and making the light spot more concentrated and the pixel points more compact, thereby improving the resolution and display effect of the device.

[0128] In some embodiments, combined Figure 1As shown, the display chip 1 further includes a transparent conductive layer 70 and a common conductive pillar 80. The transparent conductive layer 70 is disposed on the upper surface of each LED unit and is electrically connected to the second doped semiconductor layer of the LED unit. The transparent conductive layer 70 includes an extended region 71 located on the upper side of the LED unit. The common conductive pillar 80 is electrically connected to multiple adjacent extended regions 71. The multiple extended regions 71 are located on different LED unit layers, thereby electrically connecting the common conductive pillar 80 to the second doped semiconductor layers of multiple adjacent LED units.

[0129] A transparent conductive layer 70 is disposed on the upper surface of each LED unit and electrically connected to the second doped semiconductor layer of the corresponding LED unit, thereby electrically connecting the second doped semiconductor layers of multiple LED units to a common conductive pillar 80. Common conductive pillar 80 can subsequently be connected to a second contact, thereby electrically connecting the second doped semiconductor layers of multiple LED units to the second contact, allowing each LED to be driven independently. The material of transparent conductive layer 70 is not limited, and may be, for example, indium tin oxide (ITO). The material of common conductive pillar 80 is not limited, and may be, for example, copper or tungsten.

[0130] The transparent conductive layer 70 includes an extended region 71 located on the upper side of the LED unit, that is, the transparent conductive layer 70 extends from the corresponding LED unit to form the extended region 71, so that the second doped semiconductor layer of the LED unit is connected to the common conductive column 80 through the transparent conductive layer 70, thereby increasing the processing space and reducing the processing difficulty.

[0131] The common conductive pillar 80 is electrically connected to the extended regions 71 of the adjacent plurality of transparent conductive layers 70, so that the second doped semiconductor layers of the adjacent plurality of LED units are electrically connected to the common conductive pillar 80. The extended regions 71 of the plurality of transparent conductive layers 70 are located in different LED unit layers. For example, a common conductive pillar 80 is electrically connected to at least one extended region 71 formed on the first LED unit layer 20 and at the same time, is electrically connected to at least one extended region 71 formed on the second LED unit layer 30. This facilitates processing and makes the device structure more compact.

[0132] In some embodiments, as Figure 1 As shown, each LED unit layer also includes a passivation layer. The passivation layer is disposed between the LED unit and the corresponding conductive reflector cup. The passivation layer covers at least the side surfaces of the LED unit and extends to the outside of the LED unit, so that the upper surface of the passivation layer is flush with the upper surface of the LED unit.

[0133] like Figure 1As shown, the passivation layer is provided between the LED unit and the corresponding conductive reflector cup. The passivation layer covers at least the side surfaces of the LED unit to protect the LED unit and prevent or reduce leakage. The passivation layer extends to the outside of the LED unit, so that the upper surface of the passivation layer is flush with the upper surface of the LED unit. This allows the passivation layer to serve as a position reference during processing, reducing the difficulty of the processing, avoiding or reducing damage to the device caused by excessive processing, and protecting the LED unit during processing. For example, when etching the LED epitaxial layer, etching stops when it reaches the passivation layer to protect the LED unit, obtain a complete LED unit, and improve processing efficiency and accuracy. The material of the passivation layer is not limited; for example, it can be silicon dioxide (SiO2) or aluminum oxide (Al2O3).

[0134] Combine Figure 18 As shown, according to the second aspect of the embodiment of the present application, a method for preparing a Micro-LED display chip is provided, comprising the following steps:

[0135] S181. Provide a substrate, wherein the substrate includes a plurality of first contacts.

[0136] The plurality of first contacts 11 may be electrically connected to the first doped semiconductor layers of the plurality of LED units, so that each LED unit can be driven individually.

[0137] S182. Prepare an LED unit layer, the LED unit layer including a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units one by one, the LED unit including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer arranged in a stacked manner, the conductive reflective cup being electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cup including an extension extending to the outside of the side surface of the corresponding LED unit.

[0138] By preparing the LED unit layer, preparation is made for stacking at least two LED unit layers on the substrate 10. The technical effects of each structure in the LED unit layer refer to the above embodiments of the present disclosure and will not be repeated here.

[0139] S183. Stack at least two layers of LED units on top of the substrate, wherein vertical projections of the multiple LED units and the multiple first contacts on the substrate do not overlap, and the protruding portions of the conductive reflective cups are electrically connected to the corresponding first contacts through conductive columns, so that each LED unit can be driven individually.

[0140] Combine Figure 1As shown, at least two layers of LED units are stacked on top of a substrate 10. The vertical projections of the multiple LED units and the multiple first contacts 11 on the substrate 10 do not overlap, reducing the alignment accuracy requirements during processing, thereby reducing the difficulty of the processing and improving the device yield. This also extends the current path, dissipates thermal and mechanical stresses, and further improves device performance.

[0141] Combine Figure 19 As shown, in some embodiments, the steps of preparing the LED unit layer include:

[0142] S191. Provide a substrate, wherein an LED epitaxial layer is provided on one side of the substrate.

[0143] Combine Figures 2 to 10 As shown, the substrate can be used to provide support. LED epilayers can be grown on one side of the substrate, providing stable support for the growth of the LED epilayers and the processing of the LED unit. The substrate material is not limited; for example, it can be silicon. The LED epilayer material is also not limited; for example, it can be gallium nitride (GaN).

[0144] In the embodiments of the present disclosure, Figures 2 to 10 As shown, the first substrate 26 refers to the substrate of the first LED unit layer 20, the first LED epitaxial layer 25 refers to the LED epitaxial layer of the first LED unit layer 20, the second substrate 36 refers to the substrate of the second LED unit layer 30, and the second LED epitaxial layer 35 refers to the LED epitaxial layer of the second LED unit layer 30, which will not be repeated below.

[0145] S192, etching the side of the LED epitaxial layer away from the substrate to form a plurality of LED units.

[0146] By etching the side of the LED epitaxial layer away from the substrate, multiple LED units are formed. Specifically, the LED epitaxial layer can be etched by the mesa (MESA) etching process to form multiple LED units. For example, Figure 2 and Figure 3 As shown, the side of the first LED epitaxial layer 25 away from the first substrate 26 is etched to form a plurality of first LED units 21. For example, Figure 7 As shown, the side of the second LED epitaxial layer 35 facing away from the second substrate 36 is etched to form a plurality of second LED units 31 .

[0147] S193 , forming a passivation layer, wherein the passivation layer at least covers the side surfaces of the LED units and the LED epitaxial layers between adjacent LED units.

[0148] A passivation layer can be formed by depositing a material (e.g., aluminum oxide or silicon dioxide) so that the passivation layer at least covers the side surfaces of the LED unit and the LED epitaxial layer between adjacent LED units. Figure 4 and Figure 8 As shown, a material can be deposited on the surface of the etched LED epitaxial layer and the surface of the LED unit to form a passivation material layer. The passivation material layer is then etched to form a window, which exposes a portion of the surface of the LED unit facing away from the substrate, preparing for electrical connection between the first doped semiconductor layer of the LED unit and the conductive reflector cup.

[0149] A specific example, combined with Figure 4 As shown, when preparing the first LED unit layer 20 , a first passivation layer 24 is formed. The first passivation layer 24 at least covers the side surfaces of the first LED units 21 and the first LED epitaxial layers 25 between adjacent first LED units 21 .

[0150] Another specific example, combined with Figure 8 As shown, when preparing the second LED unit layer 30 , a second passivation layer 34 is formed. The second passivation layer 34 at least covers the side surfaces of the second LED units 31 and the second LED epitaxial layers 35 between adjacent second LED units 31 .

[0151] S194 , forming a plurality of conductive reflective cups, wherein the plurality of conductive reflective cups correspond to the plurality of LED units one by one and are electrically connected to the first doped semiconductor layers of the plurality of LED units.

[0152] The plurality of conductive reflective cups are used to prepare for electrical connection between the first doped semiconductor layer of the LED unit and the corresponding first contacts 11. The technical effects of the conductive reflective cups are described in the foregoing embodiments of the present disclosure and will not be elaborated on here.

[0153] Specifically, a metal material can be deposited on the side of the passivation layer facing away from the substrate to form a reflective metal layer. The reflective metal layer can also cover a portion of the surface of the LED unit facing away from the substrate, and the reflective metal layer is electrically connected to the first doped semiconductor layer of the corresponding LED unit. The reflective metal layer is processed through a photolithography patterning process to form a conductive reflective cup, which is then positioned around the side of the LED unit and the side of the LED unit facing away from the substrate.

[0154] A specific example, such as Figure 5 As shown, when preparing the first LED unit layer 20 , a plurality of first conductive reflective cups 22 are formed. The plurality of first conductive reflective cups 22 correspond to the plurality of first LED units 21 one by one and are electrically connected to the first doped semiconductor layers of the plurality of first LED units 21 .

[0155] Another specific example, such as Figure 9As shown, when preparing the second LED unit layer 30 , a plurality of second conductive reflective cups 32 are formed. The plurality of second conductive reflective cups 32 correspond to the plurality of second LED units 31 one by one and are electrically connected to the first doped semiconductor layers of the plurality of second LED units 31 .

[0156] S195. Form a filling layer, where the filling layer covers the passivation layer and the plurality of conductive reflective cups.

[0157] A fill layer is formed to cover the passivation layer and multiple conductive reflector cups in preparation for melt bonding. Specifically, a material (for example, silicon dioxide) is deposited on the surface of the passivation layer facing away from the substrate and the surface of the conductive reflector cups facing away from the substrate to form a fill layer. Chemical mechanical polishing (CMP) is then used to partially remove the fill layer to form a fill layer. This facilitates melt bonding and creates a gap between the surface of the fill layer facing away from the substrate and the conductive reflector cups.

[0158] A specific example, such as Figure 6 As shown, when preparing the first LED unit layer 20, a first filler layer 23 is formed, which covers the first passivation layer 24 and the plurality of first conductive reflective cups 22. A gap is formed between the surface of the first filler layer 23 facing away from the first substrate 26 and the first conductive reflective cups 22, so that after the first filler layer 23 is melt-bonded to the substrate 10, a gap is formed between the first conductive reflective cups 22 and the substrate 10.

[0159] Another specific example, such as Figure 10 As shown, when preparing the second LED unit layer 30, a second fill layer 33 is formed, which covers the second passivation layer 34 and the plurality of second conductive reflective cups 32. A gap is formed between the surface of the second fill layer 33 facing away from the second substrate 36 and the second conductive reflective cups 32, so that after the second fill layer 33 is melt-bonded to the first planarizing layer 50, a gap is formed between the second conductive reflective cups 32 and the first planarizing layer 50.

[0160] Combine Figure 11 and Figure 12 As shown, in some embodiments, the at least two LED unit layers include a first LED unit layer 20 and a second LED unit layer 30. The step of stacking the at least two LED unit layers on the substrate 10 includes: melt-bonding the first LED unit layer 20 on the substrate 10, and forming a gap between the LED units of the first LED unit layer 20 and the substrate 10. Removing the substrate and a portion of the LED epitaxial layer of the first LED unit layer 20 to expose the upper surface of the corresponding passivation layer and the upper surface of the LED units.

[0161] Specifically, the first filling layer 23 is melt-bonded to the substrate 10, so that the first LED unit layer 20 is melt-bonded above the substrate 10, and a gap is formed between the LED units of the first LED unit layer 20 and the substrate 10, thereby simplifying the processing technology and achieving a reliable connection between the first LED unit layer 20 and the substrate 10.

[0162] In this embodiment, the first substrate 26 and a portion of the first LED epitaxial layer 25 are removed, exposing the upper surface of the first passivation layer 24 and the upper surface of the first LED unit 21. By using the first passivation layer 24 as a processing position reference, the processing difficulty is reduced, the device yield is improved, and preparation is made for forming the transparent conductive layer 70. Specifically, the first substrate 26 and a portion of the first LED epitaxial layer 25 can be removed by chemical mechanical polishing (CMP).

[0163] Combine Figure 20 As shown, in some embodiments, a method for preparing a Micro-LED display chip is provided, comprising the following steps:

[0164] S201 , providing a substrate, wherein the substrate includes a plurality of first contacts.

[0165] S202. Prepare an LED unit layer, the LED unit layer including a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units one by one, the LED unit including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer arranged in a stacked manner, the conductive reflective cup being electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cup including an extension extending to the outside of the side surface of the corresponding LED unit.

[0166] S203 , melt-bonding the first LED unit layer onto the substrate, and forming gaps between the LED units of the first LED unit layer and the substrate.

[0167] S204 , removing the substrate and part of the LED epitaxial layer of the first LED unit layer to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

[0168] S205. Form a transparent conductive layer, which covers at least the upper surface of each LED unit of the first LED unit layer and is electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covers the upper surface of at least part of the passivation layer of the first LED unit layer to form an extended area.

[0169] Combine Figure 13As shown, the transparent conductive layer 70 covers at least the upper surface of each first LED unit 21 and is electrically connected to the second doped semiconductor layer of each corresponding first LED unit 21, preparing for the electrical connection between the second doped semiconductor layer of each first LED unit 21 and the common conductive column 80.

[0170] The transparent conductive layer 70 also covers at least a portion of the upper surface of the first passivation layer 24 to form an extended region 71. The extended region 71 can smoothly connect the second doped semiconductor layer of the first LED unit 21 to the common conductive column 80, reducing processing difficulty and improving yield.

[0171] Specifically, a material (e.g., indium tin oxide) can be deposited on the upper surfaces of the first passivation layer 24 and the first LED unit 21 to form a conductive material layer, and the conductive material layer is electrically connected to the second doped semiconductor layer of the corresponding first LED unit 21. The conductive material layer can be processed by a photolithography patterning process to form a transparent conductive layer 70.

[0172] S206 , forming a first planarization layer, where the first planarization layer covers the first LED unit layer and the transparent conductive layer formed on the first LED unit layer.

[0173] Combine Figure 14 and Figure 15 As shown, the first LED unit layer 20 and the transparent conductive layer 70 formed on the first LED unit layer 20 are covered by the first planarization layer 50 to protect the LED units of the first LED unit layer 20 and prepare for fusion bonding with the second LED unit layer 30 .

[0174] In some embodiments, combined Figure 14 and Figure 15 As shown, the steps of forming the first planarization layer 50 include: forming a first transition layer 51, the first transition layer 51 covering the passivation layer of the first LED unit layer 20 and the transparent conductive layer 70 formed on the first LED unit layer 20. Etching the first transition layer 51 and the first LED unit layer 20 to form a plurality of first through holes 27 exposing the plurality of first contacts 11, with some of the first through holes 27 penetrating the extended portions of the conductive reflector cups of the first LED unit layer 20. Forming a plurality of conductive pillars 40 in the plurality of first through holes 27, wherein some of the conductive pillars 40 are respectively electrically connected to the first contacts 11 and the extended portions of the conductive reflector cups of the corresponding first LED unit layer 20. Removing a portion of the first transition layer 51 to form the first planarization layer 50.

[0175] Specifically, combined Figure 14As shown, a material (e.g., silicon dioxide) can be deposited on the upper surface of the first passivation layer 24 and the upper surface of the transparent conductive layer 70 formed on the first LED unit layer 20 to form a first transition layer 51. The first transition layer 51 prepares a material layer for forming the first planarization layer 50.

[0176] Combine Figure 14 As shown, first through holes 27 are formed by etching the first transition layer 51 and the first LED unit layer 20, and the plurality of first through holes 27 are arranged to expose the plurality of first contacts 11 in a one-to-one correspondence. A portion of the plurality of first through holes 27 penetrates the first extension 221 of the first conductive reflector cup 22, facilitating electrical connection between the first extension 221 and the corresponding first contacts 11. Another portion of the plurality of first through holes 27 does not penetrate the first extension 221, facilitating electrical connection between the second extension 321 of the second conductive reflector cup 32 and the corresponding first contacts 11.

[0177] Combine Figure 15 As shown, a plurality of conductive posts 40 are formed in the plurality of first through-holes 27. A portion of these conductive posts 40 are electrically connected to the first contacts 11 and the corresponding first extensions 221. In other words, the conductive posts 40 that pass through the first extensions 221 are electrically connected to the first contacts 11 and the corresponding first extensions 221, thereby electrically connecting the first LED units 21 to the corresponding first contacts 11. Meanwhile, another portion of these conductive posts 40 are electrically connected only to the corresponding first contacts 11, paving the way for the second extensions 321 to be electrically connected to the corresponding first contacts 11.

[0178] A portion of the first transition layer 51 is removed to form the first planarization layer 50. Specifically, a portion of the first transition layer 51 can be removed by chemical mechanical polishing (CMP) to form the first planarization layer 50.

[0179] S207. Melt-bond the second LED unit layer on top of the first planarization layer, wherein vertical projections of the multiple LED units and the multiple first contacts on the substrate do not overlap, and the protruding portion of the conductive reflective cup is electrically connected to the corresponding first contact through a conductive column, so that each LED unit can be driven individually.

[0180] Combine Figure 16As shown, the fusion bonding of the second LED unit layer 30 and the first planarization layer 50 simplifies the manufacturing process, reduces the difficulty, and improves the device yield. By ensuring that the vertical projections of the multiple LED units and the multiple first contacts 11 on the substrate 10 do not overlap, the extension of the conductive reflector cup is electrically connected to the corresponding first contact 11 via the conductive pillar 40, allowing each LED unit to be driven independently. This reduces the alignment accuracy requirements during processing, further reducing the difficulty of the manufacturing process and improving the device yield. This also extends the current path, dissipates thermal and mechanical stresses, and further improves device performance.

[0181] In some embodiments, the step of melt-bonding the second LED unit layer 30 onto the first planarization layer 50 includes melt-bonding the fill layer of the second LED unit layer 30 onto the first planarization layer 50, and forming a gap between the LED units of the second LED unit layer 30 and the first planarization layer 50. The substrate and a portion of the LED epitaxial layer of the second LED unit layer 30 are removed to expose the upper surface of the corresponding passivation layer and the upper surface of the LED units.

[0182] By melt-bonding the second filling layer 33 on top of the first planarization layer 50 and forming a gap between the second LED unit 31 and the first planarization layer 50, the process is simple and a reliable connection between the second LED unit layer 30 and the first planarization layer 50 is achieved.

[0183] The second substrate 36 and a portion of the second LED epitaxial layer 35 are removed to expose the corresponding upper surface of the second passivation layer 34 and the upper surface of the second LED unit 31. By using the second passivation layer 34 as a processing position reference, the processing difficulty is reduced, the device yield is improved, and preparation is made for forming the transparent conductive layer 70. Specifically, the second substrate 36 and a portion of the second LED epitaxial layer 35 can be removed by chemical mechanical polishing (CMP).

[0184] Combine Figure 21 As shown, in some embodiments, a method for preparing a Micro-LED display chip is provided, comprising the following steps:

[0185] S2101. Provide a substrate, wherein the substrate includes a plurality of first contacts.

[0186] S2102. Prepare an LED unit layer, the LED unit layer including a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units one by one, the LED unit including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer arranged in a stacked manner, the conductive reflective cup being electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cup including an extension extending to the outside of the side surface of the corresponding LED unit.

[0187] S2103 , melt-bonding the first LED unit layer onto the substrate, and forming a gap between the LED units of the first LED unit layer and the substrate.

[0188] S2104 , removing the substrate and part of the LED epitaxial layer of the first LED unit layer to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

[0189] S2105. Form a transparent conductive layer, which covers at least the upper surface of each LED unit of the first LED unit layer and is electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covers the upper surface of at least part of the passivation layer of the first LED unit layer to form an extended area.

[0190] S2106 , forming a first planarization layer, where the first planarization layer covers the first LED unit layer and the transparent conductive layer formed on the first LED unit layer.

[0191] S2107 , melt-bonding the second LED unit layer onto the first planarization layer.

[0192] The vertical projections of the plurality of LED units and the plurality of first contacts on the substrate do not overlap, and the protruding portion of the conductive reflective cup is electrically connected to the corresponding first contact through a conductive column, so that each LED unit can be driven individually.

[0193] S2108. Form a transparent conductive layer, which covers at least the upper surface of each LED unit of the second LED unit layer and is electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covers the upper surface of at least part of the passivation layer of the second LED unit layer to form an extended area.

[0194] Combine Figure 17 As shown, the transparent conductive layer 70 covers at least the upper surface of each second LED unit 31 and is electrically connected to the second doped semiconductor layer of the corresponding second LED unit 31, preparing for the electrical connection between the second doped semiconductor layer of each second LED unit 31 and the common conductive column 80.

[0195] The transparent conductive layer 70 also covers at least a portion of the upper surface of the second passivation layer 34 to form an extended region 71. The extended region 71 can smoothly connect the second doped semiconductor layer of the second LED unit 31 to the common conductive column 80, reducing processing difficulty and improving yield.

[0196] Specifically, a material (e.g., indium tin oxide) can be deposited on the upper surfaces of the second passivation layer 34 and the second LED unit 31 to form a conductive material layer, and the conductive material layer is electrically connected to the second doped semiconductor layer of the corresponding second LED unit 31. The conductive material layer can be processed by a photolithography patterning process to form a transparent conductive layer 70.

[0197] S2109 , forming a second transition layer, where the second transition layer covers the passivation layer of the second LED unit layer and the transparent conductive layer formed on the second LED unit layer.

[0198] Combine Figure 17 As shown, a material (e.g., silicon dioxide) can be deposited on the upper surface of the second passivation layer 34 and the upper surface of the transparent conductive layer 70 formed on the second LED unit layer 30 to form a second transition layer 61. The second transition layer 61 prepares a material layer for forming the second planarization layer 60.

[0199] S2110 , removing a portion of the second transition layer to form a second planarization layer.

[0200] Combine Figure 1 and Figure 17 As shown, a portion of the second transition layer 61 is removed to form a second planarization layer 60, which protects the second LED unit 31 and prepares for the fusion bonding of the third LED unit layer. The second planarization layer 60 can be formed by removing a portion of the second transition layer 61 through chemical mechanical polishing (CMP).

[0201] Combine Figure 22 As shown, in some embodiments, a method for preparing a Micro-LED display chip is provided, comprising the following steps:

[0202] S2201. Provide a substrate, wherein the substrate includes a plurality of first contacts.

[0203] S2202. Prepare an LED unit layer, the LED unit layer including a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units one by one, the LED unit including a first doped semiconductor layer, an active layer, and a second doped semiconductor layer arranged in a stacked manner, the conductive reflective cup being electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cup including an extension extending to the outside of the side surface of the corresponding LED unit.

[0204] S2203 , melt-bonding the first LED unit layer onto the substrate, and forming a gap between the first LED unit 21 and the substrate 10 .

[0205] S2204 , removing the substrate and part of the LED epitaxial layer of the first LED unit layer to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

[0206] S2205. Form a transparent conductive layer, which covers at least the upper surface of each LED unit of the first LED unit layer and is electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covers the upper surface of at least part of the passivation layer of the first LED unit layer to form an extended area.

[0207] S2206 , forming a first planarization layer, where the first planarization layer covers the first LED unit layer and the transparent conductive layer formed on the first LED unit layer.

[0208] S2207 , melt-bonding the second LED unit layer onto the first planarization layer.

[0209] S2208. Form a transparent conductive layer, which covers at least the upper surface of each LED unit of the second LED unit layer and is electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covers the upper surface of at least part of the passivation layer of the second LED unit layer to form an extended area.

[0210] S2209 , forming a second transition layer, where the second transition layer covers the passivation layer of the second LED unit layer and the transparent conductive layer formed on the second LED unit layer.

[0211] S2210, etching the second transition layer and the second LED unit layer to form a second through hole, the second through hole passing through the protruding portion of the conductive reflective cup of the second LED unit layer and exposing part of the conductive column formed in the first through hole; etching the second transition layer and the second LED unit layer to form the second through hole and forming a third through hole at the same time, the third through hole passing through the extended area of the transparent conductive layer formed in the first LED unit layer and the extended area of the transparent conductive layer formed in the second LED unit layer.

[0212] Combine Figure 17 As shown, a second through hole 37 and a third through hole 38 are formed by etching the second transition layer 61 and the second LED unit layer 30. The second through hole 37 penetrates the second extension 321 and exposes a portion of the conductive pillar 40 formed in the first through hole 27, preparing for electrical connection between the second extension 321 and the conductive pillar 40 formed in the first through hole 27. The third through hole 38 penetrates the extended region 71 of the transparent conductive layer 70 located above the first LED unit 21 and the extended region 71 of the transparent conductive layer 70 located above the second LED unit 31, preparing for electrical connection between the transparent conductive layer 70 located above the first LED unit 21 and the transparent conductive layer 70 located above the second LED unit 31.

[0213] S2211. Fill the second through hole and form a conductive column in the second through hole. The conductive column formed in the second through hole is electrically connected to the corresponding conductive column formed in the first through hole, so as to electrically connect the extended portion of the conductive reflective cup of the second LED unit layer and the corresponding first contact; form a common conductive column in the third through hole, wherein the common conductive column is electrically connected to the extended area of the transparent conductive layer formed in the first LED unit layer and the extended area of the transparent conductive layer formed in the second LED unit layer, respectively.

[0214] Combine Figure 1 As shown, a conductive column 40 is formed in the second through hole 37, and the conductive column 40 is electrically connected to the corresponding conductive column 40 formed in the first through hole 27, so that the second extension portion 321 and the corresponding first contact 11 are electrically connected, thereby realizing the electrical connection between the first doped semiconductor layer of the second LED unit 31 and the corresponding first contact 11.

[0215] Combine Figure 1 As shown, a common conductive column 80 is formed in the third through hole 38, and the common conductive column 80 is electrically connected to the transparent conductive layer 70 located above the first LED unit 21 and the transparent conductive layer 70 located above the second LED unit 31, respectively, so that the second doped semiconductor layer of the first LED unit 21 and the second doped semiconductor layer of the second LED unit 31 are electrically connected to the common conductive column 80, which helps to electrically connect the second doped semiconductor layer of the first LED unit 21 and the second doped semiconductor layer of the second LED unit 31 to the second contact, so that the first LED unit 21 and the second LED unit 31 can be driven separately.

[0216] S2212, combined Figure 1 and Figure 17 As shown, part of the second transition layer is removed to form a second planarization layer.

[0217] In this embodiment, vertical projections of the plurality of LED units and the plurality of first contacts 11 on the substrate 10 do not overlap, and the protruding portion of the conductive reflector cup is electrically connected to the corresponding first contact 11 through the conductive column 40, so that each LED unit can be driven individually.

[0218] It should be noted that the steps involved in the preparation method of the embodiment of the present disclosure do not limit the order in which the actual operations are performed. For example, some steps can be performed substantially in parallel. For another example, some steps described later can be performed in advance.

[0219] The present disclosure also provides a display device. The display device includes a Micro-LED display chip 1 as described in any of the previous embodiments. Therefore, the display device has the beneficial effects of the Micro-LED display chip 1 as described in any of the previous embodiments, which will not be further described here.

[0220] It should be noted that the Micro-LED display chip 1 or display device can be applied to augmented reality (AR) display devices, virtual reality (VR) display devices, near-eye display (NED) devices, head-up display (HUD) devices and other devices.

[0221] The above are merely preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, and improvements made within the spirit and principles of the present application shall be included within the scope of protection of the present application. The above are merely preferred embodiments of the present application. It should be noted that those skilled in the art may make various improvements and variations without departing from the technical principles of the present application, and such improvements and variations shall also be considered within the scope of protection of the present application.

Claims

1. A Micro-LED display chip, characterized in that: include: a substrate comprising a plurality of first contacts; At least two LED unit layers are stacked above the substrate, each of the LED unit layers includes a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units one-to-one, the vertical projections of the plurality of LED units and the plurality of first contacts on the substrate do not overlap, the LED units include a first doped semiconductor layer, an active layer, and a second doped semiconductor layer arranged in a stacked manner, the conductive reflective cups are electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cups include protrusions extending to the outside of the side surfaces of the corresponding LED unit; a conductive column, configured to electrically connect the protruding portion and the corresponding first contact point, so that each of the LED units can be driven individually; The at least two LED unit layers include a first LED unit layer and a second LED unit layer, wherein the first LED unit layer includes a plurality of first LED units arranged at intervals and a first filling layer located between adjacent first LED units, wherein the first filling layer is melt-bonded to the top of the substrate and forms a gap between the first LED units and the substrate; the second LED unit layer is disposed above the first LED unit layer and includes a plurality of second LED units arranged at intervals; The display chip further includes a first planarization layer formed above the first LED unit layer, the first planarization layer being used to protect the first LED unit and prepare for a fusion bonding process of the second LED unit layer; The second LED unit layer further includes a second filling layer located between adjacent second LED units. The second filling layer is melt-bonded on top of the first planarization layer and forms a gap between the second LED units and the first planarization layer.

2. The display chip according to claim 1, wherein: Also includes: a second planarization layer formed above the second LED unit layer; A third LED unit layer, comprising a plurality of third LED units arranged at intervals and a third filling layer located between adjacent third LED units, wherein the third filling layer is melt-bonded to the second planarization layer to form intervals between the third LED units and the second planarization layer; At least one of the first LED units, at least one of the adjacent second LED units, and at least one of the adjacent third LED units form a full-color pixel point.

3. The display chip according to claim 1, wherein: Vertical projections of the plurality of LED units located in different LED unit layers on the substrate do not overlap.

4. The display chip according to claim 1, wherein: The conductive reflective cup is disposed around the side and / or bottom of the corresponding LED unit.

5. The display chip according to claim 1, wherein: Also includes: a transparent conductive layer disposed on the upper surface of each LED unit and electrically connected to the second doped semiconductor layer of the LED unit, wherein the transparent conductive layer includes an extended region located on the upper side of the LED unit; A common conductive column is electrically connected to a plurality of adjacent extended regions, and the plurality of extended regions are located in different LED unit layers, so that the common conductive column is electrically connected to the second doped semiconductor layers of the plurality of adjacent LED units.

6. The display chip according to claim 1, wherein: Each LED unit layer further comprises: A passivation layer is provided between the LED unit and the corresponding conductive reflector cup. The passivation layer at least covers the side surface of the LED unit and extends to the outside of the LED unit, so that the upper surface of the passivation layer is flush with the upper surface of the LED unit.

7. A method for preparing a Micro-LED display chip, characterized in that: The steps include: providing a substrate comprising a plurality of first contacts; Prepare an LED unit layer, the LED unit layer comprising a plurality of LED units arranged at intervals and a plurality of conductive reflective cups corresponding to the plurality of LED units, the LED units comprising a first doped semiconductor layer, an active layer, and a second doped semiconductor layer stacked in layers, the conductive reflective cups being electrically connected to the first doped semiconductor layer of the corresponding LED unit, and the conductive reflective cups comprising protruding portions extending to the outside of the side surfaces of the corresponding LED units; At least two layers of the LED units are stacked on the substrate, wherein vertical projections of the plurality of LED units and the plurality of first contacts on the substrate do not overlap, and the protruding portion of the conductive reflector cup is electrically connected to the corresponding first contact via a conductive column, so that each of the LED units can be driven independently; The at least two LED unit layers include a first LED unit layer and a second LED unit layer, wherein the first LED unit layer includes a plurality of first LED units arranged at intervals and a first filling layer located between adjacent first LED units, wherein the first filling layer is melt-bonded to the top of the substrate and forms a gap between the first LED units and the substrate; the second LED unit layer is disposed above the first LED unit layer and includes a plurality of second LED units arranged at intervals; The display chip further includes a first planarization layer formed above the first LED unit layer, the first planarization layer being used to protect the first LED unit and prepare for the fusion bonding process of the second LED unit layer; The second LED unit layer further includes a second filling layer located between adjacent second LED units. The second filling layer is melt-bonded on top of the first planarization layer and forms a gap between the second LED units and the first planarization layer.

8. The preparation method according to claim 7, characterized in that The steps of preparing the LED unit layer include: Providing a substrate, wherein one side of the substrate is provided with an LED epitaxial layer; Etching a side of the LED epitaxial layer away from the substrate to form a plurality of LED units; forming a passivation layer, wherein the passivation layer at least covers the side surfaces of the LED units and the LED epitaxial layers between adjacent LED units; forming a plurality of the conductive reflective cups, wherein the plurality of the conductive reflective cups correspond one-to-one to the plurality of the LED units and are electrically connected to the first doped semiconductor layers of the plurality of the LED units; A filling layer is formed, where the filling layer covers the passivation layer and the plurality of conductive reflective cups.

9. The preparation method according to claim 8, characterized in that The at least two LED unit layers include a first LED unit layer and a second LED unit layer, and the step of stacking the at least two LED unit layers on the substrate includes: Melting and bonding the first LED unit layer onto the substrate, and forming a gap between the LED units of the first LED unit layer and the substrate; The substrate and part of the LED epitaxial layer of the first LED unit layer are removed to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

10. The preparation method according to claim 9, characterized in that The step of stacking at least two layers of the LED units on the substrate further includes: forming a transparent conductive layer, the transparent conductive layer covering at least the upper surface of each LED unit of the first LED unit layer and electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covering at least a portion of the upper surface of the passivation layer of the first LED unit layer to form an extended region; forming a first planarization layer, wherein the first planarization layer covers the first LED unit layer and the transparent conductive layer formed on the first LED unit layer; The second LED unit layer is melt-bonded on top of the first planarization layer.

11. The preparation method according to claim 10, characterized in that: The step of forming a first planarization layer includes: forming a first transition layer, wherein the first transition layer covers the passivation layer of the first LED unit layer and the transparent conductive layer formed on the first LED unit layer; Etching the first transition layer and the first LED unit layer to form a plurality of first through holes exposing a plurality of the first contacts, wherein some of the first through holes penetrate the protruding portion of the conductive reflective cup of the first LED unit layer; forming a plurality of conductive pillars in the plurality of the first through holes, wherein some of the conductive pillars are electrically connected to the first contacts and the protruding portions of the conductive reflective cups of the corresponding first LED unit layers respectively; A portion of the first transition layer is removed to form a first planarization layer.

12. The preparation method according to claim 11, characterized in that The step of melt-bonding the second LED unit layer onto the first planarization layer comprises: Melting and bonding the filling layer of the second LED unit layer onto the first planarization layer, and forming a gap between the LED units of the second LED unit layer and the first planarization layer; The substrate and part of the LED epitaxial layer of the second LED unit layer are removed to expose the upper surface of the corresponding passivation layer and the upper surface of the LED unit.

13. The preparation method according to claim 12, characterized in that After the step of melt-bonding the second LED unit layer on top of the first planarization layer, the preparation method further includes: forming a transparent conductive layer, the transparent conductive layer covering at least the upper surface of each LED unit of the second LED unit layer and being electrically connected to the second doped semiconductor layer of each corresponding LED unit; the transparent conductive layer also covering at least a portion of the upper surface of the passivation layer of the second LED unit layer to form an extended region; forming a second transition layer, wherein the second transition layer covers the passivation layer of the second LED unit layer and the transparent conductive layer formed on the second LED unit layer; A portion of the second transition layer is removed to form a second planarization layer.

14. The preparation method according to claim 13, characterized in that Before the step of removing a portion of the second transition layer, the preparation method further comprises: Etching the second transition layer and the second LED unit layer to form a second through hole, wherein the second through hole passes through the extended portion of the conductive reflector cup of the second LED unit layer and exposes a portion of the conductive column formed in the first through hole; The second through hole is filled and a conductive column is formed in the second through hole. The conductive column formed in the second through hole is electrically connected to the corresponding conductive column formed in the first through hole, so as to electrically connect the extended portion of the conductive reflector cup of the second LED unit layer and the corresponding first contact.

15. The preparation method according to claim 14, characterized in that Etching the second transition layer and the second LED unit layer to form a second through hole and simultaneously forming a third through hole, the third through hole penetrating an extended region of the transparent conductive layer formed on the first LED unit layer and an extended region of the transparent conductive layer formed on the second LED unit layer; A common conductive column is formed in the third through hole, wherein the common conductive column is electrically connected to the extended region of the transparent conductive layer formed on the first LED unit layer and the extended region of the transparent conductive layer formed on the second LED unit layer, respectively.

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