PUCCH channel resource optimization method in 5G communication based on FPGA

Abstract

The application relates to the technical field of communication, and discloses a PUCCH channel resource optimization method in 5G communication based on FPGA, which comprises the following steps: S1, performing multi-scale spectrum analysis on a physical uplink control channel signal, decomposing the signal by using wavelet transform, and extracting sparse frequency components in the signal; and S2, converting the frequency domain signal into a sparse matrix representation; and a PUCCH channel resource optimization system in 5G communication based on FPGA is also provided, which comprises a signal analysis module used for performing multi-scale spectrum analysis on a PUCCH signal and extracting sparse frequency components of the signal. Through FPGA-based hardware acceleration, deep reinforcement learning optimization of resource scheduling, and sparse matrix optimization calculation, the application realizes efficient computing performance, flexible resource scheduling, and low-power operation, and significantly improves the throughput and resource utilization efficiency of the system.

Description

Technical Field

[0001] This invention relates to the field of communication technology, specifically to a method for optimizing PUCCH channel resources in 5G communication based on FPGA. Background Technology

[0002] In modern society, with the rapid growth of Internet of Things (IoT) devices, smartphones, and various communication devices, 5G communication networks are becoming the infrastructure supporting various applications. In 5G networks, the Physical Uplink Control Channel (PUCCH) plays a crucial role in ensuring efficient, low-latency communication. Especially in high-density communication environments, the PUCCH needs to handle requests from a large number of concurrent users simultaneously, ensuring that each user can stably upload control information.

[0003] In existing technologies, PUCCH channel processing typically relies on general-purpose processors such as CPUs or DSPs. These processors offer high flexibility and are capable of performing various complex computational tasks, including modulation and Discrete Fourier Transform (DFT). However, while traditional processors demonstrate good adaptability to various tasks, their computational power and resource allocation efficiency are often limited when faced with large-scale user access and high concurrency. To address this issue, existing technologies have introduced optimization methods, such as hardware acceleration and dynamic scheduling algorithms, to improve the utilization of PUCCH channel resources. These technologies have improved the system's computational efficiency and resource management to some extent.

[0004] However, existing technologies still have some shortcomings. Traditional calculation methods usually rely on serial calculation, which makes it difficult to process large-scale data and meet real-time response requirements. Existing resource scheduling schemes are mostly static scheduling, which cannot adapt to changes in network load in real time, resulting in uneven resource allocation, which in turn reduces the efficiency of channel resource utilization and the overall performance of the system. In addition, existing DFT calculation methods fail to make full use of the sparsity of PUCCH signals, resulting in high computational complexity, high power consumption, and serious waste of hardware resources. Summary of the Invention

[0005] To address the shortcomings of existing technologies, this invention provides a PUCCH channel resource optimization method based on FPGA in 5G communication, which solves the problems of low computational efficiency, inflexible resource scheduling, and waste of hardware resources in existing technologies.

[0006] To achieve the above objectives, the present invention provides the following technical solution: a PUCCH channel resource optimization method for 5G communication based on FPGA, comprising the following steps:

[0007] S1. Perform multi-scale spectral analysis on the Physical Uplink Control Channel (PUCCH) signal, decompose the signal using wavelet transform, and extract the sparse frequency components in the signal.

[0008] S2. Convert the frequency domain signal into a sparse matrix representation, identify the non-zero frequency components in the signal, and reduce redundant calculations based on the sparse matrix optimization algorithm;

[0009] S3. Based on the signal optimized by the sparse matrix, the Discrete Fourier Transform (DFT) is used for calculation, skipping low-amplitude frequency points and only performing DFT calculation on important frequency components.

[0010] S4. Parallel processing of the sparse DFT optimization calculation is performed using an FPGA platform;

[0011] S5. Optimize the scheduling of PUCCH channel resources using deep reinforcement learning algorithms based on real-time load, adjust the FPGA operating frequency, and manage power consumption.

[0012] S6. Channel resources are scheduled through time division multiplexing and frequency division multiplexing techniques to achieve efficient sharing of the PUCCH channel by multiple users.

[0013] Preferably, the multi-scale spectral analysis step includes:

[0014] The PUCCH signal is decomposed into frequency components of different scales using wavelet transform;

[0015] By using wavelet transform coefficients to filter frequency components, sparse regions in the signal can be identified, and frequency components with small amplitudes can be ignored.

[0016] The signal spectrum is reconstructed based on sparse regions, redundant frequencies are removed, and the frequency domain characteristics of the signal are optimized.

[0017] Preferably, the sparse matrix optimization step includes:

[0018] Based on the spectral characteristics of the PUCCH signal, it is converted into a sparse matrix form;

[0019] The zero-norm optimization method is applied to select non-zero elements in the sparse matrix;

[0020] By using sparse matrix optimization algorithms, frequency components are optimized, reducing computational load and hardware resource consumption.

[0021] Preferably, the discrete Fourier transform calculation steps include:

[0022] Based on the frequency components optimized by the sparse matrix, perform discrete Fourier transform calculations;

[0023] Based on the amplitude of the frequency components, skip the frequency points with smaller amplitudes and only perform DFT calculations on the important frequency components;

[0024] Parallel processing is implemented on the FPGA platform, with multiple hardware units simultaneously calculating the DFT.

[0025] Preferably, the deep reinforcement learning algorithm optimization steps include:

[0026] Real-time monitoring of system load and signal characteristics is achieved through a deep neural network model.

[0027] Based on real-time load prediction results, the deep reinforcement learning model dynamically adjusts the allocation of computing resources and the FPGA operating frequency.

[0028] Adjust the power management strategy based on the scheduling results, optimize the system's power control, and ensure reduced power consumption under low load and increased computing power under high load.

[0029] Preferably, the time-division multiplexing and frequency-division multiplexing scheduling steps include:

[0030] Time-division multiplexing technology is used to allocate the resources of the PUCCH channel to different time periods;

[0031] Frequency division multiplexing (FDM) technology is used to allocate the resources of the PUCCH channel to different frequency bandwidths;

[0032] By using a deep reinforcement learning scheduling algorithm, time slots and frequency bands are dynamically adjusted according to user needs to ensure efficient utilization of resources under multi-user concurrency.

[0033] Preferably, the sparse matrix optimization algorithm is performed through the following steps:

[0034] Calculate the sparsity characteristics in the spectrum and select important frequency components;

[0035] By compressing the frequency components and reducing redundant parts, a sparse matrix representation is obtained.

[0036] By applying sparse optimization techniques, redundant computations are minimized through zero-norm optimization or gradient descent methods, thereby reducing hardware resource consumption.

[0037] Preferably, the FPGA parallel processing steps include:

[0038] Based on the spectral analysis results of the PUCCH signal, the DFT calculation is distributed to multiple FPGA hardware units for parallel processing.

[0039] Each hardware unit performs DFT calculations in parallel, leveraging the parallel computing capabilities of the FPGA to improve signal processing speed.

[0040] During the calculation process, the operating frequency of the hardware unit is dynamically adjusted to adapt to different computing loads.

[0041] Preferably, the power consumption management is performed through the following steps:

[0042] Power consumption demand is predicted based on real-time load using a deep reinforcement learning model.

[0043] The FPGA's operating frequency and voltage are dynamically adjusted according to power consumption requirements to reduce power consumption.

[0044] Under low load conditions, the system automatically enters a low-power mode, reducing the FPGA's operating frequency and minimizing unnecessary energy consumption.

[0045] This invention also provides a PUCCH channel resource optimization system for 5G communication based on FPGA, comprising:

[0046] The signal analysis module is used to perform multi-scale spectral analysis on PUCCH signals and extract sparse frequency components of the signals.

[0047] The sparse matrix optimization module is used to represent the frequency domain of a signal as a sparse matrix and optimize its frequency components.

[0048] The DFT calculation module is used to perform discrete Fourier transform calculations based on the optimized sparse matrix.

[0049] The FPGA processing unit is used to process DFT calculations in parallel and dynamically adjust computing resources.

[0050] A deep reinforcement learning module is used to optimize resource scheduling and power management;

[0051] The time-space multiplexing module is used to schedule PUCCH channel resources according to the needs of multiple users and to realize time-division multiplexing and frequency-division multiplexing.

[0052] This invention provides a method for optimizing PUCCH channel resources in 5G communication based on FPGA. It has the following beneficial effects:

[0053] 1. This invention improves the processing efficiency of the PUCCH channel by introducing FPGA hardware acceleration. Compared with traditional CPU or DSP processing solutions, FPGA can process more computational tasks in parallel, reducing latency. Through this hardware acceleration, the system can more efficiently support large-scale device access and high-concurrency communication scenarios, thereby improving throughput and response speed.

[0054] 2. This invention employs a deep reinforcement learning algorithm to dynamically optimize PUCCH channel resource scheduling. Unlike the static resource allocation strategies in existing technologies, deep reinforcement learning can intelligently adjust resource configuration based on real-time network load and signal changes. In this way, the system can avoid resource waste and ensure optimal power consumption, adapting to changing network environments.

[0055] 3. This invention combines time-division multiplexing and frequency-division multiplexing technologies to optimize resource allocation in both time and frequency dimensions. Unlike traditional single-resource allocation schemes, this innovative resource scheduling method can flexibly select the most suitable strategy based on user needs and network load, improving spectrum utilization efficiency, reducing interference, and ensuring efficient communication in multi-user environments. Attached Figure Description

[0056] Figure 1 This is a flowchart of the method of the present invention;

[0057] Figure 2 This is a system structure diagram of the present invention. Detailed Implementation

[0058] The technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] Please see the appendix Figure 1 This invention provides a method for optimizing PUCCH channel resources in 5G communication based on FPGA, comprising the following steps:

[0060] S1. Perform multi-scale spectrum analysis on the physical uplink control channel signal, and use wavelet transform to decompose the signal and extract the sparse frequency components in the signal.

[0061] S1 effectively extracts valuable frequency components from the original PUCCH signal while removing unimportant ones, providing simplified and accurate input for subsequent sparse matrix optimization and DFT calculations. Multi-scale signal analysis not only accurately captures frequency domain characteristics but also provides a theoretical basis for subsequent computational acceleration and optimization.

[0062] In step S1, the original PUCCH signal is first transmitted to the signal analysis module. The primary task of this module is to convert the time-domain signal into a frequency-domain signal. To efficiently accomplish this conversion, we use wavelet transform as the main signal analysis tool. Wavelet transform has excellent time-frequency localization characteristics, effectively capturing both high-frequency and low-frequency components in the signal, thus meeting the needs of multi-scale signal analysis.

[0063] Wavelet transform analyzes the local features of a signal by projecting it onto a set of basis functions. In this invention, wavelet transform is used to perform multi-scale analysis on the PUCCH signal. The main purpose of wavelet transform is to decompose the signal into components of different frequencies in order to effectively identify the sparse parts of the signal.

[0064] The basic formula for wavelet transform is as follows:

[0065] ;

[0066] in: These are wavelet transform coefficients, representing the scale... and location Below, the signal at time wavelet coefficients; It is the mother wavelet function. Commonly used mother wavelets include Daubechies wavelet, Haar wavelet, etc. It is the scaling factor that determines the degree of scaling of the wavelet; a smaller scaling factor results in a smaller scaling factor. Corresponding to higher frequency components, larger Corresponding to lower frequency components; It is the translation factor, representing the translation position of the wavelet; It is a time variable, representing the moment of the signal.

[0067] The core of wavelet transform is the scaling factor. and position factor By changing these two parameters, we can analyze the signal at different time and frequency scales.

[0068] In multi-scale analysis, the result of a signal undergoing a series of scaling transformations includes both high-frequency and low-frequency components. Signal components at different scales possess different frequency characteristics, reflecting the signal's local properties. For example, smaller scales correspond to higher-frequency components, reflecting the rapidly changing parts of the signal; larger scales correspond to lower-frequency components, reflecting the smoother parts of the signal.

[0069] After wavelet transform, many frequency components in the resulting transform coefficients have very small amplitudes, and these low-amplitude components do not significantly affect signal transmission. Therefore, the system identifies these sparse regions and selectively removes low-amplitude frequency components, thereby improving signal sparsity and reducing redundancy in subsequent calculations.

[0070] By analyzing the coefficients after wavelet transform, the system can represent the signal in the frequency domain as a sparse matrix. This contains a large number of zero values ​​and a small number of non-zero elements. To optimize computation and reduce the consumption of computing resources, the system applies a sparse matrix optimization algorithm to extract these non-zero elements, thereby optimizing the computation path and reducing redundant computation.

[0071] Sparse matrix optimization formula: ;

[0072] in: It is the optimized sparse matrix, representing the spectral result of the signal after wavelet transform and sparse optimization, containing frequency components that are crucial for PUCCH signal transmission; It is the spectral representation of the original signal, containing all frequency components of the signal. This matrix contains all frequency information, including redundant low-amplitude components; It is a matrix The zero norm of a matrix represents the number of non-zero elements in the matrix. This means finding the solution that minimizes the objective function. .

[0073] The optimization objective is to find a sparse matrix by minimizing the zero norm, such that most elements are zero, retaining only the frequency components important for signal transmission. Through sparse matrix optimization, the signal spectrum is simplified, retaining only the frequency components crucial for communication, significantly reducing unnecessary computational and hardware resource consumption.

[0074] In this embodiment, the Daubechies wavelet of wavelet transform was chosen as the mother wavelet because it has good frequency localization characteristics and can effectively analyze signal changes at different scales. In practice, the choice of mother wavelet can be adjusted according to the actual characteristics of the PUCCH signal to achieve the best signal analysis results.

[0075] Furthermore, in the process of removing redundant frequency components, this invention also incorporates a sparse matrix optimization algorithm, further improving the sparsity of the signal frequency domain representation through zero-norm optimization and gradient descent methods. This approach significantly reduces subsequent computational complexity, minimizes hardware resource consumption, and avoids the loss of effective signal information.

[0076] By employing a multi-scale spectral analysis process, this invention effectively extracts key frequency components from PUCCH signals and removes redundant parts. This not only optimizes the subsequent DFT calculation path but also significantly reduces computational complexity. For the system, this process achieves signal compression, reduces hardware resource consumption, and improves the speed and efficiency of signal processing.

[0077] S2. Convert the frequency domain signal into a sparse matrix representation, identify the non-zero frequency components in the signal, and reduce redundant calculations based on the sparse matrix optimization algorithm;

[0078] S2 further optimizes the frequency domain representation of the signal, transforming it into a sparse matrix form. A sparse matrix optimization algorithm is then used to reduce redundant computations, improving the computational efficiency of subsequent steps. By optimizing the sparse matrix, the system can effectively retain important frequency components of the signal while removing frequency components that have little impact on signal transmission, thereby improving computational efficiency and hardware resource utilization.

[0079] In step S2, our goal is to reduce the computational burden by optimizing the sparse matrix. We transform the frequency domain representation of the signal into a sparse matrix containing mostly zero or near-zero elements. The non-zero elements of this matrix represent the frequency components in the signal that have a significant impact. By optimizing the sparse matrix, we can reduce redundant frequency components, thereby reducing the complexity of subsequent calculations.

[0080] This sparsity optimization allows us to selectively process frequency components, retaining only those crucial for signal transmission. Traditional signal processing methods typically fail to remove redundant frequencies, wasting computational resources and potentially impacting transmission efficiency. Through sparse matrix optimization, we can significantly reduce computational load and hardware resource requirements while maintaining signal transmission quality.

[0081] This invention employs a zero-norm optimization method to achieve sparse matrix optimization. Its core idea is to reduce the complexity of signal processing by minimizing the number of non-zero elements in the sparse matrix, using the "sparse matrix optimization formula" disclosed in S1.

[0082] In this embodiment, sparse matrix optimization first obtains the frequency domain signal through wavelet transform, and then removes redundant frequency components using a zero-norm optimization algorithm. The specific steps are as follows:

[0083] Transforming a frequency domain signal into a sparse matrix: First, the frequency domain signal after wavelet transform is converted into a sparse matrix form. At this point, most frequency components of the signal will be represented as zero or close to zero.

[0084] Zero-norm optimization: Zero-norm optimization removes frequency components with small amplitudes from sparse matrices. It identifies and retains frequency components that significantly impact signal transmission by minimizing the number of non-zero elements in the matrix.

[0085] The optimized matrix contains only the frequency components that significantly contribute to signal transmission. This matrix is ​​simpler and requires less computation than the original spectrum matrix.

[0086] Through the above optimizations, redundant components in the signal spectrum are effectively removed, making subsequent DFT calculations more efficient and accurate. Furthermore, since sparse matrices contain a large number of zero elements, compressed storage and fast algorithms can be employed during storage and computation, further improving computational efficiency.

[0087] Choosing a suitable zero-norm optimization algorithm is crucial during implementation. Specifically, optimization algorithms can employ L1 norm optimization, gradient descent, and other methods. L1 norm optimization, by summing the absolute values ​​of the elements in the matrix, minimizes the number of non-zero elements while preserving the important information of the signal. These optimization methods effectively reduce the unimportant parts of the signal and ensure the convergence of the optimization process.

[0088] Furthermore, hardware acceleration is also a crucial factor in achieving sparse matrix optimization. The system utilizes FPGA parallel processing, enabling simultaneous sparse matrix optimization calculations on multiple hardware units, thereby significantly improving computation speed. Within the FPGA, multiple hardware units can simultaneously compute different parts of the matrix, greatly reducing processing time through parallel computation.

[0089] To further improve optimization results, sparse coding and compressed sensing methods can be combined for more efficient optimization. Sparse coding enhances the sparsity of the signal by representing it as a linear combination of a set of basis vectors. Compressed sensing reduces the amount of data required by sampling a sparse representation of the signal instead of the complete signal. These methods can further improve computational and storage efficiency.

[0090] Through sparse matrix optimization, redundant frequency components in the signal are effectively removed, resulting in a more concise spectral matrix. By reducing redundant computations and frequency components, the system can significantly improve computational efficiency and hardware resource utilization while ensuring signal transmission accuracy. This optimization process not only reduces the computational load in subsequent processing steps but also lays the foundation for efficient processing on the FPGA platform. Ultimately, this optimization provides a significant performance improvement for the system in high-concurrency, large-scale device access 5G network environments.

[0091] The zero-norm optimization method effectively removes redundant frequency components, reducing unnecessary computation and storage requirements in the signal processing. Through this step, the system can significantly reduce computational complexity, lower power consumption, and improve overall processing efficiency while maintaining transmission quality.

[0092] S3. Based on the signal optimized by the sparse matrix, the Discrete Fourier Transform is used for calculation, skipping low-amplitude frequency points and only performing DFT calculation on important frequency components.

[0093] The goal of S3 is to further improve computational efficiency based on these optimizations. By optimizing the Discrete Fourier Transform (DFT) calculation, we can skip low-amplitude frequency components, reducing unnecessary computation and hardware resource consumption while ensuring signal transmission quality. This optimization not only reduces computational complexity but also provides a more efficient computational foundation for subsequent signal processing steps.

[0094] The Discrete Fourier Transform (DFT) is used to transform a signal from the time domain to the frequency domain. Its basic principle is to extract frequency domain information by representing the time-domain signal as a linear combination of basis functions (sine waves) of different frequencies. Conventional DFT calculations require calculations at all frequency points, which consumes a lot of computational resources and time, especially when the signal spectrum is sparse, as the amplitudes of many frequency components are very small and can be ignored.

[0095] The traditional DFT formula is as follows:

[0096] ;

[0097] in: The frequency domain result at the i-th frequency point is usually a complex number representing the amplitude and phase of the signal at that frequency; It is the first in the time domain signal The value of each sampling point represents the input signal in the time domain; This indicates the length of the signal, which is the total number of sampling points. It is the imaginary unit; A constant representing the frequency interval, ensuring a uniform distribution of the DFT in the frequency domain; The index representing the frequency point refers to the location of the frequency we are calculating.

[0098] In this invention, due to the strong sparsity of the PUCCH signal, the amplitude of many frequency points in the signal's frequency domain representation is close to zero, or their influence is very small. Therefore, we can skip these frequency points with small amplitudes and only perform DFT calculations on the frequency components with larger amplitudes. This not only reduces the amount of computation but also effectively reduces the consumption of hardware resources.

[0099] In the optimized DFT calculation, we set an amplitude threshold; frequency components with amplitudes smaller than this threshold are skipped from the calculation. The optimized DFT calculation formula is as follows:

[0100] ;

[0101] Where: I is an index set, representing the indexes of frequency points that correspond to frequency component amplitudes greater than a set threshold; It is the first in the time domain signal The values ​​of each sampling point; This represents the total number of sampling points for the signal. This indicates that we are calculating the first... One frequency point; It is the imaginary unit.

[0102] The core idea of ​​the above optimization formula is to skip unimportant frequency components based on an amplitude threshold. Specifically, this is achieved by setting an amplitude threshold. When the amplitude at a certain frequency point When the frequency is below this threshold, we consider that the frequency component has little impact on signal transmission, and therefore skips its calculation. This method significantly improves the efficiency of DFT calculation by reducing the calculation of unimportant frequencies.

[0103] With optimized DFT calculations, the frequency domain transformation of the signal can be simplified, focusing only on the frequency components critical to transmission. This provides a concise and efficient spectral input for subsequent signal processing, avoiding redundant calculations and thus improving the system's computational efficiency and resource utilization.

[0104] In practical implementation, based on the dynamic characteristics of the signal, the system can dynamically adjust the amplitude threshold. The system automatically selects which frequency components to retain based on signal activity. Specifically, when the signal is more active, the system can choose a lower threshold to retain more frequency components; when the signal is more stable, the system can choose a higher threshold to skip more unnecessary calculations.

[0105] FPGA Hardware Acceleration: To further improve the efficiency of DFT calculations, this invention employs an FPGA platform for hardware acceleration. The parallel computing capabilities of the FPGA enable simultaneous DFT calculations at multiple frequency points. Thus, the system can simultaneously calculate DFT results at different frequency points on multiple hardware units, significantly improving computational efficiency.

[0106] In some embodiments, the system may further optimize the calculation accuracy based on the characteristics of the frequency to meet the calculation accuracy requirements of different frequency components. For example, the system may increase the calculation accuracy for important frequency components and decrease the calculation accuracy for low-amplitude frequency components.

[0107] By optimizing DFT calculations, this invention reduces computational load and hardware resource consumption while ensuring signal transmission quality. This optimization significantly improves the system's computational speed and reduces power consumption, making it particularly suitable for high-concurrency, low-latency 5G communication environments. Specifically, this optimization effectively addresses the frequency calculation pressure caused by a large number of connected devices, ensuring stable system operation.

[0108] Overall, by optimizing the DFT calculation, this invention not only improves computational efficiency but also reduces computational complexity while maintaining transmission quality. This optimization provides strong support for subsequent signal processing, resource scheduling, and other steps, effectively enhancing the overall processing capability of PUCCH channel resources in 5G communication.

[0109] By setting an amplitude threshold, calculations are performed only on important frequency components, significantly improving the efficiency of DFT calculations. The parallel computing capabilities of FPGAs further accelerate this process, making the entire signal processing more efficient.

[0110] S4. Parallel processing of sparse DFT optimization calculations is performed using an FPGA platform;

[0111] S4 is used to apply the DFT (Discrete Fourier Transform) calculation to the optimized signal and accelerate these calculations in parallel using the FPGA platform. The main goal of this step is to leverage the parallel computing capabilities of the FPGA to significantly improve the speed of signal processing and further reduce hardware resource consumption.

[0112] An FPGA (Field-Programmable Gate Array) is a hardware platform optimized for specific tasks. Its parallel computing capabilities give it a significant advantage in tasks such as signal processing and data acceleration. In this invention, sparse DFT computation is performed in parallel using an FPGA platform, enabling the simultaneous execution of computation tasks at different frequency points on multiple hardware units, thereby greatly accelerating the entire computation process.

[0113] In this embodiment, we first pass the sparse matrix-optimized signal to the FPGA, and then perform DFT calculations in multiple parallel computing units. Traditional DFT calculations are performed serially, but on the FPGA, we can decompose the entire DFT calculation task into multiple smaller tasks through parallel processing, each processed by a different hardware unit. This parallel processing method can significantly reduce the computation time and improve the speed of signal processing.

[0114] Specifically, each hardware unit is responsible for calculating the DFT result at a specific frequency point and performing a product calculation with the time-domain signal using a composite factor. Through distributed computing, the calculation tasks at all frequency points can be executed simultaneously, thereby accelerating the overall calculation process.

[0115] In parallel computing on the FPGA platform, we decompose the DFT calculation task into multiple smaller tasks and process them using parallel computing methods. The calculation formula performed by each hardware unit can be expressed as:

[0116] ;

[0117] in: Indicates the first The DFT calculation result at each frequency point. It is a complex value containing the amplitude and phase information of that frequency component; It is the first in the time domain signal Each sample point value is used as the input to the DFT; The total number of sampling points for the signal determines the frequency resolution and computational complexity of the DFT. The imaginary unit is used to process complex signals; Represents hardware unit The index set of the time-domain signal sampling points processed represents the specific time-domain signal part that the unit is responsible for calculating; Represents hardware unit The set of indexes of the calculated frequency points defines the frequency calculation task that each hardware unit is responsible for; This is a frequency interval constant used to ensure a uniform distribution of frequency components in the DFT calculation; Indicates the index of the frequency point.

[0118] Each hardware unit performs DFT calculations within its corresponding computational task scope, thereby improving computation speed. Multiple hardware units simultaneously calculate different frequency points, significantly reducing overall computation time.

[0119] On an FPGA platform, signal processing involves more than just simple parallel computation; it also includes dynamic task allocation and hardware resource scheduling. Typically, DFT computation tasks are dynamically allocated to different FPGA hardware units based on the characteristics of the signal.

[0120] During signal processing, the system can dynamically adjust the task allocation of each hardware unit based on the frequency characteristics of the signal and the processing load. Specifically, when the frequency components in the signal are relatively active and have large amplitudes, the system will allocate more computing resources according to the computing load; while when the signal is relatively stable or has small amplitudes, the system can reduce the allocation of resources and skip unimportant frequency points, thereby reducing the amount of computation and hardware resource consumption.

[0121] By performing parallelized sparse DFT calculations on an FPGA platform, this invention significantly improves computational efficiency. Compared to traditional serial computing methods, the parallel computing capabilities of FPGAs enable simultaneous computation tasks at different frequencies across multiple hardware units, drastically reducing computation time and increasing overall system throughput. For complex, large-scale data processing, this parallel computing method can significantly accelerate signal processing, thereby achieving low-latency, high-efficiency data transmission.

[0122] Specifically, FPGA's parallel computing and dynamic resource scheduling mechanisms can intelligently adjust the allocation of computing resources based on the actual load and signal characteristics. When the signal is active, more computing resources can be allocated, while when the signal is relatively stable, unnecessary computations can be reduced, further optimizing power consumption and resource utilization.

[0123] In some embodiments, the system can incorporate dynamic scheduling algorithms to further improve the efficiency of parallel computing. Through algorithm optimization, the system can intelligently select the most suitable hardware resources for task allocation to adapt to signal processing requirements under different loads. Furthermore, combining hardware acceleration algorithms (such as FFT optimization algorithms) can further improve computational efficiency, ensuring the system can operate stably and efficiently in complex communication scenarios with high concurrency and large-scale device access.

[0124] Parallel computing and dynamic resource scheduling mechanisms ensure the efficiency and flexibility of signal processing, especially in environments with large-scale device access and complex communication, providing low latency and high throughput performance. This optimization provides strong support for subsequent signal processing and resource scheduling, driving the performance improvement of 5G communication systems.

[0125] S5. Optimize the scheduling of PUCCH channel resources using deep reinforcement learning algorithms based on real-time load, adjust the FPGA operating frequency, and manage power consumption.

[0126] S5 further improves the overall performance of the system by introducing a deep reinforcement learning (DRL) algorithm to dynamically optimize PUCCH channel resource scheduling and power management.

[0127] The introduction of deep reinforcement learning algorithms allows PUCCH channel resource scheduling to move away from traditional static scheduling strategies. Instead, it uses intelligent learning methods to dynamically optimize resource allocation strategies based on real-time signal changes and network load. Simultaneously, the system dynamically adjusts the FPGA's operating frequency and voltage according to the current load conditions to achieve optimal power consumption management.

[0128] In this embodiment, the goal of the deep reinforcement learning algorithm is to intelligently schedule PUCCH channel resources and optimize FPGA power consumption based on real-time load conditions. By learning optimal resource scheduling and power management strategies under different states, the system ensures efficient operation in various application scenarios.

[0129] System state definition: The state of the system ( The input data is the data for the deep reinforcement learning model. State information includes current system load, signal strength, network throughput, and current power consumption. This information is fed back to the agent in real time, serving as the basis for its decision-making.

[0130] Action selection and reward design: Based on the current state, the agent selects an action ( This refers to the allocation scheme or power consumption adjustment strategy for PUCCH channel resources. Each action selection receives a reward based on the actual feedback from the system. Rewards are typically based on a comprehensive evaluation of factors such as network throughput, signal latency, and power consumption. Higher rewards are given when the system's resource allocation or power management strategies are effective, and lower rewards are given when these strategies are ineffective.

[0131] Q-value update and policy optimization: The Q-value is updated using the Q-learning algorithm and the deep reinforcement learning model. This algorithm optimizes resource scheduling and power management strategies. The Q-value represents the expected total reward after choosing a certain action in a given state. The algorithm continuously learns and updates the Q-value to obtain the optimal strategy.

[0132] The core algorithm of deep reinforcement learning is Q-learning, and its mathematical formula is as follows:

[0133] ;

[0134] in: Indicates the state Next, select an action. The Q value represents the expected reward of choosing this action in this state; The learning rate controls the degree to which newly acquired information affects the existing Q value. A larger learning rate will result in a greater impact of new information on the Q value, while a smaller learning rate will result in a slower update of the Q value. Indicates the state Next, execute the action. The system then receives an immediate reward. The reward calculation takes into account factors such as resource scheduling effectiveness and power consumption control effectiveness. The discount factor represents the degree of importance placed on future rewards. A larger discount factor indicates that the algorithm focuses more on future returns, while a smaller discount factor indicates that the algorithm focuses more on immediate returns. Indicates the next state Next, select all possible actions. The Q value is the value that will bring the greatest return. This value reflects the system's expectation of the optimal future return.

[0135] In this invention, the intelligent decision-making process of the deep reinforcement learning algorithm enables the scheduling of PUCCH channel resources to be dynamically adjusted according to the real-time status. For example, when the signal load is high, the system will increase the throughput by increasing computing resources; while when the load is low, the system will reduce unnecessary resource allocation and reduce power consumption, thereby achieving optimized power consumption management.

[0136] Specifically, the intelligent agent learns a suitable scheduling and power management strategy through interaction with the environment. By continuously adjusting resource allocation and power control, the system can maintain efficient operation, ensuring that user needs are fully met while reducing the system's energy consumption.

[0137] By employing deep reinforcement learning algorithms, this invention can adjust the allocation of PUCCH channel resources in real time based on system load, signal characteristics, and power consumption requirements. Specifically, deep reinforcement learning can intelligently optimize resource allocation schemes in scenarios with large-scale user access and complex communication, thereby improving system throughput, reducing latency, and achieving optimal power consumption management under different load conditions.

[0138] Because deep reinforcement learning algorithms are adaptive, the system can cope with various dynamically changing network states and load requirements, avoiding the static scheduling problem in traditional methods. Specifically, the system can intelligently adjust resource and power consumption configurations based on user access and real-time load to ensure that the system operates in an optimal state.

[0139] In some embodiments, the system may also employ a multi-agent reinforcement learning approach, where multiple agents are responsible for different tasks, such as resource scheduling and power management. Each agent can learn within its own sub-task, thereby improving the overall system efficiency.

[0140] Furthermore, by incorporating adaptive deep learning algorithms, the system can continuously adjust its learning strategy to cope with more complex communication environments and sudden changes in traffic, thereby further improving the system's flexibility and stability.

[0141] Step S5 optimizes PUCCH channel resource scheduling and power management through a deep reinforcement learning algorithm, which can intelligently adjust resource allocation and power configuration according to the real-time status of the system. Through this algorithm, the present invention can ensure that the 5G communication system provides efficient performance in application scenarios with large-scale user access, low latency and high throughput.

[0142] S6. Channel resources are scheduled through time division multiplexing and frequency division multiplexing techniques to achieve efficient sharing of the PUCCH channel by multiple users;

[0143] As network complexity increases, especially with the high-density user access and large-scale device access in 5G, the combination of Time Division Multiplexing (TDM) and Frequency Division Multiplexing (FDM) technologies provides strong support for further optimization of channel resources. In step S6, the scheduling scheme of TDM and FDM technologies ensures efficient and low-latency data transmission.

[0144] Time-division multiplexing (TDM) and frequency-division multiplexing (FDM) technologies divide resources along both time and frequency dimensions, avoiding spectrum waste and resource contention among users. TDM divides time into multiple time slots, with each user using the same frequency band in different time slots; while FDM divides the spectrum into multiple frequency bands, allowing multiple users to transmit data in parallel within the same time frame. Using both in combination ensures efficient utilization of system resources even with diverse user demands and massive data volumes.

[0145] In this embodiment, the system dynamically selects the combination of time-division multiplexing and frequency-division multiplexing based on network load, user demand, and signal quality. Specifically, the system automatically adjusts the resource allocation of the PUCCH channel according to the user's quality of service requirements, the actual network load, and the communication characteristics of each user, ensuring that the network can still maintain efficient operation under heavy load.

[0146] The system combines time-division multiplexing and frequency-division multiplexing scheduling, and mainly performs scheduling through the following methods:

[0147] Time Division Multiplexing (TDM) scheduling: The system allocates time slots to each user based on their communication needs and load. Users transmit data within their allocated time slots, sharing the same spectrum resources but communicating at different times. This method effectively avoids interference between users.

[0148] Frequency Division Multiplexing (FDM) scheduling: The system divides the PUCCH channel into multiple frequency bands, with each user communicating on a different band. Frequency band allocation is dynamically adjusted based on user needs and communication characteristics. FDM can support communication from multiple users simultaneously and improve system throughput.

[0149] By combining these two technologies, the system can flexibly allocate resources dynamically based on the real-time network load and user needs, avoiding excessive waste of resources and improving channel utilization efficiency.

[0150] In time-division multiplexing and frequency-division multiplexing scheduling, the system dynamically calculates the time slot and frequency band resource allocation for each user to ensure efficient use of channel resources. The system uses the following formula for calculation:

[0151] ;

[0152] ;

[0153] in: Indicates allocation to user Time slot resources; Indicates user Data transmission rate; This represents the total bandwidth resources of the system; This represents the total available time resources of the system; Indicates allocation to user Frequency band resources; This indicates the total available frequency band resources of the system.

[0154] The system dynamically adjusts the allocation of time slots and frequency bands by monitoring network load and user demand in real time. Deep reinforcement learning (DRL) algorithms play a crucial role in this process, enabling dynamic optimization of resource allocation strategies based on network status.

[0155] Dynamic timeslot adjustment: The system adjusts the timeslot size for each user in real time based on their bandwidth requirements and network load. Users with high bandwidth needs are allocated larger timeslots, while users with low bandwidth needs are allocated smaller timeslots.

[0156] Dynamic frequency band allocation: For the communication needs of multiple users at the same time, the system will dynamically adjust the frequency band allocation according to the user's needs and signal quality. Users with high-quality signals may be allocated a wider frequency band, while users with poor signals will be allocated a narrower frequency band.

[0157] By combining time-division multiplexing (TDM) and frequency-division multiplexing (FDM), this invention effectively improves the utilization efficiency of PUCCH channel resources. TDM ensures efficient time sharing, while FDM avoids resource conflicts and interference in the frequency dimension. The combined use of both enables efficient data transmission in high-density network environments.

[0158] Specifically, time-division multiplexing reduces interference between users within the same frequency band, while frequency-division multiplexing enables multiple users to transmit data concurrently, further improving system throughput. The system dynamically adjusts resource allocation through deep reinforcement learning algorithms to ensure efficient operation under high load, avoiding resource bottlenecks or overload.

[0159] In some embodiments, the system can incorporate intelligent scheduling algorithms to further optimize the allocation of time-division multiplexing and frequency-division multiplexing resources based on user priority, latency requirements, and network conditions. For example, in cases of low latency requirements, the system may prioritize allocating time slot resources for critical applications (such as real-time communication); while in cases of high bandwidth requirements, it may prioritize allocating frequency band resources.

[0160] Step S6 utilizes time-division multiplexing and frequency-division multiplexing techniques to schedule PUCCH channel resources, achieving efficient sharing and optimized management. Combined with deep reinforcement learning algorithms, the system can dynamically adjust resource allocation strategies based on network load, user demand, and signal quality, ensuring efficient resource utilization under multi-user concurrency conditions.

[0161] The FPGA-based 5G communication PUCCH channel resource optimization system described below can be referred to in conjunction with the FPGA-based 5G communication PUCCH channel resource optimization method described above.

[0162] Please see the appendix Figure 2 The present invention also provides a PUCCH channel resource optimization system for 5G communication based on FPGA, comprising:

[0163] The signal analysis module is used to perform multi-scale spectral analysis on PUCCH signals and extract sparse frequency components of the signals.

[0164] The sparse matrix optimization module is used to represent the frequency domain of a signal as a sparse matrix and optimize its frequency components.

[0165] The DFT calculation module is used to perform discrete Fourier transform calculations based on the optimized sparse matrix.

[0166] The FPGA processing unit is used to process DFT calculations in parallel and dynamically adjust computing resources.

[0167] A deep reinforcement learning module is used to optimize resource scheduling and power management;

[0168] The time-space multiplexing module is used to schedule PUCCH channel resources according to the needs of multiple users and to realize time-division multiplexing and frequency-division multiplexing.

[0169] The system in this embodiment can be used to execute the above method embodiments, and its principle and technical effect are similar, so they will not be described again here.

[0170] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. A method for optimizing PUCCH channel resources in 5G communication based on FPGA, characterized in that, Includes the following steps: S1. Perform multi-scale spectrum analysis on the physical uplink control channel signal, and use wavelet transform to decompose the signal and extract the sparse frequency components in the signal. S2. Convert the frequency domain signal into a sparse matrix representation, identify the non-zero frequency components in the signal, and reduce redundant calculations based on the sparse matrix optimization algorithm; S3. Based on the signal optimized by the sparse matrix, the Discrete Fourier Transform is used for calculation, skipping low-amplitude frequency points and only performing DFT calculation on important frequency components. S4. Parallel processing of sparse DFT optimization calculations is performed using an FPGA platform; S5. Optimize the scheduling of PUCCH channel resources using deep reinforcement learning algorithms based on real-time load, adjust the FPGA operating frequency, and manage power consumption. S6. Channel resources are scheduled through time division multiplexing and frequency division multiplexing techniques to achieve efficient sharing of the PUCCH channel by multiple users; The discrete Fourier transform calculation steps include: Based on the frequency components optimized by the sparse matrix, perform discrete Fourier transform calculations; Based on the amplitude of the frequency components, skip the frequency points with smaller amplitudes and only perform DFT calculations on the important frequency components; Parallel processing is implemented on the FPGA platform, with multiple hardware units simultaneously calculating the DFT. The optimization steps of the deep reinforcement learning algorithm include: Real-time monitoring of system load and signal characteristics is achieved through a deep neural network model. Based on real-time load prediction results, the deep reinforcement learning model dynamically adjusts the allocation of computing resources and the FPGA operating frequency. Adjust the power management strategy based on the scheduling results, optimize the system's power control, and ensure reduced power consumption under low load and increased computing power under high load.

2. The FPGA-based 5G communication PUCCH channel resource optimization method according to claim 1, characterized in that, The multi-scale spectral analysis steps include: The PUCCH signal is decomposed into frequency components of different scales using wavelet transform; By using wavelet transform coefficients to filter frequency components, sparse regions in the signal can be identified, and frequency components with small amplitudes can be ignored. The signal spectrum is reconstructed based on sparse regions, redundant frequencies are removed, and the frequency domain characteristics of the signal are optimized.

3. The FPGA-based 5G communication PUCCH channel resource optimization method according to claim 1, characterized in that, The sparse matrix optimization steps include: Based on the spectral characteristics of the PUCCH signal, it is converted into a sparse matrix form; The zero-norm optimization method is applied to select non-zero elements in the sparse matrix; By using sparse matrix optimization algorithms, frequency components are optimized, reducing computational load and hardware resource consumption.

4. The FPGA-based 5G communication PUCCH channel resource optimization method according to claim 1, characterized in that, The time-division multiplexing and frequency-division multiplexing scheduling steps include: Time-division multiplexing technology is used to allocate the resources of the PUCCH channel to different time periods; Frequency division multiplexing technology is used to allocate the resources of the PUCCH channel to different frequency bandwidths; By using a deep reinforcement learning scheduling algorithm, time slots and frequency bands are dynamically adjusted according to user needs to ensure efficient utilization of resources under multi-user concurrency.

5. The FPGA-based 5G communication PUCCH channel resource optimization method according to claim 3, characterized in that, The sparse matrix optimization algorithm is performed through the following steps: Calculate the sparsity characteristics in the spectrum and select important frequency components; By compressing the frequency components and reducing redundant parts, a sparse matrix representation is obtained. By applying sparse optimization techniques, redundant computations are minimized through zero-norm optimization or gradient descent methods, thereby reducing hardware resource consumption.

6. The FPGA-based 5G communication PUCCH channel resource optimization method according to claim 1, characterized in that, The FPGA parallel processing steps include: Based on the spectral analysis results of the PUCCH signal, the DFT calculation is distributed to multiple FPGA hardware units for parallel processing. Each hardware unit performs DFT calculations in parallel, leveraging the parallel computing capabilities of the FPGA to improve signal processing speed. During the calculation process, the operating frequency of the hardware unit is dynamically adjusted to adapt to different computing loads.

7. The FPGA-based 5G communication PUCCH channel resource optimization method according to claim 1, characterized in that, The power consumption management is performed through the following steps: Power consumption demand is predicted based on real-time load using a deep reinforcement learning model. The FPGA's operating frequency and voltage are dynamically adjusted according to power consumption requirements to reduce power consumption. Under low load conditions, the system automatically enters a low-power mode, reducing the FPGA's operating frequency and minimizing unnecessary energy consumption.

8. A FPGA-based PUCCH channel resource optimization system for 5G communication, characterized in that, The method for optimizing PUCCH channel resources in 5G communication based on FPGA as described in any one of claims 1-7 includes: The signal analysis module is used to perform multi-scale spectral analysis on PUCCH signals and extract sparse frequency components of the signals. The sparse matrix optimization module is used to represent the frequency domain of a signal as a sparse matrix and optimize its frequency components. The DFT calculation module is used to perform discrete Fourier transform calculations based on the optimized sparse matrix. The FPGA processing unit is used to process DFT calculations in parallel and dynamically adjust computing resources. A deep reinforcement learning module is used to optimize resource scheduling and power management; The time-space multiplexing module is used to schedule PUCCH channel resources according to the needs of multiple users and to realize time-division multiplexing and frequency-division multiplexing.

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