Distributed absolute timing system

Abstract

The invention provides a distributed absolute timing system, which comprises a sending end and a plurality of receiving ends, and is characterized in that the sending end is used for modulating a main clock signal according to a main timing signal and sending a modulation signal to the receiving ends in a delayed manner; the time of the main hardware pulse signal generated according to the main clock signal is consistent with the time of the reference hardware pulse signal; the plurality of receiving ends are used for receiving the modulation signals and returning the modulation signals to the sending end; the sending end is also used for receiving the returned modulation signal and demodulating the modulation signal after time delay to obtain a returned timing signal; determining inherent transmission delay according to the returned timing signal and the main hardware pulse signal; and adjusting the time delay of the sending end according to the inherent transmission time delay, so that the time of the master hardware pulse signal generated by the sending end is consistent with the time of the slave timing signal generated by the receiving end. The system replaces a mode of realizing high-precision absolute timing by completely relying on the Ethernet, so that the timing precision is improved, and the system realization difficulty and cost are reduced.

Description

Technical Field

[0001] The present invention relates to the technical field of absolute timing, and particularly to a distributed absolute timing system. Background Art

[0002] In modern measurement and control systems, precise time synchronization is of crucial importance.

[0003] For measuring the time relationship between different signals, the most direct method is to use the same signal measurement device (such as an oscilloscope), because the multiple signal measurement channels of these devices usually work in the same clock domain and the time relationship between signals can be directly read. However, when the signal generation locations are distributed within a range from hundreds of meters to dozens of kilometers and the time relationship between multiple signals needs to be measured simultaneously, a single measurement device obviously cannot meet the requirements. At this time, multiple measurement devices must be used to separately collect signals at different locations, which requires a highly consistent time reference between the measurement devices, that is, a distributed absolute timing system is needed.

[0004] In large-scale distributed control systems, multiple devices physically dispersed also need to cooperate under a determined time relationship. For example, in fields such as high-precision physical experiments, industrial automation control, and large-scale network communication, the accuracy of time synchronization directly affects the performance and reliability of the entire system. Therefore, the role of a distributed absolute timing system is to calibrate the time of different measurement devices or control nodes to be consistent with the reference clock, thereby ensuring clock synchronization between devices and guaranteeing the accuracy of data acquisition and operations.

[0005] Currently, Ethernet, as a widely used technology, has become the main communication means in various large-scale distributed measurement and control systems. Absolute timing technology solutions based on Ethernet have also gradually become popular, and existing commercial solutions include NTP (Network Time Protocol), PTP (Precision Time Protocol), and SyncE (Synchronous Ethernet). These technologies can achieve timing accuracy at the sub-second or sub-microsecond level and are applicable to most application scenarios.

[0006] However, for some fields with extremely high requirements for time synchronization accuracy, such as particle physics research, cosmic ray observation, etc., the accuracy of existing technologies is still insufficient. For this reason, the European Organization for Nuclear Research (CERN) has developed the White Rabbit technology, which is based on Ethernet and uses single-fiber bidirectional transmission of Ethernet data packets, combined with the clock data recovery (CDR: Clock and Data Recovery) function of the Ethernet PHY chip, to achieve sub-nanosecond-level timing accuracy.

[0007] Although White Rabbit technology has achieved significant breakthroughs in timing accuracy, it is complex and costly. In the system, except for the time server which can use commercial products, other hardware and software need to be specially designed, which limits its wide application to a certain extent.

[0008] Therefore, how to solve the problems of low timing accuracy, difficulty in system implementation and high cost in existing absolute timing systems is an important issue that needs to be urgently addressed in the field of absolute timing. Summary of the invention

[0009] The present invention provides a distributed absolute timing system to overcome the defects of the existing absolute timing system, such as low timing accuracy, great difficulty in system implementation and high cost, effectively improve the timing accuracy, and make the system implementation simpler and more cost-effective.

[0010] On the one hand, the present invention provides a distributed absolute timing system, including: a transmitting end and multiple receiving ends, wherein the transmitting end is used to modulate a master clock signal according to a master timing signal, and send the modulated signal obtained by modulation to the receiving end with a delay; wherein the time of the master hardware pulse signal generated according to the master clock signal is consistent with the time of the reference hardware pulse signal; the multiple receiving ends are connected to the transmitting end, and are used to receive the modulated signal and return the modulated signal to the transmitting end; the transmitting end is also used to receive the modulated signal returned by the receiving end, and demodulate the modulated signal after a delay to obtain a returned timing signal; determine the inherent transmission delay according to the returned timing signal and the master hardware pulse signal; adjust the delay of the transmitting end according to the inherent transmission delay, so that the time of the master hardware pulse signal generated by the transmitting end is consistent with the time of the slave timing signal generated by the receiving end.

[0011] Furthermore, the distributed absolute timing system also includes: a time server, connected to the main clock source and the sending end, for receiving standard time information and clock frequency information provided by the main clock source, generating a reference clock signal and a reference hardware pulse signal according to the standard time information and clock frequency information, and forwarding the reference clock signal and the reference hardware pulse signal to the sending end; correspondingly, the sending end is also used to generate the main clock signal, the main hardware pulse signal and the main timing signal according to the reference clock signal and the reference hardware pulse signal; wherein, the main timing signal and the reference hardware pulse signal have a definite delay relationship.

[0012] Further, the sending end includes: a phase-locked loop connected to the time server for generating the master clock signal according to the reference clock signal; a master timer connected to the phase-locked loop for generating the master hardware pulse signal and the master timing signal according to the master clock signal; a master-time digital conversion chip connected to the time server and the master timer for determining the time difference between the master hardware pulse signal and the reference hardware pulse signal; wherein the time difference is used to adjust the delay or phase of the master clock signal to ensure that the time of the master hardware pulse signal is consistent with the time of the reference hardware pulse signal.

[0013] Further, the sending end includes: a modulation chip connected to the master timer for modulating the master clock signal according to the master timing signal to obtain a modulation signal; a first delay chip connected to the modulation chip for delaying the modulation signal according to an additional delay; a second delay chip for delaying the modulation signal returned by the receiving end according to an additional delay; a master-demodulation chip connected to the second delay chip for demodulating the delayed modulation signal returned by the receiving end to obtain the returned timing signal; correspondingly, the master-time digital conversion chip is further used to determine the time difference between the returned timing signal and the master hardware pulse signal; when the additional delays of the first delay chip and the second delay chip are 0, the time difference is twice the inherent transmission delay.

[0014] Further, the multiple receiving ends are further used for receiving the modulation signal and recovering a continuous slave clock signal and a slave timing signal from the modulation signal.

[0015] Further, the multiple receiving ends include: a slave-demodulation chip connected to the sending end for demodulating the modulation signal to obtain the slave timing signal; a jitter removal chip connected to the sending end for recovering the continuous slave clock signal from the modulation signal; a slave timer connected to the jitter removal chip and the slave-demodulation chip.

[0016] Second aspect, the present invention further provides a distributed absolute timing system, including: a sending end and multiple receiving ends, wherein, the sending end is configured to modulate a master clock signal according to a master timing signal, and send the modulated signal to the receiving ends; wherein, the time of the master hardware pulse signal generated according to the master clock signal is consistent with the time of the reference hardware pulse signal; the multiple receiving ends are connected to the sending end, and are configured to receive the modulated signal and return the modulated signal to the sending end; the sending end is further configured to receive the modulated signal returned by the receiving end, and demodulate the modulated signal to obtain a returned timing signal; determine a transmission delay according to the returned timing signal and the master hardware pulse signal, and send the transmission delay to the receiving ends; the multiple receiving ends are further configured to receive the transmission delay, and adjust a slave clock delay according to the transmission delay, so that the time of the slave hardware pulse signal generated by the receiving end is consistent with the time of the master hardware pulse signal generated by the sending end.

[0017] Further, the receiving end includes: a slave-demodulation chip, connected to the sending end, and configured to receive the modulated signal and demodulate the modulated signal to obtain a slave timing signal; a jitter removal chip, connected to the sending end, and configured to recover the continuous slave clock signal from the modulated signal; a slave timer, connected to the jitter removal chip, and configured to generate a slave hardware pulse signal according to the continuous slave clock signal; a slave-time digital conversion chip, connected to the slave-demodulation chip and the slave timer, and configured to determine a time difference between the slave timing signal and the slave hardware pulse signal; wherein, the time difference is used to guide the transmission delay to adjust the slave clock delay, so that the slave hardware pulse signal is advanced by a transmission delay compared with the slave timing signal.

[0018] Further, the receiving end further includes: a third delay chip, connected to the jitter removal chip and the slave timer, and configured to delay the continuous clock signal according to the transmission delay, so that the slave hardware pulse signal is advanced by a transmission delay compared with the slave timing signal.

[0019] Further, a single optical fiber is used as a transmission carrier between the sending end and the receiving end for two-way transmission.

[0020] The distributed absolute timing system provided by the present invention includes a sending end and multiple receiving ends. Among them, the sending end is used to modulate the master clock signal according to the master timing signal, and delay and send the modulated signal to the receiving end; wherein, the time of the master hardware pulse signal generated according to the master clock signal is the same as the time of the reference hardware pulse signal; the multiple receiving ends are connected to the sending end, and are used to receive the modulated signal and return the modulated signal to the sending end; the sending end is further used to receive the modulated signal returned from the receiving end, and demodulate the modulated signal after a delay to obtain the returned timing signal; determine the inherent transmission delay according to the returned timing signal and the master hardware pulse signal; adjust the master clock delay according to the inherent transmission delay, so that the time of the master hardware pulse signal generated by the sending end is the same as the time of the slave timing signal generated by the receiving end. This system replaces the method of relying entirely on Ethernet to achieve high-precision absolute timing, greatly improves the timing accuracy, and reduces the system implementation difficulty and cost. Description of the Drawings

[0021] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0022] Figure 1 It is one of the schematic diagrams of the distributed absolute timing system provided by the embodiments of the present invention.

[0023] Figure 2 It is the schematic diagram of the master clock adjustment of the distributed absolute timing system provided by the embodiments of the present invention.

[0024] Figure 3 It is the second schematic diagram of the distributed absolute timing system provided by the embodiments of the present invention. Detailed Embodiments

[0025] To make the objectives, technical solutions, and advantages of the present invention clearer, the following will clearly and completely describe the technical solutions in the present invention in conjunction with the drawings in the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0026] It should be noted that the distributed absolute timing system is used to calibrate the time of different measurement devices or control nodes to be consistent with the reference clock. Its timing accuracy determines the time accuracy of multiple signal measurements and the time accuracy of multiple device operations. Although the timing accuracy of the current White Rabbit technology can reach the sub-nanosecond level, it cannot provide better timing accuracy, and the system implementation difficulty and cost are relatively high.

[0027] Considering this, the present invention proposes a new distributed absolute timing system, which includes a sending end and multiple receiving ends. A single optical fiber is used as the transmission medium for bidirectional transmission between the sending end and the receiving ends.

[0028] In the first embodiment, the distributed absolute timing system performs delay adjustment at the sending end.

[0029] The distributed absolute timing system includes: a sending end and multiple receiving ends. Among them, the sending end is used to modulate the master clock signal according to the master timing signal and delay the modulated signal to send it to the receiving ends; among them, the time of the master hardware pulse signal generated according to the master clock signal is consistent with the time of the reference hardware pulse signal; the multiple receiving ends are connected to the sending end and are used to receive the modulated signal and return the modulated signal to the sending end; the sending end is also used to receive the modulated signal returned by the receiving end, demodulate the modulated signal after delay to obtain the returned timing signal; determine the inherent transmission delay according to the returned timing signal and the master hardware pulse signal; adjust the delay of the sending end according to the inherent transmission delay so that the time of the master hardware pulse signal generated by the sending end is consistent with the time of the slave timing signal generated by the receiving end.

[0030] Figure 1 Fig. shows one of the schematic diagrams of the distributed absolute timing system provided by the embodiment of the present invention.

[0031] It is easy to understand that before calibrating the time of the master hardware pulse signal (master 1PPS signal) generated by the sending end to be consistent with the time of the slave timing signal generated by the receiving end, it is necessary to calibrate the time of the master 1PPS signal generated by the sending end to be consistent with the time of the reference hardware pulse signal (reference 1PPS signal).

[0032] Specifically, the distributed absolute timing system provided in this embodiment includes a time server, which communicates with the master clock source and the sending end simultaneously through NTP (Network Time Protocol) or PTP (Precision Time Protocol) of Ethernet. Among them, the time server can be a commercial time server or other types of time servers, and no specific limitation is made here.

[0033] The master clock source refers to the source device or service that provides standard time information and is used to provide precise time calibration for other clocks or systems. In a specific embodiment, the master clock source is the Global Navigation Satellite System (GNSS), which can be used to provide internationally recognized standard time information and clock frequency information.

[0034] Among them, the standard time information refers to the precise time signals obtained by GNSS from satellites. These time signals are based on atomic clocks and have extremely high accuracy and stability. The clock frequency information refers to the stable frequency reference provided by GNSS.

[0035] The time server can receive the signals of the master clock source, that is, the standard time information and the clock frequency information, and output a reference 1PPS signal and a continuous reference clock signal at each whole second moment. Among them, the frequency of the reference clock signal is usually 10MHz and is phase-locked with the reference 1PPS signal. That is to say, each clock cycle is exactly 1×10-7 seconds and is used for precise timing.

[0036] The time server will forward the output reference 1PPS signal and reference clock signal to the sending end. Based on these two reference signals, the sending end calibrates the time of the main 1PPS signal generated by itself to be consistent with the time of the reference 1PPS signal.

[0037] Specifically, Figure 2 shows a schematic diagram of the master clock adjustment of the distributed absolute timing system provided by the embodiment of the present invention.

[0038] As Figure 2 shown, the sending end includes a Phase-Locked Loop (PLL), a main timer, a Time to Digital Converter (TDC) chip, and a delay chip.

[0039] Among them, the PLL is a feedback control system, including a phase detector, a loop filter, and a voltage-controlled oscillator, mainly used to maintain the phase synchronization between the output signal and the reference signal. In this embodiment, the PLL is connected to the time server, can receive the reference clock signal from the time server in real time, and takes the reference clock signal as the input to output the master clock signal, and the phase of the master clock signal is consistent with or maintains a fixed relationship with the reference clock signal.

[0040] The master timer refers to the timer at the sending end, which is used to ensure the time synchronization of all devices and processes in the system, so as to support various applications and services that rely on accurate timestamps. In this embodiment, the master timer is connected to the phase-locked loop, can generate the master 1PPS signal according to the master clock signal output by the phase-locked loop, and further generate the master timing signal, and the master timing signal has a definite delay relationship with the reference hardware pulse signal. Among them, the master timer can be implemented by an FPGA (Field-Programmable Gate Array), or can be implemented by other digital chips with similar functions, such as CPLD (Complex Programmable Logic Device) and ASIC (Application-Specific Integrated Circuit), which are not specifically limited here.

[0041] The master-TDC chip refers to the time-to-digital conversion chip at the sending end, such as AS6501, which can measure the time relationship between the input pulse signal and the reference signal with extremely high precision, and the measurement accuracy can reach up to 10 ps at most. In this embodiment, the master-TDC chip is used to measure the time difference between the master 1PPS signal generated at the sending end and the reference 1PPS signal. Specifically, first, the master 1PPS signal and the reference 1PPS signal are respectively input into the two input channels of the master-TDC chip; then, the master-TDC chip is configured to start measurement when one 1PPS signal arrives and stop measurement when the other 1PPS signal arrives; finally, the time difference output by the master-TDC chip is read, and this difference is the time offset between the master 1PPS signal and the reference 1PPS signal.

[0042] The delay chip is an integrated circuit used to introduce precise time delays in digital or analog signal paths. In this embodiment, the delay chip can adjust the master clock delay according to the time offset between the master 1PPS signal and the reference 1PPS signal, so that the time of the master 1PPS signal generated by the master clock signal is consistent with the time of the reference 1PPS signal. In a specific embodiment, the delay chip can be MC100EP195, its delay resolution is 10 ps, the maximum delay is 10.2 ns, and the inherent delay is 2.2 ns.

[0043] It should be explained here that the minimum step of the main timing signal adjustment delay is the main clock period. For example, for a 125 MHz main clock period, the corresponding minimum adjustment step is 8 ns, but the adjustment range is infinite, that is, 8 ns * N. In order to achieve more precise delay adjustment, a delay chip is introduced, but its delay adjustment range is limited. Therefore, by combining the main timing signal and the delay chip, the ability to adjust the delay infinitely and precisely is achieved.

[0044] After calibrating the time of the main 1PPS signal generated at the sending end with the time of the reference 1PPS signal, it is also necessary to calibrate the time of the main 1PPS signal generated at the sending end with the time of the slave timing signal generated at the receiving end.

[0045] As can be seen from the above, the sending end generates a main clock signal based on the reference clock signal transmitted by the time server, and generates a main 1PPS signal based on the main clock signal. Further, a main timing signal can be generated based on the main 1PPS signal.

[0046] According to Figure 1 it can be seen that at the sending end, in addition to the phase-locked loop, the main timer, and the main-time digital conversion chip described above, it also includes a modulation chip, a main demodulation chip, a first delay chip, and a second delay chip.

[0047] Specifically, first, the modulation chip uses the main timing signal to modulate the main clock signal to obtain a modulation signal. There are various applicable modulation methods here. Preferably, in this embodiment, the main timing signal is used to perform ASK (Amplitude Shift Keying) modulation on the main clock signal.

[0048] ASK modulation is a digital modulation in which the amplitude of a sinusoidal carrier changes with the change of a digital baseband signal. For example, in binary ASK modulation, when the digital signal is 1, a sinusoidal carrier signal is output, and when the digital signal is 0, no sinusoidal carrier signal is output. In this embodiment, the main timing signal is a digital signal, and the main clock signal is a sinusoidal carrier signal.

[0049] Through ASK modulation, the main timing signal can be effectively embedded into the main clock signal, and then the modulated modulation signal is transmitted to multiple receiving ends together after passing through the first delay chip. After receiving the modulation signal, the receiving end directly forwards it back to the sending end. Among them, the specific models of the first delay chip and the second delay chip are the same, and both are set to 0 additional delay.

[0050] After the sending end receives the modulated signal directly returned from the receiving end, it also first passes the signal through a delay chip, namely the second delay chip, and then demodulates the modulated signal through the master-demodulation chip to obtain the returned timing signal.

[0051] Subsequently, the master-TDC chip is used to determine the time difference between the returned timing signal and the master 1PPS signal. This time difference corresponds to twice the inherent transmission delay (Td0). Immediately afterwards, the master clock delay is adjusted according to the inherent transmission delay so that the time of the master 1PPS signal generated by the sending end is consistent with the time of the slave timing signal generated by the receiving end.

[0052] Specifically, first calculate the minimum value (Td) greater than the inherent transmission delay (Td0) among integer multiples of the master clock period. For example, if the master clock period is 8 ns and Td0 is 15 ns, then Td is twice the master clock period, that is, 16 ns.

[0053] Then, advance the time of the master timing signal at the sending end by one Td ahead of the master 1PPS signal, and at the same time adjust the additional delays of the two delay chips to Td - Td0. For example, if Td is 16 ns and Td0 is 15 ns, the additional delays of the first delay chip and the second delay chip are Td - Td0 = 16 ns - 15 ns = 1 ns. In this case, the time of the slave timing signal obtained at the receiving end is consistent with the time of the master 1PPS signal, and the returned timing signal obtained at the sending end lags behind the master 1PPS signal by one Td.

[0054] After the delay calibration at the sending end is completed, if the optical fiber length changes with the ambient temperature, resulting in a change in the transmission delay, the sending end can monitor the time relationship between the returned timing signal and the master 1PPS signal in real time, and at the same time adjust the additional delays of the two delay chips to keep the measurement value of the master-TDC chip unchanged at Td. Then, the time of the slave timing signal obtained at the receiving end will be consistent with the time of the master 1PPS signal.

[0055] According to Figure 1 It can also be seen that the receiving end includes a slave-demodulation chip, a jitter removal chip, and a slave timer. Among them, the slave-demodulation chip is connected to the sending end and is used to demodulate the modulated signal to obtain the slave timing signal. The jitter removal chip is connected to the sending end and is used to recover the continuous slave clock signal from the modulated signal. The slave timer is connected to the jitter removal chip and the slave-demodulation chip and is used to meet its own timing application requirements according to the continuous slave clock signal and the slave timing signal.

[0056] The jitter cleaner chip (Jitter Cleaner chip) uses a phase-locked loop (PLL) and a low-noise voltage-controlled oscillator (VCO) to generate a low-noise, continuous slave clock signal that is phase-locked to the input clock signal (i.e., the modulation signal). In a specific embodiment, the LMK04828 is used as the Jitter Cleaner chip, and its frequency holding function can maintain the frequency and phase stability of the output signal in the case of a short-term loss of the input clock signal, and then continue the phase-locked control when the input clock signal is restored. In this embodiment, the receiving end uses the Jitter Cleaner chip to restore the modulation signal into a continuous slave clock signal and maintain a very high phase accuracy.

[0057] When the delay calibration at the sending end is completed, the time of the slave timing signal obtained at the receiving end is the same as the time of the main 1PPS signal.

[0058] It is worth mentioning that in this embodiment, the main timing signal is used to perform (ASK) modulation on the main clock signal, and the modulation signal is transmitted bidirectionally in a single optical fiber. At the receiving end, the Jitter Cleaner chip is used to restore the continuous slave clock signal from the modulation signal, replacing the CDR function of the Ethernet PHY chip and improving the phase accuracy of the clock.

[0059] At the same time, the return timing signal is restored from the modulation signal through the demodulation chip, and then the main-TDC chip is used to measure the transmission delay of the return timing signal, replacing the measurement of the transmission delay of the Ethernet timing data packet and improving the delay measurement accuracy. In addition, a timer implemented by FPGA, combined with the first delay chip and the second delay chip, is used to adjust the time of the timing signal at the sending end, further improving the delay calibration accuracy. It is worth mentioning that the measurement accuracy of the main-TDC chip and the adjustment accuracy of the first delay chip and the second delay chip are both 10 ps, which is far better than that of White Rabbit. The system implementation is simpler and the cost is lower.

[0060] Here, it needs to be explained that the minimum step size for adjusting the delay of the return timing signal is the main clock period. For example, for a 125 MHz main clock period, the corresponding minimum adjustment step size is 8 ns, but the adjustment range is infinite, that is, 8 ns * N. In order to achieve finer delay adjustment, the first delay chip and the second delay chip are introduced, but their delay adjustment ranges are limited. Therefore, by combining the return timing signal with the first delay chip and the second delay chip, the ability to adjust the delay infinitely finely is achieved.

[0061] In the distributed absolute timing system provided in this embodiment, after the master 1PPS signal at the sending end and the slave timing signal at the receiving end have been calibrated to be consistent with the reference 1PPS signal in time, and after each 1PPS signal is generated, the time information published by the time server is obtained through the NTP or PTP protocol of the Ethernet, and rounded to the nearest integer, and the coarse timing with a resolution of 1 second can be obtained.

[0062] In this embodiment, the distributed absolute timing system includes a sending end and multiple receiving ends. Among them, the sending end is used to modulate the master clock signal according to the master timing signal, and delay the modulated signal and send it to the receiving end; among them, the time of the master hardware pulse signal generated according to the master clock signal is consistent with the time of the reference hardware pulse signal; the multiple receiving ends are connected to the sending end and are used to receive the modulated signal and return the modulated signal to the sending end; the sending end is also used to receive the modulated signal returned from the receiving end, and demodulate the modulated signal after delay to obtain the returned timing signal; determine the inherent transmission delay according to the returned timing signal and the master hardware pulse signal; adjust the delay of the sending end according to the inherent transmission delay, so that the time of the master hardware pulse signal generated by the sending end is consistent with the time of the slave timing signal generated by the receiving end. This system replaces the method of achieving high-precision absolute timing completely relying on Ethernet, greatly improves the timing accuracy, and reduces the system implementation difficulty and cost.

[0063] In the second embodiment, the distributed absolute timing system adjusts the delay at the receiving end.

[0064] The distributed absolute timing system includes: a sending end and multiple receiving ends. Among them, the sending end is used to modulate the master clock signal according to the master timing signal and send the modulated signal to the receiving end; among them, the time of the master hardware pulse signal generated according to the master clock signal is consistent with the time of the reference hardware pulse signal; the multiple receiving ends are connected to the sending end and are used to receive the modulated signal and return the modulated signal to the sending end; the sending end is also used to receive the modulated signal returned from the receiving end and demodulate the modulated signal to obtain the returned timing signal; determine the transmission delay according to the returned timing signal and the master hardware pulse signal, and send the transmission delay to the receiving end; the multiple receiving ends are also used to receive the transmission delay and adjust the slave clock delay according to the transmission delay, so that the time of the slave hardware pulse signal generated by the receiving end is consistent with the time of the master hardware pulse signal generated by the sending end.

[0065] Figure 3 Fig. 2 shows the second schematic diagram of the distributed absolute timing system provided by the embodiment of the present invention.

[0066] It is easy to understand that first, the time of the main 1PPS signal generated by the sending end needs to be calibrated with the time of the reference 1PPS signal. The calibration process is the same as that in the previous embodiment and will not be elaborated here.

[0067] After calibrating the time of the main 1PPS signal generated by the sending end with the time of the reference 1PPS signal, it is necessary to calibrate the time of the main 1PPS signal generated by the sending end with the time of the slave hardware pulse signal (slave 1PPS signal) generated by the receiving end.

[0068] As can be seen from the above, the sending end generates a main clock signal according to the reference clock signal transmitted by the time server, and generates a main 1PPS signal according to the main clock signal. Further, a main timing signal can be generated according to the main 1PPS signal.

[0069] At the sending end, first, the modulation chip modulates the main clock signal according to the main timing signal to obtain a modulation signal. There are various applicable modulation methods here. Preferably, in this embodiment, the main timing signal is used to perform ASK (Amplitude Shift Keying) modulation on the main clock signal.

[0070] ASK modulation is a digital modulation in which the amplitude of a sine carrier changes with the change of a digital baseband signal. For example, in binary ASK modulation, when the digital signal is 1, a sine carrier signal is output, and when the digital signal is 0, no sine carrier signal is output. In this embodiment, the main timing signal is a digital signal, and the main clock signal is a sine carrier signal.

[0071] Through ASK modulation, the main timing signal can be effectively embedded into the main clock signal, and then the modulated modulation signal is transmitted to multiple receiving ends together. After receiving the modulation signal, the receiving end directly forwards it back to the sending end. When the sending end receives the modulation signal directly returned from the receiving end, the main-demodulation chip demodulates the modulation signal to obtain a return timing signal.

[0072] Subsequently, the main-TDC chip is used to determine the time difference between the return timing signal and the main 1PPS signal. This time difference corresponds to twice the transmission delay (T). Then, the transmission delay (T) is sent to the receiving end, and the receiving end adjusts the slave clock delay so that the slave 1PPS signal generated by the receiving end is one transmission delay (T) earlier than the slave timing signal. That is, the time of the slave hardware pulse signal generated by the receiving end is the same as the time of the main 1PPS signal generated by the sending end.

[0073] Specifically, according to Figure 3It can be known that the receiving end includes a slave demodulation chip, a jitter cleaning chip (Jitter Cleaner chip), a slave timer, and a slave time-to-digital conversion chip (slave-TDC chip).

[0074] Specifically, the slave demodulation chip is connected to the sending end, and is used to receive the modulated signal and demodulate the modulated signal to obtain a slave timing signal. The Jitter Cleaner chip is connected to the sending end, and is used to recover a continuous slave clock signal from the modulated signal. The slave timer is connected to the Jitter Cleaner chip, and is used to generate a slave 1PPS signal according to the continuous slave clock signal; the slave-TDC chip is connected to the slave demodulation chip and the slave timer, and is used to determine the time difference between the slave timing signal and the slave 1PPS signal. Wherein, this time difference is used to guide the transmission delay (T) to adjust the slave clock delay, so that the slave 1PPS signal is one transmission delay (T) ahead of the slave timing signal, that is, the time of the slave 1PPS signal generated by the receiving end is the same as the time of the master 1PPS signal generated by the sending end.

[0075] Among them, the slave timer refers to the timer of the receiving end. Like the master timer, it can be implemented by an FPGA, or can be implemented by other digital chips with similar functions (such as CPLD and ASIC), and specific limitations are not made here.

[0076] The slave-TDC chip refers to the time-to-digital conversion chip of the receiving end, such as AS6501, which can measure the time relationship between the input pulse signal and the reference signal with extremely high precision, and the measurement precision can reach up to 10ps at most.

[0077] In this embodiment, the slave-TDC chip is used to measure the time difference between the slave 1PPS signal generated by the receiving end and the slave timing signal. Specifically, first, the slave 1PPS signal and the slave timing signal are respectively input into two input channels of the slave-TDC chip; then, the slave-TDC chip is configured to start measurement when a 1PPS signal arrives and stop measurement when another 1PPS signal arrives; finally, the time difference output by the slave-TDC chip is read, and this difference is the time offset between the slave 1PPS signal and the slave timing signal.

[0078] In addition, according to Figure 3 It can also be seen that the receiving end further includes a delay chip, that is, a third delay chip, which is connected to the Jitter Cleaner chip and the slave timer, and is used to delay the recovered continuous slave clock signal according to the transmission delay (T), so that the slave 1PPS signal is one transmission delay (T) ahead of the slave timing signal, that is, the time of the slave 1PPS signal generated by the receiving end is the same as the time of the master 1PPS signal generated by the sending end.

[0079] Based on the above, after the delay calibration at the receiving end is completed, if the optical fiber length changes with the ambient temperature, resulting in a change in the transmission delay, the sending end can monitor the T measurement value in real time and inform the receiving end to make real-time adjustments, so that the time of the 1PPS signal generated at the receiving end is consistent with the time of the main 1PPS signal generated at the sending end.

[0080] It is worth mentioning that in this embodiment, the main timing signal is used to modulate the main clock signal (ASK), and the modulated signal is transmitted bidirectionally in a single optical fiber. At the receiving end, a continuous slave clock signal is recovered from the modulated signal through a Jitter Cleaner chip, replacing the CDR function of the Ethernet PHY chip, and improving the phase accuracy of the clock.

[0081] At the same time, the slave timing signal is recovered from the modulated signal through a demodulation chip, and then the transmission delay of the slave timing signal is measured using a slave-TDC chip, replacing the transmission delay measurement of the Ethernet timing data packet, and improving the delay measurement accuracy. In addition, a timer implemented by an FPGA, combined with a third delay chip, adjusts the time of the timing signal at the sending end, further improving the delay calibration accuracy. It is worth mentioning that the measurement accuracy of the slave-TDC chip and the adjustment accuracy of the delay chip are both 10 ps, far better than that of White Rabbit. The system implementation is simpler and the cost is lower.

[0082] Here, it needs to be explained that the minimum step size for adjusting the delay of the slave timing signal is the slave clock cycle. For example, for a 125 MHz slave clock cycle, the corresponding minimum adjustment step size is 8 ns, but the adjustment range is infinite, that is, 8 ns * N. In order to achieve more precise delay adjustment, a third delay chip is introduced, but its delay adjustment range is limited. Therefore, by combining the slave timing signal and the third delay chip, the ability to adjust the delay infinitely and precisely is achieved.

[0083] For the distributed absolute timing system provided in this embodiment, after the 1PPS signals at the sending end and the receiving end have been calibrated to be consistent with the reference 1PPS signal time, and after each 1PPS signal is generated, the time information published by the time server is obtained through the NTP or PTP protocol of the Ethernet, and rounded to the nearest integer, then the coarse timing with a resolution of 1 second can be obtained.

[0084] In this embodiment, the distributed absolute timing system includes a sending end and multiple receiving ends. Among them, the sending end is used to modulate the master clock signal according to the master timing signal and send the modulated signal to the receiving ends; the multiple receiving ends are connected to the sending end, used to receive the modulated signal and return the modulated signal to the sending end; the sending end is also used to receive the modulated signal returned from the receiving ends and demodulate the modulated signal to obtain the returned timing signal; determine the transmission delay according to the returned timing signal and the master hardware pulse signal, and send the transmission delay to the receiving ends; the multiple receiving ends are also used to receive the transmission delay and adjust the slave clock delay according to the transmission delay, so that the time of the slave hardware pulse signal generated by the receiving ends is consistent with the time of the master hardware pulse signal generated by the sending end. This system replaces the method of achieving high-precision absolute timing completely relying on Ethernet, greatly improves the timing accuracy, and reduces the system implementation difficulty and cost. In addition, the distributed absolute timing system provided by the present invention can be applied to large-scale distributed measurement systems and large-scale distributed control systems, such as cosmic ray observation systems and accelerator control systems, and can also be applicable to other systems with timing requirements, which are not specifically limited here.

[0085] Through the description of the above embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus a necessary general hardware platform, and of course, it can also be implemented by hardware. Based on such an understanding, the essence of the above technical solution, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to enable a computer device (which can be a personal computer, a server, or a network device, etc.) to execute the methods described in each embodiment or some parts of the embodiments.

[0086] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of each embodiment of the present invention.

Claims

1. A distributed absolute timing system, characterized in that: include: One sender and multiple receivers, where The transmitting end is used to modulate the main clock signal according to the main timing signal, and send the modulated signal obtained by the modulation to the receiving end with a delay; wherein the time of the main hardware pulse signal generated according to the main clock signal is consistent with the time of the reference hardware pulse signal; The multiple receiving ends are connected to the transmitting end and are used to receive the modulated signal and return the modulated signal to the transmitting end; The transmitting end is also used to receive the modulated signal returned by the receiving end, and demodulate the modulated signal after a delay to obtain a return timing signal; determine the inherent transmission delay based on the return timing signal and the master hardware pulse signal; and adjust the delay of the transmitting end based on the inherent transmission delay so that the time of the master hardware pulse signal generated by the transmitting end is consistent with the time of the slave timing signal generated by the receiving end.

2. The distributed absolute timing system according to claim 1, characterized in that: Also includes: A time server, connected to the master clock source and the transmitting end, configured to receive standard time information and clock frequency information provided by the master clock source, generate a reference clock signal and a reference hardware pulse signal according to the standard time information and the clock frequency information, and forward the reference clock signal and the reference hardware pulse signal to the transmitting end; Correspondingly, the transmitting end is also used to generate the master clock signal, the master hardware pulse signal and the master timing signal according to the reference clock signal and the reference hardware pulse signal; wherein the master timing signal has a definite delay relationship with the reference hardware pulse signal.

3. The distributed absolute timing system according to claim 2, characterized in that: The transmitting end comprises: a phase-locked loop, connected to the time server, and configured to generate the master clock signal according to the reference clock signal; A master timer, connected to the phase-locked loop, for generating the master hardware pulse signal and the master timing signal according to the master clock signal; A master-time digital conversion chip is connected to the time server and the master timer, and is used to determine the time difference between the master hardware pulse signal and the reference hardware pulse signal; wherein the time difference is used to adjust the delay or phase of the master clock signal to ensure that the time of the master hardware pulse signal is consistent with the time of the reference hardware pulse signal.

4. The distributed absolute timing system according to claim 3, characterized in that: The transmitting end comprises: A modulation chip, connected to the master timer, and used to modulate the master clock signal according to the master timing signal to obtain a modulation signal; A first delay chip, connected to the modulation chip, for delaying the modulation signal according to the additional delay; A second delay chip, used to delay the modulated signal returned by the receiving end according to the additional delay; A main-demodulation chip, connected to the second delay chip, for demodulating the delayed modulated signal returned by the receiving end to obtain the return timing signal; Correspondingly, the master-time digital conversion chip is also used to determine the time difference between the return timing signal and the master hardware pulse signal; when the additional delay of the first delay chip and the second delay chip is 0, the time difference is twice the inherent transmission delay.

5. The distributed absolute timing system according to any one of claims 1 to 4, characterized in that: The multiple receiving ends are also used to receive the modulated signal and recover continuous slave clock signals and slave timing signals from the modulated signal.

6. The distributed absolute timing system according to claim 5, characterized in that: The multiple receiving ends include: A slave-demodulation chip, connected to the transmitting end, for demodulating the modulated signal to obtain the slave timing signal; A jitter cleaning chip, connected to the transmitting end, and used for recovering the continuous slave clock signal from the modulated signal; A slave timer is connected to the jitter cleaning chip and the slave-demodulation chip.

7. A distributed absolute timing system, characterized in that: include: One sender and multiple receivers, where The transmitting end is used to modulate the main clock signal according to the main timing signal, and send the modulated signal to the receiving end; wherein the time of the main hardware pulse signal generated according to the main clock signal is consistent with the time of the reference hardware pulse signal; The multiple receiving ends are connected to the transmitting end and are used to receive the modulated signal and return the modulated signal to the transmitting end; The transmitting end is further used to receive the modulated signal returned by the receiving end, and demodulate the modulated signal to obtain a returned timing signal; determine the transmission delay according to the returned timing signal and the main hardware pulse signal, and send the transmission delay to the receiving end; The multiple receiving ends are also used to receive the transmission delay and adjust the slave clock delay according to the transmission delay so that the time of the slave hardware pulse signal generated by the receiving end is consistent with the time of the master hardware pulse signal generated by the transmitting end.

8. The distributed absolute timing system according to claim 7, characterized in that: The receiving end comprises: A slave-demodulation chip, connected to the transmitting end, for receiving the modulated signal and demodulating the modulated signal to obtain a slave timing signal; A jitter cleaning chip, connected to the transmitting end, and used for recovering the continuous slave clock signal from the modulated signal; A slave timer, connected to the jitter cleaning chip, for generating a slave hardware pulse signal according to the continuous slave clock signal; A slave-time digital conversion chip is connected to the slave-demodulation chip and the slave timer, and is used to determine the time difference between the slave timing signal and the slave hardware pulse signal; wherein the time difference is used to guide the transmission delay to adjust the slave clock delay so that the slave hardware pulse signal is one transmission delay ahead of the slave timing signal.

9. The distributed absolute timing system according to claim 8, characterized in that: The receiving end also includes: The third delay chip is connected to the jitter removal chip and the slave timer, and is used to delay the continuous clock signal according to the transmission delay so that the slave hardware pulse signal is one transmission delay ahead of the slave timing signal.

10. The distributed absolute timing system according to any one of claims 7 to 9, characterized in that: A single optical fiber is used as a transmission carrier for bidirectional transmission between the transmitting end and the receiving end.

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