Light emitting element, display device including the same, method of manufacturing the light emitting element, and method of manufacturing the display device

Abstract

Provided are a light emitting element, a display device including the light emitting element, a method of manufacturing the light emitting element, and a method of manufacturing the display device, the light emitting element including: a first element bar including a first semiconductor layer and an active layer, and having a first inclination angle on a side surface; a second element bar on the first element bar and having a second tilt angle on a side surface; a third element bar on the second element bar and having a third inclination angle on the side surface, the second inclination angle being smaller than the first inclination angle and the third inclination angle; a protective layer around one surface and a side surface of the first element rod, a side surface of the second element rod, and a side surface of the third element rod; and a contact electrode around the protective layer and electrically connected to the first semiconductor layer.

Description

[0001] This application claims the priority and benefit of Korean Patent Application No. 10-2023-0176362, filed with the Korean Intellectual Property Office on December 7, 2023, the entire disclosure of which is incorporated herein by reference. Technical Field

[0002] With the development of the information society, the demand for display devices for displaying images is increasing in various forms. The display device may be a flat panel display such as a liquid crystal display, a field emission display, a light-emitting display, or the like.

[0003] The light-emitting display device may be implemented as an organic light-emitting display device including an organic light-emitting diode (OLED) element as a light-emitting element, an inorganic light-emitting display device including an inorganic semiconductor element as a light-emitting element, or a micro light-emitting diode display device including a micro light-emitting diode element as a light-emitting element. Background Art

[0004] The present disclosure relates to a light-emitting element, a display device including the light-emitting element, and a method of manufacturing the light-emitting element. Summary of the Invention

[0005] Aspects and features of embodiments of the present disclosure provide a method of manufacturing a display device, a light-emitting element, and a display device manufactured using the method, which can ensure the width of the active layer with respect to the width of the light-emitting element while reducing or minimizing damage to the active layer.

[0006] However, the aspects of the present disclosure are not limited to the aspects set forth herein. The above and other aspects of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to one or more embodiments, a light-emitting element includes: a first element bar including a first semiconductor layer and an active layer, and having a first inclination angle on a side surface; a second element bar on the first element bar and having a second inclination angle on a side surface; a third element bar on the second element bar and having a third inclination angle on a side surface, the second inclination angle being smaller than the first inclination angle and the third inclination angle; a protective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar; and a contact electrode around the protective layer and electrically connected to the first semiconductor layer.

[0008] According to one or more embodiments, the second inclination angle is in the range of 60 degrees to 80 degrees.

[0009] According to one or more embodiments, the protective layer includes: a first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; a reflective layer on the first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; and a second insulating layer on the reflective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar.

[0010] According to one or more embodiments, the first insulating layer and the reflective layer are not on the side surface of the third element bar.

[0011] According to one or more embodiments, the second element bar widens towards the third element bar, and the width of the third element bar is greater than the width of the first element bar.

[0012] According to one or more embodiments, the contact electrode extends from one surface of the first element bar and is on at least a portion of the side surfaces of the first element bar, the second element bar, and the third element bar.

[0013] According to one or more embodiments, a light-emitting element includes: an element bar including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence and divided into a first element bar, a second element bar, and a third element bar according to an inclination angle, the first element bar including the first semiconductor layer and the active layer, the inclination angle including a first inclination angle, a second inclination angle, and a third inclination angle, the second inclination angle of the second element bar being smaller than the first inclination angle of the first element bar and the third inclination angle of the third element bar; a protective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar; and a first contact electrode and a second contact electrode separated from each other on one surface of the first element bar, the first contact electrode being electrically connected to the first semiconductor layer, and the second contact electrode being electrically connected to the second semiconductor layer.

[0014] According to one or more embodiments, the protective layer includes: a first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; a reflective layer on the first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; and a second insulating layer on the reflective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar.

[0015] According to one or more embodiments, the first contact electrode and the second contact electrode are disposed on at least a portion of the side surface of the element bar on the protective layer.

[0016] According to one or more embodiments, a display device includes: a substrate; a pixel electrode on the substrate; a light-emitting element on the pixel electrode and including a contact electrode on one surface; a connection electrode connecting the contact electrode and the pixel electrode; and a common electrode on the light-emitting element. The light-emitting element further includes: a first element bar including a first semiconductor layer and an active layer and having a first inclination angle on a side surface; a second element bar on the first element bar and having a second inclination angle on a side surface; a third element bar on the second element bar and having a third inclination angle on a side surface; and a protective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar. The contact electrode is around at least a part of a side surface of the protective layer, and the second inclination angle is smaller than the first inclination angle and the third inclination angle.

[0017] According to one or more embodiments, the second inclination angle is in a range of 60 degrees to 80 degrees.

[0018] According to one or more embodiments, the protective layer includes: a first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; a reflective layer on the first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; and a second insulating layer on the reflective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar. According to one or more embodiments, the first insulating layer and the reflective layer are not on side surfaces of the third element bar.

[0019] According to one or more embodiments, the contact electrode extends from one surface of the first element bar and is on at least a part of side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar.

[0020] In one or more embodiments, the display device further includes: an organic pattern layer between the light-emitting element and the pixel electrode, wherein the connection electrode is on the pixel electrode on a part of a side surface of the organic pattern layer and on a side surface of the contact electrode.

[0021] According to one or more embodiments, a display device includes: a substrate; a pixel electrode and a common electrode, on the substrate and separated from each other; a light-emitting element, on the pixel electrode and the common electrode and including a first contact electrode and a second contact electrode on one surface; a first connection electrode, connecting the pixel electrode and the first contact electrode; and a second connection electrode, connecting the common electrode and the second contact electrode. The light-emitting element includes: an element bar including a first semiconductor layer, an active layer, a second semiconductor layer, and a third semiconductor layer stacked in sequence and divided into a first element bar, a second element bar, and a third element bar according to an inclination angle, the inclination angle including a first inclination angle, a second inclination angle, and a third inclination angle, and the second inclination angle of the second element bar being smaller than the first inclination angle of the first element bar and the third inclination angle of the third element bar; and a protective layer, around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar, and the first contact electrode and the second contact electrode being separated from each other on one surface of the first element bar and on at least a part of the side surface of the element bar on the protective layer.

[0022] According to one or more embodiments, the protective layer includes: a first insulating layer, around one surface and side surfaces of the first element bar and side surfaces of the second element bar; a reflective layer, on the first insulating layer around one surface and side surfaces of the first element bar and side surfaces of the second element bar; and a second insulating layer, on the reflective layer around one surface and side surfaces of the first element bar, side surfaces of the second element bar, and side surfaces of the third element bar.

[0023] According to one or more embodiments, the display device further includes: an organic pattern layer, between the pixel electrode and the common electrode, wherein the light-emitting element is on the organic pattern layer, wherein the first connection electrode is on a part of the side surface of the organic pattern layer and the side surface of the first contact electrode, and wherein the second connection electrode is on another part of the side surface of the organic pattern layer and the side surface of the second contact electrode.

[0024] According to one or more embodiments, a method of manufacturing a light-emitting element includes: forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on a growth substrate; forming a first element bar having a first tilt angle by etching the active material layer and the first semiconductor material layer using a first mask; masking the first element bar using a second mask and etching the second semiconductor material layer and the third semiconductor material layer; forming a first insulating layer and a first reflective layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer; forming a second element bar having a second tilt angle and a third element bar having a third tilt angle by etching at least one side surface of at least one of the first semiconductor material layer, the second semiconductor material layer, the third semiconductor material layer, the first insulating layer, and the first reflective layer using a third mask; forming a second insulating layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer; and forming a contact electrode on the second insulating layer.

[0025] According to one or more embodiments, a method of manufacturing a display device includes: forming a third semiconductor material layer, a second semiconductor material layer, an active material layer, and a first semiconductor material layer on a growth substrate; forming a first element bar having a first tilt angle by etching the active material layer and the first semiconductor material layer using a first mask; masking the first element bar using a second mask and then etching the second semiconductor material layer and the third semiconductor material layer; forming a first insulating layer and a first reflective layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer; forming a second element bar having a second tilt angle and a third element bar having a third tilt angle by etching at least one side surface of at least one of the first semiconductor material layer, the second semiconductor material layer, the third semiconductor material layer, the first insulating layer, and the first reflective layer using a third mask; forming a second insulating layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer, and the first semiconductor material layer; forming a light-emitting element by forming a contact electrode on the second insulating layer; transferring the light-emitting element to a circuit board having a pixel electrode; and forming a connection electrode connecting the contact electrode and the pixel electrode.

[0026] According to one or more embodiments, in the display device and the method of manufacturing the same, it is possible to ensure a sufficient width of the active layer with respect to the chip size while reducing or minimizing damage to the active layer during the process.

[0027] However, the effects of the present disclosure are not limited to the above effects, and various other effects are included in the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0029] Figure 2 is a layout diagram showing a display device according to one or more embodiments.

[0030] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0031] Figure 4 is an equivalent circuit diagram showing sub-pixels according to one or more embodiments.

[0032] Figure 5 is an equivalent circuit diagram showing sub-pixels according to one or more embodiments.

[0033] Figure 6 is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments.

[0034] Figure 7 is a cross-sectional view showing an example of a cross-section corresponding to the line I1-I1' of the display panel and Figure 6

[0035] Figure 8A and Figure 8B is a cross-sectional view showing an example in detail of area A of Figure 7

[0036] Figure 9 is a cross-sectional view showing another example in detail of area A of Figure 7

[0037] Figure 10 is a cross-sectional view showing another example in detail of area A of Figure 7

[0038] Figure 11 is a cross-sectional view showing another example in detail of area A of Figure 7

[0039] Figure 12 is a layout diagram showing pixels in a display area according to one or more embodiments.

[0040] Figure 13 is a cross-sectional view showing an example of a cross-section corresponding to the line I2-I2' in Figure 12 of the display panel.

[0041] Figure 14 is a cross-sectional view showing an example in detail of area B of Figure 13

[0042] Figure 15 and Figure 16 is a cross-sectional view showing an example in detail of Figure 13 ​​​​​​A cross-sectional view of another example of region B.

[0043] Figure 17 FIG. is a flowchart showing a method of manufacturing a display device according to one or more embodiments.

[0044] Figures 18 to 33 FIG. is a cross-sectional view showing a method of manufacturing a display device according to one or more embodiments.

[0045] Figure 34 FIG. is an exemplary view schematically showing a virtual reality device including a display device according to one or more embodiments.

[0046] Figure 35 FIG. is an exemplary view schematically showing a smart device including a display device according to one or more embodiments.

[0047] Figure 36 FIG. is a view schematically showing an example of a vehicle including a display device according to one or more embodiments.

[0048] Figure 37 FIG. is a view schematically showing an example of a transparent display device including a display device according to one or more embodiments. DETAILED DESCRIPTION

[0049] Now, embodiments of the present disclosure will be described more fully hereinafter with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as restrictive. Throughout the present disclosure, the same reference numerals indicate the same components. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

[0050] To describe the embodiments of the present disclosure, some components irrelevant to the description may not be provided in the components.

[0051] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it can be directly on the other layer or substrate, or an intermediate layer may also be present. In contrast, when an element is referred to as being "directly on" another element, no intermediate element may be present.

[0052] In addition, the phrase "in a plan view" means when viewing the object part from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the object part from the side. The term "superposed" or its variants means that the first object can be above, below, or beside the second object, and vice versa. Additionally, the term "superposed" can include layering, stacking, facing or being oriented towards, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by a person of ordinary skill in the art. The expression "not superposed" can include meanings such as "spaced apart from", "separated from", "offset from", or "biased from", and any other suitable equivalents as would be appreciated and understood by a person of ordinary skill in the art. The terms "face" and "be oriented towards" can mean that the first object can be directly or indirectly opposite the second object. In the case where a third object is between the first object and the second object, although the first object and the second object still face each other, the first object and the second object can be understood to be indirectly opposite each other.

[0053] For ease of description, spatial relative terms such as "below", "beneath", "under", "above", "over", etc. may be used herein to describe the relationship between one element or component and another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. For example, in the case where the device shown in the figures is flipped, a device "below" or "beneath" another device may be placed "above" the other device. Thus, the exemplary term "below" can include both the lower and upper positions. The device can also be oriented in other directions, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0054] When an element is referred to as "connected" or "coupled" to another element, the element can be "directly connected" or "directly coupled" to the other element, or can be "electrically connected" or "electrically coupled" to the other element with one or more intervening elements therebetween. It will be further understood that when the terms "comprise", "include", "have", and / or their variants are used, they can specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, integers, steps, operations, elements, components, and / or any combination thereof.

[0055] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or to facilitate description and illustration. For example, when discussing a "first element" in a description, it may be referred to as a "second element" or a "third element" without departing from the teachings herein, and the "second element" and "third element" may be named in a similar manner.

[0056] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (e.g., limitations of the measurement system), the term "about" or "approximate" as used herein includes the stated value and means within an acceptable deviation range of a particular value as determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0057] In the present disclosure and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" may be understood to mean "A, B, or A and B". The terms "and" and "or" may be used in a conjunctive or disjunctive sense and may be understood to be equivalent to "and / or". In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one of the group consisting of...". For example, "at least one of A and B" may be understood to mean "A, B, or A and B".

[0058] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and will not be interpreted in an idealized or overly formal sense unless expressly so defined in the present disclosure.

[0059] In view of the entire content of the present disclosure, a person of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure can be partially or fully combined or combined with each other, and can be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment can be implemented independently of each other or in combination with each other in any suitable way.

[0060] Hereinafter, specific embodiments will be described with reference to the accompanying drawings.

[0061] Figure 1 is a perspective view showing a display device according to one or more embodiments.

[0062] Referring to Figure 1 , the display device 10 is a device for displaying video or still images, such as mobile phones, smart phones, tablet personal computers, and portable electronic devices (such as smart watches, watch phones, mobile communication terminals, electronic notebooks, e-books, portable multimedia players (PMPs), navigation devices, and ultra-mobile personal computers (UMPCs)), as well as display screens for various products (such as televisions, laptop computers, monitors, billboards, and / or Internet of Things (IoT) devices).

[0063] The display device 10 may be a light-emitting display device, such as an organic light-emitting display device using organic light-emitting diodes (OLEDs), a quantum dot light-emitting display device including a quantum dot light-emitting layer, an inorganic light-emitting display device including an inorganic semiconductor, and a miniaturized light-emitting display device using micro or nano light-emitting diodes (micro LEDs or nano LEDs). Hereinafter, the description focuses on the fact that the display device 10 is a micro light-emitting display device, but the present disclosure is not limited thereto. On the other hand, for ease of explanation, micro light-emitting diodes are hereinafter referred to as light-emitting diodes.

[0064] The display device 10 includes a display panel 100, a display driving circuit 250, a circuit board 300, and a power supply circuit 500.

[0065] The display panel 100 may be formed as a rectangular plane having a short side in a first direction DR1 and a long side in a second direction DR2 that intersects the first direction DR1. The corners where the short side in the first direction DR1 and the long side in the second direction DR2 meet may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may be formed at right angles. The planar shape of the display panel 100 is not limited to a rectangle and may be formed in other polygonal shapes, circular shapes, or elliptical shapes. The display panel 100 may be formed flat, but is not limited thereto. For example, the display panel 100 is formed at the left and right ends and may include curved portions having a constant curvature or a varying curvature. Additionally, the display panel 100 may be formed to be flexible, such as being capable of bending, folding, and / or curling.

[0066] The substrate SUB of the display panel 100 may include a main region MA and a sub-region SBA.

[0067] The main area MA may include a display area DA and a non-display area NDA. The display area DA displays an image, and the non-display area NDA is an outer area of the display area DA and surrounds the display area DA along the edge or periphery of the display area DA (e.g., around the display area DA along the edge or periphery of the display area DA). The display area DA may include a plurality of pixels for displaying an image. For example, a pixel may include a first sub-pixel that emits a first light, a second sub-pixel that emits a second light, and a third sub-pixel that emits a third light.

[0068] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2. Although Figure 1 the sub-area SBA is shown as being unfolded, the sub-area SBA may be curved, and in this case, the sub-area SBA may be provided on the bottom surface of the display panel 100. When the sub-area SBA is curved, it may overlap with the main area MA in the third direction DR3, which is the thickness direction of the display panel 100. The display driving circuit 250 may be provided in the sub-area SBA.

[0069] The display driving circuit 250 may generate signals and voltages for driving the display panel 100. The display driving circuit 250 may be formed as an integrated circuit (IC) and may be attached to the display panel 100 using a chip on glass (COG) method, a chip on plastic (COP) method, or an ultrasonic bonding method, but is not limited thereto. For example, the display driving circuit 250 may be attached to the circuit board 300 using a chip on film (COF) method.

[0070] The circuit board 300 may be attached to one end of the sub-area SBA of the display panel 100. Thus, the circuit board 300 may be electrically connected to the display panel 100 and the display driving circuit 250. The display panel 100 and the display driving circuit 250 may receive digital video data, timing signals, and driving voltages through the circuit board 300. The circuit board 300 may be a flexible printed circuit board (FPCB), a rigid printed circuit board (PCB), or a flexible film such as a chip on film (COF).

[0071] The power circuit 500 (e.g., a power supply unit) may generate and / or supply a plurality of panel driving voltages according to an external power supply voltage. The power circuit 500 may be formed as an integrated circuit (IC) and attached to the circuit board 300 using the COF method.

[0072] Figure 2 is a layout diagram showing a display device according to one or more embodiments. Figure 2 shows the sub-area SBA as being unfolded rather than curved.

[0073] Refer to Figure 2, the display panel 100 may include a main area MA and a sub - area SBA.

[0074] The main area MA may include a display area DA for displaying an image and a non - display area NDA that is a peripheral area of the display area DA. The display area DA may occupy most of the main area MA. The display area DA may be placed at the center of the main area MA.

[0075] The display area DA may include a plurality of pixels PX for displaying an image, and each of the plurality of pixels PX may include a plurality of sub - pixels SPX. A pixel PX may be defined as a group of sub - pixels that is the smallest unit capable of representing a white gray level.

[0076] The non - display area NDA may be placed adjacent to the display area DA. The non - display area NDA may be an area outside the display area DA. The non - display area NDA may be arranged around the display area DA (e.g., surrounding the display area DA). The non - display area NDA may be an edge area of the display panel 100.

[0077] A first scan driving unit (or first scan driving part) SDC1 and a second scan driving unit (or second scan driving part) SDC2 may be provided in the non - display area NDA. The first scan driving unit SDC1 may be provided on one side (e.g., the left side) of the display panel 100, and the second scan driving unit SDC2 may be provided on the other side (e.g., the right side) of the display panel 100. However, it is not limited thereto. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may be electrically connected to the display driving circuit 250 through a scan fan - out line. Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may receive a scan control signal from the display driving circuit 250, generate a scan signal according to the scan control signal, and output the scan signal to the scan line.

[0078] The sub - area SBA may protrude from one side of the main area MA in a second direction DR2. The length of the sub - area SBA in the second direction DR2 may be less than the length of the main area MA in the second direction DR2. The length of the sub - area SBA in a first direction DR1 may be less than the length of the main area MA in the first direction DR1, or may be substantially equal to the length of the main area MA in the first direction DR1. The sub - area SBA may be curved and may be provided at the lower part of the display panel 100. In this case, the sub - area SBA may overlap the main area MA in a third direction DR3.

[0079] The sub - area SBA may include a connection area CA, a pad (or referred to as a "bond pad") area PA, and a bending area BA.

[0080] The connection area CA is an area that protrudes from one side of the main area MA in the second direction DR2. One side of the connection area CA can be in contact with the non-display area NDA of the main area MA, and the other side of the connection area CA can be in contact with the bending area BA.

[0081] The pad area PA is an area where the pads PD and the display driving circuit 250 are provided. The display driving circuit 250 can be attached to the driving pads of the pad area PA using a conductive bonding member such as an anisotropic conductive film. The circuit board 300 can be attached to the pads PD of the pad area PA using a conductive bonding member such as an anisotropic conductive film. One side of the pad area PA can be in contact with the bending area BA.

[0082] The bending area BA is a bent area. When the bending area BA is bent, the pad area PA can be arranged (for example, in the thickness direction (e.g., the third direction DR3)) below the connection area CA and below the main area MA. The bending area BA can be arranged between the connection area CA and the pad area PA. One side of the bending area BA can be in contact with the connection area CA, and the other side of the bending area BA can be in contact with the pad area PA.

[0083] The non-display power supply line NVSL can be arranged in the non-display area NDA, the connection area CA, the bending area BA, and the pad area PA.

[0084] The non-display power supply line NVSL can be arranged on four sides of the display area DA in the non-display area NDA. The non-display power supply line NVSL can be arranged to surround at least three sides of the display area DA (for example, around at least three sides of the display area DA). For example, the non-display power supply line NVSL can surround the left side, the top side, and the right side of the display area DA (for example, can surround the left side, the top side, and the right side of the display area DA), and can be arranged on at least a part of the lower side. In addition, the non-display power supply line NVSL can be arranged outside the first scan driving unit SDC1 and outside the second scan driving unit SDC2. For example, the non-display power supply line NVSL can be arranged on the left side of the first scan driving unit SDC1 and on the right side of the second scan driving unit SDC2. The non-display power supply line NVSL can be arranged at the edge of the first scan driving unit SDC1 and the substrate SUB and at the edge of the second scan driving unit SDC2 and the substrate SUB. Optionally, the non-display power supply line NVSL can be stacked with the first scan driving unit SDC1 and the second scan driving unit SDC2.

[0085] The non-display power supply line NVSL can be disposed at left and right edges of the connection area CA and the bending area BA. The non-display power supply line NVSL can be connected to the pads PD adjacent to one side edge and the pads PD adjacent to the other side edge among the pads PD in the pad area PA. The non-display power supply line NVSL can receive a second driving voltage VSS from a power supply circuit 500 disposed on the circuit board 300.

[0086] Figure 3 is a block diagram showing a display device according to one or more embodiments.

[0087] Referring to Figure 3 , the display area DA can include a plurality of pixels PX, a plurality of scan lines SL, a plurality of emission control lines EL, and a plurality of data lines DL. According to one or more embodiments, each of the plurality of pixels PX includes a plurality of sub-pixels SPX.

[0088] The plurality of pixels PX can be arranged in a matrix form in a first direction DR1 and a second direction DR2. For example, the plurality of pixels PX can be arranged along rows and columns of the matrix in the first direction DR1 and the second direction DR2. The plurality of scan lines SL and the plurality of emission control lines EL can extend in the first direction DR1 and can be arranged along the second direction DR2. The plurality of data lines DL can extend in the second direction DR2 and can be arranged along the first direction DR1. The plurality of scan lines SL can include a plurality of write scan lines GWL, a plurality of control scan lines GCL, a plurality of initialization scan lines GIL, and a plurality of bias scan lines GBL.

[0089] Each of the plurality of sub-pixels SPX can be connected to a write scan line GWL among the plurality of write scan lines GWL, a control scan line GCL among the plurality of control scan lines GCL, an initialization scan line GIL among the plurality of initialization scan lines GIL, a bias scan line GBL among the plurality of bias scan lines GBL, an emission control line EL among the plurality of emission control lines EL, and a data line DL among the plurality of data lines DL. Each of the plurality of sub-pixels SPX can be supplied with a data voltage of the data line DL according to a write scan signal of the write scan line GWL, and can cause a light-emitting element to emit light according to the data voltage.

[0090] The non-display area NDA includes a first scan driving unit SDC1, a second scan driving unit SDC2, and a display driving circuit 250.

[0091] Each of the first scan driving unit SDC1 and the second scan driving unit SDC2 may include a write scan signal output unit 611, a control scan signal output unit 612, an initialization scan signal output unit 613, a bias scan signal output unit 614, and a light emission signal output unit 615. Each of the write scan signal output unit 611, the control scan signal output unit 612, the initialization scan signal output unit 613, the bias scan signal output unit 614, and the light emission signal output unit 615 may receive a scan timing control signal SCS from a timing control circuit (or a timing controller) 251. The write scan signal output unit 611 may generate write scan signals according to the scan timing control signal SCS of the timing control circuit 251, and sequentially output them to the write scan lines GWL. The control scan signal output unit 612 may generate control scan signals according to the scan timing control signal SCS, and sequentially output them to the control scan lines GCL. The initialization scan signal output unit 613 may generate initialization scan signals according to the scan timing control signal SCS, and sequentially output them to the initialization scan lines GIL. The bias scan signal output unit 614 may generate bias scan signals according to the scan timing control signal SCS, and sequentially output them to the bias scan lines GBL. The light emission signal output unit 615 may generate light emission control signals according to the scan timing control signal SCS, and sequentially output them to the emission control lines EL.

[0092] The display driving circuit 250 includes a timing control circuit 251 and a data driving circuit (or a data driver) 252.

[0093] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251. The data driving circuit 252 converts the digital video data DATA into analog data voltages according to the data timing control signal DCS, and outputs them to the data lines DL. In this case, the sub-pixels SPX are selected by the write scan signals of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the data voltages may be supplied to the selected sub-pixels SPX.

[0094] The timing control circuit 251 may receive digital video data DATA and a timing signal from an external source. The timing control circuit 251 may generate a scan timing control signal SCS and a data timing control signal DCS according to the timing signal to control the display panel 100. The timing control circuit 251 may output the scan timing control signal SCS to the first scan driving unit SDC1 and the second scan driving unit SDC2. The timing control circuit 251 may output the digital video data DATA and the data timing control signal DCS to the data driving circuit 252.

[0095] The data driving circuit 252 may receive digital video data DATA and a data timing control signal DCS from the timing control circuit 251.

[0096] The data driving circuit 252 may supply corresponding data signals (e.g., analog data voltages) to the sub-pixels SPX. For example, the data driving circuit 252 may convert the digital video data DATA into analog data voltages according to the data timing control signal DCS, and output them to the data lines DL. The sub-pixels SPX may be selected by the write scan signals of the first scan driving unit SDC1 and the second scan driving unit SDC2, and the data signals may be supplied to the selected sub-pixels SPX.

[0097] The power supply circuit 500 may generate a plurality of panel driving voltages according to an external power supply voltage. For example, the power supply circuit 500 may generate a first driving voltage VDD, a second driving voltage VSS, and a third driving voltage VINT, and may supply the first driving voltage VDD, the second driving voltage VSS, and the third driving voltage VINT to the display panel 100.

[0098] Figure 4 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0099] Referring to Figure 4 , the sub-pixel SPX according to one or more embodiments may be connected to scan lines GWL, GIL, GCL, and GBL, an emission control line EL, and a data line DL. For example, the sub-pixel SPX may be connected to a write scan line GWL, an initialization scan line GIL, a control scan line GCL, a bias scan line GBL, an emission control line EL, and a data line DL.

[0100] The sub-pixel SPX according to one or more embodiments includes a driving transistor DT, a switching element, a capacitor C1, and a light-emitting element LE. The switching element includes a first transistor ST1, a second transistor ST2, a third transistor ST3, a fourth transistor ST4, a fifth transistor ST5, and a sixth transistor ST6. The driving transistor DT, the switching element, and the capacitor C1 may be referred to as a pixel circuit. The pixel circuit may include a driving transistor DT, at least one switching transistor ST (e.g., ST1, ST2, ST3, ST4, ST5, and ST6), and a capacitor C1. In one or more embodiments, the pixel circuit may include the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 as the switching transistor ST. The configuration of the pixel circuit is not limited to Figure 4 and Figure 5 the embodiments of, and may be changed in various ways.

[0101] The driving transistor DT may include a gate electrode, a first electrode, and a second electrode. The driving transistor DT controls a drain-source current (e.g., Ids, hereinafter referred to as "driving current") flowing between the first electrode and the second electrode according to a data voltage applied to the gate electrode.

[0102] The light-emitting element LE may be a micro light-emitting diode.

[0103] The light-emitting element LE emits light according to the driving current Ids. The amount of light emitted from the light-emitting element LE may be proportional to the driving current Ids. The anode electrode of the light-emitting element LE is connected to the second electrode of the fourth transistor ST4 and the second electrode of the sixth transistor ST6, and the cathode electrode may be connected to a second power supply line VSL to which a second power supply voltage is applied. A parasitic capacitance Cel may be formed between the anode electrode and the cathode electrode of the light-emitting element LE.

[0104] A capacitor C1 is formed between the gate electrode of the driving transistor DT and a first power supply line VDL to which a first power supply voltage is applied. The first power supply voltage may be at a level higher than the second power supply voltage. One electrode of the capacitor C1 may be connected to the gate electrode of the driving transistor DT, and the other electrode of the capacitor C1 may be connected to the first power supply line VDL.

[0105] As Figure 4 shown, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, and the driving transistor DT may all be formed as P-type metal-oxide-semiconductor field-effect transistors (P-type MOSFETs). In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6, and the driving transistor DT may be formed of polysilicon.

[0106] The gate electrode of the second transistor ST2 may be connected to the write scan line GWL, and the gate electrode of the first transistor ST1 may be connected to the control scan line GCL. The gate electrode of the third transistor ST3 may be connected to the initialization scan line GIL, and the gate electrode of the fourth transistor ST4 may be connected to the bias scan line GBL. The gate electrodes of the fifth transistor ST5 and the sixth transistor ST6 may be connected to the emission control line EL. Since the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, they can be turned on when a scan signal with a low gate voltage and an emission signal (e.g., a low voltage) are applied to the control scan line GCL, the initialization scan line GIL, the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively. One electrode of the third transistor ST3 and one electrode of the fourth transistor ST4 may be connected to the initialization voltage line VIL.

[0107] For example, the first transistor ST1 may be connected between the second electrode and the gate electrode of the driving transistor DT. The second transistor ST2 may be connected between the data line DL and the first electrode of the driving transistor DT. The third transistor ST3 may be connected between the initialization voltage line VIL and the gate electrode of the driving transistor DT. The fourth transistor ST4 may be connected between the initialization voltage line VIL and the light-emitting element LE. The fifth transistor ST5 may be connected between the first power supply line VDL and the first electrode of the driving transistor DT. The sixth transistor ST6 may be connected between the second electrode of the driving transistor DT and the light-emitting element LE.

[0108] Figure 5 is an equivalent circuit diagram of a sub-pixel according to one or more embodiments.

[0109] Referring to Figure 5 , the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed of P-type MOSFETs, and the first transistor ST1 and the third transistor ST3 may be formed as N-type MOSFETs. The active layer of each of the driving transistor DT, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 formed as P-type MOSFETs is formed of polysilicon, and the active layer of each of the first transistor ST1 and the third transistor ST3 formed as N-type MOSFETs is formed of an oxide semiconductor. In this case, the transistors formed of polysilicon and the transistors formed of an oxide semiconductor may be arranged in different layers.

[0110] Since the first transistor ST1 and the third transistor ST3 are formed as N-type MOSFETs, when a control scan signal with a high gate voltage is applied to the control scan line GCL, the first transistor ST1 can be turned on, and when an initialization scan signal (e.g., with a high voltage) is applied to the initialization scan line GIL, the third transistor ST3 can be turned on. In contrast, the second transistor ST2, the fourth transistor ST4, the fifth transistor ST5, and the sixth transistor ST6 are formed as P-type MOSFETs, so when scan signals with a low gate voltage and an emission signal (e.g., with a low voltage) are applied to the write scan line GWL, the bias scan line GBL, and the emission control line EL, respectively, they can be turned on.

[0111] Optionally, Figure 4 the fourth transistor ST4 in can be formed of an N-type MOSFET. In this case, the active layer of each fourth transistor ST4 can be formed of an oxide semiconductor. When the fourth transistor ST4 is formed of an N-type MOSFET, the fourth transistor ST4 can be turned on when a bias scan signal with a high gate voltage is applied to the bias scan line GBL.

[0112] In one or more embodiments, the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can all be formed as N-type MOSFETs. In this case, the active layer of each of the first transistor ST1, the second transistor ST2, the third transistor ST3, the fourth transistor ST4, the fifth transistor ST5, the sixth transistor ST6, and the driving transistor DT can be formed of an oxide semiconductor.

[0113] Figure 6 is a layout diagram showing a plurality of pixels in a display area according to one or more embodiments.

[0114] Referring to Figure 6 , each of the plurality of pixels PX in the display area DA can include a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3.

[0115] The plurality of pixels PX can be arranged in a matrix form. In each of the plurality of pixels PX, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can be arranged along a first direction DR1.

[0116] The first sub-pixel SPX1 can emit first light, the second sub-pixel SPX2 can emit second light, and the third sub-pixel SPX3 can emit third light. Here, the first light can be light in the red wavelength band, the second light can be light in the green wavelength band, and the third light can be light in the blue wavelength band. For example, the blue wavelength band can refer to the main peak wavelength of light included in the wavelength band of about 370 nm to 460 nm, the green wavelength band can refer to the main peak wavelength of light included in the wavelength band of about 480 nm to 560 nm, and the red wavelength band can refer to the main peak wavelength of light included in the wavelength band of about 600 nm to 750 nm. However, the present disclosure is not limited thereto, and each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can output any one of the first light, the second light, and the third light.

[0117] The first sub-pixel SPX1 includes a first pixel electrode PXE1, a plurality of light-emitting elements LE, and a first wavelength conversion layer QDL1. The second sub-pixel SPX2 includes a second pixel electrode PXE2, a plurality of light-emitting elements LE, and a second wavelength conversion layer QDL2. The third sub-pixel SPX3 includes a third pixel electrode PXE3, a plurality of light-emitting elements LE, and a light transmission layer TPL.

[0118] When the light-emitting elements LE of the first sub-pixel SPX1, the light-emitting elements LE of the second sub-pixel SPX2, and the light-emitting elements LE of the third sub-pixel SPX3 emit light in the blue wavelength band, the first wavelength conversion layer QDL1 and the second wavelength conversion layer QDL2 are required for wavelength conversion. However, the present disclosure is not limited thereto. When the light-emitting element LE of the first sub-pixel SPX1 emits light of a first color, the light-emitting element LE of the second sub-pixel SPX2 emits light of a second color, and the light-emitting element LE of the third sub-pixel SPX3 emits light of a third color, the first wavelength conversion layer QDL1, the second wavelength conversion layer QDL2, and the light transmission layer TPL can be omitted. Each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 can have a rectangular planar shape having a short side in a first direction DR1 and a long side in a second direction DR2. The area of the first sub-pixel SPX1, the area of the second sub-pixel SPX2, and the area of the third sub-pixel SPX3 can be set according to the light conversion efficiency of the first wavelength conversion layer QDL1 and the light conversion efficiency of the second wavelength conversion layer QDL2.

[0119] For example, as Figure 6As shown, the area of the second pixel electrode PXE2 may be larger than the area of the first pixel electrode PXE1, and the area of the first pixel electrode PXE1 may be larger than the area of the third pixel electrode PXE3. When the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the first direction DR1 are the same, the length of the second pixel electrode PXE2 in the second direction DR2 may be greater than the length of the first pixel electrode PXE1 in the second direction DR2, and the length of the first pixel electrode PXE1 in the second direction DR2 may be greater than the length of the third pixel electrode PXE3 in the second direction DR2. However, the present disclosure is not limited thereto, and the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the first direction DR1 may be the same, and the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the second direction DR2 may be different. Optionally, the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the second direction DR2 may be the same, and the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the first direction DR1 may be different. Optionally, the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the first direction DR1, the lengths of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 in the second direction DR2 may be the same. Optionally, any two of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 may have the same lengths in the first direction DR1 and the second direction DR2, and the remaining one of the pixel electrodes may have lengths in the first direction DR1 and the second direction DR2 different from those of any two of the pixel electrodes in the first direction DR1 and the second direction DR2.

[0120] The first pixel electrode PXE1 may be electrically connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 ST4 therein) of the first sub-pixel SPX1 and the second electrode of the sixth transistor ( Figure 4 and Figure 5The second electrode of ST6) in. The second pixel electrode PXE2 can be electrically connected to the fourth transistor of the second sub-pixel SPX2 through the second connection hole CT2 ( Figure 4 and Figure 5 The second electrode of ST4) in and the sixth transistor ( Figure 4 and Figure 5 The second electrode of ST6) in. The third pixel electrode PXE3 can be electrically connected to the fourth transistor of the third sub-pixel SPX3 through the third connection hole CT3 ( Figure 4 and Figure 5 The second electrode of ST4) in and the sixth transistor ( Figure 4 and Figure 5 The second electrode of ST6) in.

[0121] A plurality of light-emitting elements LE can be provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The same number of light-emitting elements LE can be provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. For example, two light-emitting elements LE can be provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The plurality of light-emitting elements LE can emit third light, that is, light in the blue wavelength band.

[0122] However, the present disclosure is not limited thereto, and one light-emitting element LE can be provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3, or two or more light-emitting elements LE (such as three light-emitting elements LE or four light-emitting elements LE) can be provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. When two or more light-emitting elements LE are provided on each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3, even if a contact defect occurs between one light-emitting element LE and the pixel electrode, the remaining light-emitting elements LE can emit light by contacting the pixel electrode, and thus, it has the advantage of not requiring repair.

[0123] The first light conversion layer QDL1 can be completely stacked with the first pixel electrode PXE1 of the first sub-pixel SPX1 and the plurality of light-emitting elements LE. The area of the first light conversion layer QDL1 can be larger than the area of the first pixel electrode PXE1. The first light conversion layer QDL1 can convert the peak wavelength of the incident light into or shift it to light of another specific peak wavelength and emit the light. For example, the first light conversion layer QDL1 can convert the third light emitted from the plurality of light-emitting elements LE of the first sub-pixel SPX1 into or shift it to the first light.

[0124] The second light conversion layer QDL2 can be completely superimposed on the second pixel electrode PXE2 and the plurality of light-emitting elements LE of the second sub-pixel SPX2. The area of the second light conversion layer QDL2 can be larger than the area of the second pixel electrode PXE2. The second light conversion layer QDL2 can convert the peak wavelength of incident light into or shift it to light of another specific peak wavelength and emit the light. For example, the second light conversion layer QDL2 can convert the third light emitted from the plurality of light-emitting elements LE of the second sub-pixel SPX2 into or shift it to the second light.

[0125] The light transmission layer TPL can be completely superimposed on the third pixel electrode PXE3 and the plurality of light-emitting elements LE of the third sub-pixel SPX3. The light transmission layer TPL can transmit incident light as it is. For example, the light transmission layer TPL can directly transmit the third light emitted from the plurality of light-emitting elements LE of the third sub-pixel SPX3.

[0126] Figure 7 is a cross-sectional view corresponding to the line I1-I1' of the display panel Figure 6 of. Figure 8A and Figure 8B is a cross-sectional view showing in detail Figure 7 an example of the region A of.

[0127] Referring to Figure 7 , Figure 8A and Figure 8B , the substrate SUB can be made of an insulating material such as glass, polymer resin, etc. If the substrate SUB is made of a polymer resin, it can be a flexible substrate that can be stretched. The polymer resin can be an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0128] The barrier film BR can be provided on the substrate SUB. The barrier film BR is a film for protecting the transistors of the thin film transistor layer TFTL and the light-emitting elements LE of the light-emitting element layer EML from moisture that penetrates through the substrate SUB (the substrate SUB is vulnerable to moisture penetration). The barrier film BR can be composed of a plurality of inorganic films stacked alternately. For example, the barrier film BR can be formed as a multi-layer of an alternating inorganic film of one or more of a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, and / or an aluminum oxide layer.

[0129] The first thin film transistor TFT1 can be provided on the barrier film BR. The first thin film transistor TFT1 can be Figure 5 either the fourth transistor ST4 or the sixth transistor ST6 shown in. The first thin film transistor TFT1 can include a first active layer ACT1 and a first gate electrode G1.

[0130] The first active layer ACT1 of the first thin film transistor TFT1 may be disposed on the barrier film BR. The first active layer ACT1 of the first thin film transistor TFT1 may include polysilicon, single crystal silicon, low temperature polysilicon, and / or amorphous silicon.

[0131] The first active layer ACT1 may include a first channel region CHA1, a first source region S1, and a first drain region D1. The first channel region CHA1 may be a region that overlaps with the first gate electrode G1 in a third direction DR3 in the thickness direction of the substrate SUB. The first source region S1 may be disposed on one side of the first channel region CHA1, and the first drain region D1 may be disposed on the other side of the first channel region CHA1. The first source region S1 and the first drain region D1 may be regions that do not overlap with the first gate electrode G1 in the third direction DR3. The first source region S1 and the first drain region D1 may be regions in which silicon semiconductor is doped with ions to make it conductive.

[0132] The first gate insulating film 131 may be disposed on the first channel region CHA1, the first source region S1, the first drain region D1 of the first thin film transistor TFT1, and the barrier film BR. The first gate insulating film 131 may be formed of an inorganic film (e.g., a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0133] The first gate metal layer GTL1 may be disposed on the first gate insulating film 131. The first gate metal layer GTL1 may include the first gate electrode G1 and the first capacitor electrode CAE1 of the first thin film transistor TFT1. The first gate electrode G1 may overlap with the first active layer ACT1 in the third direction DR3. In Figure 7 the first gate electrode G1 and the first capacitor electrode CAE1 are shown as being separated from each other (e.g., being spaced apart from each other), but the first gate electrode G1 and the first capacitor electrode CAE1 may be connected to each other. The first gate metal layer GTL1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys.

[0134] The second gate insulating film 132 may be disposed on the first gate electrode G1, the first capacitor electrode CAE1, and the first gate insulating film 131 of the first thin film transistor TFT1. The second gate insulating film 132 may be formed of an inorganic film (e.g., a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0135] The second gate metal layer GTL2 may be disposed on the second gate insulating film 132. The second gate metal layer GTL2 may include a second capacitor electrode CAE2. The second capacitor electrode CAE2 may be stacked with the first capacitor electrode CAE1 in the third direction DR3. Since the second gate insulating film 132 has a suitable dielectric constant (e.g., a predetermined dielectric constant), the capacitor ( Figure 5 C1 in) may be formed by the first capacitor electrode CAE1, the second capacitor electrode CAE2, and the second gate insulating film 132 disposed therebetween. The second gate metal layer GTL2 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys.

[0136] The first interlayer insulating film 141 may be disposed on the second capacitor electrode CAE2 and the second gate insulating film 132. The first interlayer insulating film 141 may be formed of an inorganic film (such as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0137] The second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second thin film transistor TFT2 may be Figure 5 either the first transistor ST1 or the third transistor ST3 shown in. The second thin film transistor TFT2 may include a second active layer ACT2 and a second gate electrode G2.

[0138] The second active layer ACT2 of the second thin film transistor TFT2 may be disposed on the first interlayer insulating film 141. The second active layer ACT2 may include an oxide semiconductor. For example, the second active layer ACT2 may include IGZO (indium (In), gallium (Ga), zinc (Zn), and oxygen (O)), IGZTO (indium (In), gallium (Ga), zinc (Zn), tin (Sn), and oxygen (O)), and / or IGTO (indium (In), gallium (Ga), tin (Sn), and oxygen (O)).

[0139] The second active layer ACT2 may include a second channel region CHA2, a second source region S2, and a second drain region D2. The second channel region CHA2 may be a region stacked with the second gate electrode G2 in the third direction DR3. The second source region S2 may be disposed on one side of the second channel region CHA2, and the second drain region D2 may be disposed on the other side of the second channel region CHA2. The second source region S2 and the second drain region D2 may be regions that are not stacked with the second gate electrode G2 in the third direction DR3. The second source region S2 and the second drain region D2 may be regions in which the oxide semiconductor is doped with ions to make it conductive.

[0140] The third gate insulating film 133 may be disposed on the second active layer ACT2 of the second thin film transistor TFT2 and the first interlayer insulating film 141. The third gate insulating film 133 may be formed of an inorganic film (e.g., a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0141] The third gate metal layer GTL3 may be disposed on the third gate insulating film 133. The third gate metal layer GTL3 may include the second gate electrode G2 of the second thin film transistor TFT2. The second gate electrode G2 may be stacked with the second active layer ACT2 in the third direction DR3. The third gate metal layer GTL3 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys.

[0142] The second interlayer insulating film 142 may be disposed on the second gate electrode G2 of the second thin film transistor TFT2 and the third gate insulating film 133. The second interlayer insulating film 142 may be formed of an inorganic film (e.g., a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0143] The first data metal layer DTL1 may be disposed on the second interlayer insulating film 142. The first data metal layer DTL1 may include a first source connection electrode SBE3, a second source connection electrode SBE1, and a third source connection electrode SBE2. The first source connection electrode SBE3 may be connected to the first drain region D1 of the first active layer ACT1 through a first source contact hole PCT1 that penetrates the first gate insulating film 131, the second gate insulating film 132, the first interlayer insulating film 141, the third gate insulating film 133, and the second interlayer insulating film 142. The second source connection electrode SBE1 may be connected to the second source region S2 of the second active layer ACT2 through a second source connection contact hole BCT1 that penetrates the second interlayer insulating film 142 and the third gate insulating film 133. The third source connection electrode SBE2 may be connected to the second drain region D2 of the second active layer ACT2 through a third source connection contact hole BCT2 that penetrates the second interlayer insulating film 142 and the third gate insulating film 133. The first data metal layer DTL1 may be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. For example, the first data metal layer DTL1 may include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0144] The first organic film 160 can be disposed on the first source connection electrode SBE3, the second source connection electrode SBE1, and the third source connection electrode SBE2, and on the second interlayer insulating film 142 to planarize the steps caused by the first thin film transistor TFT1 and the second thin film transistor TFT2. The first organic film 160 can be formed of an organic film (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.).

[0145] The second data metal layer DTL2 can be disposed on the first organic film 160. The second data metal layer DTL2 can include a fourth source connection electrode SBE4. The fourth source connection electrode SBE4 can be connected to the first source connection electrode SBE3 through a second pixel contact hole PCT2 that penetrates the first organic film 160. The second data metal layer DTL2 can be formed as a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. For example, the second data metal layer DTL2 can include a first layer made of titanium (Ti), a second layer made of aluminum (Al), and a third layer made of titanium (Ti).

[0146] The second organic film 180 can be disposed on the fourth source connection electrode SBE4 and the first organic film 160. The second organic film 180 can be formed of an organic film (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.).

[0147] The light emitting element layer EML can be disposed on the second organic film 180. The light emitting element layer EML can include pixel electrodes PXE1, PXE2, and PXE3, a light emitting element LE, a common electrode CE, a connection electrode BE, and a bank 190.

[0148] The pixel electrode layer PXL can be disposed on the second organic film 180. The pixel electrode layer PXL can include a first pixel electrode PXE1, a second pixel electrode PXE2, and a third pixel electrode PXE3. In the first sub-pixel SPX1, the first pixel electrode PXE1 can be connected to the fourth source connection electrode SBE4 through a first connection hole ( Figure 6 CT1 in) that penetrates the second organic film 180. In the second sub-pixel SPX2, the second pixel electrode PXE2 can be connected to the fourth source connection electrode SBE4 through a second connection hole ( Figure 6 CT2 in) that penetrates the second organic film 180. In the third sub-pixel SPX3, the third pixel electrode PXE3 can be connected to the fourth source connection electrode SBE4 through a third connection hole ( Figure 6 CT3 in) that penetrates the second organic film 180.

[0149] In the first sub-pixel SPX1, the first pixel electrode PXE1 can be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, the voltage controlled by the first thin film transistor TFT1 in the first sub-pixel SPX1 can be applied to the first pixel electrode PXE1.

[0150] In addition, in the second sub-pixel SPX2, the second pixel electrode PXE2 can be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, the voltage controlled by the first thin film transistor TFT1 in the second sub-pixel SPX2 can be applied to the second pixel electrode PXE2.

[0151] Furthermore, in the third sub-pixel SPX3, the third pixel electrode PXE3 can be connected to the first source region S1 or the first drain region D1 of the first thin film transistor TFT1 through the first source connection electrode SBE3 and the fourth source connection electrode SBE4. Therefore, the voltage controlled by the first thin film transistor TFT1 in the third sub-pixel SPX3 can be applied to the third pixel electrode PXE3.

[0152] The pixel electrode layer PXL can be formed of a single layer or multiple layers of molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu) and / or their alloys. For example, the pixel electrode layer PXL can be formed of multiple layers of copper (Cu) having a low surface resistance to reduce the resistance of each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3, and an alloy of titanium (Ti) and copper (Cu).

[0153] The bank 190 can be provided between the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. The bank 190 can be formed of an organic film (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.). The bank 190 can include a light-blocking material to prevent light from the light-emitting element LE of one sub-pixel from traveling to an adjacent sub-pixel. For example, the bank 190 can include an inorganic black pigment such as carbon black or an organic black pigment.

[0154] A plurality of light-emitting elements LE can be provided on the pixel electrode layer PXL. Figure 7It shows that each of the plurality of light-emitting elements LE is a vertical micro-LED extending in the third direction DR3. That is, the length of the light-emitting element LE in the third direction DR3 can be greater than the length in the horizontal direction. The length in the horizontal direction refers to the length in the first direction DR1 and / or the length in the second direction DR2. For example, the length of the light-emitting element LE in the third direction DR3 can be in the range of about 5 μm to 5.5 μm, but is not limited thereto. However, the present disclosure is not limited thereto, and in one or more other embodiments, the length of the light-emitting element LE in the third direction DR3 can be equal to or less than the length in the horizontal direction.

[0155] The light-emitting element LE can have a cylindrical shape, a disk shape, or a rod shape with a width longer than the height. However, it is not limited thereto, and the light-emitting element LE can have a shape such as a rod, a wire, or a tube, a polyhedral shape such as a cube, a cuboid, or a hexagonal prism, or a shape extending in one direction but having a partially inclined outer surface.

[0156] Each of the plurality of light-emitting elements LE can be formed of an inorganic material such as gallium nitride (GaN). Each of the plurality of light-emitting elements LE can have a length of several micrometers to several hundred micrometers in the first direction DR1, a length of several micrometers to several hundred micrometers in the second direction DR2, and a length of several micrometers to several hundred micrometers in the third direction DR3. For example, each of the plurality of light-emitting elements LE can have a length in the first direction DR1, a length in the second direction DR2, and a length in the third direction DR3 of about 100 μm or less.

[0157] Each of the plurality of light-emitting elements LE can be formed by growing on a semiconductor substrate such as a silicon substrate and / or a sapphire substrate. The plurality of light-emitting elements LE can be directly transferred from the semiconductor substrate to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100. Alternatively, the plurality of light-emitting elements LE can be transferred to the pixel electrodes PXE1, PXE2, and PXE3 of the display panel 100 by an electrostatic method using an electrostatic head or an imprint method using an elastic polymer material such as PDMS and / or silicone as a transfer substrate.

[0158] The light-emitting element LE can include a contact electrode CTE, a first semiconductor layer SEM1, a multi-quantum well active layer MQW, a second semiconductor layer SEM2, a third semiconductor layer SEM3, and a protective layer INL. A vertical micro-LED refers to an LED having a structure in which the first semiconductor layer SEM1, the multi-quantum well active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3 are sequentially arranged in the third direction DR3 as the vertical direction.

[0159] The contact electrode CTE can be disposed on the pixel electrode layer PXL. The contact electrode CTE can be disposed on the entire lower surface of the first semiconductor layer SEM1 and at least a part of the side surface of the light-emitting element LE. In addition, the contact electrode CTE can be disposed on the protective layer INL which is disposed on the side surface of the light-emitting element LE. The contact electrode CTE can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0160] The contact electrode CTE can be electrically connected to the first semiconductor layer SEM1.

[0161] The first semiconductor layer SEM1 can be disposed on the contact electrode CTE. The length of the bottom surface of the first semiconductor layer SEM1 in the first direction DR1 or in the second direction DR2 can be less than the length of the contact electrode CTE in the first direction DR1 or in the second direction DR2. The first semiconductor layer SEM1 can be made of GaN doped with a first-conductivity-type dopant such as Mg, Zn, Ca, Sr, Ba, etc.

[0162] The active layer MQW can be disposed on the first semiconductor layer SEM1. The active layer MQW can emit light by recombining electron-hole pairs according to an electrical signal applied through the first semiconductor layer SEM1 and the second semiconductor layer SEM2.

[0163] The active layer MQW can include a material having a single quantum well structure or a multi-quantum well structure. When the active layer MQW includes a material having a multi-quantum well structure, the active layer MQW can have a structure in which a plurality of well layers and barrier layers are alternately stacked. In this case, the well layer can be formed of InGaN, and the barrier layer can be formed of GaN or AlGaN, but is not limited thereto. Optionally, the active layer MQW can have a structure in which a semiconductor material having a high energy bandgap and a semiconductor material having a low energy bandgap are alternately stacked with each other, and can include other group III-V semiconductor materials according to the wavelength range of the emitted light.

[0164] When the active layer MQW includes InGaN, the color of the emitted light can vary according to the content of indium (In). For example, as the content of indium (In) increases, the wavelength band of the light emitted by the active layer can shift to the red wavelength band, and as the content of indium (In) decreases, the wavelength band of the light emitted by the active layer can shift to the blue wavelength band. For example, the content of indium (In) in the active layer MQW of the light-emitting element LE that emits the third light (e.g., light in the blue wavelength band) can be about 10 wt% to 20 wt%.

[0165] An electron blocking layer can be disposed between the first semiconductor layer SEM1 and the active layer MQW. The electron blocking layer can be a layer for suppressing or preventing excessive electrons from flowing into the active layer MQW. For example, the electron blocking layer can be AlGaN and / or P-AlGaN doped with p-type Mg. The electron blocking layer can be omitted. The second semiconductor layer SEM2 can be disposed on the active layer MQW. The second semiconductor layer SEM2 can be doped with a second conductive type dopant such as Si, Ge, Se, Sn, etc. For example, the second semiconductor layer SEM2 can be N-GaN doped with n-type Si.

[0166] A superlattice layer can be disposed between the active layer MQW and the second semiconductor layer SEM2. The superlattice layer can be a layer for relieving the stress between the second semiconductor layer SEM2 and the active layer MQW. For example, the superlattice layer can be formed of InGaN and / or GaN. The superlattice layer can be omitted. When the superlattice layer is disposed on the active layer MQW, the superlattice layer can be included in the first element bar LD1.

[0167] The third semiconductor layer SEM3 can be an undoped semiconductor. The third semiconductor layer SEM3 can include the same material as the second semiconductor layer SEM2, but can be a material not doped with an n-type or p-type dopant. In one or more embodiments, the third semiconductor layer SEM3 can be undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, but is not limited thereto.

[0168] In one or more embodiments, a current spreading layer can be further disposed on the first semiconductor layer SEM1. The current spreading layer can be made of a transparent conductive material (TCO) (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)) that can transmit light.

[0169] The first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 of the light emitting element LE can be referred to as the first element bar LD1.

[0170] The element bar LD can include a first element bar LD1, a second element bar LD2, and a third element bar LD3 classified according to the change of the inclination angle of the side surface.

[0171] The first element bar LD1 can include a first side wall SS1 having a first inclination angle θ1. As Figure 8A shown, the first inclination angle θ1 of the first side wall SS1 can be formed to be 90 degrees, but is not limited thereto. For example, the first inclination angle θ1 can be greater than 70 degrees and less than 90 degrees. The first inclination angle θ1 is the angle between the extension of the contact surface of the first element bar LD1 and the second element bar LD2 and the first side wall SS1 of the first element bar LD1.

[0172] The first element bar LD1 may have a height in the range of 0.3 μm to 0.5 μm, but is not limited thereto.

[0173] The height h1 of the first element bar LD1 may be the lowest among the first element bar LD1, the second element bar LD2, and the third element bar LD3. That is, the height h1 of the first element bar LD1 is less than the height h2 of the second element bar LD2 and less than the height of the third element bar LD3.

[0174] The second element bar LD2 is disposed on the first element bar LD1.

[0175] The second element bar LD2 may include a second side wall SS2 having a second inclination angle θ2. The second inclination angle θ2 of the second side wall SS2 may be greater than 60 degrees and less than or equal to 80 degrees. In addition, the second inclination angle θ2 may be less than the first inclination angle θ1. Therefore, the second side wall SS2 may be formed as a regular cone. The second element bar LD2 becomes wider toward the top (i.e., toward the third element bar LD3). The second inclination angle θ2 is the angle between the extension of the contact surface of the second element bar LD2 and the third element bar LD3 and the second side wall SS2 of the second element bar LD2.

[0176] As Figure 8A shown, the side surface of the first element bar LD1 and the side surface of the second element bar LD2 may not coincide with each other and may have a step difference, but is not limited thereto. As Figure 8B shown, the side surface of the first element bar LD1 and the side surface of the second element bar LD2 may be aligned with each other and coincide with each other.

[0177] The second element bar LD2 may include a second semiconductor layer SEM2.

[0178] The third element bar LD3 may be disposed on the second element bar LD2. The third element bar LD3 may include a third side wall SS3 having a third inclination angle θ3. As Figure 8A shown, the third inclination angle θ3 of the third side wall SS3 may be formed as 90 degrees, but is not limited thereto. For example, the third inclination angle θ3 may be greater than 70 degrees and less than 90 degrees.

[0179] The third element bar LD3 may include a part of the second semiconductor layer SEM2 and a third semiconductor layer SEM3.

[0180] The protective layer INL may be disposed on one surface and the side surface of the element bar LD. The protective layer INL may include a plurality of insulating layers INS1 and INS2 and a first reflective layer RF1.

[0181] Multiple insulating layers INS1 and INS2 may include a first insulating layer INS1 and a second insulating layer INS2.

[0182] The first insulating layer INS1 may be arranged to surround the first sidewall SS1 and the second sidewall SS2 of the element rod LD and one surface LD-B of the element rod LD (e.g., surrounding the first sidewall SS1 and the second sidewall SS2 of the element rod LD and one surface LD-B of the element rod LD). The first insulating layer INS1 may include a first opening OP1 exposing the first semiconductor layer SEM1 on one surface LD-B of the element rod LD.

[0183] The first insulating layer INS1 may be formed of an inorganic film (e.g., a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0184] The first reflective layer RF1 may include a sidewall reflective portion RF-W and a bottom reflective portion RF-B. The sidewall reflective portion RF-W is arranged to surround the first sidewall SS1 of the first element rod LD1 and the second sidewall SS2 of the second element rod LD2 on the first insulating layer INS1 (e.g., surrounding the first sidewall SS1 of the first element rod LD1 and the second sidewall SS2 of the second element rod LD2), and the bottom reflective portion RF-B is arranged on one surface LD-B of the element rod LD. The sidewall reflective portion RF-W and the bottom reflective portion RF-B of the first reflective layer RF1 may be integrally formed.

[0185] The top of the sidewall reflective portion RF-W may be formed to become thinner towards the top.

[0186] The bottom reflective portion RF-B may be formed to extend from the bottom of the sidewall reflective portion RF-W and cover one surface LD-B of the element rod LD. That is, the first reflective layer RF1 may cover one surface LD-B of the element rod LD and a part of the side surface. Optionally, the first reflective layer RF1 may cover the entire area of the element rod LD except for the other surface LD-T opposite to one surface LD-B. However, the bottom reflective portion RF-B may have a second opening OP2 that overlaps with the first opening OP1. The width of the second opening OP2 may be greater than the width of the first opening OP1.

[0187] The first reflective layer RF1 emits the light emitted from the element bar LD upward. Specifically, the second inclination angle θ2 of the second element bar LD2 provided on the top of the first element bar LD1 is formed to be smaller than the first inclination angle θ1 of the first element bar LD1, so that the light concentration efficiency toward the top can be improved. The first reflective layer RF1 can use an omnidirectional reflector (ODR), but is not limited thereto. The omnidirectional reflector (ODR) refers to a reflector that maintains a high reflectivity within a wide wavelength range and a wide incident angle range. The first reflective layer RF1 can have a reflectivity of 90% or more in the visible light range and can have a thickness of about 5 nm or more.

[0188] The height h2 of the second element bar LD2 on which the first reflective layer RF1 is provided can have a range of about 2.0 μm to 2.3 μm, but is not limited thereto. The height h2 of the second element bar LD2 on which the first reflective layer RF1 is provided can be about four times the height h1 of the first element bar LD1, but is not limited thereto.

[0189] The height of the element bar LD on which the first reflective layer RF1 is not provided can have a range of about 2.1 μm to 2.6 μm, but is not limited thereto.

[0190] The second insulating layer INS2 can be provided on the side surface of the element bar LD on the first reflective layer RF1 as an insulating layer to protect the first reflective layer RF1. The second insulating layer INS2 can be provided on one surface LD-B of the first element bar LD1. The second insulating layer INS2 can have a third opening OP3 that overlaps with the first opening OP1 and the second opening OP2. In one or more embodiments, the width of the third opening OP3 can be greater than the width of the first opening OP1 and less than the width of the second opening OP2. However, in one or more embodiments, the width of the third opening OP3 can be greater than the widths of the first opening OP1 and the second opening OP2. Therefore, the second insulating layer INS2 can be around the second opening OP2 defined by the first reflective layer RF1 (for example, can surround the second opening OP2 defined by the first reflective layer RF1). The first reflective layer RF1 can be covered by the second insulating layer INS2.

[0191] The contact electrode CTE can contact the first semiconductor layer SEM1 through the first opening OP1, the second opening OP2, and the third opening OP3 that penetrate the first insulating layer INS1, the first reflective layer RF1, and the second insulating layer INS2. The second insulating layer INS2 can be formed of aluminum oxide (Al 2 O 3 ), but is not limited thereto. For example, the second insulating layer INS2 can be formed of the same inorganic film as the first insulating layer INS1 (such as a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0192] The first reflective layer RF1 can be completely surrounded by the second insulating layer INS2 and the first insulating layer INS1. Therefore, the first reflective layer RF1 can be electrically disconnected from the element bar LD.

[0193] The connection electrode BE connects the contact electrode CTE of the light-emitting element LE to the first pixel electrode PXE1, the second pixel electrode PXE2, or the third pixel electrode PXE3. The connection electrode BE can be disposed on the top surface of the first pixel electrode PXE1, the second pixel electrode PXE2, or the third pixel electrode PXE3 where the light-emitting element LE is not provided. In addition, the connection electrode BE can be disposed on the side surface of the contact electrode CTE. Additionally, the connection electrode BE can be disposed on a part of the side surface of the light-emitting element LE. For example, the connection electrode BE can be disposed on the side surface of the first element bar LD1 of the light-emitting element LE and can be disposed on at least a part of the second element bar LD2.

[0194] The connection electrode BE can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Optionally, the connection electrode BE can be made of a transparent conductive material (TCO) (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)) that can transmit light.

[0195] When the connection electrode BE is made of a highly reflective metal material such as aluminum (Al), the light traveling in the lateral direction of the light-emitting element LE emitted from the active layer MQW of the light-emitting element LE can be reflected from the connection electrode BE and can travel in the upward direction of the light-emitting element LE. Therefore, since the light loss from the light-emitting element LE can be reduced, the light efficiency of the light-emitting element LE can be improved. The connection electrode BE can be formed as a single layer of a highly reflective metal or can be formed as a multilayer (such as titanium (Ti) / aluminum (Al) / titanium (Ti) and / or ITO / aluminum (Al) / ITO).

[0196] The third organic film 191 can be provided to cover the bank 190 and a part of the side surfaces of the plurality of light-emitting elements LE. In addition, the third organic film 191 can be provided to cover the connection electrode BE, but at least a part of the connection electrode BE can be exposed and not covered by the third organic film 191. The third organic film 191 can be formed of an organic film (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.).

[0197] The fourth organic film 192 may be disposed on the third organic film 191. The fourth organic film 192 may be disposed to cover a part of the side surface of each of the plurality of light-emitting elements LE. The fourth organic film 192 may be disposed on at least a part of the second element bar LD2 that is exposed and not covered by the third organic film 191 and at least a part of the third element bar LD3. The top surface of each of the plurality of light-emitting elements LE may be exposed without being covered by the fourth organic film 192. The fourth organic film 192 may be formed of an organic film (such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, and / or polyimide resin, etc.).

[0198] The third organic film 191 and the fourth organic film 192 are layers for flattening the steps caused by the plurality of light-emitting elements LE. When the height of the third organic film 191 is arranged to cover most of the side surface of each of the plurality of light-emitting elements LE, the fourth organic film 192 may be omitted.

[0199] The common electrode CE may be disposed on the top surface of each of the plurality of light-emitting elements LE and on the top surface of the fourth organic film 192. The common electrode CE may be a common layer commonly formed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3. The common electrode CE may be made of a transparent conductive material (TCO) (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)) that can transmit light.

[0200] In one or more embodiments, the pixel electrodes PXE (PXE1, PXE2, and PXE3) may be referred to as anode electrodes or first electrodes, and the common electrode CE may be referred to as a cathode electrode or a second electrode.

[0201] The first cover layer CAP1 may be disposed on the common electrode CE. The first cover layer CAP1 may be formed of an inorganic film (for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0202] The light-blocking layer BM, the first light-converting layer QDL1, the second light-converting layer QDL2, and the light-transmitting layer TPL may be disposed on the first cover layer CAP1. However, the present disclosure is not limited thereto, and a third light-converting layer may be provided instead of the light-transmitting layer TPL. In this case, the third light-converting layer may include a material different from that of the first light-converting layer QDL1 and the second light-converting layer QDL2. For example, the first light-converting layer QDL1 may include quantum dots that convert light in the blue wavelength band into light in the red wavelength band, the second light-converting layer QDL2 may include quantum dots that convert light in the blue wavelength band into light in the green wavelength band, and the third light-converting layer may include blue phosphors. In addition, in addition to quantum dots, each of the first light-converting layer QDL1, the second light-converting layer QDL2, and the third light-converting layer may further include a light scatterer such as titanium dioxide (TiO 2 ). In this case, the number of titanium dioxide (TiO 2 particles in the third light-converting layer may be greater than the number of titanium dioxide (TiO 2 particles in the first light-converting layer QDL1 or the number of titanium dioxide (TiO 2 particles in the second light-converting layer QDL2.

[0203] The first light-converting layer QDL1, the second light-converting layer QDL2, and the light-transmitting layer TPL may be divided by the light-blocking layer BM. Therefore, the first light-converting layer QDL1 may be disposed on the first cover layer CAP1 in the first sub-pixel SPX1, the second light-converting layer QDL2 may be disposed on the first cover layer CAP1 in the second sub-pixel SPX2, and the light-transmitting layer TPL may be disposed on the first cover layer CAP1 in the third sub-pixel SPX3. The light-blocking layer BM may be superimposed on the bank 190 in the third direction DR3 and may not be superimposed on the plurality of light-emitting elements LE.

[0204] The first light-converting layer QDL1 may convert a part of the third light (e.g., light in the blue wavelength band) incident from the light-emitting element LE into the first light (e.g., light in the red wavelength band). The first light-converting layer QDL1 may include a first matrix resin BRS1 and first wavelength-converting particles WCP1. The first matrix resin BRS1 may include a light-transmitting organic material. For example, the first matrix resin BRS1 may include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The first wavelength-converting particles WCP1 may convert a part of the third light (e.g., light in the blue wavelength band) incident from the light-emitting element LE into the first light (e.g., light in the red wavelength band). The first wavelength-converting particles WCP1 may be quantum dots (QD), quantum rods, fluorescent materials, and / or phosphorescent materials. The first light-converting layer QDL1 may further include a light scatterer such as titanium dioxide (TiO 2 ).

[0205] The second light conversion layer QDL2 can convert a part of the third light (for example, light in the blue wavelength band) incident from the light-emitting element LE into the second light (for example, light in the green wavelength band). The second light conversion layer QDL2 can include a second base resin BRS2 and second wavelength conversion particles WCP2. The second base resin BRS2 can include a light-transmissive organic material. For example, the second base resin BRS2 can include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin. The second wavelength conversion particles WCP2 can convert a part of the third light (for example, light in the blue wavelength band) incident from the light-emitting element LE into the second light (for example, light in the green wavelength band). The second wavelength conversion particles WCP2 can be quantum dots (QDs), quantum rods, fluorescent materials, and / or phosphorescent materials. The second light conversion layer QDL2 can also include a light scattering agent such as titanium dioxide (TiO 2 ).

[0206] The light-transmissive layer TPL can include a light-transmissive organic material. For example, the light-transmissive layer TPL can include an epoxy resin, an acrylic resin, a cardo resin, and / or an imide resin.

[0207] The light-blocking layer BM can include a first light-blocking layer BM1 and a second light-blocking layer BM2 stacked in sequence. The length of the first light-blocking layer BM1 in the first direction DR1 or in the second direction DR2 can be wider than the length of the second light-blocking layer BM2 in the first direction DR1 or in the second direction DR2. The length (or height) of the first light-blocking layer BM1 in the third direction DR3 can be greater than the length (or height) of the second light-blocking layer BM2 in the third direction DR3. The first light-blocking layer BM1 and the second light-blocking layer BM2 can include an organic film formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc. For example, the first light-blocking layer BM1 and the second light-blocking layer BM2 can include an inorganic black pigment such as carbon black and / or an organic black pigment.

[0208] The second cover layer CAP2 can be disposed on the first cover layer CAP1 and the light blocking layer BM. The second cover layer CAP2 can be disposed on the side surface and the top surface of the light blocking layer BM. That is to say, the second cover layer CAP2 can be disposed on the side surface of the first light blocking layer BM1 and the side surface and the top surface of the second light blocking layer BM2. The second cover layer CAP2 is used to protect the first wavelength conversion particles WCP1 of the first light conversion layer QDL1 and the second wavelength conversion particles WCP2 of the second light conversion layer QDL2 from moisture penetration. Therefore, in one or more embodiments, the second cover layer CAP2 can be arranged around the top, bottom, and sides of the first light conversion layer QDL1 and the second light conversion layer QDL2 (for example, surrounding the top, bottom, and sides of the first light conversion layer QDL1 and the second light conversion layer QDL2).

[0209] The second reflective layer RF2 can be disposed between the light blocking layer BM and the first light conversion layer QDL1, between the light blocking layer BM and the second light conversion layer QDL2, and between the light blocking layer BM and the light transmissive layer TPL. The second reflective layer RF2 can be disposed on the second cover layer CAP2 disposed on the side surfaces of the first light blocking layer BM1 and the second light blocking layer BM2. The second reflective layer RF2 is used to reflect the light traveling in the lateral direction from the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmissive layer TPL.

[0210] The second reflective layer RF2 can include a highly reflective metal material such as aluminum (Al). The thickness of the second reflective layer RF2 can be about 0.1 μm.

[0211] Optionally, the second reflective layer RF2 can include M (where M is an integer greater than or equal to 2) pairs of a first layer and a second layer having different refractive indices to be used as a distributed Bragg reflector (DBR). In this case, the M first layers and the M second layers can be alternately arranged. The first layer and the second layer can be formed of an inorganic film (for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film).

[0212] The third cover layer CAP3 can be disposed on the second cover layer CAP2, the first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmissive layer TPL. The third cover layer CAP3 can be formed of an inorganic film (for example, a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, or an aluminum oxide film). The first light conversion layer QDL1, the second light conversion layer QDL2, and the light transmissive layer TPL can be encapsulated by the first cover layer CAP1, the second cover layer CAP2, and the third cover layer CAP3. The refractive index of the third cover layer CAP3 can be lower than the refractive index of the second cover layer CAP2. In addition, the refractive index of the third cover layer CAP3 can be lower than the refractive index of the fifth organic film 193.

[0213] The fifth organic film 193 may be disposed on the third cover layer CAP3. The fifth organic film 193 may be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0214] A plurality of color filters CF1, CF2, and CF3 may be disposed on the fifth organic film 193. The plurality of color filters CF1, CF2, and CF3 may include a first color filter CF1, a second color filter CF2, and a third color filter CF3. However, the present disclosure is not limited thereto. When the light-emitting element LE of the first sub-pixel SPX1 emits light of a first color, the light-emitting element LE of the second sub-pixel SPX2 emits light of a second color, and the light-emitting element LE of the third sub-pixel SPX3 emits light of a third color, the first light conversion layer QDL1, the second light conversion layer QDL2, the light transmission layer TPL, and the light blocking layer BM may be omitted, the fifth organic film 193 is disposed on the common electrode CE, and the plurality of color filters CF1, CF2, and CF3 are disposed on the fifth organic film 193, or the plurality of color filters CF1, CF2, and CF3 may be omitted.

[0215] The first color filter CF1 disposed in the first sub-pixel SPX1 may transmit first light (e.g., light in a red wavelength band) and absorb or block third light (e.g., light in a blue wavelength band). Accordingly, the first color filter CF1 may transmit the first light (e.g., light in a red wavelength band) converted by the first light conversion layer QDL1 among the third light (e.g., light in a blue wavelength band) emitted by the light-emitting element LE, and absorb or block the third light (e.g., light in a blue wavelength band) not converted by the first light conversion layer QDL1. Accordingly, the first sub-pixel SPX1 may emit first light (e.g., light in a red wavelength band).

[0216] The second color filter CF2 disposed in the second sub-pixel SPX2 may transmit second light (e.g., light in a green wavelength band) and absorb or block third light (e.g., light in a blue wavelength band). Accordingly, the second color filter CF2 may transmit the second light (e.g., light in a green wavelength band) converted by the second light conversion layer QDL2 among the third light (e.g., light in a blue wavelength band) emitted by the light-emitting element LE, and absorb or block the third light (e.g., light in a blue wavelength band) not converted by the second light conversion layer QDL2. Accordingly, the second sub-pixel SPX2 may emit second light (e.g., light in a green wavelength band).

[0217] The third color filter CF3 disposed in the third sub-pixel SPX3 can transmit third light (e.g., light in the blue wavelength band). Thus, the third color filter CF3 can cause the third light (e.g., light in the blue wavelength band) that is emitted from the light-emitting element LE and passes through the light-transmitting layer TPL to be transmitted. Accordingly, the third sub-pixel SPX3 can emit the third light (e.g., light in the blue wavelength band).

[0218] Each of the first color filter CF1, the second color filter CF2, and the third color filter CF3 is configured to block external light incident from the outside. For example, the first color filter CF1 disposed in the first sub-pixel SPX1 can block the second light as light in the green wavelength band and the third light as light in the blue wavelength band incident from the outside, thereby increasing the purity (color purity) of the color corresponding to the first light as light in the red wavelength band.

[0219] The first color filter CF1, the second color filter CF2, and the third color filter CF3 stacked in the third direction DR3 can be stacked with the bank 190 and the light-blocking layer BM in the third direction DR3.

[0220] The sixth organic film 194 for planarization can be disposed on the plurality of color filters CF1, CF2, and CF3. The sixth organic film 194 can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, or the like.

[0221] According to Figure 7 、 Figure 8A and Figure 8B , the light-emitting element LE includes a first element bar LD1 having a first tilt angle θ1, a second element bar LD2 having a second tilt angle θ2, and a third element bar LD3 having a third tilt angle θ3. As a result, it is possible to ensure a sufficient width of the active layer to accommodate the chip size while reducing or minimizing damage to the active layer during the process. This effect will be explained again in the process description to be described later.

[0222] In addition, by adopting a protective layer INL having a structure in which a first insulating layer INS1, a first reflective layer RF1, and a second insulating layer INS2 are disposed on the side surface of the light-emitting element LE, the light emitted from the side surface of the light-emitting element LE is guided upward, but the first reflective layer RF1 is formed to be surrounded by an insulator so that the first reflective layer RF1 can be protected during subsequent processes.

[0223] Furthermore, since the contact electrode CTE is disposed on the protective layer INL disposed on the side surface of the first semiconductor layer SEM1, the contact area between the contact electrode CTE and the connection electrode BE can be increased. Accordingly, the contact resistance between the contact electrode CTE and the connection electrode BE can be reduced, and the contact electrode CTE and the connection electrode BE can be connected more stably.

[0224] Figure 9 Another cross-sectional view showing in detail Figure 7 region A.

[0225] Figure 9 The embodiment of Figure 8A and Figure 8B differs from the embodiment of Figure 9 in that an organic pattern layer BOL is provided between the pixel electrode PXE and the light-emitting element LE, and in the embodiment of Figure 8A and Figure 8B the description that duplicates the embodiment of

[0226] Referring to Figure 9 the organic pattern layer BOL is provided on the pixel electrode PXE, and the light-emitting element LE is provided on the organic pattern layer BOL.

[0227] The organic pattern layer BOL is used to temporarily fix or attach a plurality of light-emitting elements LE to prevent the plurality of light-emitting elements LE from tilting or falling during the process of transferring the plurality of light-emitting elements LE to the display panel 100. That is to say, the organic pattern layer BOL can be a diaphragm for temporarily attaching the plurality of light-emitting elements LE to each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. For the convenience of temporary attachment, the thickness of the organic pattern layer BOL can be greater than the thickness of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0228] After the transfer process of the light-emitting element LE is completed, the organic pattern layer BOL can be cured to form a robust bond between the light-emitting element LE and the organic pattern layer BOL. Different from the eutectic process as a general bonding process, the bonding process using the organic pattern layer BOL does not require heat and pressure that may damage the light-emitting element LE, so it has the effect of preventing defects from occurring in the light-emitting element LE.

[0229] The organic pattern layer BOL can include an insulating material without electrical connection. In addition, the organic pattern layer BOL can be a photosensitive organic layer such as a photoresist. Optionally, the organic pattern layer BOL can be formed of an acrylic resin, an epoxy resin, a phenolic resin, a polyamide resin, a polyimide resin, etc.

[0230] The light-emitting element LE can be provided on the organic pattern layer BOL.

[0231] The organic pattern layer BOL can be set to be narrower or wider than the light-emitting element LE, but at least a part of the pixel electrode PXE should be exposed. The connection electrode BE can be provided on the side of the organic pattern layer BOL and the light-emitting element LE and the exposed pixel electrode PXE. The connection electrode BE electrically connects the pixel electrode PXE and the contact electrode CTE.

[0232] Figure 10 is a cross-sectional view showing another example of region A in detail Figure 7 of the region A

[0233] Figure 10 The embodiment of Figure 8A and Figure 8B differs from the embodiments of Figure 10 in that the connection electrode BE is provided between the contact electrode CTE and the first pixel electrode PXE1, and in the embodiment of Figure 8A and Figure 8B the description that is repeated with the embodiments of

[0234] Referring to Figure 10 the light-emitting element LE and the first pixel electrode PXE1 can be joined by electrostatic bonding. Accordingly, the connection electrode BE can be provided between the contact electrode CTE and the first pixel electrode PXE1

[0235] Figure 11 is a cross-sectional view showing another example of region A in detail Figure 7 of the region A

[0236] Figure 11 The embodiment of Figure 8A and Figure 8B differs from the embodiments of Figure 11 in that the protective layer INL is composed of the first insulating layer INS1, and in the embodiment of Figure 8A and Figure 8B the description that is repeated with the embodiments of

[0237] Referring to Figure 11 the protective layer INL can include the first insulating layer INS1

[0238] The first insulating layer INS1 can be around one surface and side surfaces of the first element bar LD1, side surfaces of the second element bar LD2, and side surfaces of the third element bar LD3 (e.g., around one surface and side surfaces of the first element bar LD1, side surfaces of the second element bar LD2, and side surfaces of the third element bar LD3). The first insulating layer INS1 has a first opening OP1 penetrating the first insulating layer INS1 on one surface of the first element bar LD1. One surface of the first element bar LD1 can be exposed through the first opening OP1

[0239] The contact electrode CTE can be provided on the first insulating layer INS1 on the first element bar LD1 and the second element bar LE2. In one or more embodiments, the contact electrode CTE can be implemented to be provided only on the first element bar LD1 on the first insulating layer INS1

[0240] The contact electrode CTE can be electrically connected to the first element bar LD1 exposed through the first opening OP1.

[0241] The connection electrode BE can be disposed on one side of the first pixel electrode PXE1 and can be disposed on the side surface of the light-emitting element LE along the contact electrode CTE.

[0242] As Figure 11 shown, when the first reflective layer RF1 and the second insulating layer INS2 are omitted, the process can be simplified.

[0243] Figure 12 is a layout diagram showing pixels in a display area according to one or more embodiments.

[0244] Figure 12 The embodiment of Figure 6 differs from the embodiment of Figure 12 in that each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 includes pixel electrodes PXE1, PXE2, and PXE3 and a common electrode CE at both ends. In Figure 6 the embodiment, the description repeated with

[0245] the embodiment will be omitted. Figure 12 Referring to

[0246] For example, as Figure 12 shown, the area of the second pixel electrode PXE2 can be larger than the area of the first pixel electrode PXE1, and the area of the first pixel electrode PXE1 can be larger than the area of the third pixel electrode PXE3. In addition, the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 can commonly include a common electrode CE.

[0247] The common electrode CE can be disposed in the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3 when the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 are not in proper positions, but is not limited thereto. In one or more embodiments, the common electrode CE can be disposed in each of the first sub-pixel SPX1, the second sub-pixel SPX2, and the third sub-pixel SPX3.

[0248] In the first sub-pixel SPX1, the first pixel electrode PXE1 and the common electrode CE can be arranged to be separated from each other (e.g., spaced apart) in the second direction DR2. In the second sub-pixel SPX2, the second pixel electrode PXE2 and the common electrode CE can be arranged to be separated from each other (e.g., spaced apart) in the second direction DR2. In the third sub-pixel SPX3, the third pixel electrode PXE3 and the common electrode CE can be arranged to be separated from each other (e.g., spaced apart) in the second direction DR2.

[0249] The first pixel electrode PXE1 can be connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 ST4 therein) and the second electrode of the sixth transistor ( Figure 4 and Figure 5 ST6 therein) in the first sub-pixel SPX1 through the first connection hole CT1. The second pixel electrode PXE2 can be connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 ST4 therein) and the second electrode of the sixth transistor ( Figure 4 and Figure 5 ST6 therein) in the second sub-pixel SPX2 through the second connection hole CT2. The third pixel electrode PXE3 can be connected to the second electrode of the fourth transistor ( Figure 4 and Figure 5 ST4 therein) and the second electrode of the sixth transistor ( Figure 4 and Figure 5 ST6 therein) in the third sub-pixel SPX3 through the third connection hole CT3.

[0250] The common electrode CE can be connected to the second power line VSL to which the second driving voltage VSS is applied through a connection hole (e.g., the fourth connection hole). Accordingly, the second driving voltage VSS can be applied to the common electrode CE.

[0251] Figure 13 is a cross-sectional view of the display panel corresponding to the line I2-I2' in Figure 12 . Figure 14 is a cross-sectional view showing in detail an example of the region B of Figure 13 .

[0252] Figure 13 and Figure 14 are different from the embodiments of Figure 7 and FIG. 8 in that the light-emitting element LE is a flip-chip type micro LED. In the embodiments of Figure 13 and Figure 14 , descriptions overlapping with the embodiments of Figure 7 and FIG. 8 will be omitted.

[0253] Referring to Figure 13 and Figure 14, the light-emitting element LE can be a flip-chip micro-LED. A flip-chip micro-LED refers to an LED in which the contact electrodes CTE1 and CTE2 are formed on one side (e.g., the bottom side) of the light-emitting element LE. In one or more embodiments, the contact electrodes CTE1 and CTE2 can also be formed on the side surfaces of the light-emitting element LE.

[0254] A pixel electrode layer PXL including pixel electrodes PXE1, PXE2, and PXE3 and a common electrode CE can be disposed on the second organic film 180.

[0255] The light-emitting element LE includes a first portion LEP1, a second portion LEP2, and a third portion LEP3. The first portion LEP1 and the second portion LEP2 can be separated from each other (e.g., spaced apart). The third portion LEP3 can be connected to the first portion LEP1 and the second portion LEP2. The third portion LEP3 can be disposed on the first portion LEP1 and the second portion LEP2.

[0256] The first portion LEP1 includes a first contact electrode CTE1, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a protective layer INL. The second portion LEP2 includes a second contact electrode CTE2, a first semiconductor layer SEM1, an active layer MQW, a second semiconductor layer SEM2, and a protective layer INL, and the third portion LEP3 includes a second semiconductor layer SEM2, a third semiconductor layer SEM3, and a protective layer INL. In one or more embodiments, the third portion LEP3 can also include the first contact electrode CTE1 and the second contact electrode CTE2.

[0257] The first semiconductor layer SEM1 can be disposed on the first contact electrode CTE1 and the second contact electrode CTE2, the active layer MQW can be disposed on the first semiconductor layer SEM1, and the second semiconductor layer SEM2 can be disposed on the active layer MQW.

[0258] The third semiconductor layer SEM3 of the third portion LEP3 can be connected to the second semiconductor layer SEM2 of the first portion LEP1 and the second semiconductor layer SEM2 of the second portion LEP2. The second semiconductor layer SEM2 of the first portion LEP1, the second semiconductor layer SEM2 of the second portion LEP2, and the third semiconductor layer SEM3 of the third portion LEP3 can be integrally formed.

[0259] The first contact electrode CTE1 can be disposed on the bottom surface and the outer surface of the first semiconductor layer SEM1. The second contact electrode CTE2 can be disposed on the bottom surface and the outer surface of the first semiconductor layer SEM1 of the second portion LEP2. In one or more embodiments, the first contact electrode CTE1 can be disposed on the outer surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. In one or more embodiments, the second contact electrode CTE2 can be disposed on the outer surfaces of the first semiconductor layer SEM1, the active layer MQW, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. The first contact electrode CTE1 and the second contact electrode CTE2 can include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu).

[0260] The protective layer INL can be disposed on the outer surface of the first portion LEP1, the outer surface of the second portion LEP2, and the side surface of the third portion LEP3. Specifically, the protective layer INL can be disposed on the outer surface of the first semiconductor layer SEM1 in the first portion LEP1, the outer surface of the active layer MQW, and the outer surface of the second semiconductor layer SEM2. In addition, the protective layer INL can be disposed on the outer surfaces of the first semiconductor layer SEM1, the active layer MQW, and the second semiconductor layer SEM2 in the second portion LEP2.

[0261] The organic pattern layer BOL can be disposed between each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3 and the common electrode CE. The organic pattern layer BOL temporarily fixes or attaches a plurality of light-emitting elements LE to prevent the plurality of light-emitting elements LE from tilting or falling during the process of transferring the plurality of light-emitting elements LE to the display panel 100. That is, the organic pattern layer BOL can be a diaphragm for temporarily attaching the plurality of light-emitting elements LE to each of the first pixel electrode PXE1, the second pixel electrode PXE2, and the third pixel electrode PXE3. For easy temporary attachment, the thickness of the organic pattern layer BOL can be greater than the thickness of each of the pixel electrodes PXE1, PXE2, and PXE3.

[0262] After the transfer process of the light-emitting element LE is completed, the organic pattern layer BOL can be cured to form a robust bond between the light-emitting element LE and the organic pattern layer BOL. Different from the eutectic process which is a general bonding process, the bonding process using the organic pattern layer BOL does not require heat and pressure that may damage the light-emitting element LE, so it has the effect of preventing defects from occurring in the light-emitting element LE.

[0263] The organic pattern layer BOL may include an insulating material without electrical connection. Additionally, the organic pattern layer BOL may be a photosensitive organic layer such as a photoresist. Optionally, the organic pattern layer BOL may be formed of acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, etc.

[0264] The light-emitting element LE may be disposed on the organic pattern layer BOL. The first contact electrode CTE1 and the second contact electrode CTE2 may be disposed on the organic pattern layer BOL.

[0265] As Figure 13 shown, the organic pattern layer BOL may be set wider than the width of the light-emitting element LE.

[0266] The first connection electrode BE1 connects the first contact electrode CTE1 and the first pixel electrode PXE1, the second pixel electrode PXE2, or the third pixel electrode PXE3. The first connection electrode BE1 may be disposed on the top surface of the first pixel electrode PXE1, the second pixel electrode PXE2, and / or the third pixel electrode PXE3 that is exposed and not covered by the organic pattern layer BOL. Additionally, the first connection electrode BE1 may be disposed on the side surface of the organic pattern layer BOL and the side surface of the first contact electrode CTE1. Further, the first connection electrode BE1 may be disposed on the outer surface of the first portion LEP1 of the light-emitting element LE and the side surface of the third portion LEP3. The first connection electrode BE1 may be disposed on a part of the protective layer INL of the light-emitting element LE.

[0267] The second connection electrode BE2 connects the second contact electrode CTE2 and the common electrode CE. The second connection electrode BE2 may be disposed on the exposed top surface of the common electrode CE that is not covered by the organic pattern layer BOL. Additionally, the second connection electrode BE2 may be disposed on the side surface of the organic pattern layer BOL and the side surface of the second contact electrode CTE2. Further, the second connection electrode BE2 may be disposed on the outer surface of the second portion LEP2 of the light-emitting element LE and the side surface of the third portion LEP3. The second connection electrode BE2 may be disposed on a part of the protective layer INL of the light-emitting element LE.

[0268] Each of the first connection electrode BE1 and the second connection electrode BE2 may include molybdenum (Mo), aluminum (Al), chromium (Cr), gold (Au), titanium (Ti), nickel (Ni), neodymium (Nd), and / or copper (Cu). Optionally, each of the first connection electrode BE1 and the second connection electrode BE2 may be formed of a transparent conductive material (TCO) (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)) that can transmit light.

[0269] When each of the first connection electrode BE1 and the second connection electrode BE2 is made of a highly reflective metal material such as aluminum (Al), light emitted from the active layer MQW of the light-emitting element LE and traveling in the lateral direction of the light-emitting element LE can be reflected from the connection electrodes BE (e.g., BE1 and BE2), and can travel in the upward direction of the light-emitting element LE. Therefore, light loss of the light-emitting element LE can be reduced, and the light efficiency of the light-emitting element LE can be improved.

[0270] Figure 15 and Figure 16 is a cross-sectional view showing another example of the region B in detail. Figure 13 of the region B.

[0271] Figure 15 and Figure 16 The embodiment of Figure 14 differs from the embodiment of Figure 15 and Figure 16 in that the organic pattern layer BOL is formed to be narrower than the light-emitting element LE, and in the embodiments of Figure 14 the description repeated with the embodiment of

[0272] will be omitted. Figure 15 and Figure 16 Referring to

[0273] Since the side surfaces of the first contact electrode CTE1 and the second contact electrode CTE2 protrude from the side surface of the organic pattern layer BOL, portions of the bottom surfaces of the first contact electrode CTE1 and the second contact electrode CTE2 can be exposed. As a result, the connection electrode BE can be provided on the side surface of the organic pattern layer BOL and on portions of the side surfaces and bottom surfaces of the first contact electrode CTE1 and the second contact electrode CTE2. In addition, the width of the organic pattern layer BOL can be smaller than the width of the bottom surface of the light-emitting element LE. Figure 15 and Figure 16 According to the embodiments of

[0274] Since the connection electrode BE also contacts portions of the bottom surfaces of the first contact electrode CTE1 and the second contact electrode CTE2, the contact area between the first contact electrode CTE1 and the second contact electrode CTE2 and the connection electrode BE can be increased. Therefore, the contact resistance between the first contact electrode CTE1 and the second contact electrode CTE2 and the connection electrode BE can be reduced, and the connection between the first contact electrode CTE1 and the second contact electrode CTE2 and the connection electrode BE can be more stable.

[0274] Therefore, as Figure 16As shown, since the contact areas between the connection electrode BE and the first contact electrode CTE1 and the second contact electrode CTE2 are sufficiently ensured, the connection electrode BE, the first contact electrode CTE1, and the second contact electrode CTE2 can be provided only on one side surface of the first element bar LD1 and the side surface of the second element bar LD2.

[0275] Figure 17 is a flowchart showing a method of manufacturing a display device according to one or more embodiments. Figures 18 to 33 is a cross-sectional view showing a method of manufacturing a display device according to one or more embodiments.

[0276] Figures 18 to 33 are respectively shown in cross-sectional views according to the formation order of the light-emitting element ( Figures 8A to 8B LE) and the structure according to the formation order of each layer of the display panel ( Figure 7 100) including the light-emitting element. Figures 18 to 33 Focusing on the formation of the light-emitting element and the light-emitting element layer ( Figure 7 EML), each of the light-emitting element and the light-emitting element layer ( Figure 7 EML) can roughly correspond to the Figure 7 cross-sectional view.

[0277] Form a plurality of semiconductor material layers SEM3L, SEM2L, MQWL, and SEM1L on the growth substrate SUB2. The plurality of semiconductor material layers grown by the epitaxial method can be formed by growing a seed crystal. Here, the method of forming the semiconductor material layer can be electron beam deposition, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma laser deposition (PLD), dual-mode thermal evaporation, sputtering, metalorganic chemical vapor deposition (MOCVD), etc., and preferably the semiconductor material layer is formed by metalorganic chemical vapor deposition (MOCVD). However, it is not limited thereto.

[0278] The precursor materials for forming the plurality of semiconductor material layers are not particularly limited within the range that can be conventionally selected to form the target materials. In one example, the precursor material may be a metal precursor containing an alkyl group such as methyl or ethyl. For example, the precursor material may be a compound such as trimethylgallium (Ga(CH 3 ) 3 ), trimethylaluminum (Al(CH 3 ) 3 ), and / or triethyl phosphate ((C 2 H 5 ) 3 PO 4 ), but is not limited thereto.

[0279] Specifically, a third semiconductor material layer SEM3L is formed on the growth substrate SUB2. Although the accompanying drawings show that the third semiconductor material layer SEM3L is further stacked, it is not limited thereto, and multiple layers can be formed. The third semiconductor material layer SEM3L can be provided to reduce the lattice constant difference between the second semiconductor material layer SEM2L and the growth substrate SUB2. In one example, the third semiconductor material layer SEM3L can include an undoped semiconductor that may not be doped with an N-type or P-type dopant. In one or more embodiments, the third semiconductor material layer SEM3L can be undoped InAlGaN, GaN, AlGaN, InGaN, AlN, and / or InN, but is not limited thereto.

[0280] The second semiconductor material layer SEM2L, the active material layer MQWL, and the first semiconductor material layer SEM1L are sequentially formed on the third semiconductor material layer SEM3L using the above method. In one or more embodiments, a superlattice material layer can be formed between the second semiconductor material layer SEM2L and the active material layer MQWL. In addition, an electron blocking material layer can be formed between the active material layer MQWL and the first semiconductor material layer SEM1L. In one or more embodiments, a current spreading layer can also be included on the first semiconductor material layer SEM1L. The current spreading layer can be made of a transparent conductive material (TCO) that can transmit light (such as indium tin oxide (ITO) and / or indium zinc oxide (IZO)).

[0281] Next, referring to Figure 19 , a first element bar LD1 (S120 in Figure 17 ) is formed by an etching process using a first mask.

[0282] For example, referring to Figure 19 , dry etching is performed on at least the first semiconductor material layer SEM1L and the active material layer MQWL of each light-emitting element using the first mask. At this time, a part of the second semiconductor layer SEM2 can be further etched.

[0283] Then, referring to Figure 20 , wet etching is performed on the first element bar LD1.

[0284] During dry etching, as the etching depth increases, the process time increases, and the plasma exposure time of the semiconductor material layer increases, which may increase the damage to the active layer. Therefore, in one or more embodiments, instead of etching the first semiconductor material layer SEM1L, the active material layer MQWL, the second semiconductor material layer SEM2L, and the third semiconductor material layer SEM3L all at once, only a portion corresponding to approximately 1 / 10 of the entire semiconductor material layer of the first semiconductor material layer SEM1L, the active material layer MQWL, and the second semiconductor material layer SEM2L is etched. Thus, the damage to the active layer can be reduced or minimized.

[0285] Next, the second semiconductor material layer SEM2L and the third semiconductor material layer SEM3L are etched using the second mask ( Figure 17 S130 in).

[0286] Refer to Figure 21 and Figure 22 , after forming the hard mask M as the second mask around the first element bar LD1 (e.g., surrounding the first element bar LD1 or masking the first element bar LD1), the patterned hard mask M is used as a mask to pattern the second semiconductor material layer SEM2L and the third semiconductor material layer SEM3L. For example, the second semiconductor material layer SEM2L and the third semiconductor material layer SEM3L can be etched by a dry etching process. The hard mask can be formed of silicon oxide (SiO x ).

[0287] The slope of the side surfaces of the second semiconductor layer SEM2 and the third semiconductor layer SEM3 can be less than the slope of the side surface of the first element bar LD1 etched by wet etching. Therefore, the width can increase from the second semiconductor layer SEM2 to the third semiconductor layer SEM3.

[0288] Next, refer to Figure 23 and Figure 24 , a first reflective layer RF1 and a first insulating layer INS1 having a second opening OP2 are formed ( Figure 17 S140 in).

[0289] First, refer to Figure 23 , a first insulating material layer INS1L is formed on the first element bar LD1, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. The first insulating material layer INS1L can be formed of an inorganic film (e.g., a silicon nitride film, a silicon oxynitride film, a silicon oxide film, a titanium oxide film, and / or an aluminum oxide film), but is not limited thereto.

[0290] Refer to Figure 24, a first reflective material layer RF1L is deposited to cover the light-emitting element LE. Then, a second opening OP2 is formed in the first reflective material layer RF1L on the top surface of the first element bar LD1 of the light-emitting element LE using a third mask. The second opening OP2 may be formed to expose the first insulating material layer INS1L by passing through the first reflective material layer RF1L on the first element bar LD1.

[0291] Next, referring to Figure 25 , the second semiconductor layer SEM2 and the third semiconductor layer SEM3 are etched using a fourth mask to form a second element bar LD2 and a third element bar LD3 ( Figure 17 S150 in). For example, in one or more embodiments, the third element bar LD3 having a third tilt angle θ3 may be formed by etching at least one side surface of at least one of the first semiconductor material layer, the second semiconductor material layer, and the third semiconductor material layer.

[0292] After forming the photoresist in the region covering the light-emitting element LE, the photoresist overlapping the opening of the fourth mask is removed to expose the region other than the region that will become the third element bar LD3, and the exposed semiconductor layer is etched to form the second element bar LD2 and the third element bar LD3. The photoresist can be removed by an ashing process.

[0293] The portion not etched due to the fourth mask becomes the third element bar LD3, and the portion of the second semiconductor layer SEM2 not etched due to the fourth mask becomes the second element bar LD2. Therefore, the widths of the second element bar LD2 and the third element bar LD3 can be wider than the width of the first element bar LD1. As a result, the width W of the light-emitting element LE can be reduced with respect to the width W MQ of the active layer MQW LE to improve the luminous efficiency. For example, the width W MQ of the active layer MQW LE with respect to the width W of the light-emitting element LE

[0294] In addition, when forming the common electrode CE on the third element bar LD3 formed by the third etching, the disconnection in the common electrode CE at the boundary of the light-emitting element can be reduced or minimized compared to when forming the common electrode on the element bar formed by the second etching.

[0295] Next, referring to Figure 26 and Figure 27 , a second insulating layer INS2 having a third opening OP3 may be formed on the first element bar LD1, the second element bar LD2, and the third element bar LD3 ( Figure 17 S160 in).

[0296] A second insulating material layer is formed on the first element bar LD1, the second semiconductor layer SEM2, and the third semiconductor layer SEM3. Then, a third opening OP3 that overlaps with the second opening OP2 is formed in the second insulating material layer on the first element bar LD1.

[0297] Next, a first opening OP1 that overlaps with the second opening OP2 and the third opening OP3 is formed in the first insulating layer INS1 on the first element bar LD1 using a fifth mask. Thus, on the first element bar LD1, the first semiconductor layer SEM1 can be exposed through the openings OP1, OP2, and OP3 that penetrate the first insulating layer INS1, the first reflective layer RF1, and the second insulating layer INS2.

[0298] Next, referring to Figure 28 , a contact electrode CTE (S170 in Figure 17 ) that is electrically connected to the first semiconductor layer SEM1 is formed on the second insulating layer INS2.

[0299] The contact electrode CTE is formed to cover the light-emitting element LE. The contact electrode CTE can be electrically connected to the first semiconductor layer SEM1 through the openings OP1, OP2, and OP3. The contact electrode CTE can be in direct contact with the first semiconductor layer SEM1 through the openings OP1, OP2, and OP3. The contact electrode CTE can include gold (Au), copper (Cu), tin (Sn), silver (Ag), aluminum (Al), and / or titanium (Ti). In another variant, when the first semiconductor layer SEM1 has a current spreading layer or the like, the contact electrode CTE can be in direct contact with the current spreading layer and can be electrically connected to the first semiconductor layer SEM1.

[0300] Then, referring to Figure 29 and Figure 30 , the light-emitting element LE is transferred onto a circuit board (S180 in Figure 17 ).

[0301] For ease of explanation, the transfer of the light-emitting element LE on the growth substrate SUB2 onto the circuit board is shown, but the light-emitting element LE on the growth substrate SUB2 can be transferred onto a relay substrate or the like multiple times and then transferred onto the circuit board. Optionally, the light-emitting element LE can be transferred onto the circuit board using a stamper or the like.

[0302] The first element bar LD1 of the light-emitting element LE is aligned to be positioned on the pixel electrode PXE. Then, the growth substrate SUB2 is separated from the light-emitting element LE and the growth substrate SUB2 is removed. For example, a laser lift-off process can be used to separate multiple light-emitting elements LE from the growth substrate SUB2.

[0303] Thereafter, referring toFigure 31 , a connection electrode BE is formed to connect the contact electrode CTE of the light-emitting element LE and the pixel electrode PXE ( Figure 17 S190 in).

[0304] For this purpose, first, a connection electrode layer covering each pixel electrode PXE and a plurality of light-emitting elements LE is formed. After forming a photoresist covering the entire connection electrode layer, the photoresist overlapping with the openings of the mask is removed to expose the connection electrode layer between each pixel electrode, and then the exposed connection electrode layer is etched to form the connection electrode BE. The photoresist can be removed by an ashing process. The connection electrode BE can be used as a bonding metal for bonding the pixel electrode PXE and the light-emitting element LE.

[0305] Next, referring to Figure 32 , a third organic film 191 can be formed by applying an organic material between a plurality of light-emitting elements LE. The third organic film 191 can fix the light-emitting element LE.

[0306] Referring to Figure 33 , a fourth organic film 192 is formed on the third organic film 191, and then a common electrode CE is formed on the fourth organic film 192 and the light-emitting element LE.

[0307] Then, a light-blocking layer BM, a first light-converting layer QDL1 and a second light-converting layer QDL2, a light-transmitting layer TPL, and color filters CF1, CF2, and CF3 are formed.

[0308] Figure 34 is an exemplary diagram of a virtual reality device including a display device according to one or more embodiments. Figure 34 A virtual reality device 1 using the display device 10 according to one or more embodiments is shown.

[0309] Referring to Figure 34 , the virtual reality device 1 according to one or more embodiments may be a device in the form of glasses. The virtual reality device 1 according to one or more embodiments may include a display device 10, a left-eye lens 10a, a right-eye lens 10b, a support frame 20, a left leg 30a and a right leg 30b, a reflection member 40, and a display device housing 50.

[0310] Figure 34 A virtual reality device 1 including two legs 30a and 30b is shown. However, the present disclosure is not limited thereto. The virtual reality device 1 according to one or more embodiments may be used in a head-mounted display including a head-mounted band that can be worn on the head instead of the legs 30a and 30b. For example, the virtual reality device 1 according to one or more embodiments may not be limited to Figure 34The example shown in and can be applied in various forms and can be applied in various electronic devices.

[0311] The display device housing 50 can accommodate the display device 10 and the reflection member 40. An image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the right eye of the user through the right eye lens 10b. Accordingly, the user can view a virtual reality image displayed on the display device 10 through the right eye.

[0312] Figure 34 It is shown that the display device housing 50 is provided at the right end of the support frame 20. However, the present disclosure is not limited thereto. For example, the display device housing 50 can be provided at the left end of the support frame 20. In this case, an image displayed on the display device 10 can be reflected from the reflection member 40 and provided to the left eye of the user via the left eye lens 10a. Accordingly, the user can view a virtual reality image displayed on the display device 10 through the left eye. As another example, the display device housing 50 can be provided at each of the left and right ends of the support frame 20. In this case, the user can view a virtual reality image displayed on the display device 10 through both the left and right eyes.

[0313] Figure 35 is an example diagram showing a smart device including a display device according to one or more embodiments.

[0314] Refer to Figure 35 , the display device 10 according to one or more embodiments can be applied to a smart watch 2 which is one of smart devices.

[0315] Figure 36 is an example diagram showing a vehicle including a display device according to one or more embodiments. Figure 36 It shows a vehicle using a display device according to one or more embodiments.

[0316] Refer to Figure 36 , the display devices 10_a, 10_b, and 10_c according to one or more embodiments can be applied to the instrument panel of a vehicle, applied to the center instrument panel of a vehicle, or applied to a center information display (CID) provided on the instrument panel of a vehicle. In addition, each of the display devices 10_d and 10_e according to one or more embodiments can be applied to respective in-vehicle mirror displays instead of each of the side mirrors of a vehicle.

[0317] Figure 37 is an example diagram showing a transparent display device including a display device according to one or more embodiments.

[0318] Refer to Figure 37, a display device according to one or more embodiments can be applied to a transparent display device. The transparent display device can transmit light while displaying an image IM thereon. Accordingly, a user located in front of the transparent display device can not only view the image IM displayed on the display device 10, but also view an object RS or a background located behind the transparent display device. In the case where the display device 10 is applied to a transparent display device, Figure 7 the substrate SUB of the display device 10 shown in

[0319] may include a light-transmissive portion through which light can be transmitted, or may be made of a material through which light can be transmitted. At the end of the detailed description, those skilled in the art will understand that many changes and modifications can be made to the embodiments without substantially departing from the principles and scope of the present disclosure. Accordingly, the embodiments of the present disclosure are used only in a general and descriptive sense and not for the purpose of limitation.

Claims

1. A light-emitting element, comprising: A first element rod including a first semiconductor layer and an active layer and having a first inclination angle on a side surface; a second element rod, on the first element rod and having a second inclination angle on a side surface; a third element rod, which is on the second element rod and has a third inclination angle on a side surface, wherein the second inclination angle is smaller than the first inclination angle and the third inclination angle; a protective layer around one surface and side of the first element rod, side of the second element rod, and side of the third element rod; as well as A contact electrode surrounds the protection layer and is electrically connected to the first semiconductor layer.

2. The light-emitting element according to claim 1, wherein The second inclination angle is in the range of 60 degrees to 80 degrees.

3. The light-emitting element according to claim 1, wherein The protective layer comprises: a first insulating layer around said one surface and said side of said first element bar and said side of said second element bar; a reflective layer on the first insulating layer around the one surface and the side surface of the first element rod and the side surface of the second element rod; and a second insulating layer on the reflective layer around the one surface and the side surface of the first element rod, the side surface of the second element rod, and the side surface of the third element rod.

4. The light-emitting element according to claim 3, wherein The first insulating layer and the reflective layer are not on the side surface of the third element rod.

5. The light emitting element according to claim 1, wherein The second element rod becomes wider toward the third element rod, and the width of the third element rod is greater than the width of the first element rod.

6. The light emitting element according to claim 4, wherein The contact electrode extends from the one surface of the first element bar and is on at least a portion of the side surface of the first element bar, the side surface of the second element bar, and the side surface of the third element bar.

7. A light-emitting element, comprising: An element bar, comprising a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer stacked in sequence, and divided into a first element bar, a second element bar and a third element bar according to an inclination angle, wherein the first element bar comprises the first semiconductor layer and the active layer, the inclination angle comprises a first inclination angle, a second inclination angle and a third inclination angle, and the second inclination angle of the second element bar is smaller than the first inclination angle of the first element bar and the third inclination angle of the third element bar; a protective layer around one surface and side of the first element rod, side of the second element rod, and side of the third element rod; as well as A first contact electrode and a second contact electrode are separated from each other on the one surface of the first element rod, the first contact electrode is electrically connected to the first semiconductor layer, and the second contact electrode is electrically connected to the second semiconductor layer.

8. The light-emitting element according to claim 7, wherein The protective layer comprises: a first insulating layer around said one surface and said side of said first element bar and said side of said second element bar; a reflective layer on the first insulating layer around the one surface and the side surface of the first element rod and the side surface of the second element rod; and a second insulating layer on the reflective layer around the one surface and the side surface of the first element rod, the side surface of the second element rod, and the side surface of the third element rod.

9. The light emitting element according to claim 7, wherein The first contact electrode and the second contact electrode are provided on the protective layer on at least a portion of a side surface of the element rod.

10. A display device, comprising: substrate; A pixel electrode, on the substrate; a light emitting element on the pixel electrode and including a contact electrode on one surface; A connecting electrode, connecting the contact electrode and the pixel electrode; as well as A common electrode, on the light emitting element, The light emitting element further includes: a first element rod including a first semiconductor layer and an active layer and having a first inclination angle on a side surface; a second element rod on the first element rod and having a second inclination angle on a side surface; a third element rod on the second element rod and having a third inclination angle on a side surface; and a protective layer around one surface and a side surface of the first element rod, a side surface of the second element rod, and a side surface of the third element rod, The contact electrode is around at least a portion of a side surface of the protection layer, and the second inclination angle is smaller than the first inclination angle and the third inclination angle.

11. The display device according to claim 10, wherein: The second inclination angle is in the range of 60 degrees to 80 degrees.

12. The display device according to claim 10, wherein: The protective layer comprises: a first insulating layer around said one surface and said side of said first element bar and said side of said second element bar; a reflective layer on the first insulating layer around the one surface and the side surface of the first element rod and the side surface of the second element rod; and a second insulating layer on the reflective layer around the one surface and the side surface of the first element rod, the side surface of the second element rod, and the side surface of the third element rod.

13. The display device according to claim 12, wherein: The first insulating layer and the reflective layer are not on the side surface of the third element rod.

14. The display device according to claim 13, wherein: The contact electrode extends from the one surface of the first element bar and is on at least a portion of the side surface of the first element bar, the side surface of the second element bar, and the side surface of the third element bar.

15. The display device according to claim 10, further comprising: An organic pattern layer is between the light emitting element and the pixel electrode. Wherein, the connection electrode is on a portion of a side surface of the organic pattern layer and a side surface of the contact electrode on the pixel electrode.

16. A display device, comprising: substrate; a pixel electrode and a common electrode, on the substrate and separated from each other; a light emitting element on the pixel electrode and the common electrode and including a first contact electrode and a second contact electrode on one surface; a first connecting electrode connected to the pixel electrode and the first contact electrode; as well as a second connecting electrode connected to the common electrode and the second contact electrode, The light emitting element comprises: an element rod comprising a first semiconductor layer, an active layer, a second semiconductor layer and a third semiconductor layer stacked in sequence, and divided into a first element rod, a second element rod and a third element rod according to an inclination angle, the inclination angle comprising a first inclination angle, a second inclination angle and a third inclination angle, the second inclination angle of the second element rod being smaller than the first inclination angle of the first element rod and the third inclination angle of the third element rod; and a protective layer around one surface and a side surface of the first element rod, a side surface of the second element rod and a side surface of the third element rod, and The first contact electrode and the second contact electrode are separated from each other on the one surface of the first element bar, and on at least a portion of a side surface of the element bar on the protective layer.

17. The display device according to claim 16, wherein: The protective layer comprises: a first insulating layer around said one surface and said side of said first element bar and said side of said second element bar; a reflective layer on the first insulating layer around the one surface and the side surface of the first element rod and the side surface of the second element rod; and a second insulating layer on the reflective layer around the one surface and the side surface of the first element rod, the side surface of the second element rod, and the side surface of the third element rod.

18. The display device according to claim 16, further comprising: an organic pattern layer, between the pixel electrode and the common electrode, Wherein, the light emitting element is on the organic pattern layer, wherein the first connecting electrode is on a portion of the side surface of the organic pattern layer and on the side surface of the first contact electrode, and Wherein, the second connecting electrode is on another portion of the side surface of the organic pattern layer and on the side surface of the second contact electrode.

19. A method for manufacturing a light-emitting element, the method comprising: forming a third semiconductor material layer, a second semiconductor material layer, an active material layer and a first semiconductor material layer on a growth substrate; forming a first element rod having a first tilt angle by etching the active material layer and the first semiconductor material layer using a first mask; using a second mask to mask the first element rod and to etch the second semiconductor material layer and the third semiconductor material layer; forming a first insulating layer and a first reflective layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer and the first semiconductor material layer; forming a second element bar having a second inclination angle and a third element bar having a third inclination angle by etching at least one side surface of at least one of the first semiconductor material layer, the second semiconductor material layer, the third semiconductor material layer, the first insulating layer, and the first reflective layer using a third mask; forming a second insulating layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer and the first semiconductor material layer; as well as A contact electrode is formed on the second insulating layer.

20. A method for manufacturing a display device, the method comprising: forming a third semiconductor material layer, a second semiconductor material layer, an active material layer and a first semiconductor material layer on a growth substrate; forming a first element rod having a first tilt angle by etching the active material layer and the first semiconductor material layer using a first mask; using a second mask to mask the first element rod, and then etching the second semiconductor material layer and the third semiconductor material layer; forming a first insulating layer and a first reflective layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer and the first semiconductor material layer; forming a second element bar having a second inclination angle and a third element bar having a third inclination angle by etching at least one side surface of at least one of the first semiconductor material layer, the second semiconductor material layer, the third semiconductor material layer, the first insulating layer, and the first reflective layer using a third mask; forming a second insulating layer covering the third semiconductor material layer, the second semiconductor material layer, the active material layer and the first semiconductor material layer; forming a light emitting element by forming a contact electrode on the second insulating layer; Transferring the light-emitting element to a circuit board having a pixel electrode; as well as A connection electrode is formed to connect the contact electrode and the pixel electrode.

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