Processor verification method and device, electronic equipment and storage medium

Abstract

The application provides a processor verification method and device, electronic equipment and storage medium, and relates to the technical field of processors, and comprises the following steps: obtaining first instruction information corresponding to a processor to be verified; determining second instruction information corresponding to a reference model based on the first instruction information; determining a verification result of the processor to be verified based on the first instruction information and the second instruction information; and the verification result is used to represent whether the instruction set architecture behavior in the processor to be measured conforms to the specification definition of the instruction set architecture. The application compares the instruction information of the processor to be verified and the reference model in the granularity of instructions, so that the verification process can accurately detect errors of the processor in instruction execution and memory access operations, and the accuracy and efficiency of the verification of the processor to be verified are improved.

Description

Technical Field

[0001] This invention relates to the field of processor technology, and in particular to a processor verification method, apparatus, electronic device, and storage medium. Background Technology

[0002] Currently, the main methods for processor verification include using a software-implemented instruction set functional model as a reference model, and comparing the register contents of each cycle at the cycle level to verify the correctness of the instruction stream and memory access stream.

[0003] However, comparing register contents at the cycle level is a coarse-grained verification method, which reduces the error rate of the processor in instruction execution and memory access operations, and further reduces the accuracy of processor verification. Summary of the Invention

[0004] This invention provides a processor verification method, apparatus, electronic device, and storage medium to address the shortcomings of existing technologies that use cycle-level comparison of register contents for verification, which has a coarse granularity. This reduces the error rate of the processor in instruction execution and memory access operations, further reducing the deficiencies in the accuracy and efficiency of processor verification. The invention achieves instruction-level comparison of instruction information between the processor to be verified and the reference model, enabling the verification process to accurately detect errors in instruction execution and memory access operations, thereby improving the accuracy and efficiency of processor verification.

[0005] This invention provides a processor verification method, apparatus, electronic device, and storage medium, comprising:

[0006] Obtain first instruction information corresponding to the processor to be verified; the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction.

[0007] Based on the first instruction information, second instruction information corresponding to the reference model is determined; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize the attribute information obtained by the reference model after executing the target instruction; the instruction set architecture in the processor to be verified is established based on the instruction set architecture in the reference model;

[0008] Based on the first instruction information and the second instruction information, the verification result of the processor to be verified is determined; the verification result is used to characterize whether the instruction set architecture behavior in the processor under test conforms to the specification definition of instruction set architecture.

[0009] According to a processor verification method provided by the present invention, the first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: comparing a first content in the first instruction stream and a second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; and determining the verification result based on the first comparison result.

[0010] According to a processor verification method provided by the present invention, the first instruction information is an out-of-order load memory access stream, and the second instruction information is a reference load memory access stream; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: reordering the out-of-order load memory access stream based on a reordering buffer pointer to obtain a reordered load memory access stream; inserting the reordered load memory access stream into an initial load reordering queue to obtain a second load reordering queue; and determining the verification result based on the second load reordering queue and the reference load memory access stream.

[0011] According to a processor verification method provided by the present invention, determining the verification result based on a second load reordering queue and a reference load-memory stream includes: acquiring a pipeline flushing signal of the processor to be verified; the pipeline flushing signal being used to characterize a signal for clearing invalid instructions; based on the pipeline flushing signal, deleting load-memory stream entries located in erroneous instruction paths in the second load reordering queue to obtain a third load reordering queue; dequeuing and comparing a first queue head entry in the third load reordering queue with a second queue head entry in the reference load-memory stream to obtain a second comparison result; if the second comparison result indicates that the first queue head entry and the second queue head entry are inconsistent, determining that the verification result is that the instruction set architecture in the processor to be verified does not conform to the specification definition of the instruction set architecture in the reference model.

[0012] According to a processor verification method provided by the present invention, the first instruction information is a sequential memory access stream, and the second instruction information is a reference memory access stream; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: inserting the sequential memory access stream into the end of an initial test memory queue to obtain a second test memory queue; inserting the reference memory access stream into the end of an initial reference memory queue to obtain a second reference memory queue; dequeuing and comparing the third queue head entry of the second test memory queue and the fourth queue head entry of the second reference memory queue to obtain a third comparison result; and determining the verification result based on the third comparison result.

[0013] According to a processor verification method provided by the present invention, the step of determining the second instruction information corresponding to the reference model based on the first instruction information includes: determining the target instruction to be executed by the processor to be verified based on the first instruction information; and calling the reference model to execute the target instruction to obtain the second instruction information.

[0014] According to a processor verification method provided by the present invention, before obtaining the first instruction information corresponding to the processor to be verified, the method further includes: obtaining the configuration information of the processor to be verified; and adjusting the configuration information in the initial model based on the configuration information to obtain the reference model.

[0015] The present invention also provides a processor verification device, comprising the following modules:

[0016] The acquisition module is used to acquire first instruction information corresponding to the processor to be verified; the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction.

[0017] The second instruction information determination module is used to determine the second instruction information corresponding to the reference model based on the first instruction information; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize the attribute information obtained by the reference model after executing the target instruction; the processor to be verified and the reference model are established based on the same instruction set architecture specification definition;

[0018] The verification result determination module is used to determine the verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0019] The present invention also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein the processor executes the computer program to implement the processor verification method described above.

[0020] The present invention also provides a non-transitory computer-readable storage medium having a computer program stored thereon, which, when executed by a processor, implements the processor verification method as described above.

[0021] The present invention also provides a computer program product, including a computer program that, when executed by a processor, implements the processor verification method as described above.

[0022] The processor verification method, apparatus, electronic device, and storage medium provided by this invention acquire first instruction information corresponding to the processor to be verified, which characterizes the attribute information obtained after the processor to be verified executes the target instruction; second instruction information characterizes the attribute information obtained after a reference model executes the target instruction; based on the first instruction information, second instruction information corresponding to the reference model is determined; the first instruction information and the second instruction information are of the same type; the second instruction information characterizes the attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the same instruction set architecture specification definition; based on the first instruction information and the second instruction information, the verification result of the processor to be verified is determined; the verification result characterizes whether the instruction set architecture in the processor to be verified conforms to the specification definition of the instruction set architecture in the reference model. Thus, by comparing the instruction information of the processor to be verified and the reference model at the instruction granularity, the verification process can accurately detect errors in instruction execution and memory access operations, improving the accuracy and efficiency of the verification of the processor to be verified. Attached Figure Description

[0023] To more clearly illustrate the technical solutions in this invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of this invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0024] Figure 1 This is a flowchart illustrating the processor verification method provided by the present invention.

[0025] Figure 2 This is a schematic diagram of the processor verification system provided by the present invention.

[0026] Figure 3 This is a schematic diagram of the processor verification device provided by the present invention.

[0027] Figure 4 This is a schematic diagram of the structure of the electronic device provided by the present invention. Detailed Implementation

[0028] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of this invention. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0029] Currently, traditional processor system-level verification methods, besides lacking accuracy due to their coarse-grained nature, also lack flexible configurability. Typically, a set of verification logic code and reference models is only applicable to a specific processor architecture under test. When the behavior of the processor architecture under test changes, the verification logic and reference model need to be manually adjusted, which is cumbersome and inefficient. With the introduction of agile hardware design languages, the configurability of processors has been significantly improved, making the inflexibility of traditional processor system verification methods increasingly apparent.

[0030] To address the aforementioned issues, this invention proposes a processor verification method that compares the instruction information of the processor to be verified with that of a reference model at the instruction level. This enables the verification process to accurately detect errors in instruction execution and memory access operations, thereby improving the accuracy and efficiency of processor verification.

[0031] The following is combined with Figures 1-3 The present invention describes a processor verification method applicable to the verification of any processor. The execution subject of this method can be an electronic device or a processor verification method installed in the electronic device. The processor verification device can be implemented by software, hardware, or a combination of both.

[0032] Figure 1 This is one of the flowcharts illustrating the processor verification method provided by the present invention, such as... Figure 1 As shown, the method includes the following:

[0033] Step 101: Obtain the first instruction information corresponding to the processor to be verified.

[0034] The first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction.

[0035] Here, the processor architecture to be verified includes, but is not limited to, RISC-V architecture processors and ARM architecture processors.

[0036] Here, the first instruction information may include, but is not limited to, instruction stream, load memory access stream, store memory access stream, etc.

[0037] Here, the processor to be verified can be a processor model implemented based on a software programming language or a processor model implemented based on a hardware description language.

[0038] Here, the first instruction information can be obtained through a signal sent by the processor to be verified, or it can be obtained directly from the processor to be verified.

[0039] Step 102: Based on the first instruction information, determine the second instruction information corresponding to the reference model.

[0040] The first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize the attribute information obtained by the reference model after executing the target instruction; the processor to be verified and the reference model are established based on the same instruction set architecture specification definition. Here, the reference model is a software-implemented instruction set functional model, such as the RISC-V instruction set, ARM instruction set, etc.

[0041] It should be noted that the instruction set architecture in the reference model conforms to the specification definition, while the instruction set architecture in the processor to be verified is uncertain to conform to the specification definition. Therefore, the reference model needs to be used to verify the processor.

[0042] Here, the second instruction information includes, but is not limited to, instruction streams, load memory access streams, and store memory access streams. For example, after the instruction stream comparison module receives the first instruction stream of the processor to be verified, it calls the reference model to execute an instruction. After the reference model executes the instruction, it returns the second instruction stream of that instruction. The instruction stream comparison module then compares the first instruction stream and the second instruction stream.

[0043] Step 103: Based on the first instruction information and the second instruction information, determine the verification result of the processor to be verified.

[0044] The verification results are used to characterize whether the instruction set architecture behavior of the tested processor conforms to the specification definition of instruction set architecture.

[0045] It should be noted that the first instruction information and the second information are of the same type. For example, if the first instruction information is an instruction stream, then the second instruction information is also an instruction stream; if the first instruction stream is a Load memory access stream, then the second instruction information is also a Load memory access stream.

[0046] Here, the first instruction information and the second instruction information are compared. If they are inconsistent, it means that the verification result does not conform to the specification definition of the instruction set architecture.

[0047] In this embodiment of the invention, first instruction information corresponding to the processor to be verified is obtained; second instruction information corresponding to the reference model is determined based on the first instruction information; and verification result of the processor to be verified is determined based on the first instruction information and the second instruction information. The verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture. In this way, by comparing the instruction information of the processor to be verified and the reference model at the instruction granularity, the verification process can accurately detect errors in the processor's instruction execution and memory access operations, thereby improving the accuracy and efficiency of the verification of the processor to be verified.

[0048] Furthermore, the first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; determining the verification result for the processor to be verified based on the first instruction information and the second instruction information includes: comparing the first content in the first instruction stream and the second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; and determining the verification result based on the first comparison result.

[0049] Here, the first instruction stream and the second instruction stream can include, but are not limited to, the current instruction storage address (ProgramCounter, PC), the instruction physical address, the instruction code, the instruction write-back register number, the instruction write-back value, and the type of register that the instruction writes back to.

[0050] Here, the first comparison result can be whether the first instruction stream and the second instruction stream are consistent or inconsistent. If the first instruction stream and the second instruction stream are inconsistent, it means that the instruction set architecture behavior in the tested processor does not conform to the specification definition of the instruction set architecture in the reference model.

[0051] Specifically, when the first instruction information is the first instruction stream, the reference model is instructed to execute the same number of instructions as the first instruction stream to obtain the second instruction stream. Then, the information in the first instruction stream and the second instruction stream is compared to obtain the first comparison result. If the first comparison result is incorrect, the implementation of the processor to be verified is considered to be incorrect and does not conform to the specification definition of the instruction set architecture. If the second comparison result is correct, the implementation of the processor to be verified is considered to be correct and conforms to the specification definition of the instruction set architecture. If any of the current instruction PC, instruction physical address, instruction code, instruction write-back register number, instruction write-back value, or instruction write-back register type in the first instruction information is inconsistent with any of the information in the second instruction information, the verification result is determined to be incorrect.

[0052] In this embodiment of the invention, by comparing the instruction stream of the processor to be verified with the instruction stream of the reference model, the verification process can accurately detect errors in the processor's instruction execution and memory access operations, ensuring that it conforms to the specification definition of the instruction set architecture, and further improving the accuracy and efficiency of the verification.

[0053] Furthermore, the first instruction information is an out-of-order load memory access stream, and the second instruction information is a reference load memory access stream; determining the verification result for the processor to be verified based on the first instruction information and the second instruction information includes: reordering the out-of-order load memory access stream based on the reordering buffer pointer to obtain a reordered load memory access stream; inserting the reordered load memory access stream into an initial load reordering queue to obtain a second load reordering queue; and determining the verification result based on the second load reordering queue and the reference load memory access stream.

[0054] Here, both out-of-order load memory access streams and reference load memory access streams can include, but are not limited to, virtual addresses, physical addresses, memory access data, and memory access size. Load memory access operations are the operations by which the processor reads data from memory. When the processor executes a program, it frequently needs to load data from memory into registers for processing. A memory access stream refers to a series of memory access operations generated by the processor during program execution. These memory access operations are executed sequentially according to the program, forming a memory access stream.

[0055] Here, the out-of-order load memory access stream is obtained when the processor executes instructions in an out-of-order manner, and the execution order may differ from the order specified by the program.

[0056] Here, the reorder buffer is a buffer used to temporarily store the results of out-of-order instructions. After an instruction finishes executing, its result is temporarily stored in the reorder buffer instead of being directly committed to registers or memory. The result is only committed after all instructions preceding its position in the reorder buffer have been committed.

[0057] Here, invalid instructions refer to instructions that the processor needs to clear (flush) in the pipeline when it detects a branch prediction error, out-of-order load violation, exception, or interrupt, in order to ensure the correct execution of subsequent instructions.

[0058] Specifically, when the first instruction information is an out-of-order load memory access stream, the out-of-order load memory access stream is first reordered according to the reordering buffer pointer to obtain a reordered load memory access stream; then, the reordered load memory access stream is inserted into the initial load reordering queue to obtain a second load reordering queue; next, when the processor to be verified experiences a pipeline flush, the pipeline flush signal is acquired; finally, the verification result is determined based on the pipeline flush signal and the reference load memory access stream.

[0059] In this embodiment of the invention, by reordering the out-of-order load memory access stream, the complexity caused by out-of-order execution is effectively handled, enabling verification to cope with complex execution paths in modern processors.

[0060] In another embodiment of the present invention, the first instruction information can be directly a sequential load memory access stream, without the need to reorder the load memory access stream, and the verification result can be determined by directly comparing the sequential load memory access stream and the reference load memory access stream.

[0061] For example, determining the verification result based on the second load reordering queue and the reference load-memory stream includes: acquiring the pipeline flushing signal of the processor to be verified; the pipeline flushing signal is used to characterize the signal for clearing invalid instructions; based on the pipeline flushing signal, deleting the load-memory stream table entry located in the erroneous instruction path in the second load reordering queue to obtain a third load reordering queue; dequeuing and comparing the first queue head entry in the third load reordering queue with the second queue head entry in the reference load-memory stream to obtain a second comparison result; if the second comparison result is that the first queue head entry and the second queue head entry are inconsistent, determining that the verification result is that the instruction set architecture in the processor to be verified does not conform to the specification definition of the instruction set architecture in the reference model.

[0062] Here, the Load memory access stream entry is a type of memory access stream entry, specifically used to record and manage information about Load memory access operations. The memory access stream entry is a data structure in the processor used to record and manage information about each memory access operation in the memory access stream, including virtual address, physical address, memory access data, and memory access size.

[0063] It should be noted that the queue contains multiple elements, and each element can include a virtual address, a physical address, memory access data, and memory access size. Here, the head entry can be understood as an element, including a virtual address, a physical address, memory access data, and memory access size.

[0064] Here, the second comparison result can be whether the first pair of header entries is consistent with or inconsistent with the second pair of header entries. When any one of the first pair of header entries (i.e., virtual address, physical address, memory access data, and memory access size) is inconsistent with any one of the second pair of header entries, the verification result is determined to be that the instruction set architecture in the tested processor does not conform to the specification definition of the instruction set architecture in the reference model; otherwise, the verification result is determined to be that the instruction set architecture in the tested processor conforms to the specification definition of the instruction set architecture in the reference model.

[0065] Specifically, after receiving the pipeline flushing signal, the load memory access stream table entries located in the erroneous instruction path in the second load reordering queue are deleted according to the pipeline flushing signal to obtain the third load reordering queue. The first queue head entry in the third load reordering queue is compared with the second queue head entry in the reference load memory access stream to obtain the second comparison result. Based on the second comparison result, the verification result is determined.

[0066] In this embodiment of the invention, when the processor to be verified experiences pipeline flushing, all Load memory access flow table entries located in the erroneous instruction path in the Load reordering queue are deleted accordingly. This improves the accuracy of the Load reordering queue, ensures that it conforms to the specification definition of the instruction set architecture, and further improves the accuracy and efficiency of verification.

[0067] Further, the first instruction information is a sequential memory access stream, and the second instruction information is a reference memory access stream; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: inserting the sequential memory access stream into the end of the initial test memory queue to obtain a second test memory queue; inserting the reference memory access stream into the end of the initial reference memory queue to obtain a second reference memory queue; dequeuing and comparing the third queue head entry of the second test memory queue and the fourth queue head entry of the second reference memory queue to obtain a third comparison result; and determining the verification result based on the third comparison result.

[0068] Here, both sequential memory access streams and reference memory access streams can include, but are not limited to, pseudo-address, physical address, accessed data, and access size.

[0069] Here, the third comparison result can be whether the head entries of the third queue and the head entries of the fourth queue are the same or different. If the head entries of the third queue and the head entries of the fourth queue are different, it means that the instruction set architecture in the processor under test does not conform to the specification definition of the instruction set architecture in the reference model; if they are the same, it means that the instruction set architecture behavior in the processor under test conforms to the specification definition of the instruction set architecture.

[0070] It should be noted that when neither the second tested storage queue nor the second reference storage queue is empty, the head entries of the third queue and the head entries of the fourth queue are compared to verify the processor to be verified.

[0071] In this embodiment of the invention, by comparing the Store memory access flow of the processor to be verified with the Store memory access flow of the reference model, the verification process can accurately detect errors in the processor's instruction execution and memory access operations, ensuring that it conforms to the specification definition of the instruction set architecture, and further improving the accuracy and efficiency of the verification.

[0072] It should be noted that this invention can verify the processor under test using any one or more comparison results from the instruction stream, load memory access stream, or store memory access stream. For example, taking one as an example, if the processor under test matches the instruction stream in the reference model, or if the processor under test matches the load memory access stream in the reference model, or if the processor under test matches the store memory access stream in the reference model, it is determined that the processor under test conforms to the specification definition of the instruction set architecture in the reference model. Taking two as an example, if the processor under test matches the load memory access stream in the reference model and also matches the store memory access stream in the reference model, it is determined that the processor under test conforms to the specification definition of the instruction set architecture in the reference model. Taking three as an example, if the processor under test matches the load memory access stream in the reference model, and also matches the store memory access stream in the reference model, it is determined that the processor under test conforms to the specification definition of the instruction set architecture in the reference model. The above are just a few embodiments for determining the verification results and are not specific limitations.

[0073] Furthermore, determining the second instruction information corresponding to the reference model based on the first instruction information includes: determining the target instruction to be executed by the processor to be verified based on the first instruction information; and calling the reference model to execute the target instruction to obtain the second instruction information.

[0074] Here, target instructions refer to instructions that the processor to be verified needs to execute or has already executed. Target instructions include, but are not limited to, instruction streams, Load instructions, and Store instructions.

[0075] In this embodiment of the invention, the target instruction of the processor to be verified is first determined based on the instruction information corresponding to the processor to be verified, and then the reference model is guided to execute the target instruction to obtain the instruction information corresponding to the reference model. This ensures that the instruction information of the processor to be verified and the instruction information of the reference model are obtained for the same instruction, thereby improving the accuracy of the comparison and further improving the precision and efficiency of the verification.

[0076] Furthermore, before obtaining the first instruction information corresponding to the processor to be verified, the method further includes: obtaining the configuration information of the processor to be verified; and adjusting the configuration information in the initial model based on the configuration information to obtain the reference model.

[0077] Here, the configuration information may include, but is not limited to, supported instruction set architecture (such as RISC-V) extensions, supported instruction set architecture (such as RISC-V) privileged modes, virtual address management unit configuration, physical memory start address, physical memory size, and whether unaligned memory access is supported.

[0078] Specifically, before verifying the processor to be verified, the configuration information of the processor to be verified is obtained, and the configuration information of the reference model is guided by the configuration information. It is important to understand that the configuration information in the processor to be verified must be aligned with the configuration information in the reference model.

[0079] In another embodiment, the configuration information of the processor to be verified can also adjust the verification logic of instruction information during the verification process. It is understood that if the configuration information of the processor to be verified does not have a configuration vector, then the verification process does not need to compare the vector, and the reference model does not need to configure the vector.

[0080] In this embodiment of the invention, by obtaining the configuration information of the processor to be verified and the configuration information of the reference model, it is possible to flexibly adapt to RISC-V processors with different configurations, achieve automated alignment, reduce manual intervention, and improve verification efficiency, thereby accelerating the processor development cycle and reducing development costs.

[0081] The following is an application scenario of a processor verification method provided by an embodiment of the present invention.

[0082] It should be noted that in this application scenario, the processor to be verified is a RISC-V processor, and the reference model is an instruction set functional model that conforms to the RISC-V specification. The instruction information includes instruction stream, Load memory access stream, and Store memory access stream.

[0083] Figure 2 This is a schematic diagram of the processor verification system provided by the present invention, as shown below. Figure 2 As shown, the processor verification system 200 can execute the above-mentioned processor verification method, including: a processor model 201, a reference model 202, a configuration information collection module 203, an instruction flow comparison module 204, a load reordering queue 205, a load memory access flow comparison module 206, a test store queue 207, a store memory access flow comparison module 208, and a reference store queue 209. The processor verification process includes:

[0084] (1) The configuration information collection module obtains the configuration information in the processor model 201 and adjusts the configuration information in the reference model 202 according to the configuration information. The configuration information includes, but is not limited to, the supported RISC-V extensions, the supported RISC-V privileged modes, the virtual address management unit configuration, the physical memory start address, the physical memory size, and whether unaligned memory access is supported.

[0085] (2) Each clock cycle, processor model 201 sends the submitted sequential instruction stream signal to instruction stream comparison module 204 in its ROB; instruction stream comparison module 204 instructs reference model 202 to execute the same number of instructions and obtains the instruction stream of the reference model; instruction stream comparison module 204 compares the instruction stream information of processor model 201 and reference model 202. When a comparison error occurs, it is considered that the implementation of processor model 201 is incorrect and does not conform to the instruction set specification, an error message is given and the simulation ends. Among them, instruction stream information includes, but is not limited to, the current instruction PC, instruction physical address, instruction code, instruction write-back register number, instruction write-back value, and register class of instruction write-back.

[0086] (3) Each clock cycle, processor model 201 sends its speculative out-of-order Load memory access stream signal to Load reordering queue 205. After collecting the Load memory access stream signal of processor model 201, Load reordering queue 205 reorders the Load memory access stream according to its ROB pointer order and inserts it into the Load reordering queue. When pipeline flushing occurs in processor model 201, pipeline flushing signal is sent to Load reordering queue 205. Load reordering queue 205 deletes all Load memory access stream entries in the Load reordering queue located in the erroneous instruction path according to the pipeline flushing signal. After the reference model 202 executes the same Load instruction, Load memory access stream comparison module 206 obtains the Load memory access stream of reference model 202, retrieves the head entry of Load reordering queue and compares it with the Load memory access stream of reference model 202. When the comparison is incorrect, it is considered that the implementation of processor model 201 is incorrect and does not conform to the instruction set specification. An error message is given and the simulation ends. Among them, Load memory access stream information includes: virtual address, physical address, memory access data, memory access size, etc.

[0087] (4) Each clock cycle, processor model 201 sends the deterministic sequential Store access flow signal written to the next level memory to the Store queue under test 207; after collecting the Store access flow signal of processor model 201, the Store queue under test 207 inserts it at the end of the queue; after the reference model 202 executes the same Store instruction, the reference Store queue 209 obtains the Store access flow of the reference model 202 and inserts it at the end of the reference Store queue; when neither the Store queue under test 207 nor the reference Store queue 209 is empty, the Store access flow comparison module 208 retrieves the queue head entries of the two and compares them. If the comparison is incorrect, it is considered that the implementation of processor model 201 is incorrect and does not conform to the instruction set specification, an error message is given and the simulation ends. Among them, the Store access flow information includes: virtual address, physical address, access data, access size, etc.

[0088] In this embodiment of the invention, firstly, by designing a configuration information collection module, it is possible to flexibly adapt to RISC-V processors with different configurations, achieving automated alignment, reducing manual intervention, and improving verification efficiency. Secondly, the introduction of instruction stream comparison and memory access stream comparison modules enables the verification process to accurately detect errors in processor instruction execution and memory access operations, ensuring compliance with RISC-V specifications. Furthermore, the load reordering queue design effectively handles the complexity caused by out-of-order execution, enabling verification to cope with complex execution paths in modern processors. Overall, this invention significantly improves the automation level, flexibility, and efficiency of processor verification, which is of great significance for accelerating processor development cycles and reducing development costs.

[0089] The processor verification apparatus provided by the present invention is described below. The processor verification apparatus described below and the processor verification method described above can be referred to in correspondence.

[0090] Figure 3 This is a schematic diagram of the processor verification device provided by the present invention, as shown below. Figure 3 As shown, the processor verification device 300 includes:

[0091] The acquisition module 301 is used to acquire first instruction information corresponding to the processor to be verified; the first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction.

[0092] The second instruction information determination module 302 is used to determine the second instruction information corresponding to the reference model based on the first instruction information; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize the attribute information obtained by the reference model after executing the target instruction; the instruction set architecture behavior in the processor to be verified is established based on the instruction set architecture; the reference model is established based on the specification definition of the instruction set architecture.

[0093] The verification result determination module 303 is used to determine the verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture.

[0094] In another embodiment, the first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; the verification result determination module 303 is specifically used to: compare the first content in the first instruction stream and the second content in the second instruction stream to obtain a first comparison result; the first content and the second content are of the same type; and determine the verification result based on the first comparison result.

[0095] In another embodiment, the first instruction information is an out-of-order load memory access stream, and the second instruction information is a reference load memory access stream; the verification result determination module 303 is further specifically used for: reordering the out-of-order load memory access stream based on the reordering buffer pointer to obtain a reordered load memory access stream; inserting the reordered load memory access stream into the initial load reordering queue to obtain a second load reordering queue; and determining the verification result based on the second load reordering queue and the reference load memory access stream.

[0096] In another embodiment, the verification result determination module 303 is further configured to: acquire the pipeline flushing signal of the processor to be verified; the pipeline flushing signal is used to characterize the signal for clearing invalid instructions; based on the pipeline flushing signal, delete the load-memory stream table entry located in the erroneous instruction path in the second load reordering queue to obtain a third load reordering queue; dequeue and compare the first queue head entry in the third load reordering queue with the second queue head entry in the reference load-memory stream to obtain a second comparison result; if the second comparison result is that the first queue head entry and the second queue head entry are inconsistent, determine that the verification result is that the instruction set architecture behavior in the processor to be verified does not conform to the specification definition of the instruction set architecture.

[0097] In another embodiment, the first instruction information is a sequential memory access stream, and the second instruction information is a reference memory access stream; the verification result determination module 303 is further specifically used for: determining the verification result of the processor to be verified based on the first instruction information and the second instruction information, including: inserting the sequential memory access stream into the end of the initial test memory queue to obtain a second test memory queue; inserting the reference memory access stream into the end of the initial reference memory queue to obtain a second reference memory queue; dequeuing and comparing the third queue head entry of the second test memory queue and the fourth queue head entry of the second reference memory queue to obtain a third comparison result; and determining the verification result based on the third comparison result.

[0098] In another embodiment, the second instruction information determination module 302 is specifically used to: determine the target instruction to be executed by the processor to be verified based on the first instruction information; call the reference model to execute the target instruction to obtain the second instruction information.

[0099] In another embodiment, before obtaining the first instruction information corresponding to the processor to be verified, the processor verification device 300 further includes a configuration module, specifically used for: obtaining the configuration information of the processor to be verified; and adjusting the configuration information in the initial model based on the configuration information to obtain the reference model.

[0100] Figure 4A schematic diagram of the structure of the electronic device provided by the present invention is shown below. Figure 4 As shown, the electronic device may include: a processor 410, a communications interface 420, a memory 430, and a communication bus 440, wherein the processor 410, the communications interface 420, and the memory 430 communicate with each other through the communication bus 440. The processor 410 can invoke logical instructions in the memory 430 to execute a processor verification method. This method includes: acquiring first instruction information corresponding to the processor to be verified; the first instruction information is used to characterize attribute information obtained after the processor to be verified executes a target instruction; based on the first instruction information, determining second instruction information corresponding to a reference model; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the same instruction set architecture specification definition; based on the first instruction information and the second instruction information, determining the verification result for the processor to be verified; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the instruction set architecture specification definition.

[0101] Furthermore, the logical instructions in the aforementioned memory 430 can be implemented as software functional units and, when sold or used as independent products, can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0102] On the other hand, the present invention also provides a computer program product, which includes a computer program that can be stored on a non-transitory computer-readable storage medium. When the computer program is executed by a processor, the computer can execute the processor verification method provided by the above methods. The method includes: obtaining first instruction information corresponding to the processor to be verified; the first instruction information is used to characterize attribute information obtained after the processor to be verified executes the target instruction; determining second instruction information corresponding to a reference model based on the first instruction information; the first instruction information and the second instruction information are of the same type; the second instruction information is used to characterize attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model are established based on the same instruction set architecture specification definition; determining the verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the instruction set architecture specification definition.

[0103] In another aspect, the present invention also provides a non-transitory computer-readable storage medium storing a computer program thereon, which, when executed by a processor, is implemented to perform the processor verification method provided by the above methods. The method includes: acquiring first instruction information corresponding to a processor to be verified; the first instruction information being used to characterize attribute information obtained after the processor to be verified executes a target instruction; determining second instruction information corresponding to a reference model based on the first instruction information; the first instruction information and the second instruction information being of the same type; the second instruction information being used to characterize attribute information obtained after the reference model executes the target instruction; the processor to be verified and the reference model being established based on the same instruction set architecture specification definition; determining a verification result for the processor to be verified based on the first instruction information and the second instruction information; the verification result being used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the instruction set architecture specification definition.

[0104] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs. Those skilled in the art can understand and implement this without any creative effort.

[0105] Through the above description of the embodiments, those skilled in the art can clearly understand that each embodiment can be implemented by means of software plus necessary general-purpose hardware platforms, and of course, it can also be implemented by hardware. Based on this understanding, the above technical solutions, in essence or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product can be stored in a computer-readable storage medium, such as ROM / RAM, magnetic disk, optical disk, etc., and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute the methods described in the various embodiments or some parts of the embodiments.

[0106] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A processor verification method, characterized in that, include: Obtain the first instruction information corresponding to the processor to be verified; The first instruction information is used to characterize the attribute information obtained after the processor to be verified executes the target instruction; Based on the first instruction information, determine the second instruction information corresponding to the reference model; The first instruction information and the second instruction information are of the same type; The second instruction information is used to characterize the attribute information obtained by the reference model after executing the target instruction; The processor to be verified and the reference model are established based on the same instruction set architecture specification definition; Based on the first instruction information and the second instruction information, the verification result of the processor to be verified is determined; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture. Wherein, the first instruction information is an out-of-order load memory access flow, and the second instruction information is a reference load memory access flow; the step of determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: Based on the reordering buffer pointer, the out-of-order load memory access stream is reordered to obtain a reordered load memory access stream. The reordered load memory access stream is inserted into the initial load reordering queue to obtain the second load reordering queue; The verification result is determined based on the second load reordering queue and the reference load memory access stream.

2. The processor verification method according to claim 1, characterized in that, The first instruction information is a first instruction stream, and the second instruction information is a second instruction stream; Determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: The first content in the first instruction stream and the second content in the second instruction stream are compared to obtain a first comparison result; the first content and the second content are of the same type. Based on the first comparison result, the verification result is determined.

3. The processor verification method according to claim 1, characterized in that, The determination of the verification result based on the second load reordering queue and the reference load memory access stream includes: Obtain the pipeline flush signal of the processor to be verified; the pipeline flush signal is used to characterize the signal for clearing invalid instructions; Based on the pipeline flushing signal, the load memory access flow table entries located in the erroneous instruction path in the second load reordering queue are deleted to obtain the third load reordering queue; The first queue header entry in the third load reordering queue is dequeued and compared with the second queue header entry in the reference load memory access stream to obtain a second comparison result. If the second comparison result shows that the first queue head entry and the second queue head entry are inconsistent, the verification result is determined to be that the instruction set architecture in the processor to be verified does not conform to the specification definition of instruction set architecture.

4. The processor verification method according to claim 1, characterized in that, The first instruction information is a sequential memory access stream, and the second instruction information is a reference memory access stream; Determining the verification result of the processor to be verified based on the first instruction information and the second instruction information includes: The sequential memory access stream is inserted into the end of the initial test memory queue to obtain the second test memory queue; The reference memory access stream is inserted into the end of the initial reference memory queue to obtain the second reference memory queue; The third queue head entry of the second tested storage queue and the fourth queue head entry of the second reference storage queue are dequeued and compared to obtain the third comparison result; The verification result is determined based on the third comparison result.

5. The processor verification method according to any one of claims 1 to 4, characterized in that, The step of determining the second instruction information corresponding to the reference model based on the first instruction information includes: Based on the first instruction information, the target instruction to be executed by the processor to be verified is determined; The reference model is invoked to execute the target instruction, thereby obtaining the second instruction information.

6. The processor verification method according to any one of claims 1 to 4, characterized in that, Before obtaining the first instruction information corresponding to the processor to be verified, the method further includes: Obtain the configuration information of the processor to be verified; Based on the configuration information, the configuration information in the initial model is adjusted to obtain the reference model.

7. A processor verification device, characterized in that, include: The acquisition module is used to acquire the first instruction information corresponding to the processor to be verified. The second instruction information determination module is used to determine the second instruction information corresponding to the reference model based on the first instruction information; The first instruction information and the second instruction information are of the same type; The verification result determination module is used to determine the verification result of the processor to be verified based on the first instruction information and the second instruction information; the verification result is used to characterize whether the instruction set architecture behavior in the processor to be verified conforms to the specification definition of the instruction set architecture; The verification result determination module is further configured to reorder the out-of-order load memory access stream based on the reordering buffer pointer when the first instruction information is an out-of-order load memory access stream and the second instruction information is a reference load memory access stream, so as to obtain a reordered load memory access stream. The reordered load memory access stream is inserted into the initial load reordering queue to obtain the second load reordering queue; The verification result is determined based on the second load reordering queue and the reference load memory access stream.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and running on the processor, characterized in that, When the processor executes the computer program, it implements the processor verification method as described in any one of claims 1 to 6.

9. A non-transitory computer-readable storage medium having a computer program stored thereon, characterized in that, When the computer program is executed by the processor, it implements the processor verification method as described in any one of claims 1 to 6.

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