Wake-up circuit, chip and electronic product

Abstract

The invention provides a wake-up circuit, a chip and an electronic product, and the circuit comprises a first-stage wake-up module which generates a starting signal when an input signal is valid; the low-frequency clock generation module is used for generating a low-frequency clock signal when the starting signal is effective; the filtering module is used for filtering the input signal and outputting a filtered signal; the secondary wake-up module judges the filtering signal based on the low-frequency clock signal, generates a wake-up signal, and generates an overtime signal to reset the filtering module and the secondary wake-up module when wake-up is not completed within a preset time; and the control module is used for generating a reset signal of the first-stage wake-up module when wake-up is successful or wake-up is overtime. According to the invention, a two-stage wake-up mechanism is adopted, the anti-interference capability to an input signal is enhanced, false wake-up caused by identification errors is avoided, and the power consumption is further reduced; meanwhile, the wake-up circuit is closed when wake-up is successful and wake-up is overtime, so that the wake-up circuit enters a low-power-consumption state, first-stage detection and recognition are carried out on the input signal again, and power consumption is further reduced.

Description

Technical Field

[0001] The present invention relates to the field of electronic circuits, and particularly to a wake-up circuit, a chip, and an electronic product. Background Art

[0002] With the continuous development of the integrated circuit field, the requirement for power consumption is getting higher and higher. Taking the in-vehicle MCU chip as an example, a reliable wake-up mechanism for the low-power mode of the in-vehicle MCU chip is a prerequisite for the low-power application of the in-vehicle MCU. In applications, a digital interface signal is usually used to wake up the MCU chip from the low-power mode, and the chip end realizes wake-up by detecting the level or edge of the digital signal.

[0003] After entering the low-power mode, it is an important mechanism for the in-vehicle MCU chip to effectively identify the wake-up signal and avoid being mis-triggered by interference signals such as glitches. Because once a mis-trigger occurs, the in-vehicle MCU chip will be unnecessarily woken up, losing the function of the low-power mode. In an environment with less electromagnetic interference, the glitches on the digital interface signal are small, and an ordinary short-time filtering circuit (filtering range of about 10 ns to 200 ns) can filter out the glitches, and it is not easily woken up by mistake. However, in some environments with severe electromagnetic conditions, such as in a car or near a mobile phone base station, affected by large electromagnetic interference, the amplitude and time of the glitches on the digital signal for waking up the chip will be relatively serious (the glitch amplitude can be greater than 50% of the input signal amplitude, and the time can be as long as several hundred microseconds to dozens of milliseconds).

[0004] One prior art uses a combination of a delay circuit and logic gates, which can filter out glitches with a width from several nanoseconds to several hundred nanoseconds, and since only the wake-up signal is required without using an additional clock source, filtering and wake-up can be completed under the condition that the chip is in the low-power mode and the internal clock is completely turned off; however, its filtering ability is weak, usually only able to filter out glitches with a width of several hundred nanoseconds, so it is not applicable to the environment of large electromagnetic interference.

[0005] Another prior art is to sample and filter the wake-up signal using an internal ring oscillator clock, which can achieve a stronger filtering ability and avoid the chip being mis-woken up; however, since the internal ring oscillator needs to be always turned on for real-time filtering processing when the chip is in the low-power mode, it is not applicable to application scenarios with very strict requirements for the current consumption of the low-power mode.

[0006] Therefore, how to balance the anti-interference ability and power consumption of the wake-up circuit has become one of the problems that need to be urgently solved by those skilled in the art.

[0007] It should be noted that the above introduction to the technical background is only for the convenience of providing a clear and complete description of the technical solutions of the present invention and for the convenience of understanding by those skilled in the art. It cannot be considered that the above technical solutions are well known to those skilled in the art simply because these solutions are described in the background technology section of the present invention. Summary of the invention

[0008] In view of the above-mentioned shortcomings of the prior art, an object of the present invention is to provide a wake-up circuit, a chip and an electronic product, so as to solve the problem that the anti-interference ability and power consumption of the wake-up circuit in the prior art cannot be taken into account at the same time.

[0009] In order to achieve the above-mentioned object and other related objects, the present invention provides a wake-up circuit, characterized in that the wake-up circuit at least includes:

[0010] Primary wake-up module, low-frequency clock generation module, filtering module, secondary wake-up module and control module;

[0011] The first-level wake-up module receives an input signal and generates a start signal when the input signal is valid;

[0012] The low-frequency clock generating module is connected to the output end of the first-level wake-up module, and generates a low-frequency clock signal when the start signal is valid;

[0013] The filtering module is connected to the output end of the low-frequency clock generating module, filters the input signal based on the low-frequency clock signal, and outputs a filtered signal;

[0014] The secondary wake-up module is connected to the output end of the low-frequency clock generation module and the filter module, and judges the filter signal based on the low-frequency clock signal to generate a wake-up signal; and generates a timeout signal to reset the filter module and the secondary wake-up module when the wake-up is not completed within a preset time;

[0015] The control module is connected to the output end of the secondary wake-up module, and generates a reset signal of the primary wake-up module when the wake-up is successful or the wake-up times out.

[0016] Optionally, the first-level wake-up module includes a filtering unit and a first D-type flip-flop; the input end of the filtering unit is connected to the input signal to filter the input signal; the data input end of the first D-type flip-flop receives a first level signal, the clock end is connected to the output end of the filtering unit, the reset end is connected to the reset signal, and the output end outputs the start signal.

[0017] More optionally, the filtering unit includes a delay circuit and a first AND gate; the delay circuit delays the input signal and then outputs it; a first input end of the first AND gate is connected to an output end of the delay circuit, a second input end is connected to the input signal, and an output end is connected to the first flip-flop.

[0018] Optionally, the low-frequency clock generation module is a low-frequency ring oscillator.

[0019] More optionally, the filtering module filters the input signal based on the majority decision method or the continuous decision method.

[0020] More optionally, when the filtering module filters by the continuous decision method, the filtering module includes N D flip-flops and a second AND gate;

[0021] The D flip-flops of each stage are connected in series in sequence. An input end of the first-stage D flip-flop is connected to the input signal or the filtered signal of the input signal. The clock ends of the D flip-flops of each stage are all connected to the low-frequency clock signal; N is a natural number greater than or equal to 2;

[0022] The input ends of the second AND gate are respectively connected to the output ends of the D flip-flops. When the output signals of all the D flip-flops are valid, it is determined that the input signal is valid, and a corresponding filtered signal is output.

[0023] Optionally, the secondary wake-up module includes a first counting unit and a second counting unit;

[0024] The first counting unit receives the low-frequency clock signal and the filtered signal, counts the valid state of the filtered signal to obtain a first count value, and outputs a valid wake-up signal when the first count value is greater than or equal to a first set value;

[0025] The second counting unit receives the low-frequency clock signal, counts the working time of the secondary wake-up module to obtain a second count value, and outputs a valid timeout signal when the second count value reaches a second set value;

[0026] Wherein, the first set value is less than the second set value.

[0027] More optionally, the first counting unit includes a first counter, a first comparator, a first selector, and a second D flip-flop;

[0028] The first counter counts the valid state of the filtered signal based on the rising edge of the low-frequency clock signal;

[0029] The positive-phase input end of the first comparator is connected to the output end of the first counter, and the negative-phase input end is connected to the first set value;

[0030] The first input terminal of the first selector is connected to the output terminal of the first comparator, and the second input terminal and the control terminal are connected to the output terminal of the second D flip-flop; wherein, when the wake-up signal is invalid, the output signal of the first comparator is output, and when the wake-up signal is valid, the wake-up signal is locked in the valid state;

[0031] The data input terminal of the second D flip-flop is connected to the output terminal of the first selector, the clock terminal is connected to the low-frequency clock signal, and the output terminal outputs the wake-up signal.

[0032] More optionally, the second counting unit includes a second counter and a second comparator;

[0033] The second counter counts based on the falling edge of the low-frequency clock signal;

[0034] The positive-phase input terminal of the second comparator is connected to the output terminal of the second counter, the negative-phase input terminal is connected to the second set value, and the output terminal outputs the timeout signal.

[0035] Optionally, the control module includes an OR gate and a second selector;

[0036] The input terminals of the OR gate are respectively connected to the wake-up signal and the timeout signal;

[0037] The first input terminal of the second selector is connected to the output terminal of the OR gate, the second input terminal is connected to the second level signal, and the control terminal is connected to the inverted signal of the enable signal of the wake-up circuit; wherein, when the enable signal is valid, the first-level wake-up module is reset based on the output signal of the OR gate, and when the enable signal is invalid, the reset signal is locked in the valid state.

[0038] To achieve the above object and other related objects, the present invention provides a chip, which at least includes: a main circuit and the above-mentioned wake-up circuit;

[0039] The wake-up circuit provides a wake-up signal for the main circuit;

[0040] The main circuit is connected to the output terminal of the wake-up circuit, and is woken up to work when the wake-up signal is valid, and invalidates the enable signal of the wake-up circuit after being woken up.

[0041] Optionally, the chip is an in-vehicle MCU chip.

[0042] To achieve the above object and other related objects, the present invention further provides an electronic product, which at least includes: the above-mentioned wake-up circuit.

[0043] As described above, the wake-up circuit, chip and electronic product of the present invention have the following beneficial effects:

[0044] The wake-up circuit, chip and electronic product of the present invention adopt a two-stage wake-up mechanism, which enhances the anti-interference ability of the input signal, avoids false wake-up caused by misrecognition, and thus reduces power consumption. At the same time, when the wake-up is successful and the wake-up times out, the wake-up circuit is turned off, so that the wake-up circuit enters a low-power state and re-detects and recognizes the input signal, further reducing power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 It shows a schematic block diagram of the wake-up circuit of the present invention.

[0046] Figure 2 It shows a schematic structural diagram of the wake-up circuit of the present invention.

[0047] Figure 3 It shows a schematic structural diagram of the filtering module of the present invention.

[0048] Figure 4 It shows a schematic structural diagram of the chip of the present invention.

[0049] DESCRIPTION OF REFERENCE NUMERALS

[0050] 1 Wake-up circuit

[0051] 11 First-stage wake-up module

[0052] 111 Filtering unit

[0053] 111a Delay circuit

[0054] 111b First AND gate

[0055] 112 First D flip-flop

[0056] 12 Low-frequency clock generation module

[0057] 13 Filtering module

[0058] 131 Second AND gate

[0059] 132 First-stage D flip-flop

[0060] 133 Second-stage D flip-flop

[0061] 134 Third-stage D flip-flop

[0062] 14 Second-stage wake-up module

[0063] 141 First counting unit

[0064] 141a First counter

[0065] 141b First comparator

[0066] 141c First selector

[0067] 141d Second D flip-flop

[0068] 142 Second counting unit

[0069] 142a Second counter

[0070] 142b Second comparator

[0071] 142c Buffer

[0072] 14a Third selector

[0073] 14b First register

[0074] 14c First adder

[0075] 14d Second register

[0076] 14e Second adder

[0077] 15 Control module

[0078] 151 OR gate

[0079] 152 Second selector

[0080] 2 Main circuit

[0081] 21 Oscillator

[0082] 22 Functional module Specific implementation manners

[0083] The following uses specific specific examples to illustrate the implementation manners of the present invention. Those skilled in the art can easily understand other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific implementation manners. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention.

[0084] Please refer to Figures 1 to 4 . It should be noted that the diagrams provided in this embodiment only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The types, quantities, and proportions of the components in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0085] As Figure 1 shown, the present invention provides a wake-up circuit 1, and the wake-up circuit 1 includes:

[0086] A primary wake-up module 11, a low-frequency clock generation module 12, a filtering module 13, a secondary wake-up module 14, and a control module 15.

[0087] As Figure 1 shown, the first-level wake-up module 11 receives an input signal INPUT and generates a start signal ACT when the input signal INPUT is valid.

[0088] Specifically, the first-level wake-up module 11 detects the level or edge of the input signal INPUT. When the level or edge of the input signal INPUT meets a preset condition, it is determined that the input signal INPUT is valid. The preset condition can be set according to actual needs. As an example, when a high level of the input signal INPUT, a low level of the input signal INPUT, a rising edge of the input signal INPUT, or a falling edge of the input signal INPUT is detected, it is determined that the input signal INPUT is valid; in this embodiment, the input signal INPUT is valid when it is at a high level, and the first-level wake-up module 11 detects the level of the input signal INPUT.

[0089] More specifically, as Figure 2 shown, in this embodiment, the first-level wake-up module 11 includes a filtering unit 111 and a first D flip-flop 112. The input end of the filtering unit 111 is connected to the input signal INPUT to filter the input signal INPUT to remove the glitches in the input signal INPUT. The data input end D of the first D flip-flop 112 receives a first-level signal, the clock end CK is connected to the output end of the filtering unit 111, the reset end CLR is connected to a reset signal CLEAR, and the output end Q outputs the start signal ACT; in this embodiment, the first-level signal is set to a high-level signal 1, and the rising edge of the output signal of the filtering unit 111 triggers the first D flip-flop 112 to output a high-level signal, and the start signal ACT jumps to a high level (valid); when the reset signal CLEAR is valid, the first D flip-flop 112 is reset, and the start signal ACT jumps to a low level (invalid). In actual use, the level corresponding to the start signal ACT being valid can also be configured according to needs (for example, a low level 0), and this embodiment is not limiting.

[0090] As an example, the filtering unit 111 includes a delay circuit 111a and a first AND gate 111b; the delay circuit 111a delays the input signal INPUT and then outputs it; the first input terminal of the first AND gate 111b is connected to the output terminal of the delay circuit 111a, the second input terminal is connected to the input signal INPUT, and the output terminal is connected to the first flip-flop 111b; only when both the input signal INPUT and its delayed signal are at a high level, the first AND gate 111b will output a high level; the effective filtering width of the filtering unit 111 is the time for the signal to pass through the delay circuit 111a. If there is a high-level glitch on the input signal INPUT with a time width less than that of the delay circuit 111a, the high-level signal passing through the delay circuit 111a has not reached the first input terminal of the first AND gate 111b, and the input signal INPUT that has become low has reached the second input terminal of the first AND gate 111b, and the output clock of the first AND gate 111b always remains low (i.e., the glitch is filtered out).

[0091] As Figure 1 shown, the low-frequency clock generation module 12 is connected to the output terminal of the first-level wake-up module 11, and generates a low-frequency clock signal CLK_S when the start signal ACT is valid.

[0092] Specifically, the enable terminal EN of the low-frequency clock generation module 12 is connected to the start signal ACT. When the start signal ACT is valid, the low-frequency clock generation module 12 starts to work and generates a low-frequency clock signal CLK_S; when the start signal ACT is invalid, the low-frequency clock generation module 12 stops working. As an example, the frequency of the low-frequency clock signal CLK_S is set to 10KHz to 100KHz, and the specific value is set according to the actual circuit requirements, which will not be elaborated here one by one. Any circuit structure capable of providing a low-frequency clock signal is applicable to the low-frequency clock generation module 12 of the present invention. In this embodiment, the low-frequency clock generation module 12 is a low-frequency ring oscillator.

[0093] As Figure 1 shown, the filtering module 13 is connected to the output terminal of the low-frequency clock generation module 12, filters the input signal INPUT based on the low-frequency clock signal CLK_S, and outputs a filtered signal DIN_FLT.

[0094] Specifically, the filtering module 13 is a digital filter that digitally filters the input signal INPUT, including but not limited to the majority decision method and the continuous decision method, which will not be elaborated here one by one. Among them, the majority decision method samples the input signal multiple times. If the majority of the sampling results meet the requirements, the input signal is determined to be valid; otherwise, it is determined to be invalid. The continuous decision method samples the input signal multiple times. If the sampling results of a continuously set number of times meet the requirements, the input signal is determined to be valid; otherwise, it is determined to be invalid.

[0095] More specifically, as Figure 3 shown, as an example, the filtering module 13 includes N D flip-flops and a second AND gate 131, where N is a natural number greater than or equal to 2. In this embodiment, the filtering module 13 makes a decision based on the results of 3 consecutive samplings, that is, N = 3, which are respectively denoted as the first-stage D flip-flop 132, the second-stage D flip-flop 133, and the third-stage D flip-flop 134. Each stage of D flip-flops is connected in series in turn (the data input terminal of the subsequent D flip-flop is connected to the output terminal of the previous D flip-flop). The input terminal D of the first-stage D flip-flop 132 is connected to the input signal INPUT or the filtered signal of the input signal INPUT (in this example, the input signal INPUT is detected based on the output signal of the filtering unit 111). The clock terminals CK of each stage of D flip-flops are all connected to the low-frequency clock signal CLK_S. The input terminals of the second AND gate 131 are respectively connected to the output terminals of each D flip-flop. When the output signals of each D flip-flop are all valid, it is determined that the input signal INPUT is valid, and the corresponding filtered signal is output. In this embodiment, only when the outputs of all 3 D flip-flops are high, the filtered signal DIN_FLT outputs a high level; when any one of the 3 D flip-flops is not high, the filtered signal DIN_FLT outputs a low level (i.e., the input signal is filtered out). Any circuit structure that can implement digital filtering is applicable to the present invention and is not limited to this embodiment.

[0096] As Figure 1 shown, the secondary wake-up module 14 is connected to the output terminals of the low-frequency clock generation module 12 and the filtering module 13, makes a decision on the filtered signal DIN_FLT based on the low-frequency clock signal CLK_S, and generates a wake-up signal WKUP (when the filtered signal DIN_FLT meets the wake-up level or edge condition, the wake-up signal WKUP is valid); and generates a timeout signal OT to reset the filtering module 13 and the secondary wake-up module 14 when the wake-up is not completed within a preset time.

[0097] Specifically, as Figure 2As shown, in this embodiment, the secondary wake-up module 14 includes a first counting unit 141 and a second counting unit 142. The first counting unit 141 receives the low-frequency clock signal CLK_S and the filtered signal DIN_FLT, counts the valid state of the filtered signal DIN_FLT to obtain a first count value, and outputs a valid wake-up signal WKUP when the first count value is greater than or equal to a first set value, and the wake-up signal WKUP is invalid when the first count value is less than the first set value (in this example, the wake-up signal WKUP is active high and inactive low). The second counting unit 142 receives the low-frequency clock signal CLK_S, counts the working time of the secondary wake-up module 14 to obtain a second count value, and outputs a valid timeout signal OT when the second count value reaches a second set value, and the timeout signal OT is invalid when the second count value is less than the second set value (in this example, the timeout signal OT is active high and inactive low); wherein, the first set value is less than the second set value, and the specific values are set according to needs.

[0098] More specifically, as an example, the first counting unit 141 includes a first counter 141a, a first comparator 141b, a first selector 141c, and a second D flip-flop 141d. The first counter 141a counts the valid state of the filtered signal DIN_FLT based on the rising edge of the low-frequency clock signal CLK_S. In this embodiment, the first counter 141a includes a third selector 14a, a first register 14b, and a first adder 14c; a first input terminal of the third selector 14a receives data 0, a second input terminal of the third selector 14a is connected to an output terminal of the first adder 14c, and a control terminal is connected to the filtered signal DIN_FLT. When the filtered signal DIN_FLT is invalid (low level), it selects the data output from the first input terminal, and when the filtered signal DIN_FLT is valid (high level), it selects the data output from the second input terminal; an input terminal DIN of the first register 14b is connected to an output terminal of the third selector 14a, a clock terminal CLK receives the low-frequency clock signal CLK_S (triggered by the rising edge), and stores the data output from the third selector 14a; a first input terminal of the first adder 14c is connected to an output terminal of the first register 14b, and a second input terminal is connected to data 1, and adds the data stored in the first register 14b to 1. A positive-phase input terminal of the first comparator 141b is connected to an output terminal of the first counter 141a, and an anti-phase input terminal is connected to the first set value. In this embodiment, the first set value is 8. A first input terminal of the first selector 141c is connected to an output terminal of the first comparator 141b, a second input terminal is connected to an output terminal of the second D flip-flop 141d, and a control terminal is connected to an output terminal of the second D flip-flop 141d; wherein, when the wake-up signal WKUP is invalid (low level), it outputs an output signal of the first comparator 141b, and when the wake-up signal WKUP is valid (high level), it locks the wake-up signal WKUP to a valid state. A data input terminal D of the second D flip-flop 141d is connected to an output terminal of the first selector 141c, a clock terminal CK is connected to the low-frequency clock signal CLK_S, and an output terminal outputs the wake-up signal WKUP; a set terminal SET of the second D flip-flop 141d is further connected to an inverted signal WKUP_ENB of an enable signal of the wake-up circuit 1. When the enable signal is active high (the wake-up circuit 1 is in a working state and the main circuit has not been woken up), the inverted signal WKUP_ENB of the enable signal is low level, and the set terminal of the second D flip-flop 141d is invalid. When the enable signal is inactive low (the main circuit has been woken up), the inverted signal WKUP_ENB of the enable signal is high level, the set terminal of the second D flip-flop 141d is valid, and the wake-up signal WKUP is held at a high-level active state.The first counting unit 141 is responsible for identifying whether there are 8 consecutive high-level periods of the low-frequency clock (CLK_S) on the filtered signal DIN_FLT: If the filtered signal DIN_FLT is always high, the first counter 141a increments by 1 at the rising edge of each low-frequency clock until the first counter 141a counts to 8, then the wake-up signal WKUP becomes valid and the main circuit is woken up to start working (the generation of the low-frequency clock signal stops in the wake-up circuit, and the main body of the wake-up circuit stops working), and at the same time, the wake-up signal WKUP is self-locked; If the filtered signal DIN_FLT goes low during this process, the first counter 141a restarts counting from 0.

[0099] More specifically, as an example, the second counting unit 142 includes a second counter 142a and a second comparator 142b. The second counter 142a counts based on the falling edge of the low-frequency clock signal CLK_S. In this embodiment, the second counter 142a includes a second register 14d and a second adder 14e; the input terminal DIN of the second register 14d is connected to the output terminal of the second adder 14e, and the clock terminal CLK receives the low-frequency clock signal CLK_S (triggered by the falling edge) to latch the data output by the second adder 14e; the first input terminal of the second adder 14e is connected to the output terminal of the second register 14d, and the second input terminal is connected to the data 1 to add the data latched in the second register 14d to 1. The positive input terminal of the second comparator 142b is connected to the output terminal of the second counter 142a, the negative input terminal is connected to the second set value, and the output terminal outputs the timeout signal OT; in this embodiment, the second set value is 15. As another implementation manner of the present invention, the second counting unit 142 further includes a buffer 142c, and the buffer 142c is connected to the output terminal of the second comparator 142b. The second counting unit 142 is used to limit the working time of the low-frequency clock generation module 12, the filtering module 13, and the secondary wake-up module 14; when the low-frequency clock generation module 12 generates 16 clocks, that is, when the second counter 142a counts to 15, the second comparator 142b outputs a valid timeout signal OT, and the timeout signal OT is connected to the reset terminals of the filtering module 13, the first counting unit 141, and the second counting unit 142 to reset the filtering module 13, the first counting unit 141, and the second counting unit 142, and then restart the detection of the first-level wake-up.

[0100] It should be noted that any counting circuit structure capable of implementing wake-up detection and timeout detection is applicable to the first counting unit and the second counting unit of the present invention, and is not limited to this embodiment.

[0101] As shown Figure 1 in the figure, the control module 15 is connected to the output end of the secondary wake-up module 14, and generates a reset signal CLEAR for the primary wake-up module 11 when the wake-up is successful or the wake-up times out.

[0102] Specifically, the control module 15 receives the wake-up signal WKUP, the timeout signal OT, and the enable signal (or the inverted signal WKUP_ENB of the enable signal). When the enable signal is invalid, the primary wake-up module 11 is reset, the start signal ACT is invalid, the low-frequency clock generation module 12 stops generating the low-frequency clock signal CLK_S, and the main body of the wake-up circuit 1 stops working. When the enable signal is valid, the wake-up circuit 1 works normally; and when the wake-up times out, the primary wake-up module 11 is reset.

[0103] More specifically, as an example, the control module 15 includes an OR gate 151 and a second selector 152. The input ends of the OR gate 151 are respectively connected to the wake-up signal WKUP and the timeout signal OT, and output a valid control signal for resetting when the wake-up signal WKUP or the timeout signal OT is valid. The first input end of the second selector 152 is connected to the output end of the OR gate 151, the second input end is connected to a second level signal, the control end is connected to the inverted signal WKUP_ENB of the enable signal, and outputs the reset signal; in this embodiment, the second level signal is set to a high-level signal 1, and in actual use, it can also be set to a low-level signal 0 (the first level signal has nothing to do with the second level signal, and the two can be set to 1 and 0 respectively, or both can be set to 1 or 0). When the enable signal is valid (the inverted signal WKUP_ENB of the enable signal is low level), the primary wake-up module 11 is reset based on the output signal of the OR gate 151, and when the enable signal is invalid (the inverted signal WKUP_ENB of the enable signal is high level), the reset signal CLEAR is locked in a valid state.

[0104] It should be noted that the present invention adopts a two-stage wake-up mechanism for the wake-up circuit, and the wake-up can only be achieved by meeting the two-stage wake-up mechanism, which greatly improves the anti-interference ability; the primary wake-up module is reset when the wake-up is successful and the wake-up times out to turn off the low-frequency clock generation module and the filtering module, so that the wake-up circuit enters a low-power state (to avoid the internal low-frequency clock generation module being always on and unable to achieve extremely low power consumption), thereby reducing power consumption.

[0105] As shown Figure 4 in the figure, the present invention also provides a chip, which at least includes: a wake-up circuit 1 and a main circuit 2.

[0106] As shown Figure 4As shown, the wake-up circuit 1 provides a wake-up signal WKUP to the main circuit 2. For the structure and working principle of the wake-up circuit 1, please refer to the above text and will not be elaborated here one by one.

[0107] As Figure 4 shown, the main circuit 2 is connected to the output terminal of the wake-up circuit 1 and is woken up to work when the wake-up signal WKUP is valid, and invalidates the enable signal of the wake-up circuit 1 after being woken up.

[0108] Specifically, in this embodiment, the main circuit 2 includes an oscillator 21 and a functional module 22. The enable terminal of the oscillator 21 is connected to the wake-up signal WKUP. When the wake-up signal WKUP is valid, a clock signal of the main circuit 2 is generated; when the wake-up signal WKUP is invalid, the main circuit 2 has no clock signal and thus is in a non-working state. The functional module 22 is connected to the output terminal of the oscillator 21, works based on the clock signal provided by the oscillator 21, realizes the main functions of the chip, and invalidates the enable signal of the wake-up circuit 1 after being woken up to work, thereby turning off the main body of the wake-up signal 1 to achieve low power consumption.

[0109] Specifically, the chip includes, but is not limited to, in-vehicle MCU chips, battery management chips, etc., which will not be elaborated here one by one.

[0110] The present invention also provides an electronic product, which at least includes the wake-up circuit 1. Any electronic product that needs to achieve low-power operation is applicable to the present invention and will not be elaborated here one by one.

[0111] In summary, the present invention provides a wake-up circuit, a chip and an electronic product, including: a first-level wake-up module, a low-frequency clock generation module, a filtering module, a second-level wake-up module and a control module; the first-level wake-up module receives an input signal and generates a start signal when the input signal is valid; the low-frequency clock generation module is connected to the output end of the first-level wake-up module and generates a low-frequency clock signal when the start signal is valid; the filtering module is connected to the output end of the low-frequency clock generation module, filters the input signal based on the low-frequency clock signal and outputs a filtered signal; the second-level wake-up module is connected to the output ends of the low-frequency clock generation module and the filtering module, judges the filtered signal based on the low-frequency clock signal, generates a wake-up signal, and generates a timeout signal to reset the filtering module and the second-level wake-up module when the wake-up is not completed within a preset time; the control module is connected to the output end of the second-level wake-up module and generates a reset signal for the first-level wake-up module when the wake-up is successful or timed out. The wake-up circuit, chip and electronic product of the present invention adopt a two-stage wake-up mechanism, enhance the anti-interference ability of the input signal, avoid false wake-up caused by mis-identification, and thus reduce power consumption; at the same time, when the wake-up is successful and timed out, the wake-up circuit is turned off to make the wake-up circuit enter a low-power state, and the first-level detection and identification of the input signal are re-performed, further reducing power consumption. Therefore, the present invention effectively overcomes various disadvantages in the prior art and has high industrial utilization value.

[0112] The above embodiments are only illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by those with ordinary knowledge in the technical field without departing from the spirit and technical ideas disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A wake-up circuit, characterized in that, The wake-up circuit at least includes: a first-level wake-up module, a low-frequency clock generation module, a filtering module, a second-level wake-up module, and a control module; The first-level wake-up module receives an input signal and generates a start signal when the input signal is valid; The low-frequency clock generation module is connected to the output end of the first-level wake-up module and generates a low-frequency clock signal when the start signal is valid; The filtering module is connected to the output end of the low-frequency clock generation module, filters the input signal based on the low-frequency clock signal, and outputs a filtered signal; The second-level wake-up module is connected to the output ends of the low-frequency clock generation module and the filtering module, makes a decision on the filtered signal based on the low-frequency clock signal, and generates a wake-up signal; and generates a timeout signal to reset the filtering module and the second-level wake-up module when the wake-up is not completed within a preset time; The control module is connected to the output end of the second-level wake-up module and generates a reset signal for the first-level wake-up module when the wake-up is successful or timed out.

2. The wake-up circuit according to claim 1, characterized in that: The first-level wake-up module includes a filtering unit and a first D flip-flop; the input end of the filtering unit is connected to the input signal to filter the input signal; the data input end of the first D flip-flop receives a first-level signal, the clock end is connected to the output end of the filtering unit, the reset end is connected to the reset signal, and the output end outputs the start signal.

3. The wake-up circuit according to claim 2, characterized in that: The filtering unit includes a delay circuit and a first AND gate; the delay circuit delays the input signal and then outputs it; the first input end of the first AND gate is connected to the output end of the delay circuit, the second input end is connected to the input signal, and the output end is connected to the first flip-flop.

4. The wake-up circuit according to claim 1, characterized in that: The filtering module uses the continuous decision method for filtering, and the filtering module includes N-level D flip-flops and a second AND gate; The D flip-flops at all levels are connected in series in turn. The input end of the first-level D flip-flop is connected to the input signal or the filtered signal of the input signal. The clock ends of the D flip-flops at all levels are all connected to the low-frequency clock signal; N is a natural number greater than or equal to 2; The input ends of the second AND gate are respectively connected to the output ends of the D flip-flops at all levels. When the output signals of the D flip-flops at all levels are all valid, it is determined that the input signal is valid, and the corresponding filtered signal is output.

5. The wake-up circuit according to claim 1, characterized in that: The second-level wake-up module includes a first counting unit and a second counting unit; The first counting unit receives the low-frequency clock signal and the filtered signal, counts the valid state of the filtered signal to obtain a first count value, and outputs a valid wake-up signal when the first count value is greater than or equal to a first set value; The second counting unit receives the low-frequency clock signal, counts the working time of the second-level wake-up module to obtain a second count value, and outputs a valid timeout signal when the second count value reaches a second set value; Wherein, the first set value is less than the second set value.

6. The wake-up circuit according to claim 5, characterized in that: The first counting unit includes a first counter, a first comparator, a first selector, and a second D flip-flop; The first counter counts the valid state of the filtered signal based on the rising edge of the low-frequency clock signal; The non-inverting input terminal of the first comparator is connected to the output terminal of the first counter, and the inverting input terminal is connected to the first set value; The first input terminal of the first selector is connected to the output terminal of the first comparator, and the second input terminal and the control terminal are connected to the output terminal of the second D flip-flop; wherein, when the wake-up signal is invalid, the output signal of the first comparator is output, and when the wake-up signal is valid, the wake-up signal is locked in the valid state; The data input terminal of the second D flip-flop is connected to the output terminal of the first selector, the clock terminal is connected to the low-frequency clock signal, and the output terminal outputs the wake-up signal.

7. The wake-up circuit according to claim 5, characterized in that: The second counting unit includes a second counter and a second comparator; The second counter counts based on the falling edge of the low-frequency clock signal; The non-inverting input terminal of the second comparator is connected to the output terminal of the second counter, the inverting input terminal is connected to the second set value, and the output terminal outputs the timeout signal.

8. The wake-up circuit according to claim 1, characterized in that: The control module includes an OR gate and a second selector; The input terminals of the OR gate are respectively connected to the wake-up signal and the timeout signal; The first input terminal of the second selector is connected to the output terminal of the OR gate, the second input terminal is connected to the second level signal, and the control terminal is connected to the inverted signal of the enable signal of the wake-up circuit; wherein, when the enable signal is valid, the first-level wake-up module is reset based on the output signal of the OR gate, and when the enable signal is invalid, the reset signal is locked in the valid state.

9. A chip, characterized in that, The chip at least includes: a main circuit and the wake-up circuit according to any one of claims 1-8; The wake-up circuit provides a wake-up signal for the main circuit; The main circuit is connected to the output terminal of the wake-up circuit, is woken up and works when the wake-up signal is valid, and invalidates the enable signal of the wake-up circuit after being woken up.

10. An electronic product, characterized in that, The electronic product at least includes: the wake-up circuit according to any one of claims 1-8.

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