A dynamic adaptive interrupt processing method and interrupt processing system

Abstract

The present invention provides a dynamic adaptive interrupt processing method and system. The method comprises: real-time acquisition of multiple operating status parameters of each peripheral module in a processor, evaluating the interrupt priority of each interrupt based on a priority evaluation model; predicting the number of triggers of each interrupt in a future time period based on the historical trigger count of each interrupt based on a prediction algorithm; determining an interrupt scheduling strategy based on the interrupt priority of each interrupt and the number of triggers in the future time period; regularly evaluating the efficiency of the interrupt scheduling strategy, and adjusting the parameters of the priority evaluation model and the prediction algorithm based on the evaluation results to adjust the interrupt scheduling strategy. Through the present invention, the priority of each interrupt can be adjusted in real time based on the operating status parameters of the peripheral module, and a corresponding interrupt scheduling strategy can be generated. The method is suitable for performance-constrained scenarios where MCU resources are limited, real-time requirements are high, and power consumption requirements are high.

Description

Technical Field

[0001] The present invention relates to the field of interrupt processing, and more particularly to a dynamic adaptive interrupt processing method and an interrupt processing system. Background Art

[0002] As the core component of embedded systems, processors are widely used in real-time control and data processing scenarios. In processor driver development, interrupt handling is a key technology to ensure system real-time performance and efficiency.

[0003] Traditional interrupt handling mechanisms usually adopt fixed priority, static scheduling policy or round-robin priority method, such as setting fixed interrupt priority through nested vectored interrupt controller (NVIC).

[0004] The traditional interrupt handling mechanism has the following defects:

[0005] 1. Interrupt conflicts: Under high load, multiple peripheral modules (such as UART, SPI, and I2C) trigger interrupts simultaneously. The fixed priority mechanism may cause low-priority interrupts to be blocked for a long time, affecting system real-time performance. While the round-robin priority mechanism does not cause low-priority interrupts to be blocked for a long time, it may cause high-priority interrupts to be delayed, which also affects system real-time performance.

[0006] 2. Resource waste: Traditional methods do not consider the dynamic characteristics of interrupt processing. For example, some interrupts may be inactive during a specific time period but still occupy system resources.

[0007] 3. Development complexity: Driver development engineers need to manually adjust interrupt priorities and scheduling strategies, increasing development and maintenance costs.

[0008] 4. Power consumption issue: In low-power application scenarios, frequent interrupt processing may lead to unnecessary power consumption overhead.

[0009] Therefore, the traditional interrupt handling mechanism cannot meet the needs well in application scenarios with high real-time requirements, limited CPU resources, and high power consumption requirements. Summary of the Invention

[0010] The present invention aims to solve the technical problems existing in the prior art and provides a dynamic adaptive interrupt processing method and an interrupt processing system, which overcomes the problem that the requirements cannot be met well in application scenarios with high real-time requirements, limited CPU resources, and high power consumption requirements.

[0011] According to a first aspect of the present invention, there is provided a dynamic adaptive interrupt processing method, comprising:

[0012] Real-time acquisition of multiple operating status parameters of each peripheral module in the processor, wherein the multiple operating status parameters include interrupt trigger frequency, data throughput, active time, and task real-time requirements, wherein each peripheral module triggers one or more interrupts;

[0013] Evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the real-time requirement of the task of each interrupt;

[0014] Based on the number of times each interrupt has been triggered in the historical time period, the prediction algorithm is used to predict the number of times each interrupt will be triggered in the future time period.

[0015] Determine the interrupt scheduling strategy for each interrupt based on its interrupt priority and the number of times it is triggered in the future time period;

[0016] Processing each interrupt according to the interrupt scheduling strategy;

[0017] The efficiency of the interrupt handling strategy is evaluated regularly, and the parameters of the priority evaluation model and the prediction algorithm are adjusted according to the evaluation results to adjust the interrupt scheduling strategy.

[0018] According to a second aspect of the present invention, there is provided a dynamic adaptive interrupt handling system comprising a dynamic monitoring module, a priority evaluation module, an interrupt prediction module, an interrupt scheduling module and an interrupt optimization module;

[0019] The dynamic monitoring module is used to collect multiple working status parameters of each peripheral module in the processor in real time, wherein the multiple working status parameters include interrupt triggering frequency, data throughput, active time and task real-time requirements, wherein each peripheral module triggers one or more interrupts;

[0020] The priority evaluation module is configured to evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt triggering frequency, the data throughput, the active time, and the real-time requirement of the task of each interrupt;

[0021] The interrupt prediction module is used to predict the number of times each interrupt will be triggered in the future time period based on the prediction algorithm according to the number of times each interrupt has been triggered in the historical time period;

[0022] An interrupt scheduling module, configured to determine an interrupt scheduling policy for each interrupt based on the interrupt priority of each interrupt and the number of times it is triggered in a future time period, and to process each interrupt according to the interrupt scheduling policy;

[0023] The interrupt optimization module is used to regularly evaluate the efficiency of the interrupt handling strategy and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

[0024] The present invention provides a dynamic adaptive interrupt processing method and interrupt processing system, which collects multiple working state parameters of each peripheral module in the processor in real time; evaluates the interrupt priority of each interrupt based on a priority evaluation model according to the multiple working state parameters; predicts the triggering number of each interrupt in a future time period based on a prediction algorithm according to the historical triggering number of each interrupt; determines the interrupt scheduling strategy of each interrupt according to the interrupt priority and the triggering number in the future time period; speeds up the time consumed by interrupt execution through context caching and tail chaining technology; dynamically adjusts the power state of the corresponding module to reduce power consumption during the inactive interrupt switching period; regularly evaluates the efficiency of the interrupt scheduling strategy, and adjusts the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy. Through the present invention, the priority of each interrupt can be evaluated in real time according to the working state parameters of the peripheral module, the priority of each interrupt can be dynamically adjusted, and the corresponding interrupt scheduling strategy can be given. The method is suitable for scenarios with limited performance under scenarios with tight MCU resources, high real-time requirements, and high power consumption requirements. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 A flow chart of a dynamic adaptive interrupt processing method provided by one embodiment of the present invention;

[0026] Figure 2 This is an overall flow chart of a dynamic adaptive interrupt processing method according to an embodiment of the present invention;

[0027] Figure 3 A flowchart for calculating the priority score of an interrupt for one embodiment of the present invention;

[0028] Figure 4 A flowchart of predicting the number of future interrupt triggering times according to an embodiment of the present invention;

[0029] Figure 5 A structural block diagram of a dynamic adaptive interrupt processing system provided by one embodiment of the present invention. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention. In addition, the technical features in the various embodiments or single embodiments provided by the present invention can be arbitrarily combined with each other to form a feasible technical solution. This combination is not restricted by the sequence of steps and / or structural composition mode, but must be based on the ability of ordinary technicians in this field to implement it. When the combination of technical solutions is contradictory or cannot be implemented, it should be deemed that such a combination of technical solutions does not exist and is not within the scope of protection required by the present invention.

[0031] Figure 1 A flow chart of a dynamic adaptive interrupt processing method provided by the present invention is as follows: Figure 1 and Figure 2 As shown, the dynamic adaptive interrupt processing method includes:

[0032] Step 1: collect multiple working status parameters of each peripheral module in the processor in real time, wherein the multiple working status parameters include interrupt trigger frequency, data throughput, active time and task real-time requirements, wherein each peripheral module triggers one or more interrupts.

[0033] It's understandable that a processor (SoC chip) includes multiple peripheral modules, each of which may trigger one or more interrupts. When a processor's peripheral modules trigger a large number of interrupts simultaneously, processing congestion can occur. Therefore, it's necessary to configure an interrupt scheduling policy to handle these numerous interrupts in an orderly manner.

[0034] First, the working status parameters of each peripheral module are obtained. The working status parameters include interrupt trigger frequency, data throughput, module active time, module power consumption status and task real-time requirements.

[0035] Among them, a hardware counter (such as a hardware timer in a processor) is used to count the interrupt trigger frequency of each module (such as UART) and record it as Freq_module (times / second);

[0036] Use the DMA controller to count the data throughput of each module (such as SPI) and record it as Trans_module (bytes / second);

[0037] Use PMU (Power Management Unit) to count the power consumption of each module and record it as Power_module (milliwatts).

[0038] Step 2: Evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the task real-time requirement of each interrupt.

[0039] It is understandable that step 1 obtains the interrupt-related parameters of each peripheral module. This step evaluates the priority of each interrupt based on these parameters and generates an interrupt priority mapping table. In an embodiment of the present invention, a weighted scoring method is used to evaluate the priority of each interrupt based on the priority evaluation model. Multi-dimensional data (Freq_norm, Trans_norm, Active_norm, Real_norm) is input into the priority evaluation model, and the output is the priority score S_priority. The weight coefficient of the priority evaluation model is updated regularly to adapt to different application scenarios. For example, in the field of industrial control, the weight of Real_norm (w4=0.4) for real-time requirements can be increased.

[0040] For details, see Figure 3 The priority evaluation model constructs an interrupt priority evaluation model based on the relevant parameters of each collected interrupt, and calculates the priority score S_priority of each interrupt source. The formula is as follows: S_priority=w1*Freq_norm+w2*Trans_norm+w3*Active_norm+w4*Real_norm; where: Freq_norm, Trans_norm, and Active_norm are the interrupt trigger frequency, data throughput, and active time after normalization (mapping data to [0,1]); Real_norm is the normalized value of the task real-time requirement, which is provided by the RTOS task priority or the user; w1, w2, w3, and w4 are weight coefficients, which can be dynamically adjusted through the policy optimization module, and the default values ​​are 0.3, 0.3, 0.2, and 0.2.

[0041] The interrupt priority of each interrupt is determined according to the priority score of each interrupt, and an interrupt priority mapping table is generated; wherein the priorities of all interrupts are sorted according to the priority score, the interrupt with a large priority score has a large priority, and the interrupt with a small priority score has a small priority.

[0042] Step 3: According to the number of times each interrupt is triggered in the historical time period, the number of times each interrupt is triggered in the future time period is predicted based on a prediction algorithm.

[0043] In one embodiment of the present invention, based on the number of times each interrupt is triggered in a historical time period, the number of times each interrupt is triggered in a future time period is predicted based on a prediction algorithm, including:

[0044] Get the trigger time series {t1, t2, ..., t n}, convert the trigger time series into the number of interrupt triggers within the time window, where t1, t2, ..., t n Indicates the time when the interrupt is triggered within the historical time period, where n is the time index;

[0045] Count the number of interrupt triggers in each time window and generate the interrupt trigger sequence {X1, X2, ..., X m}, where X1, X2, …, X m Indicates the number of interrupt triggers in each time window;

[0046] According to the interrupt trigger sequence {X1, X2, ..., X m}, based on the prediction algorithm, the number of times each interrupt will be triggered in a future time window is predicted, and m is the number of time windows included in the historical time period.

[0047] For details, see Figure 4 , based on time series analysis algorithms (such as exponential smoothing or ARIMA model), predict the number of interrupt triggers in the next 10ms. For example, for the UART module, input the interrupt trigger time series {t1, t2, ..., t n}, output the interrupt trigger count S_t in the next 10ms. Example steps are as follows:

[0048] 1. {t1, t2, …, t n} is the timestamp of the interrupt trigger, which is converted into the number of interrupts within the time window.

[0049] 2. Assuming 1ms as the time window (50ms is divided into 50 1ms windows), count the number of interruptions in each time window and generate the sequence {X1, X2, ..., X 50}.

[0050] If t1 = 2.3ms, t2 = 2.7ms, t3 = 5.1ms, then: the 2nd ms time window: 2 interrupts (2.3ms and 2.7ms), the 5th ms time window: 1 interrupt (5.1ms), other time windows: 0 interrupts, count the total number of interrupts within 50ms, and generate a sequence of interrupt triggering times for each time window {X1, X2, ..., X 50}.

[0051] 3. Use exponential smoothing to predict the number of future interrupt triggers: S_t = α*X_t + (1-α)*S_(t-1), where S_t is the smoothed value, estimating the number of interrupt triggers within a future 1ms window; X_t is the number of interrupt triggers in the current 1ms window; and S_(t-1) is the average number of interrupt triggers within a historical 50ms window (total interrupt triggers within 50ms / 50). The calculated S_t is the number of interrupt triggers within a future 1ms window. Therefore, the number of interrupt triggers within the next 10ms is 10*S_t (10 1ms windows).

[0052] Step 4: Determine the interrupt scheduling strategy for each interrupt based on the interrupt priority of each interrupt and the number of triggers in the future time period.

[0053] It is understandable that the scheduling strategy for each interrupt is determined based on the priority of each interrupt and the probability of triggering in the future. Among them, the interrupt scheduling strategy includes interrupt masking, interrupt merging, and interrupt delay processing. Specifically, if the trigger count S_t of an interrupt source (such as I2C) is lower than the threshold, the interrupt is temporarily masked by the interrupt controller; if multiple low-priority interrupts (such as GPIO and timer interrupts) are frequently triggered in a short period of time, they are merged into a batch processing interrupt through software; for non-real-time interrupts (such as logging interrupts), they are delayed through the delay queue mechanism.

[0054] Step 5: Process the interrupt according to the interrupt scheduling policy.

[0055] It is understandable that after determining the scheduling policy for each interrupt, the interrupt is processed. This process involves context switching. The embodiments of the present invention utilize adaptive context switching technology during interrupt processing, reducing unnecessary interrupt context switching overhead (the register state of the current task) through interrupt context caching and interrupt nesting optimization (tail chaining). Traditionally, each interrupt trigger requires a complete context save and restore (approximately 50 instruction cycles). This involves saving the current task's register state (program counter, general registers, status registers, etc.) to a stack area before interrupt processing. After interrupt processing is complete, the saved register state is reloaded into the registers to resume execution of the original task. In S4, through tail chaining and a fast context cache, context switching overhead is reduced to approximately 20 instruction cycles. The fast context cache uses a hardware mechanism (hardware stack frame) to quickly store register states in the stack and restore them from the stack to registers. The tail chaining technology is that after an interrupt is processed, the processor rechecks the interrupt controller (such as NVIC) to see if there is a pending interrupt. If so, the processor jumps directly to the new interrupt entry without restoring the context of the current interrupt or saving the complete context of the new interrupt immediately. Instead, the context is restored after all pending interrupts are processed.

[0056] Based on the predicted future trigger trends of interrupts, the power state of peripheral modules is dynamically adjusted during periods of interrupt inactivity. For example, if the SPI module is predicted to have no interrupt triggers within the next 50ms, the PMU (power management unit) will place the SPI module in low-power mode (by shutting down the clock or reducing the voltage) to reduce overall system power consumption.

[0057] Step 6: regularly evaluate the efficiency of the interrupt handling strategy, and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

[0058] It is understandable that after the interrupt is processed according to the interrupt scheduling strategy, the efficiency of the interrupt processing strategy is evaluated, and the parameters of the priority evaluation model and prediction algorithm are adjusted according to the evaluation results, the priority evaluation of the interrupt and the prediction of the triggering trend are adjusted, and then the interrupt scheduling strategy is adjusted.

[0059] The evaluation of interrupt processing efficiency mainly includes the evaluation of real-time indicators, power consumption indicators and performance indicators of interrupt processing.

[0060] Real-time performance indicator: interruption delay time D_latency (milliseconds), the standard is D_latency < 1ms;

[0061] Power consumption indicator: average power consumption P_avg (milliwatts), the standard is to reduce P_avg by 30%;

[0062] Performance indicator: CPU usage C_usage (100%), with the standard being a 20% reduction in C_usage.

[0063] According to the evaluation results of various indicators of the interrupt handling strategy, the weight coefficients {w1, w2, w3, w4} of the priority evaluation model and the smoothing factor α of the prediction algorithm are adjusted to realize dynamic evaluation of interrupt priority and dynamic prediction of triggering trend, and then dynamically adjust the interrupt scheduling strategy.

[0064] See also Figure 5 , a dynamic adaptive interrupt processing system provided by the present invention, characterized in that it includes a dynamic monitoring module 301, a priority evaluation module 302, an interrupt prediction module 303, an interrupt scheduling module 304 and a strategy optimization module 305.

[0065] The dynamic monitoring module 301 is used to collect multiple working status parameters of each peripheral module in the processor in real time, wherein the multiple working status parameters include interrupt trigger frequency, data throughput, active time and task real-time requirements, wherein each peripheral module triggers one or more interrupts;

[0066] The priority evaluation module 302 is configured to evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt triggering frequency, the data throughput, the active time, and the task real-time requirement of each interrupt;

[0067] The interrupt prediction module 303 is used to predict the triggering number of each interrupt in a future time period based on the prediction algorithm according to the triggering number of each interrupt in a historical time period;

[0068] An interrupt scheduling module 304 is configured to determine an interrupt scheduling policy for each interrupt based on the interrupt priority of each interrupt and the number of times it is triggered in a future time period, and to process the interrupt according to the interrupt scheduling policy;

[0069] The policy optimization module 305 is configured to periodically evaluate the efficiency of the interrupt handling policy and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling policy.

[0070] Among them, see Figure 5 The dynamic adaptive interrupt processing system provided by the embodiment of the present invention further includes a context switching module 306 and a low power management module 307, wherein:

[0071] A context switching module 306 is used to switch contexts based on context caching and interrupt nesting optimization during interrupt processing;

[0072] The low power management module 307 is used to dynamically adjust the power state of the peripheral module during the interrupt inactivity period according to the predicted number of triggering of each interrupt in the future time period, and put the peripheral module into a low power mode.

[0073] It can be understood that the dynamic adaptive interrupt processing system provided by the present invention corresponds to the dynamic adaptive interrupt processing method provided by the aforementioned embodiments. The relevant technical features of the dynamic adaptive interrupt processing system can refer to the relevant technical features of the dynamic adaptive interrupt processing method, which will not be repeated here.

[0074] The embodiments of the present invention provide a dynamic adaptive interrupt handling method and system. By using an interrupt prediction algorithm (exponential smoothing method), a priority evaluation method, and a fast context switching processing method, the method solves the performance limitations of traditional interrupt handling mechanisms in scenarios with limited MCU resources, high real-time requirements, and high power consumption requirements. The method has the following advantages:

[0075] 1) Dynamic adaptive interrupt processing: Based on the interrupt prediction algorithm, resource allocation is dynamically adjusted, such as interrupt masking, interrupt merging, and interrupt delay, to avoid the waste of CPU resources under static interrupt configuration.

[0076] 2) High Performance: Optimizes interrupt context switching to improve CPU processing efficiency. For example, for nested interrupts, ARM's tail chaining technology is used to avoid repeated context switches. For high-frequency interrupts, interrupt processing efficiency is accelerated by embedding assembly code in the ISR. The SF pointer is used to quickly save and restore register states.

[0077] 3) Low power consumption: Based on the interrupt prediction algorithm, modules that will be inactive for a period of time in the future are placed in a low power state to reduce energy consumption.

[0078] 4) Easy to implement: The interrupt prediction algorithm uses a lightweight algorithm, which is suitable for resource-constrained MCU environments.

[0079] 5) Feedback mechanism: The strategy optimization module monitors and optimizes the prediction algorithm parameters in real time to enhance the robustness of the system.

[0080] 6) High interruption prediction accuracy: Normalization is used to process the parameters required by the interruption prediction algorithm to improve prediction accuracy.

[0081] It should be noted that, in the above embodiments, the description of each embodiment has its own focus. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant description of other embodiments.

[0082] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Thus, the present invention may take the form of an entirely hardware embodiment, an entirely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to magnetic disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0083] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowcharts and / or block diagrams, as well as combinations of processes and / or blocks in the flowcharts and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded computer, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowcharts and / or block diagrams. Figure 1 a process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0084] These computer program instructions may also be stored in a computer readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 a process or multiple processes and / or boxes Figure 1 The function specified in one or more boxes.

[0085] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing the instructions executed on the computer or other programmable device for implementing the process. Figure 1 a process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0086] Although the preferred embodiments of the present invention have been described, those skilled in the art may make additional changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0087] Obviously, those skilled in the art may make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if such changes and modifications fall within the scope of the claims and their equivalents, the present invention is intended to include such changes and modifications.

Claims

1. A dynamic adaptive interrupt processing method, characterized in that: include: Real-time acquisition of multiple operating status parameters of each peripheral module in the processor, wherein the multiple operating status parameters include interrupt trigger frequency, data throughput, active time, and task real-time requirements, wherein each peripheral module triggers one or more interrupts; Evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the real-time requirement of the task of each interrupt; Based on the number of times each interrupt has been triggered in the historical time period, the prediction algorithm is used to predict the number of times each interrupt will be triggered in the future time period. Determine the interrupt scheduling strategy for each interrupt based on its interrupt priority and the number of times it is triggered in the future time period; Processing each interrupt according to the interrupt scheduling strategy; The efficiency of the interrupt handling strategy is evaluated regularly, and the parameters of the priority evaluation model and the prediction algorithm are adjusted according to the evaluation results to adjust the interrupt scheduling strategy.

2. The dynamic adaptive interrupt processing method according to claim 1, characterized in that: The real-time acquisition processor collects multiple working status parameters of each peripheral module, including: Use the hardware counter to count the interrupt trigger frequency of each peripheral module in the processor and record it as Freq_module; Use the DMA controller to count the data throughput of each interrupt of each peripheral module in the processor, and record it as Trans_module; Determine the real-time requirements of the task based on the task type and record it as Real_module.

3. The dynamic adaptive interrupt processing method according to claim 1, characterized in that: The step of evaluating the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the real-time requirement of the task of each interrupt includes: Calculating a priority score for each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the real-time requirement of the task of each interrupt; The interrupt priority of each interrupt is determined according to the priority score of each interrupt, and an interrupt priority mapping table is generated; wherein the priorities of all interrupts are sorted according to the priority score, the interrupt with a larger priority score has a higher priority, and the interrupt with a smaller priority score has a smaller priority.

4. The dynamic adaptive interrupt processing method according to claim 3, characterized in that: Calculating the priority score of each interrupt based on a priority evaluation model according to the interrupt trigger frequency, the data throughput, the active time, and the task real-time requirement of each interrupt includes: S_priority=w1*Freq_norm+w2*Trans_norm+w3*Active_norm+w4*Real_norm; Wherein: Freq_norm is the normalized interrupt trigger frequency, Trans_norm is the normalized data throughput, Active_norm is the normalized active time, Real_norm is the normalized task real-time requirement, S_priority is the interrupt priority score, w1, w2, w3 and w4 are the weight coefficients of the interrupt trigger frequency, the data throughput, the active time and the task real-time requirement respectively.

5. The dynamic adaptive interrupt processing method according to claim 4, characterized in that: Based on the number of times each interrupt has been triggered in the historical time period, the prediction algorithm is used to predict the number of times each interrupt will be triggered in the future time period, including: Get the trigger time series {t1, t2, ..., t n }, convert the trigger time series into the number of interrupt triggers within the time window, where t1, t2, ..., t n Indicates the time when the interrupt is triggered within the historical time period, where n is the time index; Count the number of interrupt triggers in each time window and generate the interrupt trigger sequence {X1, X2, ..., X m }, where X1, X2, …, X m Indicates the number of interrupt triggers in each time window, and m is the number of time windows in the historical time period; According to the interrupt trigger sequence {X1, X2, ..., X m }, based on the prediction algorithm, the number of times each interrupt will be triggered in a future time window is predicted.

6. The dynamic adaptive interrupt processing method according to claim 5, characterized in that: The interrupt trigger sequence {X1, X2, ..., X m }, based on the prediction algorithm, predict the number of times each interrupt will be triggered in a future time window, including: S_t = α*X_t+(1-α)*S_(t-1); Among them, S_t is the predicted number of times each interrupt is triggered in a future time window; X_t is the number of interrupt triggers in the current time window, S_(t-1) is the average number of interrupt triggers in all time windows in the historical time period, and α is the smoothing factor.

7. The dynamic adaptive interrupt processing method according to claim 1, characterized in that: The method of determining the interrupt scheduling strategy for each interrupt based on the interrupt priority of each interrupt and the number of times it is triggered in a future time period includes: If the number of times an interrupt is triggered in a future time period is lower than a preset threshold, temporarily shielding the interrupt through the interrupt controller; If multiple low-priority interrupts are triggered frequently within a short period of time, the software will merge the multiple interrupts into one batch processing interrupt; For non-real-time interrupts, the interrupts are delayed by a delay queue mechanism; According to the predicted number of times each interrupt is triggered in a future time period, the power state of the peripheral module is dynamically adjusted during the interrupt inactivity period, and the peripheral module is placed in a low power consumption mode.

8. The dynamic adaptive interrupt processing method according to claim 6, characterized in that: Regularly evaluating the efficiency of the interrupt handling strategy and adjusting the parameters of the priority evaluation model and the prediction algorithm based on the evaluation results, including: After processing the interrupt according to the interrupt scheduling policy, the interrupt delay time, average power consumption and CPU occupancy of each interrupt are obtained; Evaluate the efficiency of the interrupt handling strategy based on the interrupt delay time of each interrupt, the average power consumption of the processor, and the CPU occupancy rate to obtain an evaluation result; The weight coefficients w1, w2, w3 and w4 in the priority evaluation model and the smoothing factor α of the prediction algorithm are adjusted according to the evaluation result.

9. The dynamic adaptive interrupt processing method according to claim 1, characterized in that: Also includes: During interrupt handling, context switching is performed based on context caching and interrupt nesting optimization.

10. A dynamic adaptive interrupt processing system, characterized in that: Including dynamic monitoring module, priority assessment module, interruption prediction module, interruption scheduling module, and interruption optimization module; The dynamic monitoring module is used to collect multiple working status parameters of each peripheral module in the processor in real time, wherein the multiple working status parameters include interrupt triggering frequency, data throughput, active time and task real-time requirements, wherein each peripheral module triggers one or more interrupts; The priority evaluation module is configured to evaluate the interrupt priority of each interrupt based on a priority evaluation model according to the interrupt triggering frequency, the data throughput, the active time, and the real-time requirement of the task of each interrupt; The interrupt prediction module is used to predict the number of times each interrupt will be triggered in the future time period based on the prediction algorithm according to the number of times each interrupt has been triggered in the historical time period; An interrupt scheduling module, configured to determine an interrupt scheduling policy for each interrupt based on the interrupt priority of each interrupt and the number of times it is triggered in a future time period, and to process each interrupt according to the interrupt scheduling policy; The interrupt optimization module is used to regularly evaluate the efficiency of the interrupt handling strategy and adjust the parameters of the priority evaluation model and the prediction algorithm according to the evaluation results to adjust the interrupt scheduling strategy.

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