System and method for dynamically combining memory resource allocation of multi-level switch

Abstract

The invention discloses a system and a method for dynamic combination memory resource allocation of a multi-level exchanger, and relates to the technical field of computers, which comprises the following steps: dynamically acquiring and analyzing type data of a target configuration space when a server is started, identifying a first hardware resource connected with a current peripheral interconnection link by an identification engine according to the type data, and when the first hardware resource comprises the multi-level switch, identifying the second hardware resource connected with the multi-level switch, and determining which devices need to be subjected to resource reservation according to the identification result of the second hardware resource without checking each possible connection condition one by one. And the first memory resource is allocated for the multi-level switch and the second hardware resource based on the second identification result, so that the situation that when the peripheral interconnection link has too many switches, the server starts to consume too much time for resource allocation is avoided, the time consumption during server starting is reduced, the starting efficiency of the server is improved, and the user experience is improved. And the stationarity and the stability of memory resource allocation are further ensured.

Description

Technical Field

[0001] The present invention relates to the field of computer technology, and in particular, to a system and method for dynamically allocating memory resources of a multi-level switcher. Background Art

[0002] There are many devices inside the intelligent network card, such as physical or virtual devices such as network port devices, virtual network cards, storage devices, etc. These devices all need to use memory resources and some memory resources are prioritized. For example, 32-bit memory resources need to be highly prioritized. However, some DPU (Data Processing Unit) devices also contain Switch chips inside, and other PCI devices are also connected under the Switch chips. At this time, memory resources also need to be allocated. At the same time, in addition to the DPU device containing the Switch chip in the server, the motherboard or PCI device card of the server will also contain a similar Switch chip. Similarly, the Switch chip and the PCI devices below it also need resources. However, the 32-bit memory resources are limited and the maximum is 4GB. If it exceeds 4GB, some devices will not be able to be used, such as the interfaces of the display function (DPU display interface or on-board VGA interface) will not be able to display.

[0003] The related technology reserves resources at server startup. However, the Switch chip can include multiple levels and for each level, some need to reserve memory resources while some do not. Whether to reserve resources depends on the use of the port and the device. At this time, since the server may involve many Switch chips and the levels of the Switch chips are not fixed and it is impossible to predict which Switch chip specifically needs to reserve resources, the server startup time is significantly prolonged. Summary of the Invention

[0004] The present invention provides a memory resource allocation method, an electronic device, a storage medium, and a program product to at least solve the problem that the memory resource allocation method in the related technology results in a long server startup time.

[0005] The present invention provides a system for dynamically allocating combined memory resources of a multi-level switch, including: at least one processing circuit of a server, the at least one processing circuit being interconnected with at least one peripheral interconnect link, and the at least one processing circuit being configured to: execute a reading engine, the reading engine reading type data of a target configuration space when the server starts up; propagate the type data to an identification engine, the identification engine identifying a first hardware resource connected to the current peripheral interconnect link according to the type data, and if the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; propagate the identification result of the identification engine to an allocation engine, the allocation engine determining, according to the first identification result of the first hardware resource, that when the current peripheral interconnect link is connected to a multi-level switch, allocating a first memory resource to the multi-level switch and the second hardware resource according to the second identification result of the second hardware resource.

[0006] The present invention also provides a server including the above system for dynamically allocating combined memory resources of a multi-level switch.

[0007] The present invention also provides a method for dynamically allocating combined memory resources of a multi-level switch, using at least one processing circuit interconnected with at least one peripheral interconnect link, wherein the at least one processing circuit is configured to: execute a reading engine, the reading engine reading type data of a target configuration space when the server starts up; propagate the type data to an identification engine, the identification engine identifying a first hardware resource connected to the current peripheral interconnect link according to the type data, and if the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; propagate the identification result of the identification engine to an allocation engine, the allocation engine determining, according to the first identification result of the first hardware resource, that when the current peripheral interconnect link is connected to a multi-level switch, allocating memory resources to the multi-level switch and the second hardware resource according to the second identification result of the second hardware resource.

[0008] The present invention also provides a computer-readable storage medium storing a computer program, wherein when the computer program is executed by a processor, the steps of any of the above methods for dynamically allocating combined memory resources of a multi-level switch are implemented.

[0009] The present invention also provides a computer program product including a computer program, wherein when the computer program is executed by a processor, the steps of any of the above methods for dynamically allocating combined memory resources of a multi-level switch are implemented.

[0010] In the present invention, when the server is started, type data of a target configuration space is dynamically obtained and analyzed. The recognition engine identifies the first hardware resource connected by the current peripheral interconnect link according to the type data. When the first hardware resource includes a multi-level switch, the second hardware resource connected by the multi-level switch is identified, and which devices need to perform resource reservation is determined according to the second recognition result of the second hardware resource, without checking each possible connection situation one by one. And based on the second recognition result, the first memory resource is allocated to the multi-level switch and the second hardware resource, avoiding excessive time consumption for resource allocation when there are too many switches in the peripheral interconnect link during server startup, so as to reduce the time consumption during server startup, improve the startup efficiency of the server, and further ensure the fixity and stability of memory resource allocation. Therefore, the technical problem of long server startup time caused by the memory resource allocation method in the related art can be solved. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] In order to more clearly illustrate the embodiments of the present invention, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present invention, and those of ordinary skill in the art can obtain other drawings based on these drawings without creative efforts.

[0012] Figure 1 Schematic diagram of a system for dynamically combining memory resource allocation of a multi-level switch provided by an embodiment of the present invention; Figure 2 Link schematic diagram of a Switch chip provided by an embodiment of the present invention; Figure 3 Link example diagram of a multi-level Switch chip provided by another embodiment of the present invention; Figure 4 Schematic diagram of the physical connection of a server motherboard provided by an embodiment of the present invention; Figure 5 Structural schematic diagram of a DPU device provided by an embodiment of the present invention; Figure 6 Flowchart of a method for dynamically combining memory resource allocation of a multi-level switch provided according to an embodiment of the present invention; Figure 7 Component execution connection diagram of a system for combining memory resource allocation of a multi-level switch during the server startup phase provided according to an embodiment of the present invention; Figure 8 Example diagram of memory resource allocation of a server during the startup phase provided by an embodiment of the present invention; Figure 9 Example diagram of memory resource allocation of a server during the startup phase provided by another embodiment of the present invention; Figure 10 It is a connection relationship diagram of components of a multi - level switch combined memory resource allocation system when the server enters the operating system stage according to an embodiment of the present invention; Figure 11 It is an example diagram of memory resource allocation when the server enters the operating system provided by an embodiment of the present invention. Detailed implementation manners

[0013] Next, the technical solutions in the embodiments of the present invention will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts belong to the protection scope of the present invention.

[0014] It should be noted that in the description of the present invention, the terms "include", "comprise" or any other variant thereof are intended to cover non - exclusive inclusion, so that a process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed, or further includes elements inherent to such process, method, article or device. The terms "first", "second", etc. in the present invention are used to distinguish similar objects, rather than to describe a specific order or sequence.

[0015] In order to enable those skilled in the art of the present technology to better understand the solution of the present invention, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific implementation manners.

[0016] An embodiment of the present invention provides a system for dynamically combining memory resources of a hierarchical switch.

[0017] As Figure 1 shown, the system 10 for dynamically combining memory resources of a hierarchical switch includes: At least one processing circuit 11 of the server, at least one processing circuit 11 is connected to at least one peripheral interconnect link, and at least one processing circuit 11 is configured to: execute a reading engine to read type data of a target configuration space when the server starts; propagate the type data to an identification engine, and the identification engine identifies a first hardware resource connected to the current peripheral interconnect link according to the type data. If the first hardware resource includes a multi - level switch, identify a second hardware resource connected to the multi - level switch; propagate the identification result of the identification engine to an allocation engine, and the allocation engine, according to the first identification result of the first hardware resource, when it is determined that the current peripheral interconnect link is connected to a multi - level switch, allocates a first memory resource to the multi - level switch and the second hardware resource according to the second identification result of the second hardware resource.

[0018] Among them, the target configuration space can be the PCI configuration space. When the server starts up, the BIOS (Basic Input / Output System) of the embodiment of the present invention reads the type and subtype of the PCI (Peripheral Component Interconnect) configuration space during the PCI enumeration stage in the DXE phase. The peripheral interconnect link of the embodiment of the present invention can be a PCI link; the first hardware resources can include peripheral interconnect devices (PCI devices), switches, etc., and the switch can be a Switch chip; a single-layer switch is connected to other devices below it and not connected to a switch; a multi-layer switch is a switch connected to at least one other switch below it, and is a hierarchical structure; the second hardware resources can include PCI devices, peripheral interconnect ports (PCI ports), etc. The link connection of the single-layer switch is as Figure 2 shown, and the link connection of the multi-layer switch is as Figure 3 shown.

[0019] In the embodiment of the present invention, if there are too many devices when the current device starts up, it will cause some device resources to be unable to be effectively allocated, that is, the 4G 32-bit resources cannot meet the limit that the total device demand exceeds 4G, which will cause some devices to be unusable. If all the PCI link devices of the current server are directly connected to the PCI end bridge port of the CPU (Central Processing Unit), there is no need to worry about the shortage of 4G resources. However, if the PCI link passes through a multi-layer Switch chip or multiple PCI root bridges link multiple PCI Switches, there will be a problem of insufficient Switch resource reservation, which will cause the devices in the system to not work properly. Therefore, the embodiment of the present invention first needs to determine the hardware resource data on the current PCI link according to the type and subtype of the PCI configuration space, so as to facilitate subsequent memory resource allocation for all devices of the server. The resource allocation includes both resource reservation allocation and the allocation of currently identified device resources. The physical connection of the server motherboard is as Figure 4 shown. All these hardware resources need to reserve memory resources. Therefore, when the server starts up, it takes too much time to allocate resources, resulting in an extended server startup time and low startup efficiency.

[0020] Specifically, the embodiments of the present invention can read the type data of the PCI configuration space when the server starts up, and the identification engine can identify the first hardware resource connected by the current peripheral interconnect link according to the type data, and determine whether the current PCI link contains a multi-layer Switch chip. When there are too many Switch chips in the PCI link, the BIOS will consume too much time for resource allocation when the server starts up due to the excessive Switch chips. Therefore, in order to optimize the server startup time and ensure the fixed resource allocation of specific Switch chips, the embodiments of the present invention can identify the second hardware resource connected by the multi-level switch, determine which devices need to reserve resources according to the second identification result of the second hardware resource, without checking each possible connection situation one by one, and allocate the first memory resource to the multi-level switch and the second hardware resource, so as to reduce the time consumption when the server starts up and improve the startup efficiency of the server.

[0021] In the embodiments of the present invention, the allocation engine is used to: when it is determined according to the first identification result of the first hardware resource that there is a peripheral interconnect device connected to the current peripheral interconnect link, allocate the first memory resource to the peripheral interconnect device.

[0022] It can be understood that in the embodiments of the present invention, when it is determined according to the first identification result of the first hardware resource that there is a peripheral interconnect device connected to the current peripheral interconnect link, the allocation engine allocates the first memory resource to the peripheral interconnect device and normally allocates 32-bit resources to the peripheral interconnect device.

[0023] In the embodiments of the present invention, the allocation engine is used to: before allocating the first memory resource to the peripheral interconnect device, if the peripheral interconnect device is a data processor, allocate the first memory resource according to the resource size of the data processor.

[0024] Since the DPU (Data Processing Unit) usually has specific memory resource requirements, the embodiments of the present invention can read the identifier of the peripheral interconnect device, identify whether the peripheral interconnect device is a DPU through the identifier, so as to adopt different memory allocation strategies for the peripheral interconnect device. When the peripheral interconnect device is not a DPU, allocate memory resources to it normally. If it is a DPU device, allocate memory resources to the peripheral interconnect device according to the resource size of the DPU to ensure the normal operation of the DPU device.

[0025] It should be noted that the DPU is a dedicated processor that provides virtualization services for data center infrastructure such as network, storage, security, and management around data processing. It is a computing architecture composed of a CPU based on architectures such as ARM / X86 and dedicated hardware acceleration engines such as ASIC (Application Specific Integrated Circuit) / NP (Network Processor) / FPGA (Field Programmable Gate Array), forming an entity that provides virtualization functions. Sufficient resources are required to support the operation of complex services. Therefore, resources need to be reserved. Among them, the structure of the DPU is as Figure 5 shown. Currently, DPU products have been widely used in various architecture servers in data centers (usually in the form of intelligent network cards), including but not limited to X86 architecture and ARM architecture, etc. However, regardless of the architecture of the server, resource reservation for the intelligent network card needs to be carried out in advance when applying the intelligent network card because there are many devices inside the intelligent network card, such as physical or virtual devices such as network port devices, virtual network cards, and storage devices SSD, etc. These devices all need to use memory resources and some memory resources are prioritized. For example, 32-bit memory resources need to be highly prioritized to be satisfied. Therefore, resource reservation for the DPU needs to be carried out in advance to ensure that various devices can obtain the required memory resources and operate normally.

[0026] Among them, based on the identifier, it is judged whether it is a data processor. Specifically, the DID and VID of the peripheral interconnect device can be recognized. If the DID and VID exist in the identifier information list of the pre-set data processor, it is judged that the peripheral interconnect device is a data processor; otherwise, it is not a data processor.

[0027] Specifically, when the server starts up, during the PCI enumeration stage of the DXE phase, the BIOS determines whether the current PCI link contains a Switch chip by reading the type and subtype of the PCI configuration space. If not, it continues to confirm whether the current device is a DPU device by reading the DID and VID of each PCI device. If not, 32-bit memory resources are normally allocated; if it is a DPU device, 32-bit resource reservation is carried out according to the known 32-bit resource size of the DPU; at the same time, when the PCI link physically connected to the current DPU counts the 32-bit resources required by other PCI devices, the MMIO 32-bit resources reserved by the DPU are accumulated. At the same time, the BIOS enables (turns on) the hotplug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0028] For example, the CPU of the server has multiple PCI links. Among them, a DPU device is connected to PCI link A, and several other ordinary PCI devices (including PCI device A and PCI device B) are also connected to PCI link A. There is a PCI link bridge on PCI link A for connecting the CPU and the devices on PCI link A. It can reserve 32-bit memory resources for the DPU device according to its existing 32-bit memory resource size. For example, 200MB of MIMO32 resources are reserved for it. At the same time, it also counts the 32-bit memory resources required by PCI device A and PCI device B on PCI link A. For example, PCI device A requires 30MB and PCI device B requires 15MB. Then the total 32-bit memory resources required by PCI link A are 200 + 30 + 15 = 245MB.

[0029] In the embodiment of the present invention, the allocation engine is used to: according to the first identification result of the first hardware resource, when it is determined that the current peripheral interconnect link is connected with a peripheral interconnect port and a switch, if the peripheral interconnect port is the target port, then allocate the first memory resource to the peripheral interconnect port and the switch.

[0030] It can be understood that in the BIOS of the present invention, during the PCI enumeration stage, by reading the type and subtype of the PCI configuration space, it is confirmed whether there is a Switch chip on the current PCI link and whether it is a specific PCI port (target port). If it is a specific PCI port, 32-bit memory resources are reserved and the uplink and downlink ports of the Switch chip and the hotplug function of the PCI configuration space of the PCI link bridge where the Switch chip is located are enabled; if it is not a specific PCI port and there is a PCI Switch chip, the BIOS no longer enables the hotplug function for the uplink and downlink ports of the Switch chip and reserves the PCI port resources. Thus, by only reserving resources and enabling the hotplug function for specific PCI ports, it can ensure that key devices are supported as necessary while reducing resource allocation to unnecessary ports. If it is not a specific PCI port and there is a PCI Switch chip, the BIOS no longer enables the hotplug function for the uplink and downlink ports of the Switch chip and reserves the PCI port resources, thereby avoiding unnecessary resource occupation and simplifying resource management.

[0031] In the embodiment of the present invention, the allocation engine is used to: if the downlink port of the current-level switch is connected with a peripheral interconnect device, then allocate the first memory resource to the uplink port, downlink port and peripheral interconnect device of the current-level switch; if the downlink port of the current-level switch is idle, then no memory resource is allocated to the uplink port and downlink port of the current-level switch.

[0032] It can be understood that when it is detected that a PCI device is connected to the downstream port of a certain Switch chip, the required memory resources will be allocated to these devices, and the relevant hotplug function will be ensured to be enabled. If there is no device connected to the downstream port at a certain level (i.e., it is idle), no memory resources will be allocated to this port, and the hotplug function will be turned off to save resources.

[0033] Specifically, when there is still a Switch chip at the downstream port of the Switch chip, that is, when there is a physical multi-level Switch chip in the PCI link, it is necessary to reserve resources for the PCI devices at the downstream ports of the multi-level Switch chip and the upstream and downstream ports of the Switch levels passed by the entire PCI link, and set the hotplug function for the PCI configuration space of the PCI link where it is located. By reserving resources only where they are actually needed, unnecessary resource waste can be avoided; if there is no PCI device at the terminal PCI port of the multi-level Switch chip, then there is no need to reserve resources and the hotplug function of the entire PCI link and the upstream and downstream ports of each level of Switch chip will be turned off. If the above two situations cross, then the Switch port that reserves memory resources will reserve memory resources.

[0034] In an embodiment of the present invention, at least one processing circuit 11 is configured to: execute a reading engine, and the reading engine reads the identifier of the peripheral interconnect device; an allocation engine is configured to: determine a first memory resource allocation requirement according to the identifier of the peripheral interconnect device. If it is determined that the peripheral interconnect device has a first memory resource allocation requirement, then allocate the first memory resources to the upstream port, downstream port of the current-level switch, and the peripheral interconnect device.

[0035] Wherein, the identifier is used to identify the type of the peripheral interconnect device, and the identifier can be DID (Device ID) and VID (Vendor ID). In the actual execution process, the BIOS of the embodiment of the present invention reads the DID and VID of each PCI device during the PCI enumeration stage in the DXE phase.

[0036] Based on the identifier information obtained by the reading engine in the embodiment of the present invention, the allocation engine will analyze this information to determine whether it is necessary to reserve the first memory resources for the peripheral interconnect device. If it is determined according to the identifier information of the device that the device indeed requires the allocation of the first memory resources, the allocation engine will allocate the required memory resources to the upstream port, downstream port of the current-level switch (Switch chip), and the peripheral interconnect device itself.

[0037] In an embodiment of the present invention, the allocation engine is configured to: if it is determined that the peripheral interconnect device does not have a first memory resource allocation requirement, then allocate non-memory resources to the downstream port of the current-level switch.

[0038] Specifically, in the embodiment of the present invention, the BIOS will determine the PCI devices of the multi-level Switch chip. When it is confirmed through the VID, DID, type, subtype, etc. that the PCI device requires reserved memory resources, the BIOS will reserve resources and enable the hotplug function for the PCI configuration space of the Switch link and the PCI bridge link where this terminal PCI device is located. If not, non-memory resource reservation will be performed for the downstream port of the Switch where this PCI terminal device is located, and the hotplug function of this downstream port will be disabled. For the upstream port of this Switch, it is necessary to determine whether there are other devices on the downstream port of the current Switch chip. If not, this upstream port will be closed and polled in turn until the hotplug function of this PCI link bridge is disabled. If there are other downstream ports and resource reservation is required, the hotplug function of the upstream port of this Switch chip cannot be disabled.

[0039] Thus, in the embodiment of the present invention, all downstream ports of the PCI device Switch chip are scanned to check whether there are other devices connected. If there are no devices connected to the downstream port of a certain Switch chip, it is considered that the current Switch chip does not carry an actual workload, and this upstream port can be closed and polled in turn until the hotplug function of this PCI link bridge is disabled; if there are other devices in the downstream port of the current Switch chip, the upstream port of this Switch chip must remain enabled, and memory resources need to be reserved for these devices, and the hotplug function is enabled. Thus, by dynamically judging the connection status of the downstream port of the Switch chip, the embodiment of the present invention can avoid unnecessary resource waste.

[0040] In the embodiment of the present invention, at least one processing circuit 11 is used to: execute a setting engine, and the setting engine sets the hotplug function for the peripheral interconnect link where the hardware resource that has been allocated the first memory resource is located.

[0041] In the above embodiment, the embodiment of the present invention can enable the hotplug function for the peripheral interconnect link (such as a PCI link) where the hardware resource that has been allocated the first memory resource is located. By enabling the hotplug function, the required memory resources can be automatically allocated to the device when it is inserted, and these resources can be automatically recycled when the device is removed, realizing dynamic management of resources, improving resource utilization, and avoiding resource waste.

[0042] In the embodiment of the present invention, at least one processing circuit 11 is used to: when the recognition engine polls all peripheral interconnect links, the first hardware resource, and the second hardware resource, execute a start engine, and the start engine starts the operating system of the server.

[0043] It can be understood that when the recognition engine in the embodiment of the present invention polls all the peripheral interconnection links, the first hardware resource, and the second hardware resource, the startup engine is executed to start the operating system of the server and enter the next stage of memory resource allocation, that is, the operating system stage of the server.

[0044] In summary, the process of the first memory resource allocation in the startup stage when the server is started in the embodiment of the present invention is as follows.

[0045] (1) When the server starts, the BIOS determines whether the current PCI link contains a Switch chip by reading the type and subtype of the PCI configuration space in the PCI enumeration stage of the DXE stage. If not, it continues to confirm whether the current device is a DPU device by reading the DID and VID of each PCI device. If it is not, 32-bit memory resources are normally allocated; if it is a DPU device, 32-bit resource reservation is performed according to the known 32-bit resource size of the DPU. At the same time, when the PCI link physically connected to the current DPU counts the 32-bit resources required by other PCI devices, the MMIO 32-bit resources reserved by the DPU are accumulated. At the same time, the BIOS enables the hotplug function of the PCI configuration space of the bridge of the PCI link physically connected to the DPU, that is, turns on the hotplug function. (2) During the PCI enumeration phase, the BIOS confirms the presence of a Switch chip and whether it is a specific PCI port by reading the type and subtype of the PCI configuration space. If it is a specific PCI port, the BIOS reserves 32-bit memory resources, sets the upstream and downstream ports of the Switch chip, and enables the hotplug function for the PCI configuration space of the PCI link bridge where the Switch chip is located. If it is not a specific PCI port and there is a PCI Switch chip, the BIOS does not enable the hotplug function for the upstream and downstream ports of the Switch chip and does not reserve PCI port resources. When there is a Switch chip on the downstream port of the Switch chip, that is, when there is a physical multi-level Switch chip on the PCI link, it is necessary to reserve resources for the PCI devices on the downstream port of the multi-level Switch chip and the upstream and downstream ports of the Switch levels passed by the entire PCI link, and set the hotplug function for the PCI configuration space of the PCI link where it is located. If there is no PCI device on the terminal PCI port of the multi-level Switch chip, there is no need to reserve resources, and the hotplug function for the entire PCI link and the upstream and downstream ports of each level of the Switch chip is turned off. If there is an intersection of the above two situations, the Switch port that reserves memory resources will be used to reserve memory resources. At the same time, the BIOS will judge the terminal device of the multi-level Switch chip. If it is confirmed that it is a PCI device that needs to reserve memory resources through VID, DID, type, subtype, etc., the BIOS will reserve resources for the PCI configuration space of the Switch link and the PCI bridge link where this terminal PCI device is located and enable the hotplug function. If not, non-memory resources will be reserved for the downstream port of the Switch where this PCI terminal device is located, and the hotplug function of this downstream port will be turned off. For the upstream port of this Switch, it is necessary to judge whether there are other devices on the downstream port of the current Switch chip. If not, this upstream port will be closed and polled in turn until the hotplug function of this PCI link bridge is turned off. If there are other downstream ports and resource reservation is required, the hotplug function of the upstream port of this Switch chip cannot be turned off; (3) Poll all PCI link bridges and the Switch chips and their devices under the corresponding PCI link bridges in sequence according to steps 1 and 2. After polling all the PCI links and Switch chips of all CPUs, continue to start and enter the operating system; In summary, the embodiments of the present invention can flexibly adapt to the memory resource requirements of different types of peripheral interconnect devices, switches, and peripheral interconnect ports, avoiding insufficient allocation of memory resources for devices, which may lead to abnormal operation of the devices. At the same time, the utilization rate of memory resources is improved, waste of memory resources is avoided, and thus the overall performance and stability of the server are enhanced.

[0046] In one embodiment of the present invention, at least one processing circuit is configured to: after the server enters the operating system, execute a reading engine, and the reading engine reads the memory allocation function of the server; and an allocation engine, which reallocates the first memory resource of the server according to the memory allocation function.

[0047] Among them, the memory allocation function is used to determine whether resource reallocation is required. The memory allocation function can be identified from the Grub parameters of the operating system and is PCI=realloc.

[0048] Since the resource requirements of the server may change during the stage of entering the operating system, in the embodiments of the present invention, after the server enters the operating system, the memory allocation function of the server is read to determine whether the first memory resource needs to be reallocated.

[0049] In one embodiment of the present invention, at least one processing circuit is configured to: before reallocating the first memory resource of the server according to the memory allocation function, execute a reading engine, and the reading engine reads the reallocation requirement of the server; and an allocation engine, which reallocates the first memory resource of the server according to the reallocation requirement and the memory allocation function.

[0050] It can be understood that the embodiments of the present invention can determine whether the first memory resource of the server needs to be reallocated according to the reallocation requirement and the memory allocation function.

[0051] In the embodiments of the present invention, if the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup stage.

[0052] It can be understood that in the embodiments of the present invention, when the reallocation requirement of the server is not read, the memory allocation function is deleted so as not to reallocate memory resources when the server enters the operating system, and the allocation parameters of the first memory resource in the server startup stage are retained.

[0053] Specifically, when the server enters the operating system, the Grub interface of the operating system defaults to adding the PCI=realloc parameter to the Grub parameters. If there is no need to reallocate the memory resources allocated by the BIOS under the system at this time, the PCI=realloc parameter is removed from the Grub file; if there is a need to reallocate the memory resources allocated by the BIOS under the system at this time, this PCI=realloc parameter is retained, and the operating system will reallocate all PCI resources of the server to ensure the reasonable allocation and utilization of memory resources.

[0054] In an embodiment of the present invention, at least one processing circuit 11 is configured to: execute a scanning engine, and the scanning engine scans all peripheral interconnect links of the server; propagate the scanning data of the scanning engine to an identification engine, and the identification engine identifies the scanning data. If it is identified that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link enable the hot plug function, the first memory resource allocated to the current peripheral interconnect link during the server startup phase is retained.

[0055] It can be understood that the embodiment of the present invention can execute a scanning engine, propagate the scanning data of the scanning engine to an identification engine, and the identification engine identifies the scanning data. When it is identified that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link enable the hot plug function, it indicates that the device may change dynamically, and the first memory resource allocated to the current peripheral interconnect link during the server startup phase is retained to ensure that the device can work properly when accessed or removed and to reasonably allocate memory resources.

[0056] In an embodiment of the present invention, the identification engine is configured to: if it is identified that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link disable the hot plug function, an allocation engine reallocates the first memory resource of the server according to the memory allocation function.

[0057] It can be understood that when the embodiment of the present invention identifies that the hot plug function of the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link is disabled, the first memory resource that has been allocated when the server starts up or the device that cannot allocate the first memory resource is reallocated to achieve flexible allocation of memory resources to meet new memory resource allocation requirements.

[0058] In an embodiment of the present invention, the identification engine is configured to: if it is identified that the current peripheral interconnect link is idle, or the switch connected to the current peripheral interconnect link is idle, stop allocating the first memory resource of the server.

[0059] It can be understood that in the embodiments of the present invention, when the current peripheral interconnect link space or the switch connected to the current peripheral interconnect link is idle, the allocation of the first memory resources of the server is stopped, and these resources are reserved for other more needed tasks or processes, improving the overall utilization rate of the memory resources and enabling the server to operate more efficiently.

[0060] In the embodiments of the present invention, at least one processing circuit 11 is configured to: execute a scanning engine that scans the current peripheral interconnect link level; propagate the scanning data of the scanning engine to an identification engine that identifies the scanning data. If the current peripheral interconnect link level is N, the number of times of reallocating the first memory resources is N + 1; and an allocation engine allocates the first memory resources according to the number of reallocations.

[0061] Since the peripheral interconnect link of the server may have a multi-layer structure, the embodiments of the present invention can scan the current peripheral interconnect link level. If a physical connection of a data switch appears during the scanning process, continue the scanning until all levels of data switches are scanned and the final number of levels is counted. If the number of levels is N, the number of times of reallocating resources is counted as N + 1. After scanning the levels, reallocate the resources for the scanned levels. By counting the number of levels and the number of reallocations, it can provide a basis for subsequent resource reallocation to ensure the accuracy of resource reallocation.

[0062] In the embodiments of the present invention, at least one processing circuit is configured to: execute a reading engine that reads the second memory resources of the server; propagate the remaining resources of the second memory resources to an identification engine that identifies whether the remaining resources are less than a resource threshold; and propagate the identification result of the identification engine to an allocation engine that, when the remaining resources are less than the resource threshold, stops the allocation of the first memory resources of the server and reallocates the hardware resources that do not support the hot-plug function and the first memory resources already allocated to the peripheral interconnect link.

[0063] Among them, the resource threshold can be set according to specific circumstances, such as 4G.

[0064] It can be understood that the embodiments of the present invention can identify the second memory resources to optimize the allocation of the first memory resources. When the remaining resources of the second memory resources are less than the resource threshold, it indicates that the current memory resources are insufficient, and the allocation of the first memory resources of the hardware resources at the current level or the next level is stopped to improve the rationality and effectiveness of the memory resource allocation.

[0065] In an embodiment of the present invention, the allocation engine is further configured to: if any switch of the multi-level switch does not support the hot plug function, re-allocate the first memory resource of the peripheral interconnect link where the switch that does not support the hot plug function is located; if all switches of the multi-level switch support the hot plug function, retain the allocation parameters of the first memory resource in the server startup phase.

[0066] It can be understood that in the embodiment of the present invention, if any switch of the multi-level switch does not support the hot plug function, the first memory resource of the peripheral interconnect link where the switch that does not support the hot plug function is located is re-allocated, so that the memory resource better adapts to the link that does not support the hot plug, avoiding problems caused by the mismatch between the resource allocation related to the hot plug and the actual hardware capabilities, and making the memory resource allocation more reasonable, releasing some memory resources originally reserved for the hot plug function for other more needed places, and improving the overall utilization efficiency of the memory resource; when all switches of the multi-level switch support the hot plug function, the allocation parameters of the first memory resource in the server startup phase are retained to more flexibly adapt to the dynamic changes of the device, and it can avoid system performance fluctuations or configuration errors that may be caused by frequent adjustment of the memory allocation, maintaining the overall performance and stability of the server.

[0067] Specifically, scan the levels of the current PCI link. If a switch physical connection appears during the scanning process, continue the scanning until all levels of the Switch chips are scanned and the final number of levels is counted. If the number of levels is N, the number of times of re-allocating resources is counted as N + 1; after scanning the levels, the system re-allocates resources to the scanned levels. Thus, the embodiment of the present invention can perform detailed resource re-allocation according to the device conditions and hot plug function status of each level, improving the rationality and effectiveness of resource allocation, and avoiding resource conflicts and uneven distribution among devices of multiple levels. Specifically: The purpose of resource allocation is to provide memory resources for the connected peripheral interconnect devices to support their operation. Therefore, if there are no peripheral interconnect devices under the peripheral interconnect link of the current level, it is meaningless to allocate memory resources to this peripheral interconnect link, which will cause resource waste. Therefore, no resource allocation is performed on the bridge of the current level, or the hot plug function of the data switch is turned off, indicating that there will be no device insertion or removal operations on the current data switch, and the first memory resource reserved in the startup phase will not be used due to the access or removal of devices. Therefore, the reserved first memory resource is released for subsequent allocation to other devices, improving the resource utilization rate; If there are peripheral interconnection devices under the peripheral interconnection link at the current level, in order to enable these devices to operate normally, resource allocation is performed on the peripheral interconnection devices. If the hot-plug function of the data switch bridge is enabled, it indicates that there may be access or removal operations on the devices. Therefore, resource allocation is not performed on the peripheral interconnection devices, and the resources are used according to the resource size set at the startup stage of the server to avoid device failures or data loss caused by reallocating resources; If there are peripheral interconnection devices and devices at the next level under the peripheral interconnection link at the current level, resource allocation is performed on the peripheral interconnection devices to ensure normal operation of the devices, and it is determined whether there are peripheral interconnection devices on the peripheral interconnection link at the next level to further determine whether resources need to be allocated to the devices at the next level, so as to achieve reasonable resource allocation for the entire hierarchical structure; If there are no peripheral interconnection devices connected to the peripheral interconnection link at the next level and the hot-plug function is turned off, it means that no new devices will be accessed or removed. Therefore, there is no need to allocate resources to this bridge to avoid wasting resources. If there are peripheral interconnection devices on the peripheral interconnection link at the next level, in order to ensure the normal operation of these devices, memory resources need to be allocated to them to meet the operation requirements of the devices, or the hot-plug function at the next level is enabled, indicating that there may be insertion or removal operations of devices. Therefore, there is no need to reallocate the first memory resources; After resource allocation and judgment are performed on the peripheral interconnection links and devices at all levels, when the resource reallocation of the (N + 1)-th layer is completed, it indicates that the resource allocation work of the entire server system has been completed. Ending the resource allocation can allow the system to enter a stable operation state, avoid unnecessary resource allocation operations, and improve the efficiency and stability of the system.

[0068] Specifically, the specific operations of the embodiment of the present invention after the server enters the operating system are as follows: (1)When the server enters the operating system, the Grub interface of the operating system defaults to adding the PCI=realloc parameter to the Grub parameters. If it is not necessary to reallocate the memory resources allocated by the BIOS under the system at this time, then this parameter is removed in the Grub file; if it is necessary to reallocate the memory resources allocated by the BIOS under the system at this time, then this parameter is retained, and the operating system will reallocate all PCI resources of the server; when the system driver scans that the hotplug function of the PCI configuration space of the PCI bridge, the Switch chip under the PCI bridge, and the downstream port of the Switch chip is enabled, the resources reserved by this device at BIOS startup are retained. If the hotplug function of the PCI configuration space of the PCI bridge, the Switch chip under the PCI bridge, and the downstream port of the Switch chip is disabled, the operating system will reallocate the resources already allocated by the BIOS in the DXE stage or the devices that cannot allocate 32-bit memory resources. If there is no device on the PCI bridge or the Switch chip and the downstream port of the Switch chip of the PCI link and the Hotplug function is disabled, then there is no need to allocate 32-bit memory resources. In this way, it can be ensured that the PCI devices under the system can normally obtain 32-bit memory resources and meet the usage conditions under special requirements; (2)When reallocating resources under the system, it is necessary to scan the PCI bridge devices of each PCI link. Here, only one PCI link is taken as an example for elaboration; first, scan the levels of the current PCI link. If a physical connection of the switch is encountered during the scanning process, continue scanning until all levels of the Switch chips are scanned and the final number of levels is counted. If the number of levels is N, the number of times of reallocating resources is counted as N + 1; after scanning the levels, the system reallocates resources to the scanned levels. If there are no PCI terminal devices under the bridge of the first level, this bridge will not be allocated resources or if the Hotplug function is not enabled, the reserved resources will be released; if there are PCI terminal devices under the bridge of the first level, these terminal devices will be allocated resources. If the Hotplug function of the Switch chip bridge is enabled, the operating system will not allocate resources to this PCI device and it can be used according to the resource size set at BIOS startup; if there are PCI terminal devices and a lower-level bridge device under the bridge of the first level, it is necessary to allocate resources to the PCI terminal devices and determine whether there are PCI terminal devices on the next-level bridge. If there are no terminal devices on the next-level bridge and the hotplug function of the PCI configuration space of the next-level bridge is turned off, this bridge does not need to be allocated resources. If there are PCI terminal devices under the next-level bridge, resources will be allocated to the next-level bridge or if the Hotplug function of the lower-level bridge is enabled, the system does not need to reallocate resources to this Switch and it can be used according to the memory resources allocated at BIOS startup. In this way, resource allocation is carried out for N + 1 levels until the 32-bit resource allocation is completed; when the resource allocation of all PCI devices of the server is completed, if the 4G memory resources meet all the current PCI devices, there is no problem. If there is a shortage of 4G memory resources, when the 32-bit memory resources are allocated to the PCI devices identified at the current level and there are no memory resources available for allocation, the remaining PCI devices at the current level or the Switch bridge chips and PCI devices at the next level will not be allocated resources; if in the multi-level Switch chips of the PCI link, any node's Switch chip does not support the Hotplug function, the system layer will reallocate resources for this PCI link. If in the multi-level Switch chips of the PCI link, each Switch chip level supports the hotplug function, resources will be reserved according to the resource size allocated by the BIOS at server startup and no resource reallocation will be carried out.

[0069] The multi - level switch dynamic combined memory resource allocation system proposed according to the embodiments of the present invention dynamically obtains and analyzes the type data of the target configuration space when the server starts. The recognition engine recognizes the first hardware resource connected by the current peripheral interconnect link according to the type data. When the first hardware resource includes a multi - level switch, it recognizes the second hardware resource connected by the multi - level switch, determines which devices need to reserve resources according to the second recognition result of the second hardware resource, without checking each possible connection situation one by one, and allocates the first memory resource for the multi - level switch and the second hardware resource based on the second recognition result, avoiding excessive time consumption for resource allocation when there are too many switches in the peripheral interconnect link during server startup, reducing the time consumption during server startup, improving the startup efficiency of the server, and thus ensuring the fixity and stability of memory resource allocation. Therefore, it can solve the technical problem that the memory resource allocation method in the related art leads to a long server startup time.

[0070] An embodiment of the present invention also provides a server, including the above - mentioned multi - level switch combined memory resource allocation system.

[0071] An embodiment of the present invention also provides a method for multi - level switch dynamic combined memory resource allocation.

[0072] As Figure 6 shown, the method for multi - level switch dynamic combined memory resource allocation includes the following steps: In step S101, at least one processing circuit connected by at least one peripheral interconnect link is used, where at least one processing circuit is used to: execute a reading engine, and the reading engine reads the type data of the target configuration space when the server starts.

[0073] It can be understood that the embodiments of the present invention can use at least one processing circuit connected by at least one peripheral interconnect link. At least one processing circuit is used to execute a reading engine, and the reading engine reads the type data of the target configuration space when the server starts. The target configuration space can be a PCI configuration space. When the server starts, the BIOS of the embodiments of the present invention reads the type and subtype of the PCI configuration space during the PCI enumeration stage of the DXE phase.

[0074] In step S102, the type data is propagated to the recognition engine. The recognition engine recognizes the first hardware resource connected by the current peripheral interconnect link according to the type data. If the first hardware resource includes a multi - level switch, it recognizes the second hardware resource connected by the multi - level switch.

[0075] It can be understood that the embodiments of the present invention can propagate the type data of the PCI configuration space to the recognition engine, and the recognition engine recognizes the first hardware resource connected by the current peripheral interconnect link, so as to allocate memory resources subsequently.

[0076] In step S103, the recognition result of the recognition engine is propagated to the allocation engine. When the allocation engine determines that the current peripheral interconnect link is connected to a multi-level switch according to the first recognition result of the first hardware resource, according to the second recognition result of the second hardware resource, memory resources are allocated to the multi-level switch and the second hardware resource.

[0077] It should be noted that for the description of the features in the corresponding embodiments of the method for dynamically combining memory resource allocation of a multi-level switch, reference can be made to the relevant description of the corresponding embodiments of the system for dynamically combining memory resource allocation of a multi-level switch, which will not be elaborated here one by one.

[0078] According to the method for dynamically combining memory resource allocation of a multi-level switch proposed by the embodiments of the present invention, by dynamically obtaining and analyzing the type data of the target configuration space at server startup, the recognition engine recognizes the first hardware resource connected by the current peripheral interconnect link according to the type data, and when the first hardware resource includes a multi-level switch, recognizes the second hardware resource connected to the multi-level switch, determines which devices need to reserve resources according to the second recognition result of the second hardware resource, without checking each possible connection situation one by one, and allocates the first memory resource to the multi-level switch and the second hardware resource based on the second recognition result, avoiding excessive time consumption for resource allocation during server startup when there are too many switches in the peripheral interconnect link, reducing the time consumption during server startup, improving the startup efficiency of the server, and thus ensuring the fixity and stability of memory resource allocation. Therefore, the technical problem in the related art that the memory resource allocation method leads to a long server startup time can be solved.

[0079] The following describes the process of dynamically combining memory resource allocation of a multi-level switch in the embodiments of the present invention through a specific embodiment, which specifically includes: The execution connection relationship among the components of the system for dynamically combining memory resource allocation of a multi-level switch during the server startup phase is as Figure 7As shown, during the server startup phase, the BIOS controls the processing circuit. This is equivalent to the BIOS performing memory resource allocation operations during the server startup phase. Specifically: The execution read engine reads the type data of the target configuration space when the server starts up, and propagates the type data to the recognition engine. The recognition engine identifies the first hardware resources (peripheral interconnect devices, switches, etc.). When the first hardware resources include a multi-level switch, it is necessary to identify the second hardware resources (including peripheral interconnect ports, peripheral interconnect devices, etc.) connected to the multi-level switch, and generate a recognition result. The recognition result is transmitted to the allocation engine. When the allocation engine determines that a multi-level switch is connected to the current peripheral interconnect link according to the first recognition result of the first hardware resources, it allocates the first memory resources to the multi-level switch and the second hardware resources according to the second recognition result of the second hardware resources. After the first memory resource allocation is completed, the setting engine sets the hot-plug function for the peripheral interconnect link where the hardware resources that have been allocated the first memory resources are located. Subsequently, the startup engine starts the operating system of the server.

[0080] The following combines Figure 7 the execution connection relationship diagram between the various components in the startup phase shown to describe the specific execution process of memory resource allocation in the server startup phase. The specific process is as shown in Figure 8.

[0081] 1. When the server starts up, in the DXE phase, it judges whether there is a Switch chip on the PCI link by reading the PCI type, subtype, etc. When there is no Switch chip on the PCI link, it directly reads the DID and VID of the PCI device on the PCI link for reading and judgment to confirm whether it is a DPU and a PCI-specific PCI device. If so, it reserves 32-bit memory resources. At the same time, it enables the hotplug function of the bridge of the PCI link where it is located. If it is judged that there is no device, it evaluates whether it is a specific PCI port and needs to reserve memory resources and supports the hotplug function under the system. If there is no device and it is not a PCI port that needs to reserve resources, no memory resources will be allocated. If there is a device and it is not a DPU or a specific device, the normal memory resources can be allocated. It should be noted that when counting the 32-bit resources required by other PCI devices, the MMIO 32-bit resources reserved by the DPU are accumulated for the PCI link physically connected to the current DPU. At the same time, the BIOS enables the hotplug function, that is, turns on the Hotplug function, of the PCI configuration space of the bridge of the PCI link physically connected to the DPU.

[0082] 2. During the PCI enumeration phase, the BIOS confirms the presence of a Switch chip on the current PCI link and whether it is a specific PCI port by reading the type and subtype of the PCI configuration space. If it is a specific PCI port, 32-bit memory resource reservation is performed, and the upstream and downstream ports of the Switch chip and the hotplug function enabling setting of the PCI configuration space of the PCI link bridge where the Switch chip is located are set. If it is not a specific PCI port and there is a PCI Switch chip, the BIOS does not enable the hotplug function for the upstream and downstream ports of the Switch chip and does not reserve PCI port resources.

[0083] 3. When there are multi-level Switch chips on a PCI link, as Figure 9 shown, the BIOS first scans the depth of this PCI link, that is, the Switch level. Assume the Switch level is N. Then it judges whether there is a PCI device at the Nth level. If not, the hotplug function of the Switch downstream port corresponding to this N port is turned off and no memory resources are allocated. If resource reservation is required, the hotplug function of the corresponding Switch N's downstream port is enabled. If there is a PCI device at the Switch downstream port corresponding to the N port, memory resources are allocated. If this port requires reallocation of memory resources under the system, the hotplug function is turned off. If memory resources are not allocated under the system, the hotplug function is turned off. After scanning the Nth level, the same operation is performed on the previous level Switch N-1. At this time, if the hotplug function of the N+1 downstream port of the Nth level is enabled, the corresponding upstream port also needs to be enabled. The hotplug functions of the N-1 level downstream port and the Nth level upstream port need to be enabled. According to this method, all Switch levels are executed until completion, and the hotplug function of the PCI link bridge where the Switch level is located is enabled.

[0084] 4. Poll all PCI link bridges and the Switch chips and their devices under the corresponding PCI link bridges in sequence according to steps 1-3. After polling all the PCI links and Switch chips of the CPUs, continue to start and enter the operating system.

[0085] II. Server entering the operating system phase.

[0086] The execution connection relationship among the components of the multi-level switch dynamic combined memory resource allocation system during the server entering the operating system phase is as Figure 10As shown, the operating system control processing circuit of the server, which is equivalent to the operating system performing the reallocation of the first memory resource during the stage of entering the operating system of the server. Specifically: The execution reading engine reads the memory allocation function of the server and reads whether there is a need for memory resource reallocation; The allocation engine, based on the read result of the memory resource reallocation requirement transmitted by the reading engine, executes the deletion operation of the memory allocation function (i.e., does not reallocate memory resources) or reallocates the first memory resource according to the requirement; After recognizing the instruction to reallocate the first memory resource, the scanning engine is executed. The scanning engine is used for the hierarchical structure of the peripheral interconnect link, hardware resources, settings of the hot-plug function, etc., and transmits the scanned data to the recognition engine; The recognition engine is used to recognize the scanned data and transmit it to the allocation engine; The allocation engine performs the reallocation of the first memory resource.

[0087] The following combines Figure 10 the execution connection relationship diagram among the components in the startup stage shown in the figure to describe the specific execution process of the memory resource allocation when the server enters the operating system stage. The process is as Figure 11 shown, including: 1. When the server enters the operating system, the Grub interface of the operating system defaults to adding the PCI=realloc parameter to the Grub parameters. If there is no need to reallocate the memory resources allocated by the BIOS under the system at this time, then this parameter is removed in the Grub file; If there is a need to reallocate the memory resources allocated by the BIOS under the system at this time, then this parameter is retained, and at this time the operating system will reallocate all PCI resources of the server; When the system driver scans that the Hotplug function of the PCI configuration space of the PCI bridge and the Switch chip under the PCI bridge and the downstream ports of the Switch chip is enabled, the resources reserved by this device during BIOS startup are retained at this time. If the Hotplug function of the PCI configuration space of the PCI bridge and the Switch chip under the PCI bridge and the downstream ports of the Switch chip is disabled, the operating system will reallocate the resources already allocated by the BIOS in the DXE stage or the devices that cannot allocate 32-bit memory resources. If there is no device at the PCI bridge or the Switch chip and the downstream ports of the Switch chip of the PCI link and the Hotplug function is disabled, then there is no need to allocate 32-bit memory resources. In this way, it can be ensured that the PCI devices under the system can normally obtain 32-bit memory resources and meet the usage conditions under special requirements.

[0088] 2. When reallocating resources under the operating system, it is necessary to scan the PCI bridge devices of each PCI link. If there is an N-level Switch chip, an N+1 times resource reallocation scheme will be performed on the Switch chip, and the hotplug function must be enabled for the upstream and downstream ports of each Switch chip and the bridge of the PCI link where the Switch chip is located. If the Hotplug function of any node in the entire link is not enabled, resource reallocation will be performed. If all are enabled, the memory resources allocated during BIIOS startup will be used for allocation. Therefore, when the BIOS starts and there is no Switch chip in the PCI link, the hotplug function needs to be enabled in the PCI configuration space of the bridge of the PCI link where the DPU is located, and the hotplug function of the PCI configuration space of the PCI link bridges of the already recognized PCI devices needs to be enabled. The hotplug function of the PCI configuration space of the PCI bridges that need to support the hotplug function under the system needs to be enabled, and the memory resources allocated by the BIOS are used by default. At the same time, when the PCI link contains a Switch, resources need to be reserved for the PCI settings of the downstream ports of the Switch or the PCI ports that need to reserve resources. The hotplug function of the PCI configuration space of the upstream and downstream ports of the Switch chip and the hotplug function of the PCI configuration space of the PCI link bridge where the Switch chip is located are enabled. When the Hotplug function is enabled in the above PCI link presence and absence of Switch chip scenarios, the operating system is informed that there is no need to reallocate 32-bit memory resources to the DPU, the detected PCI devices, or the PCI link ports that need to support the hotplug function. At the same time, the operating system will allocate resources to all other PCI bridges and PCI devices in the system. First, it is necessary to scan to the level of the Switch, and the memory resources are reallocated by adding 1 to the value obtained according to the level and reserved. If the hotplug function of the PCI bridge is enabled and there is no device, 2M 32-bit memory resources are allocated by default for reservation. If the PCI bridge has no hotplug function and no device, there is no need to reserve 32-bit memory resources. If the PCI bridge has no hotplug function and there is a device, it will be allocated according to the remaining capacity of the 32-bit 4G memory resources that have been allocated. If it meets the resources required by the current device, it will be allocated. If it does not meet the requirements, it will not be allocated and memory resource isolation will be performed.

[0089] In summary, the method for dynamically combining memory resources of the multi-level switch in the embodiment of the present invention uses the BIOS to determine whether there is a Switch chip on the PCI link when the server starts up. If not, it directly determines the PCI devices on the PCI link, especially actively identifies the DPU or specific PCI devices, and enables the Hotplug function for the PCI configuration space of the bridge on the PCI link where the DPU and specific devices are located. For the normally identified PCI devices, resource allocation is performed in the normal mode and the Hotplug function of the PCI link where they are located is turned off. However, for specific ports on the PCI link, resources are reserved and the Hotplug function of the PCI link is enabled. For other PCI links, no resources are allocated and the corresponding PCI link's Hotplug function is turned off; when there is a PCI link Switch chip, it is determined whether the downstream port of the Switch chip needs to reserve resources to support the hotplug function under the system and there is no PCI device, or there is a PCI device on the downstream port. When these two situations occur, the hotplug function of the upstream and downstream ports of the Switch chip and the PCI configuration space of the PCI link bridge is set to be enabled. If there are no special requirements, the Hotplug function of the Switch chip is turned off to facilitate resource reallocation under the system. If there is a PCI Switch chip, the BIOS first scans the depth of this PCI link, that is, the Switch level. Assume the Switch level is N. Then it is determined whether there is a PCI device at the Nth level. If not, the hotplug function of the Switch downstream port corresponding to this N port is turned off and no memory resources are allocated. If there is a PCI device on the Switch downstream port corresponding to the N port, memory resources are allocated. If this port needs to reallocate memory resources under the system, the hotplug function is turned off. If memory resources are not allocated under the system, the hotplug function is turned off. After scanning the Nth level, the same operation is performed on the previous level Switch N-1. At this time, if the hotplug function of the downstream port at the Nth level is enabled, the corresponding upstream port also needs to be enabled. The hotplug functions of the downstream port at the N-1 level and the upstream port at the Nth level need to be enabled. According to this method, all Switch levels are executed until completion, and the hotplug function of the PCI link bridge where the Switch level is located is enabled. Using this new solution is convenient and fast, and can reduce resource reservation for unimportant PCI devices or unused PCI ports.

[0090] After the server enters the operating system, because the PCI=Realloc parameter already exists by default and the operating system will reallocate the memory resources under the system even if the BIOS has completed the memory resource allocation (such as the 32-bit memory resource allocation has been completed), there will still be a reallocation of memory resources under the system. Since the memory resources are limited and the location information of the DPU and specific PCI devices cannot be fixed, according to the function of the parameter, the later recognized PCI devices will have no resources to allocate because the memory resources have been allocated, but the PCI links with the Hotplug function enabled do not need to reallocate memory resources. At the same time, the system will scan the Switch level. If there is an N-level Switch chip, an N+1 times resource reallocation scheme will be performed on the Switch chip, and the hotplug function must be enabled for the upstream and downstream ports of each Switch chip and the bridge of the PCI link where the Switch chip is located. If the Hotplug function of any node in the entire link is not enabled, resource reallocation will be performed. If all are enabled, the memory resources allocated during the BIIOS startup will be used for allocation; when reallocating memory resources, taking the scanned Switch level as N and the scan times as N+1, start allocating 32-bit memory resources to PCI devices from N+1. When the N+1 memory resource allocation is completed, allocate resources to the PCI devices at the N level until all devices of the PCI link bridge have completed resource allocation. If there is insufficient 32-bit memory resources, the memory resource allocation of the subsequent level Switch chips and PCI devices will be abandoned; therefore, it is necessary for the BIOS to enable the Hotplug function of the PCI link where the DPU and specific PCI devices are located by default, and enable the Hotplug function of the upstream and downstream ports of the PCI link Switch chip and the PCI link bridge to avoid the system reallocating again and causing the DPU and specific PCI devices to be unable to be used normally. If the Hotplug function where the DPU and specific PCI devices are located is closed and the DPU device has exhausted the 32-bit memory resources, it will cause the resources of the DPU and specific PCI devices to be released and unable to meet the memory resource requests during normal use, so problems such as the DPU being unable to display or the functions of the DPU or specific PCI devices being unable to be used normally will occur. By setting the above scheme, it can be ensured that the DPU and specific PCI devices can be used normally at any time without worrying about resource problems causing the DPU to be unable to be used; if it is not necessary to reallocate memory resources under the system, then remove the PCI=realloc parameter in the Grub file when the server starts, and by default, use the memory resources allocated during the BIOS process when the server starts without reallocating again under the system.

[0091] It should be noted that when there are too many Switch chips in the PCI link, the BIOS will consume too much time for resource allocation during server startup due to the excessive number of Switch chips. At this time, in order to optimize the server startup time and ensure fixed resource allocation for specific Switch chips, the resources and hotplug function of the Switch chips can be set to reserve resources through the device VID or DID, or through the hierarchical relationship, the BUS, dev, and FUN numbers of the device during BIOS enumeration, so as to reduce the time consumption during server startup, improve the server startup efficiency, and at the same time, perform resource reservation and hotplug function enabling settings for the PCI ports of specific Switch chips and their upstream and downstream ports, as well as the PCI link where the Switch chips are located.

[0092] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method.

[0093] An embodiment of the present invention also provides a computer-readable storage medium, in which a computer program is stored. Among them, the computer program is set to execute the steps in any one of the method embodiments of the above-mentioned multi-level switch dynamic combined memory resource allocation when running.

[0094] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: USB flash drives, read-only memory (ROM for short), random access memory (RAM for short), mobile hard disks, magnetic disks, or optical discs and other various media that can store computer programs.

[0095] An embodiment of the present invention also provides a computer program product. The above computer program product includes a computer program, and when the computer program is executed by a processor, it implements the steps in any one of the method embodiments of the above-mentioned multi-level switch dynamic combined memory resource allocation.

[0096] Those skilled in the art may further realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, computer software, or a combination of both. To clearly illustrate the interchangeability of hardware and software, the composition and steps of each example have been generally described according to functions in the above description. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of the present invention.

[0097] The above has introduced in detail a method for allocating memory resources provided by the present invention. Specific examples are used herein to elaborate on the principle and implementation manner of the present invention. The description of the above embodiments is only used to help understand the method and its core idea of the present invention. It should be noted that for those of ordinary skill in the art, without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the claims of the present invention.

Claims

1. A system for dynamically allocating memory resources in a multi - level switch, characterized in that, Comprising: At least one processing circuit of the server, the at least one processing circuit being connected to at least one peripheral interconnect link, the at least one processing circuit being configured to: Execute a read engine, the read engine reading type data of a target configuration space when the server starts up; Propagate the type data to an identification engine, the identification engine identifying a first hardware resource currently connected to the peripheral interconnect link according to the type data, and if the first hardware resource includes a multi-level switch, identifying a second hardware resource connected to the multi-level switch; Propagate the identification result of the identification engine to an allocation engine, the allocation engine determining, according to the first identification result of the first hardware resource, that when the current peripheral interconnect link is connected to a multi-level switch, and according to the second identification result of the second hardware resource, allocating a first memory resource to the multi-level switch and the second hardware resource.

2. The system for dynamically allocating memory resources for a multi-level switch according to claim 1, characterized in that, The allocation engine is configured to: If a downstream port of the current level switch is connected to a peripheral interconnect device, allocate a first memory resource to the upstream port, the downstream port and the peripheral interconnect device of the current level switch; If the downstream port of the current level switch is idle, do not allocate memory resources to the upstream port and the downstream port of the current level switch.

3. The system for dynamically allocating memory resources in a multi-level switch according to claim 2, characterized in that The at least one processing circuit is configured to: Execute a read engine, the read engine reading an identifier of the peripheral interconnect device; The allocation engine is configured to: determine a first memory resource allocation requirement according to the identifier of the peripheral interconnect device, and if it is determined that the peripheral interconnect device has the first memory resource allocation requirement, allocate a first memory resource to the upstream port, the downstream port and the peripheral interconnect device of the current level switch.

4. The system for dynamically allocating memory resources in a multi-level switch according to claim 3, wherein The allocation engine is configured to: If it is determined that the peripheral interconnect device does not have the allocation requirement for the first memory resource, allocate non-memory resources to the downstream port of the current level switch.

5. The system for dynamically allocating memory resources in a multi-level switch according to claim 1, characterized in that The allocation engine is configured to: According to the first identification result of the first hardware resource, when it is determined that the current peripheral interconnect link is connected to a peripheral interconnect device, allocate a first memory resource to the peripheral interconnect device.

6. The system for dynamically allocating memory resources of a multi-level switch according to claim 5, characterized in that, The allocation engine is configured to: Before allocating a first memory resource to the peripheral interconnect device, if the peripheral interconnect device is a data processor, allocate a first memory resource according to the resource size of the data processor.

7. The system for dynamically allocating memory resources in a multi-level switch according to claim 1, characterized in that, The allocation engine is configured to: According to the first identification result of the first hardware resource, when it is determined that the current peripheral interconnect link is connected to a peripheral interconnect port and a switch, if the peripheral interconnect port is a target port, allocate a first memory resource to the peripheral interconnect port and the switch.

8. The system for dynamically allocating memory resources in a multi-level switch according to any one of claims 1-7, characterized in that The at least one processing circuit is configured to: Execute a setting engine, the setting engine setting a hot plug function for a peripheral interconnect link where a hardware resource that has been allocated a first memory resource is located.

9. The system for dynamically allocating memory resources of a multi-level switch according to claim 1, wherein, The at least one processing circuit is configured to: When the identification engine polls all peripheral interconnect links, the first hardware resource and the second hardware resource, execute a startup engine, the startup engine starting the operating system of the server.

10. The system for dynamically allocating memory resources for a multi-level switch according to claim 9, characterized in that, The at least one processing circuit is configured to: After the server enters the operating system, execute the reading engine, and the reading engine reads the memory allocation function of the server; The allocation engine reallocates the first memory resource of the server according to the memory allocation function.

11. The system for dynamically allocating memory resources in a multi-level switch according to claim 9, wherein The at least one processing circuit is configured to: Before reallocating the first memory resource of the server according to the memory allocation function, execute the reading engine, and the reading engine reads the reallocation requirement of the server; The allocation engine reallocates the first memory resource of the server according to the reallocation requirement and the memory allocation function.

12. The system for dynamically allocating memory resources for a multi-level switch according to claim 10, wherein If the reading engine does not read the reallocation requirement of the server, the allocation engine deletes the memory allocation function and retains the allocation parameters of the first memory resource in the server startup phase.

13. The system for dynamically allocating memory resources in a multi-level switch according to claim 10, characterized in that, The at least one processing circuit is configured to: Execute a scanning engine, and the scanning engine scans all the peripheral interconnect links of the server; Propagate the scanning data of the scanning engine to an identification engine, and the identification engine identifies the scanning data. If it is identified that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link enable the hot plug function, then retain the first memory resource allocated to the current peripheral interconnect link in the server startup phase.

14. The system for dynamically allocating memory resources of a multi-level switch according to claim 13, characterized in that, The identification engine is configured to: If it is identified that the current peripheral interconnect link, the first hardware resource connected to the current peripheral interconnect link, and the switch connected to the current peripheral interconnect link disable the hot plug function, the allocation engine reallocates the first memory resource of the server according to the memory allocation function.

15. The system for dynamically allocating memory resources in a multi-level switch according to claim 13, wherein, The identification engine is configured to: If it is identified that the current peripheral interconnect link is idle, or the switch connected to the current peripheral interconnect link is idle, then stop allocating the first memory resource of the server.

16. The system for dynamically allocating memory resources of a multi-level switch according to any one of claims 10-15, characterized in that The at least one processing circuit is configured to: Execute a scanning engine, and the scanning engine scans the current peripheral interconnect link level; Propagate the scanning data of the scanning engine to an identification engine, and the identification engine identifies the scanning data. If the current peripheral interconnect link level is N, the number of reallocations of the first memory resource is N + 1; The allocation engine allocates the first memory resource according to the number of reallocations.

17. The system for dynamically combining memory resource allocation of a multi-level switch according to claim 16, wherein The at least one processing circuit is configured to: Execute a reading engine, and the reading engine reads the second memory resource of the server; Propagate the remaining resources of the second memory resource to the identification engine, and the identification engine identifies whether the remaining resources are less than a resource threshold; Propagate the identification result of the identification engine to the allocation engine, and when the remaining resources are less than the resource threshold, the allocation engine stops allocating the first memory resource of the server and reallocates the first memory resources already allocated to the hardware resources that do not support the hot plug function and the peripheral interconnect links.

18. The system for dynamically allocating memory resources in a multi-level switch according to claim 17, wherein The allocation engine is further configured to: If any one of the switches in the multi-level switch does not support the hot plug function, reallocate the first memory resource of the peripheral interconnect link where the switch that does not support the hot plug function is located; If all switches of the multi-level switch support the hot plug function, the allocation parameters of the first memory resource in the server startup phase are retained.

19. A server, characterized in that, Comprising: The system for dynamically allocating memory resources of the multi-level switch according to any one of claims 1 to 18.

20. A method for dynamically allocating memory resources in a multi-level switch, characterized in that Comprising: At least one processing circuit connected by at least one peripheral interconnect link, wherein the at least one processing circuit is configured to: Execute a reading engine, which reads type data of a target configuration space when the server starts up; Propagate the type data to an identification engine, which identifies a first hardware resource connected to the current peripheral interconnect link according to the type data, and if the first hardware resource includes a multi-level switch, identifies a second hardware resource connected to the multi-level switch; Propagate the identification result of the identification engine to an allocation engine, which determines that when the current peripheral interconnect link is connected with a multi-level switch according to the first identification result of the first hardware resource, and allocates memory resources for the multi-level switch and the second hardware resource according to the second identification result of the second hardware resource.

21. A computer-readable storage medium, characterized in that, A computer program is stored in the computer-readable storage medium, wherein when the computer program is executed by a processor, the steps of the method for dynamically allocating memory resources of the multi-level switch according to claim 20 are implemented.

22. A computer program product comprising a computer program, characterized in that, When the computer program is executed by a processor, the steps of the method for dynamically allocating memory resources of the multi-level switch according to claim 20 are implemented.

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