Data processing method, electronic device, storage medium and program product

Abstract

The present application provides a data processing method that can be applied to the field of flash memory technology. The data processing method includes: in response to receiving a page read request, reading multiple hard data of a storage page, where the storage page is used to store storage data that is programmed once; hard decoding the multiple hard data separately to obtain multiple check vector sums; using a predetermined check threshold to check the multiple check vector sums to determine the check result of the data stored in the storage page; the check result is used to characterize the validity of the storage data. In this way, the present application can determine whether the storage data that is programmed once in the storage page is invalid data, thereby avoiding erroneous triggering of subsequent data processing procedures for valid data and saving system resources. The present application also provides an electronic device, a storage medium, and a program product.

Description

Technical Field

[0001] The present application relates to the field of flash memory technology, and in particular to a data processing method, electronic device, storage medium and program product. Background Art

[0002] Solid-state drives (SSDs) write invalid data to storage blocks, such as NAND (NAND) open blocks, when the SSD is operating or powered off to ensure data security. However, when performing certain read operations, it can be difficult to determine whether the data stored in the storage block is invalid, making it difficult to perform operations corresponding to the invalid data. This leads to inaccurate operations and wastes system resources. Summary of the Invention

[0003] In view of the above problems, the present application provides a data processing method, electronic device, storage medium and program product.

[0004] According to a first aspect of the present application, a data processing method is provided, comprising: in response to receiving a page read request, reading multiple hard data of a storage page, the storage page being used to store storage data programmed once; hard decoding the multiple hard data separately to obtain multiple check vector sums; checking the multiple check vector sums using a predetermined check threshold to determine a check result of the data stored in the storage page; the check result is used to characterize the validity of the stored data.

[0005] The second aspect of the present application provides an electronic device, comprising: one or more processors; a memory for storing one or more computer programs, wherein the one or more processors execute the one or more computer programs to implement the steps of the above method.

[0006] The third aspect of the present application further provides a computer-readable storage medium having a computer program or instructions stored thereon, which implements the steps of the above method when the computer program or instructions are executed by a processor.

[0007] The fourth aspect of the present application further provides a computer program product, comprising a computer program or instructions, which implement the steps of the above method when executed by a processor.

[0008] According to an embodiment of the present application, by using a predetermined verification threshold to verify the verification vector sum of multiple hard data, it can be determined whether the storage data programmed once in the storage page is invalid data, thereby avoiding erroneous triggering of subsequent data processing procedures for valid data and saving system resources. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] The above contents and other objects, features and advantages of the present application will become more apparent through the following description of the embodiments of the present application with reference to the accompanying drawings, in which:

[0010] Figure 1 An application scenario diagram of the data processing method according to an embodiment of the present application is shown.

[0011] Figure 2 A flow chart of a data processing method according to an embodiment of the present application is shown.

[0012] Figure 3 A flowchart of a method for determining a verification threshold according to an embodiment of the present application is shown.

[0013] Figure 4 A flow chart of a data processing method according to another embodiment of the present application is shown.

[0014] Figure 5 A flow chart of a data processing method according to another embodiment of the present application is shown.

[0015] Figure 6 A flow chart of a data processing method according to another embodiment of the present application is shown.

[0016] Figure 7 The figure shows a structural block diagram of a data processing device according to an embodiment of the present application.

[0017] Figure 8 A block diagram of an electronic device suitable for implementing a data processing method according to an embodiment of the present application is shown. DETAILED DESCRIPTION

[0018] Hereinafter, embodiments of the present application will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present application. In the detailed description below, for ease of explanation, many specific details are set forth to provide a comprehensive understanding of the embodiments of the present application. However, it is apparent that one or more embodiments may also be implemented without these specific details. In addition, in the following description, descriptions of known structures and technologies are omitted to avoid unnecessarily confusing the concepts of the present application.

[0019] The terms used herein are only for describing specific embodiments and are not intended to limit this application. The terms "comprise," "include," etc. used herein indicate the presence of the features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0020] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0021] When expressions such as "at least one of A, B, and C, etc." are used, they should generally be interpreted in accordance with the meaning commonly understood by those skilled in the art (for example, "a system having at least one of A, B, and C" should include but is not limited to a system having A alone, B alone, C alone, A and B, A and C, B and C, and / or A, B, C, etc.).

[0022] In multi-value storage technology, "value" refers to the number of bits stored in each storage cell (cell). For example, when a cell stores only 1 bit of data, it can be recorded as 1-bit / cell and is called a single-level cell (SLC). Multi-level cell devices, on the other hand, allow each cell to store k bits of data (k ≥ 2). Based on this, a storage cell that can store 2 bits of data is called a multi-level cell (MLC), a storage cell that can store 3 bits of data is called a triple-level cell (TLC), and a storage cell that can store 4 bits of data is called a quad-level cell (QLC). QLC can store 4 bits of data, increasing storage capacity by 33% compared to TLC NAND.

[0023] In TLC NAND flash memory, invalid data is only logically invalid, but the data stored in the cell is physically valid, meaning it can be read. Based on this, metadata (meta) can be used to determine whether the data stored in TLC NAND flash memory is logically invalid. If the data is logically invalid, it can be determined to be invalid data.

[0024] Compared to TLC NAND flash memory, which only requires one programming operation to complete data writing, QLC NAND flash memory requires two programming operations to complete the writing of valid data, where the first programming operation is coarse programming and the second programming operation is fine programming. For QLC NAND flash memory, in order to improve the efficiency of data writing to QLC NAND flash memory, invalid data is generally only programmed in the first step and not in the second step. On this basis, because data in QLC NAND flash memory that has only been programmed once is difficult to read effectively, and invalid data stored in QLC NAND flash memory is logically invalid, when performing some read operations on QLC NAND flash memory, it is necessary to use a valid data frame bitmap (Valid Data Frame Bitmap) for reading. However, because the valid data frame bitmap is not completely accurate, invalid data programmed in one step of the QLC NAND flash memory may be mistakenly obtained during the garbage collection operation.

[0025] Based on this, for TLC NAND flash memory, because the data read from the TLC NAND flash memory can be determined to be invalid based on metadata, there is no need to trigger the error correction process for the data read from the TLC NAND flash memory. However, for QLC NAND flash memory, invalid data programmed in one step will cause the low-density parity-check code decoder (LDPC Decoder) to fail error correction, thus entering the error handling process, which will waste a large amount of system backend resources, affecting backend performance and the SSD's Quality of Service (QoS).

[0026] In view of this, an embodiment of the present application provides a data processing method, which can determine whether data stored in a storage page is invalid data.

[0027] Figure 1 An application scenario diagram of the data processing method according to an embodiment of the present application is shown.

[0028] like Figure 1 As shown, the application scenario 100 according to this embodiment may include a controller 1100 and a storage block. For example, the storage block may be an open block, etc. Each storage block may include multiple storage pages 1210. Each storage page 1210 may include multiple QLCs 1211. The controller 1100 may be electrically connected to each QLC 1211 of the storage block, so that data may be written to the QLC 1211 or stored data may be read from the QLC 1211. It is additionally noted that for clarity of illustration, in Figure 1Although the connection lines for connecting the controller 1100 and the plurality of QLCs 1211 are not actually drawn in the figure, it should be understood that the controller 1100 can be electrically connected to the plurality of QLCs 1211 at the same time via the connection lines.

[0029] It should be noted that the data processing method provided in the embodiment of the present application can generally be executed by the controller 1100. Accordingly, the data processing device provided in the embodiment of the present application can generally be set in the controller 1100. The data processing method provided in the embodiment of the present application can also be executed by other devices different from the controller 1100 and capable of communicating with the controller 1100 and / or the storage block. Accordingly, the data processing device provided in the embodiment of the present application can also be set in other devices different from the controller 1100 and capable of communicating with the controller 1100 and / or the storage block.

[0030] It should be understood that Figure 1 The number of controllers 1100, storage pages 1210, and QLCs 1211 in FIG. 1 is merely illustrative, and any number of terminal devices, networks, and servers may be provided as required.

[0031] The following will be based on Figure 1 The scene described by Figures 2 to 6 The data processing method of the application embodiment is described in detail.

[0032] Figure 2 A flow chart of a data processing method according to an embodiment of the present application is shown.

[0033] like Figure 2 As shown, the data processing method of this embodiment includes operations S201 to S203.

[0034] In operation S201 , in response to receiving a page read request, a plurality of hard data of a memory page is read, the memory page being used to store memory data programmed once.

[0035] In operation S202 , hard decoding is performed on a plurality of hard data to obtain a plurality of check vectors and .

[0036] In operation S203 , a plurality of check vector sums are checked using a predetermined check threshold to determine a check result of the data stored in the storage page.

[0037] In an embodiment of the present application, a page read request may be a request to read data stored in a storage page. A storage page may include multiple storage cells. The storage cell may be a QLC. The QLC in the storage page may have only been programmed once and stores the data programmed once. When data is written to a storage page through one-time programming, the storage page should store the correct storage data. The stored data may be valid data or invalid data.

[0038] Hard data can be data directly read from a storage page. For example, a plurality of different threshold voltages can be used to sequentially read the storage page, thereby obtaining a plurality of hard data. Due to the physical characteristics of some storage pages, the hard data may contain errors relative to the correct data written in the above-mentioned one-time programming. Therefore, it is necessary to hard-decode the hard data to correct the errors in the hard data and obtain the corrected storage data. For example, a decoding algorithm can be used to hard-decode the hard data to obtain the correct storage data. During the decoding process, multiple check vectors can be obtained for each hard data, and a check vector sum can be calculated based on the multiple check vectors. This check vector sum can be used to characterize the data error condition of the hard data compared to the correct storage data.

[0039] The predetermined verification threshold can be a pre-set verification vector sum threshold. This threshold can be used to determine whether the verification vector sums of multiple hard data items are within a range that the verification vector sums of invalid data items should be within, thereby verifying the verification vector sums of the multiple hard data items and further determining whether the stored data is invalid. For example, after calculating the verification vector sum, the verification vector sums of the multiple hard data items can be verified using the predetermined verification threshold to obtain a verification result indicating the validity of the stored data. This verification result can be a first verification result or a second verification result. The first verification result can be used to indicate that the stored data is invalid data. The second verification result can be used to indicate that the stored data is valid data.

[0040] On this basis, by using a predetermined verification threshold to verify the verification vector sum of multiple hard data, it is possible to determine whether the storage data programmed once in the storage page is invalid data, thereby avoiding erroneous triggering of subsequent data processing flows for valid data and saving system resources.

[0041] Optionally, hard decoding is performed on any of the multiple hard data to obtain multiple hard decision codewords of the QLC. Multiple check vectors are determined based on a predetermined check matrix and the multiple hard decision codewords. A check vector sum is calculated based on the multiple check vectors.

[0042] For example, a belief propagation algorithm, such as the minimum sum method, can be used to make hard decisions on the hard data, thereby determining multiple hard-decision codewords for each hard data point. The predetermined check matrix can be, for example, a multi-row, multi-column matrix, where the rows of the matrix can represent check equations and the columns can represent codeword bits. Based on this, the check equations for each row of the matrix and the hard-decision codewords can be calculated, and the resulting values are used as check vectors. This yields multiple check vectors for multiple hard-decision codewords. These multiple check vectors are then summed to obtain a check vector sum for each hard data point. If the check vector sum is 0, decoding is considered successful; if the check vector sum is not 0, decoding is considered unsuccessful. If the sums of the multiple hard-decoded check vectors are all 0, the multiple check vector sums can be checked using a predetermined check threshold to obtain a check result. If at least one of the multiple hard-decoded check vector sums is 0, the hard data point can be directly determined to be valid.

[0043] The multiple hard decision codewords may include error codewords, i.e., codewords corresponding to erroneous data in the hard data. The predetermined check threshold may be positively correlated with the number of error codewords. For example, the target number of error codewords may be determined based on a statistical value or a maximum value of the number of error codewords in each of the multiple hard data. For example, the statistical value may be an average, a median, or the like, and the maximum value may be a maximum value. The larger the target number of error codewords, the larger the predetermined check threshold may be. Similarly, the same principle applies, which will not be further described here. In this way, a relatively accurate threshold can be selected to check the check vector sum, thereby improving the accuracy of the check result.

[0044] Figure 3 FIG. 1 shows a flow chart of a method for determining a check threshold according to an embodiment of the present application. Figure 3 As shown, the verification threshold determination method of this embodiment includes operations S301 to S304.

[0045] In operation S301 , in response to receiving a page read request, soft decoding performance information is acquired.

[0046] In operation S302 , hard decoding is performed on any hard data among a plurality of hard data to obtain a plurality of hard decision codewords of a fourth-level memory cell.

[0047] In operation S303 , the number of erroneous codewords among the hard decision codewords is determined.

[0048] In operation S304 , a predetermined check threshold is determined from a plurality of candidate predetermined check thresholds based on the number of erroneous codewords and soft decoding performance information.

[0049] In embodiments of the present application, soft decoding performance information may refer to performance indicator information of the controller during the soft decoding process. This performance indicator information can be used to characterize the soft decoding capability of the controller. For example, this performance indicator information may include information such as bit error rate, delay duration, and throughput. A correlation between the soft decoding performance information, the number of error codewords, and candidate predetermined check thresholds can be pre-established and stored in a mapping table. For example, this correlation can be stored in the controller's memory. However, embodiments of the present application are not limited thereto. This correlation can also be stored in a control terminal, etc., used to control the controller. The controller can send its own soft decoding performance information and other information to the control terminal to query the correlation. In this way, based on the controller's soft decoding performance information and the number of error codewords (such as the target error codeword number described above), the controller's soft decoding capability and the number of error codewords can be comprehensively considered to determine a predetermined check threshold suitable for the stored data from multiple candidate predetermined check thresholds for verification. This improves the accuracy of determining the predetermined check threshold. Furthermore, this can prevent controllers with poor soft decoding capabilities from incorrectly performing soft decoding operations due to misidentification of valid data, thereby causing reliability issues in the controller.

[0050] Optionally, in the embodiment of the present application, multiple check vectors and a predetermined check threshold value can be compared to obtain multiple comparison results, and then the check result of the stored data can be determined based on the multiple comparison results. Figure 4 Provide explanation.

[0051] Figure 4 FIG. 1 is a flow chart showing a data processing method according to another embodiment of the present application. Figure 4 As shown, the data processing method of this embodiment includes operations S401 to S416.

[0052] In operation S401 , a page read request is received.

[0053] In operation S402 , first hard data is read using a first threshold voltage.

[0054] In operation S403, the first hard data is hard-decoded.

[0055] In operation S404, it is determined whether the first hard data is hard-decoded successfully. If yes, operation S416 is executed; if no, operation S405 is executed.

[0056] In operation S405 , the first check vector sum is recorded.

[0057] In operation S406 , second hard data is read using a second threshold voltage.

[0058] In operation S407 , the second hard data is hard-decoded.

[0059] In operation S408, it is determined whether the second hard data is hard-decoded successfully. If yes, operation S416 is executed; if no, operation S409 is executed.

[0060] In operation S409, the second check vector sum is recorded.

[0061] In operation S410 , third hard data is read using a third threshold voltage.

[0062] In operation S411, the third hard data is hard-decoded.

[0063] In operation S412, it is determined whether the third hard data is hard-decoded successfully. If so, operation S416 is executed; if not, operation S413 is executed.

[0064] In operation S413, the third check vector sum is recorded.

[0065] In operation S414, the recorded multiple verification vector sums are compared with a predetermined verification threshold value to obtain multiple comparison results.

[0066] In operation S415 , based on the plurality of comparison results, it is determined that the verification result of the stored data is a first verification result or a second verification result.

[0067] In operation S416 , the verification result of the stored data is directly determined as a second verification result.

[0068] In the embodiment of the present application, the first threshold voltage, the second threshold voltage, and the third threshold voltage are the aforementioned different threshold voltages. The first hard data, the second hard data, and the third hard data are the aforementioned different hard data. It should be understood that the number of threshold voltages and hard data in the present application is not limited thereto. Based on this, after hard decoding each hard data item, whether the hard data item is successfully decoded can be determined based on the check vector sum of each hard data item. If each hard data item fails to be decoded, the check vector sum of each hard data item can be checked using a predetermined check threshold to determine whether the stored data in the memory page is invalid data. If the check result of the stored data is determined to be the first check result, read failure feedback information can be generated and sent to a device such as a control terminal. If the check result of the stored data is determined to be the second check result, read success feedback information can be generated and sent to a device such as a control terminal. In this embodiment, the check result of the stored data can be determined simply by comparing multiple check vector sums with the predetermined check threshold, achieving efficient determination of the check result.

[0069] Optionally, in an embodiment of the present application, when multiple comparison results indicate that at least one of the check vector sums is less than or equal to a predetermined check threshold, it can be determined that the number of error codewords of at least one of the multiple hard data is within the range of error codewords that valid data should have. Thus, the check result of the stored data can be directly determined to be the second check result, i.e., the stored data can be determined to be valid data. In this way, the stored data can be efficiently determined to be valid data.

[0070] Furthermore, if the verification result of the stored data is determined to be the second verification result, i.e., if the stored data is determined to be valid data, soft decoding can be continued on the stored data to obtain a soft decoding result. Compared to hard decoding, soft decoding has the advantages of stronger error correction capabilities, higher resource utilization, and higher decoding latency. Therefore, soft decoding can achieve more accurate decoding operations than hard decoding. If the soft decoding result indicates a successful soft decoding, read success feedback information can be generated and sent to a device such as a control terminal. However, if the soft decoding result indicates a decoding failure, it can be determined that the valid data has an abnormality (e.g., data loss), and a data recovery operation can be performed on the storage page. For example, a Redundant Array of Independent Disks (RAID) recovery operation can be performed on the storage page to obtain a data recovery result. If the data recovery is successful, read success feedback information can be generated and sent. If the data recovery fails, read failure feedback information can be generated and sent. This ensures that the system can accurately perform operations on different types of data (e.g., valid data of the valid type and invalid data of the invalid type).

[0071] Optionally, in the embodiment of the present application, the read type identifier of the page read request can also be obtained. Based on the multiple comparison results and the read type identifier, the verification result of the stored data is determined. Figure 5 Provide explanation.

[0072] Figure 5 FIG. 1 is a flow chart showing a data processing method according to another embodiment of the present application. Figure 5 As shown, the data processing method of this embodiment may include operations S501 to S508.

[0073] In operation S501 , in response to receiving a page read request, a read type identifier of the page read request is obtained.

[0074] In operation S502 , a plurality of hard data of memory pages are sequentially read using a plurality of threshold voltages.

[0075] In operation S503 , hard decoding is performed on the plurality of hard data respectively.

[0076] In operation S504, it is determined whether at least one of the plurality of hard data is hard-decoded successfully. If so, operation S508 is executed; if not, operation S505 is executed.

[0077] In operation S505 , a check vector sum of a plurality of hard data is recorded.

[0078] In operation S506 , the plurality of check vectors and φ are respectively compared with a predetermined check threshold to obtain a plurality of comparison results.

[0079] In operation S507 , based on the plurality of comparison results and the read type identifier, it is determined whether the verification result of the stored data is the first verification result or the second verification result.

[0080] In operation S508 , the verification result of the stored data is directly determined as a second verification result.

[0081] In an embodiment of the present application, a page read request can be parsed to obtain a read type identifier carried by the page read request. The read type identifier can be divided into multiple types, such as a garbage collection read identifier, a host read identifier, and the like. The read type identifier can be used to characterize the type of read operation requested by the page read request. For example, in a case where the read type identifier is a garbage collection read identifier, the read operation requested by the page read request can be a garbage collection read operation (Garbage Collection Read). Similarly, in a case where the read type identifier is a host read identifier, the read operation requested by the page read request can be a host read (host) operation. In this way, the type of read operation requested by the page read request can be determined based on different types of read type identifiers, thereby determining that the verification result of the stored data is a different verification result for different types of read operations in combination with multiple comparison results. In this way, by using different types of read type identifiers and multiple comparison results, it is possible to relatively efficiently and accurately determine whether the stored data is invalid data.

[0082] Furthermore, in one embodiment of the present application, if multiple comparison results all represent a check vector and are greater than a predetermined check threshold, it can be determined that the number of error codewords for the multiple hard data is not within the range of error codewords expected for valid data, and thus the stored data is likely invalid. Based on this, the type of read operation performed can be further determined based on the read type identifier, thereby determining the check result of the stored data based on the type of read operation performed.

[0083] Optionally, if the multiple comparison results all indicate that the check vector sum is greater than a predetermined check threshold, and the read type identifier is a garbage collection read identifier, the currently executed read operation can be determined to be a garbage collection read operation, and the check result of the stored data can be determined to be the first check result, i.e., the stored data is determined to be invalid data. In this way, by using different types of read type identifiers and multiple comparison results, it is possible to relatively efficiently and accurately determine whether the stored data is invalid data.

[0084] Optionally, if the verification result of the stored data is determined to be the first verification result, that is, if the stored data is determined to be invalid data, the decoding operation on the storage page can be stopped. For example, the decoding operation may include a decoding operation required to be performed after hard decoding, such as a soft decoding operation. In this way, the consumption of system resources caused by performing decoding operations on invalid data can be reduced, ensuring that the system can perform accurate operations on different types of data, thereby saving system resources.

[0085] Figure 6 FIG. 1 shows a flow chart of a data processing method according to another embodiment of the present application. Figure 6 As shown, the data processing method of this embodiment includes operations S601 to S608.

[0086] In operation S601 , a verification result of stored data is determined.

[0087] In operation S602, it is determined whether the verification result of the stored data is the first verification result. If yes, operation S607 is executed; if no, operation S603 is executed.

[0088] In operation S603, soft decoding is performed on the stored data to obtain a soft decoding result.

[0089] In operation S604, it is determined whether the soft decoding result indicates that the soft decoding is successful. If yes, operation S608 is executed; if no, operation S605 is executed.

[0090] In operation S605 , a data recovery operation is performed on the storage page.

[0091] In operation S606, it is determined whether the data is restored successfully. If yes, operation S608 is executed; if not, operation S607 is executed.

[0092] In operation S607 , read failure feedback information is generated.

[0093] In operation S608 , feedback information indicating that the reading is successful is generated.

[0094] In an embodiment of the present application, if the verification result of the stored data is determined to be the first verification result, it can be determined that the soft decoding operation and data recovery operation following the hard decoding operation will not be performed on the storage page. In this way, the consumption of system resources caused by performing decoding and recovery operations on invalid data can be reduced, ensuring that the system can perform accurate operations on different types of data, thereby saving system resources.

[0095] In another embodiment of the present application, if multiple comparison results all indicate that the check vector sum is greater than a predetermined check threshold, and the read type identifier is a host read identifier, it can be determined that the read operation is a host read operation. When performing a host read operation, the read data is definitely valid, so the check result of the stored data can be directly determined to be the second check result. In this case, soft decoding operations and data recovery operations can continue to be performed on the stored data until the data is completely decoded. In this way, the system can ensure the accuracy of operations performed on different types of data.

[0096] Based on the above data processing method, this application also provides a data processing device. Figure 7 The device is described in detail.

[0097] Figure 7 The figure shows a structural block diagram of a data processing device according to an embodiment of the present application.

[0098] like Figure 7 As shown, the data processing device 700 of this embodiment includes a reading module 710 , a hard decoding module 720 and a checking module 730 .

[0099] The read module 710 is configured to read multiple hard data of a storage page in response to receiving a page read request, where the storage page is used to store the once-programmed storage data. In one embodiment, the read module 710 may be configured to perform the operation S201 described above, which will not be described in detail here.

[0100] The hard decoding module 720 is used to perform hard decoding on the multiple hard data to obtain multiple check vectors and In one embodiment, the hard decoding module 720 can be used to perform the operation S202 described above, which will not be repeated here.

[0101] Verification module 730 is configured to verify the sum of multiple verification vectors using a predetermined verification threshold to determine a verification result of the data stored in the storage page; the verification result is used to indicate the validity of the stored data. In one embodiment, verification module 730 can be configured to perform operation S203 described above, which will not be further described here.

[0102] According to an embodiment of the present application, the verification module 730 includes a comparison submodule and a first determination submodule. The comparison submodule is configured to compare the sum of multiple verification vectors with a predetermined verification threshold to obtain multiple comparison results, and the first determination submodule is configured to determine the verification result of the stored data based on the multiple comparison results.

[0103] According to an embodiment of the present application, the first determination submodule includes an acquisition unit and a first determination unit, wherein the acquisition unit is used to acquire a read type identifier of a page read request; and the first determination unit is used to determine a verification result of the stored data based on multiple comparison results and the read type identifier.

[0104] According to an embodiment of the present application, the first determining unit includes a first determining subunit configured to determine a verification result of the stored data based on the read type identifier when the plurality of comparison results all represent a verification vector and are greater than a predetermined verification threshold.

[0105] According to an embodiment of the present application, the first determination subunit is also used to determine that the verification result of the stored data is a first verification result when multiple comparison results all represent a verification vector sum greater than a predetermined verification threshold and the read type identifier is a garbage collection read identifier; the first verification result represents that the stored data is invalid data.

[0106] According to an embodiment of the present application, the first determining unit further includes a stopping subunit, wherein the stopping subunit is configured to stop decoding the storage page when determining that the verification result of the storage data is the first verification result.

[0107] According to an embodiment of the present application, the stopping subunit is further configured to determine not to perform a soft decoding operation and a data recovery operation on the storage page when it is determined that the verification result of the storage data is the first verification result.

[0108] According to an embodiment of the present application, the first determination unit further includes a second determination subunit. The second determination subunit is configured to, if the plurality of comparison results all indicate that the check vector sum is greater than a predetermined check threshold and the read type identifier is a host read identifier, determine that the check result of the stored data is a second check result; the second check result indicates that the stored data is valid data.

[0109] According to an embodiment of the present application, the first determination submodule further includes a second determination unit. The second determination unit is configured to determine that the verification result of the stored data is a second verification result if the plurality of comparison results all indicate that at least one of the verification vector sums is less than or equal to a predetermined verification threshold; the second verification result indicates that the stored data is valid data.

[0110] According to an embodiment of the present application, the data processing device further includes a soft decoding module and a recovery module. The soft decoding module is configured to, if the verification result of the stored data is determined to be the second verification result, perform soft decoding on the stored data to obtain a soft decoding result; and the recovery module is configured to, if the soft decoding result indicates a decoding failure, perform a data recovery operation on the storage page.

[0111] According to an embodiment of the present application, the hard decoding module 720 further includes a hard decoding submodule, a second determination submodule, and a calculation submodule. The hard decoding submodule is configured to hard-decode any hard data from the plurality of hard data to obtain a plurality of hard decision codewords for the fourth-order storage unit; the second determination submodule is configured to determine a plurality of check vectors based on a predetermined check matrix and the plurality of hard decision codewords; and the calculation submodule is configured to calculate a check vector sum based on the plurality of check vectors. The number of error codewords in the plurality of hard decision codewords is positively correlated with a predetermined check threshold.

[0112] According to an embodiment of the present application, the hard decoding module 720 further includes an acquisition submodule and a third determination submodule. The acquisition submodule is configured to acquire soft decoding performance information in response to receiving a page read request; and the third determination submodule is configured to determine a predetermined check threshold from a plurality of candidate predetermined check thresholds based on the number of error codewords and the soft decoding performance information.

[0113] According to embodiments of the present application, any multiple modules among the reading module 710, the hard decoding module 720, and the verification module 730 may be combined into a single module, or any one of these modules may be split into multiple modules. Alternatively, at least part of the functionality of one or more of these modules may be combined with at least part of the functionality of other modules and implemented in a single module. According to embodiments of the present application, at least one of the reading module 710, the hard decoding module 720, and the verification module 730 may be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or may be implemented in hardware or firmware through any other suitable means of circuit integration or packaging, or may be implemented in any one of software, hardware, and firmware, or any suitable combination thereof. Alternatively, at least one of the reading module 710, the hard decoding module 720, and the verification module 730 may be at least partially implemented as a computer program module that, when executed, performs the corresponding functionality.

[0114] Figure 8 A block diagram of an electronic device suitable for implementing a data processing method according to an embodiment of the present application is shown.

[0115] like Figure 8 As shown, an electronic device 800 according to an embodiment of the present application includes a processor 801, which can perform various appropriate actions and processes based on a program stored in a read-only memory (ROM) 802 or a program loaded from a storage unit 808 into a random access memory (RAM) 803. The processor 801 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and / or a related chipset and / or a dedicated microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 801 may also include onboard memory for caching purposes. The processor 801 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present application.

[0116] Various programs and data required for the operation of the electronic device 800 are stored in the RAM 803. The processor 801, ROM 802, and RAM 803 are connected to each other via a bus 804. The processor 801 performs various operations of the method flow according to the embodiment of the present application by executing the programs in the ROM 802 and / or RAM 803. It should be noted that the programs may also be stored in one or more memories other than the ROM 802 and the RAM 803. The processor 801 may also perform various operations of the method flow according to the embodiment of the present application by executing the programs stored in the one or more memories.

[0117] According to an embodiment of the present application, electronic device 800 may further include an input / output (I / O) interface 805, which is also connected to bus 804. Electronic device 800 may also include one or more of the following components connected to I / O interface 805: an input section 806 including a keyboard, mouse, etc.; an output section 807 including devices such as a cathode ray tube (CRT), liquid crystal display (LCD), and speakers; a storage section 808 including a hard disk; and a communication section 809 including a network interface card such as a LAN card or modem. Communication section 809 performs communication processing via a network such as the Internet. A drive 810 is also connected to I / O interface 805 as needed. Removable media 811, such as a magnetic disk, optical disk, magneto-optical disk, semiconductor memory, etc., is installed in drive 810 as needed, so that computer programs read from the removable media can be installed into storage section 808 as needed.

[0118] This application also provides a computer-readable storage medium, which may be included in the device / apparatus / system described in the above embodiments, or may exist independently and not be incorporated into the device / apparatus / system. The computer-readable storage medium carries one or more programs, and when the one or more programs are executed, the method according to the embodiments of this application is implemented.

[0119] According to an embodiment of the present application, a computer-readable storage medium may be a non-volatile computer-readable storage medium, and may include, for example, but not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present application, a computer-readable storage medium may be any tangible medium that contains or stores a program that can be used by or in conjunction with an instruction execution system, apparatus, or device. For example, according to an embodiment of the present application, a computer-readable storage medium may include the ROM 802 and / or RAM 803 described above and / or one or more memories other than ROM 802 and RAM 803.

[0120] The embodiments of the present application also include a computer program product, which includes a computer program containing program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the data processing method provided in the embodiments of the present application.

[0121] The computer program executes the above functions defined in the system / device of the embodiment of the present application when the processor 801 executes the computer program. According to the embodiment of the present application, the system, device, module, unit, etc. described above can be implemented by a computer program module.

[0122] In one embodiment, the computer program may be stored on a tangible storage medium such as an optical storage device or a magnetic storage device. In another embodiment, the computer program may be transmitted and distributed in the form of a signal on a network medium, downloaded and installed via the communication portion 809, and / or installed from a removable medium 811. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to wireless, wired, or any suitable combination thereof.

[0123] In such an embodiment, the computer program can be downloaded and installed from the network via the communication section 809, and / or installed from the removable medium 811. When the computer program is executed by the processor 801, the above-mentioned functions defined in the system of the embodiment of the present application are performed. According to the embodiment of the present application, the systems, devices, means, modules, units, etc. described above can be implemented by computer program modules.

[0124] According to an embodiment of the present application, the program code for executing the computer program provided by the embodiment of the present application can be written in any combination of one or more programming languages. Specifically, these computer programs can be implemented using high-level procedural and / or object-oriented programming languages, and / or assembly / machine languages. Programming languages include, but are not limited to, languages such as Java, C++, Python, "C" or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on a remote computing device, or entirely on a remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect via the Internet).

[0125] The flowcharts and block diagrams in the accompanying drawings illustrate the possible implementation architecture, functions and operations of the systems, methods and computer program products according to various embodiments of the present application. In this regard, each box in the flowchart or block diagram can represent a module, program segment, or a part of code, and the above-mentioned module, program segment, or a part of code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in an order different from that marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flowchart, and the combination of the boxes in the block diagram or flowchart, can be implemented with a dedicated hardware-based system that performs the specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

[0126] Those skilled in the art will appreciate that the features described in the various embodiments of this application may be combined and / or coupled in various ways, even if such combinations or couplings are not explicitly described in this application. In particular, the features described in the various embodiments of this application may be combined and / or coupled in various ways without departing from the spirit and teachings of this application. All such combinations and / or couplings fall within the scope of this application.

[0127] The embodiments of the present application have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present application. Although each embodiment has been described separately above, this does not mean that the measures in each embodiment cannot be advantageously used in combination. Without departing from the scope of the present application, those skilled in the art may make various substitutions and modifications, and these substitutions and modifications should all fall within the scope of the present application.

Claims

1. A data processing method, characterized in that: The data processing method includes: In response to receiving a page read request, reading a plurality of hard data of a storage page; the storage page is used to store storage data that is programmed once; performing hard decoding on the plurality of hard data respectively to obtain a plurality of check vectors and; Verifying the sum of the plurality of verification vectors using a predetermined verification threshold to determine a verification result of the stored data in the storage page; the verification result is used to characterize the validity of the stored data; The verifying the plurality of check vector sums using a predetermined verification threshold to determine the verification result of the stored data in the storage page includes: comparing the plurality of check vector sums with the predetermined verification threshold respectively to obtain a plurality of comparison results; and determining the verification result of the stored data based on the plurality of comparison results; Wherein, determining the verification result of the stored data based on the multiple comparison results further includes: if the multiple comparison results indicate that at least one of the sum of the verification vectors is less than or equal to the predetermined verification threshold, determining that the verification result of the stored data is a second verification result; the second verification result indicates that the stored data is valid data; The storage page includes a fourth-order storage unit; hard decoding the plurality of hard data to obtain a plurality of check vector sums includes: hard decoding any hard data of the plurality of hard data to obtain a plurality of hard decision codewords of the fourth-order storage unit; determining a plurality of check vectors based on a predetermined check matrix and the plurality of hard decision codewords; and calculating the check vector sum based on the plurality of check vectors; the plurality of hard decision codewords includes an error codeword; The method further includes: obtaining soft decoding performance information in response to receiving the page read request; and determining the predetermined verification threshold from a plurality of candidate predetermined verification thresholds based on the number of error codewords and the soft decoding performance information.

2. The data processing method according to claim 1, wherein: Determining a verification result of the stored data based on the multiple comparison results includes: Obtaining a read type identifier of the page read request; A verification result of the stored data is determined based on the multiple comparison results and the read type identifier.

3. The data processing method according to claim 2, characterized in that: The determining, based on the plurality of comparison results and the read type identifier, a verification result of the stored data includes: In a case where the plurality of comparison results all represent a check vector sum greater than the predetermined check threshold, a check result of the stored data is determined based on the read type identifier.

4. The data processing method according to claim 3, wherein: The determining, based on the read type identifier, of a verification result of the stored data when the plurality of comparison results all represent a verification vector sum greater than the predetermined verification threshold, includes: When the multiple comparison results all indicate that the check vector sum is greater than the predetermined check threshold and the read type identifier is a garbage collection read identifier, the check result of the stored data is determined to be a first check result; the first check result indicates that the stored data is invalid data.

5. The data processing method according to claim 4, characterized in that: Also includes: When it is determined that the verification result of the stored data is the first verification result, the decoding operation on the storage page is stopped.

6. The data processing method according to claim 5, characterized in that: The decoding operation includes a soft decoding operation; The step of stopping the decoding operation on the storage page when determining that the verification result of the storage data is the first verification result includes: When it is determined that the verification result of the stored data is the first verification result, it is determined not to perform a soft decoding operation and a data recovery operation on the storage page.

7. The data processing method according to any one of claims 3 to 6, characterized in that: The determining, based on the read type identifier, of a verification result of the stored data when the plurality of comparison results all represent a verification vector sum greater than the predetermined verification threshold, includes: When the multiple comparison results all indicate that the check vector sum is greater than the predetermined check threshold and the read type identifier is a host read identifier, the check result of the stored data is determined to be a second check result; the second check result indicates that the stored data is valid data.

8. The data processing method according to claim 1, wherein: Also includes: When it is determined that the verification result of the stored data is the second verification result, performing soft decoding on the stored data to obtain a soft decoding result; In a case where the soft decoding result indicates a decoding failure, a data recovery operation is performed on the storage page.

9. The data processing method according to any one of claims 1 to 6, characterized in that: The number of erroneous codewords in the multiple hard decision codewords is positively correlated with the size of the predetermined check threshold.

10. An electronic device comprising: one or more processors; a memory for storing one or more computer programs, It is characterized in that the one or more processors execute the one or more computer programs to implement the steps of the data processing method according to any one of claims 1 to 9.

11. A computer-readable storage medium having a computer program or instruction stored thereon, characterized in that: When the computer program or instruction is executed by a processor, the steps of the data processing method according to any one of claims 1 to 9 are implemented.

12. A computer program product comprising a computer program or instructions, characterized in that When the computer program or instruction is executed by a processor, the steps of the data processing method according to any one of claims 1 to 9 are implemented.

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