Rate adjustment method and node

Abstract

The embodiment of the invention provides a rate adjustment method and a node. The method comprises the following steps: acquiring a target code stream in a 256B / 257B format; and performing rate adjustment on the target code stream by adding or deleting the 257b idle code blocks. According to the embodiment of the invention, the problem that the implementation complexity of a rate adaptation mechanism of a high-rate Ethernet is high along with the increase of the rate in related technologies can be solved, and the rate adjustment is carried out based on the 257b coding block, so that the development of a higher-rate Ethernet technology can be better supported.

Description

Technical Field

[0001] This application relates to the field of communications, and more particularly, to a rate adjustment method and a node. Background Art

[0002] In the IEEE 802.3 standard of the Institute of Electrical and Electronics Engineers (IEEE), high-rate services are rate-adapted based on 66b. Each Media Access Control (MAC) packet is encoded into a 64B / 66B format, which includes a start encoding block S and an end encoding block T. After a MAC packet is encoded into 64B / 66B, it starts with the S code block and ends with the T code block. Since there is an average of 12 bytes of Inter-Packet Gap (IPG) between MAC packets, some IPGs will be encoded into 66b idle code blocks. IEEE 802.3 currently performs rate adaptation by adding or deleting 66b idle code blocks. For example, by deleting 66b idle code blocks, space is reserved for alignment markers (AMs) or Flexible Ethernet (FlexE) overheads, thus ensuring that the total rate remains unchanged.

[0003] The industry has also defined different service layers for carrying Ethernet services, such as FlexE and Optical Transport Network (OTN). The rate of the service layer is higher than that of the Ethernet service. During the mapping process from the Ethernet service to the corresponding service layer container, rate adjustment is also performed based on the addition and deletion of 66b Idle. Since the rate of the service layer container is high, when there is not enough Ethernet service, 66b Idle will be inserted into the service layer container.

[0004] Due to the increase in rate, the bus bit width for internal processing in the device also becomes larger, and there will be more 66b data within a bus bit width. The implementation of the rate adaptation mechanism based on 66b idle code blocks will also become increasingly complex because 66b idle code blocks can appear in any of the multiple 66b data within the bus bit width, introducing complex data splicing problems.

[0005] In summary, regarding the problem that the implementation complexity of the rate adaptation mechanism for high-rate Ethernet is high with the increase in rate in the related art, there is no good solution yet. Summary of the Invention

[0006] The embodiments of the present application provide a rate adjustment method and a node, so as to at least solve the problem of high implementation complexity of the rate adaptation mechanism of high-speed Ethernet as the rate increases in the related art.

[0007] According to an embodiment of the present application, a rate adjustment method is provided, and the method includes: obtaining a target bitstream in the 256B / 257B format; performing rate adjustment on the target bitstream by adding or deleting 257b idle code blocks.

[0008] According to another embodiment of the present application, a node is provided, and the node includes: an obtaining module, configured to obtain a target bitstream in the 256B / 257B format; a rate adjustment module, configured to perform rate adjustment on the target bitstream by adding or deleting 257b idle code blocks.

[0009] According to still another embodiment of the present application, a computer-readable storage medium is further provided, and a computer program is stored in the storage medium, wherein the computer program, when run by a processor, executes the steps in any one of the above method embodiments.

[0010] According to still another embodiment of the present application, an electronic device is further provided, including a memory and a processor, a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0011] In the embodiments of the present application, a rate adaptation mechanism based on 257b is proposed. Rate adaptation is performed by adding or deleting 257b idle code blocks in the 257b bitstream, which reduces the hardware implementation complexity of rate adaptation under high-speed interfaces, can solve the problem of high implementation complexity of the rate adaptation mechanism of high-speed Ethernet as the rate increases in the related art, and better supports the development of higher-rate Ethernet technologies. Description of the Drawings

[0012] Figure 1 is a hardware structure block diagram for executing the rate adjustment method in the embodiments of the present application;

[0013] Figure 2 is a flowchart of the rate adjustment method according to the embodiment of the present application;

[0014] Figure 3 is a processing flowchart of a source node according to the embodiment of the present application;

[0015] Figure 4 is a schematic diagram of 257b idle code blocks according to the embodiment of the present application;

[0016] Figure 5 is a schematic diagram of 257b end code blocks according to the embodiment of the present application;

[0017] Figure 6 is a processing flow chart (I) of an intermediate node according to an embodiment of the present application;

[0018] Figure 7 is a processing flow chart (II) of an intermediate node according to an embodiment of the present application;

[0019] Figure 8 is a processing flow chart (III) of an intermediate node according to an embodiment of the present application;

[0020] Figure 9 is a schematic diagram of a 257b error code block according to an embodiment of the present application;

[0021] Figure 10 is a block diagram of a node in an embodiment of the present application. Detailed implementation manners

[0022] In the following, embodiments of the present application will be described in detail with reference to the accompanying drawings and in combination with embodiments.

[0023] It should be noted that the terms "first", "second", etc. in the specification, claims and above-mentioned drawings of the present application are used to distinguish similar objects, and do not necessarily need to be used to describe a specific order or sequence.

[0024] The method embodiments provided in the embodiments of the present application can be executed in network nodes of a high-speed Ethernet, such as host nodes (including computer devices, servers, etc.), switch nodes, router nodes or gateway nodes, etc. Taking running on a computer device as an example, Figure 1 is a hardware structure block diagram for executing a rate adjustment method in an embodiment of the present application, such as Figure 1 shown, the hardware single board may include one or more ( Figure 1 only one is shown in Figure 1 a processor 12 (the processor 12 may include, but is not limited to, a processing device such as a microprocessor MCU or a programmable logic device) and a memory 14 for storing data. Among them, the above-mentioned mobile terminal may further include a transmission device 16 for communication functions and an input / output device 18. Those of ordinary skill in the art can understand that, Figure 1 the structure shown in Figure 1 is only schematic, and it does not limit the structure of the above-mentioned computer device. For example, the computer device may further include more or fewer components than

[0025] The memory 14 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the rate adjustment method in the embodiments of the present application. The processor 12 executes various functional applications and the rate adjustment method by running the computer program stored in the memory 14, that is, the above method is implemented. The memory 14 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memories, or other non-volatile solid-state memories. In some instances, the memory 14 may further include a memory remotely disposed relative to the processor 12, and these remote memories can be connected to the computer device through a network. Examples of the above networks include but are not limited to the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof.

[0026] The transmission device 16 is used to receive or send data via a network. Specific examples of the above network may include a wireless network provided by a communication provider. In one instance, the transmission device 16 includes a network adapter (Network Interface Controller, abbreviated as NIC), which can be connected to other network devices through a base station and thus can communicate with the Internet. In one instance, the transmission device 16 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0027] In an embodiment of the present application, a rate adjustment method is provided. Figure 2 It is a flowchart of the rate adjustment method according to the embodiments of the present application, as Figure 2 shown, and the process includes the following steps:

[0028] Step S202, obtain a target bitstream in the 256B / 257B format;

[0029] Step S204, perform rate adjustment on the target bitstream by adding or deleting 257b idle code blocks.

[0030] In the embodiments of the present application, through step S202 and step S204, rate adaptation can be performed based on the 257b bitstream, reducing the hardware implementation complexity of rate adaptation under a high-speed interface, and solving the problem in the related art that as the rate increases, the implementation complexity of the rate adaptation mechanism of high-speed Ethernet is high, and better supporting the development of higher-rate Ethernet technologies.

[0031] In some embodiments, step S204 performs rate adjustment on the target bitstream by adding or deleting 257b idle code blocks, including: inserting the 257b idle code block after the 257b end code block or the 257b idle code block in the target bitstream; or, deleting the 257b idle code block from the target bitstream.

[0032] In this embodiment, taking 257b idle code blocks as the basic unit for adjusting the bitstream rate can reduce the complexity of the rate adaptation mechanism in hardware implementation. Deleting 257b idle code blocks in the target bitstream can increase the bitstream rate, and adding new 257b idle code blocks in the target bitstream can decrease the bitstream rate.

[0033] In some embodiments, the target bitstream in 256B / 257B format consists of multiple 257b encoded blocks, and each 257b encoded block is formed by transcoding 4 66b encoded blocks in 256B / 257B conversion.

[0034] In some embodiments, the 257b idle code block (I) is formed by transcoding 4 66b idle code blocks; the 257b end code block is formed by transcoding a first quantity of 66b data code blocks (D), 1 66b end code block (T), and a second quantity of 66b idle code blocks (I), where the first quantity and the second quantity are greater than or equal to zero, and the sum of the first quantity and the second quantity is equal to 3.

[0035] In an exemplary embodiment, each 257b encoded block can be represented by the symbols of 4 66b encoded blocks, where the combination ways of the 4 66b encoded blocks in the 257b end code block include: TIII, DTII, DDTI, and DDDT.

[0036] In some embodiments, before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks in step S204, the method further includes: identifying the 257b idle code blocks in the target bitstream through a first mode.

[0037] Exemplarily, the first mode includes: the first bit is 0, the second to fifth bits are 0000, and a first preset pattern; the first preset pattern includes at least one of the following: the sixth to ninth bits are 0111, and the tenth to 65th bits are all 0; the sixth to 13th bits are 01110000.

[0038] In some embodiments, before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks in step S204, the method further includes: identifying the 257b end code blocks in the target bitstream through a second mode.

[0039] Exemplarily, the second mode includes at least one of the following:

[0040] The first bit is 0, the second to fifth bits are 0000, and the sixth to ninth bits are of a preset type;

[0041] The first bit is 0, and the second to fifth bits are 1000 or 1110;

[0042] The first bit is 0, the second to fifth bits are 1100, and the 202nd to 257th bits are all 0.

[0043] In some embodiments, the 257b encoding block further includes: a 257b start code block, where the 257b start code block is transcoded from 1 66b start code block and 3 66b data code blocks. Exemplarily, the 257b start code block can be represented as SDDD.

[0044] In some embodiments, the 257b encoding block further includes: a 257b connection code block, where the 257b connection code block is transcoded from one 66b end code block, one 66b start code block, and 2 66b data code blocks, and the 66b end code block is located before the 66b start code block.

[0045] In some embodiments, the 257b connection code block is transcoded from any of the following combinations:

[0046] The 66b data code block, the 66b data code block, the 66b end code block, and the 66b start code block;

[0047] The 66b data code block, the 66b end code block, the 66b start code block, and the 66b data code block;

[0048] The 66b end code block, the 66b start code block, the 66b data code block, and the 66b data code block.

[0049] In an exemplary embodiment, the 257b connection code block can be represented as DDTS, DTSD, or TSDD. The 257b connection code block is used to connect two data packets. The T code block in the 257b connection code block is the tail of the previous data packet, and the S code block is the head of the next data packet.

[0050] In some embodiments, step S202 of obtaining the target code stream in 256B / 257B format includes: performing 64B / 66B encoding on the Ethernet MAC packet to obtain a first code stream in 64B / 66B format, and performing 256B / 257B transcoding on the first code stream to obtain the target code stream;

[0051] In some other embodiments, step S202 of obtaining the target code stream in 256B / 257B format includes: receiving the target code stream sent by the previous node, where the target code stream is formed by performing 64B / 66B encoding and 256B / 257B transcoding on the Ethernet MAC packet.

[0052] In some embodiments, when performing 64B / 66B encoding on the Ethernet MAC packet, the inter-frame gap bytes in the Ethernet MAC packet are not encoded into 66b idle code blocks. The first bitstream includes 66b start code blocks, 66b data code blocks, and 66b end code blocks, and the first bitstream does not include 66b idle code blocks.

[0053] In this embodiment, each Ethernet MAC packet can be transcoded to form a group of 66b encoded blocks. Each group of 66b encoded blocks consists of a 66b start code block (S), several 66b data code blocks (D), and a 66b end code block (T). It does not contain 66b idle code blocks (I).

[0054] Exemplarily, during the process of performing 64B / 66B encoding on the Ethernet MAC packet, consecutive 8 inter-packet gap (IPG) bytes are not encoded into a 66b idle code block.

[0055] In some embodiments, performing 256B / 257B transcoding on the first bitstream to obtain the target bitstream includes: transcoding the 66b end code block of the current MAC packet in the first bitstream and the 66b start code block of the next MAC packet into a 257b connection code block, where the 257b connection code block does not contain 66b idle code blocks.

[0056] In some embodiments, performing 256B / 257B transcoding on the first bitstream to obtain the target bitstream includes: when the number of remaining 66b encoded blocks of the current MAC packet in the first bitstream is less than 4 and the next Ethernet MAC packet has not been received, inserting at least one 66b idle code block into the 66b end code block corresponding to the current MAC packet and then performing 256B / 257B transcoding to obtain the 257b end code block in the target bitstream.

[0057] In some embodiments, when the number of remaining 66b encoded blocks of the current MAC packet in the first bitstream is less than 4 and the next Ethernet MAC packet has been received, using a 257b connection code block to connect the two Ethernet MAC packets, and the 257b connection code block can be transcoded from the remaining 66b encoded blocks of the current MAC packet and the 66b encoded blocks at the head of the next MAC packet.

[0058] In some embodiments, performing 256B / 257B transcoding on the first bitstream to obtain the target bitstream further includes: when the next Ethernet MAC packet has not been received within a preset first threshold after the transcoding of the current MAC packet is completed, inserting 257b idle code blocks into the target bitstream, where the 257b idle code blocks are transcoded from 4 66b idle code blocks.

[0059] In an exemplary embodiment, the first threshold may be set according to the time required to send 4 66b encoded blocks.

[0060] In some embodiments, receiving the target bitstream sent by the previous node includes: receiving the data stream obtained by performing forward error correction coding (FEC) on the target bitstream sent by the previous node; performing forward error correction decoding processing on the data stream to obtain the target bitstream; and in the case where FEC cannot correct errors, replacing all 257b encoded blocks in the corresponding FEC codeword in the target bitstream with 257b error code blocks.

[0061] In some embodiments, the FEC codeword is 255 bytes long and consists of 239 bytes of normal data and 16 bytes of redundant overhead. If a certain FEC codeword decoding fails, all 257b encoded blocks in the FEC codeword need to be replaced with 257b error code blocks.

[0062] In some embodiments, the 257b error code block is formed by transcoding 4 66b error code blocks.

[0063] In some embodiments, the 257b error code block can be identified through a preset third mode. Exemplarily, the third mode includes that the first bit is 0, the second to fifth bits are 0000, and a second preset pattern; wherein, the second preset pattern includes at least one of the following: the sixth to ninth bits are 0111, and the tenth to sixty-fifth bits are 8 0111100s; the sixth to thirteenth bits are 01110111.

[0064] In some embodiments, when the current node is an intermediate node supporting 257b encoded block exchange, step S204 adjusts the rate of the target bitstream by adding or deleting 257b idle code blocks, including: performing exchange processing on the target bitstream based on 257b encoded blocks to obtain the target bitstream after exchange processing; and adjusting the rate of the target bitstream after exchange processing by adding or deleting the 257b idle code blocks.

[0065] In some embodiments, when the current node is an intermediate node supporting 66b encoded block swapping, step S204 adjusts the rate of the target code stream by adding or deleting 257b idle code blocks, including: transcoding the target code stream to obtain a second code stream in 64B / 66B format, where the second code stream includes 66b idle code blocks; performing swapping processing on the second code stream based on 66b encoded blocks to obtain a second code stream after the swapping processing; adjusting the rate of the second code stream after the swapping processing by adding or deleting the 66b idle code blocks to obtain a second code stream after the rate adjustment; transcoding the second code stream after the rate adjustment to 256B / 257B and performing shifting, adding, or deleting processing on the 66b idle code blocks in the second code stream after the rate adjustment during the transcoding process to obtain a target code stream after the rate adjustment in 256B / 257B format, where the type of the 257b encoded blocks in the target code stream after the rate adjustment is the same as that in the target code stream.

[0066] In some embodiments, when the current node is an intermediate node supporting 66b encoded block swapping, step S204 adjusts the rate of the target code stream by adding or deleting 257b idle code blocks, including: deleting some 257b idle code blocks in the target code stream according to a preset proportional coefficient to obtain a target code stream after the rate reduction; transcoding the target code stream after the rate reduction to obtain a second code stream in 64B / 66B format, where the second code stream includes 66b idle code blocks; performing swapping processing on the second code stream based on 66b encoded blocks to obtain a second code stream after the swapping processing; transcoding the second code stream after the swapping processing to 256B / 257B to obtain a target code stream after the swapping processing; adjusting the rate of the target code stream after the swapping processing by adding or deleting the 257b idle code blocks.

[0067] Through the embodiments of the present application, a rate adaptation mechanism based on a 257b code stream can be implemented, reducing the hardware implementation complexity of rate adaptation under a high-speed interface, and thus solving the problem in the related art that the implementation complexity of the rate adaptation mechanism of a high-speed Ethernet increases with the increase in rate, and better supporting the development of high-speed Ethernet technology.

[0068] Figure 3 is a processing flowchart of a source node according to an embodiment of the present application. As Figure 3 shown, at the source node, an Ethernet MAC packet can be encoded into 64B / 66B format and then transcoded into 256B / 257B format.

[0069] In this embodiment, each Ethernet MAC packet is encoded into a 64B / 66B format of "66b start code block (S) + multiple 66b data code blocks (D) + 66b end code block (T)". The 64B / 66B bitstream after encoding the Ethernet MAC packet does not contain 66b idle code blocks, that is, 8 consecutive IPG bytes during the encoding process will not be encoded into a 66b idle code block.

[0070] In this embodiment, when performing 256B / 257B transcoding, 4 66b code blocks are transcoded to form a 257b code block.

[0071] In some embodiments, when performing 64B / 66B to 256B / 257B transcoding, when the number N1 of remaining 66b code blocks of the current MAC packet encoded into 64B / 66B code blocks is not sufficient to be transcoded into 257b, and when the next MAC packet is received, the remaining 66b code blocks of the current MAC packet and the 66b code blocks after encoding M1 next MAC packets are transcoded together into a 257b code block, where N1 + M1 = 4. Exemplarily, when performing 256B / 257B transcoding on the 66b code blocks encoded by the current MAC packet, there is 1 remaining 66b end code block (T), and when the next MAC packet is received, the remaining T code block of the current MAC packet and 3 corresponding 66b code blocks of the next MAC packet, namely one S code block and 2 D code blocks, are transcoded into a 257b code block. That is to say, when the T code block of the current MAC packet and the S code block of the next MAC packet are transcoded together into a 257b code block, the 4 66b code blocks transcoded into the 257b code block do not contain 66b idle code blocks.

[0072] In other embodiments, when the number N2 of remaining 66b code blocks of the MAC packet encoded into 64B / 66B code blocks is not sufficient to be transcoded into 257b, and the next MAC packet has not been received, a certain number M2 of 66b Idle code blocks are inserted after the T code block corresponding to this MAC packet, and they are transcoded together with the remaining 66b code blocks into a 257b code block. The number M2 of inserted 66b Idle code blocks and the number N2 of remaining 66b code blocks of the current MAC packet sum to 4. Exemplarily, when performing 256B / 257B transcoding on the 66b code blocks encoded by the current MAC packet, there are two remaining 66b code blocks, D and T, where D is a data code block and T is an end code block, and the next MAC packet has not been received. 2 66b Idle code blocks are inserted after the T code block corresponding to this MAC packet and are transcoded together with the remaining D code block and T code block of the current MAC packet into a 257b code block.

[0073] In some embodiments, after completing the transcoding of the current MAC packet into 257B, when the next MAC packet is not received within the first threshold, 4 66b idle code blocks are inserted and the 4 66b idle code blocks are transcoded into one 257b idle code block, where the first threshold is a set fixed value. Exemplarily, the first threshold may be the transmission time corresponding to 4 66b code blocks.

[0074] Through the embodiments of the present application, it is possible to convert the MAC packet into the 256B / 257B format, laying a foundation for subsequent nodes to adjust the rate based on the 257b idle code block to support the development of higher-speed Ethernet technologies.

[0075] In some embodiments, the transcoded 257b code block includes at least one of the following types:

[0076] 257b start code block, formed by transcoding one 66b start code block (S) and three 66b data code blocks (D);

[0077] 257b end code block, composed of a first number a1 of 66b data code blocks (D), one 66b end code block (T), and a second number a2 of 66b idle code blocks (I), where a1≥0, a2≥0, and a1 + a2 = 3;

[0078] 257b idle code block, formed by transcoding four 66b idle code blocks;

[0079] 257b data code block, formed by transcoding four 66b data code blocks;

[0080] 257b error code block, formed by transcoding four 66b error code blocks (error);

[0081] 257b ordered code block, formed by transcoding four 66b ordered code blocks (O);

[0082] 257b connection code block, formed by transcoding one 66b end code block (T), one 66b start code block (S), and two 66b data code blocks (D), where the 66b end code block (T) is located before the 66b start code block (S).

[0083] In this embodiment, when inserting a 257b idle code block into the 257b data stream for rate adjustment, the 257b idle code block is inserted after the 257b end code block or after the 257b idle code block.

[0084] Figure 4 is a schematic diagram of the 257b idle code block according to the embodiments of the present application. As Figure 4 shown, the 257b idle code block is formed by transcoding four 66b idle code blocks and is recognized through the first mode.

[0085] In this embodiment, the first pattern is that the first bit of 257b is 0, the second to fifth bits are 0000, and a first fixed pattern; the first fixed pattern is at least one of the following: the sixth to ninth bits are 0111 (the reverse of 0xE), and the tenth to sixty-fifth bits are all 0; the sixth to thirteenth bits are 01110000 (the reverse of 0x1E).

[0086] Figure 5 is a schematic diagram of a 257b end code block according to an embodiment of the present application, as Figure 5 shown, there are 4 types of 257b end code blocks.

[0087] In this embodiment, the 257b end code block is composed of a first quantity a1 of 66b data code blocks, 1 66b end code block, and a second quantity a2 of 66b idle code blocks. Among them, a1≥0, a2≥0, a1 + a2 = 3, the 66b end code block can be located at any position of the 257b code block, and the 66b end code block is located after the 66b data code block and before the 66b idle code block.

[0088] In this embodiment, the combination methods of 4 66b coding blocks in the 257b end code block include: TIII, DTII, DDTI, and DDDT.

[0089] In this embodiment, the 257b end code block is identified by a second pattern, and the second pattern is that the first bit of 257B is 0, the second to fifth bits are 0000, and the sixth to ninth bits are a fixed type.

[0090] In some embodiments, the fixed Type includes any one of the following: 1001 (the reverse of 0x9), 0101 (the reverse of 0xA), 0010 (the reverse of 0x4), 0011 (the reverse of 0xC), 0100 (the reverse of 0x2), 1000 (the reverse of 0x1), 1111 (the reverse of 0xF).

[0091] In some embodiments, the second pattern is that the first bit of 257b is 0, the second to fifth bits are 1000 or 1110; or the second pattern is that the first bit of 257b is 0, the second to fifth bits are 1100, and the two-hundred-and-second to two-hundred-and-fifty-seventh bits are all 0.

[0092] Figure 6 is a processing flow chart (one) of an intermediate node according to an embodiment of the present application, as Figure 6 shown, this process includes the following steps:

[0093] Step S602, receiving a 257b-based code stream from the upstream;

[0094] Step S604, perform swapping processing based on 257b code blocks;

[0095] Step S606, perform rate adaptation based on 257b code blocks;

[0096] Step S608, send the 257b-based code stream downstream.

[0097] This embodiment is applied to a scenario where an intermediate node supports 257b code block swapping. The intermediate node receives a 257b data stream from the upstream, performs 257b code block swapping, and performs rate adaptation after 257b code block swapping by inserting 257b code blocks after the 257b termination code block or after the 257b idle code block or removing the 257b idle code blocks in the 257b code stream. The 257b termination code block is identified by the second mode, and the 257b idle code block is identified by the first mode.

[0098] Through the embodiments of the present application, the hardware implementation complexity of rate adaptation under a high-speed interface can be reduced, the problem that the implementation complexity of the rate adaptation mechanism of a high-speed Ethernet is high as the rate increases in the related art can be solved, and the development of an Ethernet technology with a higher rate can be better supported.

[0099] Figure 7 is a processing flow chart (two) of an intermediate node according to an embodiment of the present application, as Figure 7 shown. The process includes the following steps:

[0100] Step S701, receive a 257b-based code stream from the upstream;

[0101] Step S702, delete 257b idle code blocks at a fixed ratio;

[0102] Step S703, convert 256B / 257B to 64B / 66B;

[0103] Step S704, perform swapping processing based on 66b code blocks;

[0104] Step S705, convert 64B / 66B to 256B / 257B;

[0105] Step S706, perform rate adaptation based on 257b code blocks;

[0106] Step S707, send the 257b-based code stream downstream.

[0107] This embodiment is applied to a scenario where an intermediate node supports 66b code block switching. The intermediate node receives a 257B data stream from the upstream, and deletes idle 257b code blocks in the data stream at a fixed ratio, that is, deletes one idle 257b code block every M 257b code blocks. The fixed ratio is a statistical ratio, that is, within a certain time range, after statistical calculation, one idle code block is deleted every M 257b code blocks. The data stream speed is reduced by deleting 257B idle code blocks. Then, the 257b code blocks are transcoded into 66b code blocks for 66b code block switching, and after the 66b code block switching, they are transcoded back into 257b code blocks. Then, rate adaptation is performed by inserting 257b code blocks after the 257b end code blocks or after the 257b idle code blocks, or by removing 257b idle code blocks from the 257B code stream. The 257b end code blocks are identified by the second mode, and the 257b idle code blocks are identified by the first mode.

[0108] Figure 8 is a processing flowchart (III) of an intermediate node according to an embodiment of the present application, as Figure 8 shown. This process includes the following steps:

[0109] Step S801: Receive a 257b-based code stream from the upstream;

[0110] Step S802: Transcode 256B / 257B to 64B / 66B;

[0111] Step S803: Perform switching processing based on 66b code blocks;

[0112] Step S804: Perform rate adaptation based on 66b code blocks;

[0113] Step S805: Transcode 64B / 66B to 256B / 257B;

[0114] Step S806: Send a 257b-based code stream to the downstream.

[0115] This embodiment is applied to a scenario where an intermediate node supports 66b code block switching. A 257b data stream is received from the upstream, the 257b code blocks are transcoded into 66b code blocks for 66b code block switching, rate adaptation is performed after the 66b code block switching, and then transcoded back into 257b code blocks. During the transcoding process from 66b to 257b, adjustment processing of 66b idle code blocks is performed to make the type of the transcoded 257b code blocks consistent with the type of the 257b code blocks transcoded by the source node. The adjustment processing includes one of the following: shifting, adding, deleting.

[0116] Figure 9 is a schematic diagram of 257b error code blocks according to an embodiment of the present application, as Figure 9As shown, the 257b error code block is transcoded from 4 66b error code blocks.

[0117] In this embodiment, on the receiving side of any node, it is necessary to perform decoding processing of forward error correction (FEC) on the 257b code block data stream. During the FEC decoding process, there may be a situation where there are too many error codes and FEC cannot fully correct them. In this case, error marking is performed on all 257bs included in the FEC codeword, and the error marking is to replace the 257b code block with a 257b error code block.

[0118] In this embodiment, the 257b error code block is transcoded from 4 66b error code blocks and is identified through the third mode. Exemplarily, the third mode is that the first bit of 257b is 0, the second to fifth bits are 0000, and the second fixed pattern; the second fixed pattern is at least one of the following: the sixth to ninth bits are 0111 (the reverse order of 0xE), the tenth to 65th bits are 8 0111100 (the reverse order of 0011110), that is, 01111000111100011110001111000111100011110001111000111100; the sixth to 13th bits are 01110111 (the reverse order of 0x1E).

[0119] In another embodiment of the present application, a node is further provided. It is applied in an Ethernet, especially in a high-speed Ethernet, to better support the development of higher-rate Ethernet technologies.

[0120] Figure 10 It is a block diagram of a node in an embodiment of the present application, as Figure 10 shown, the node includes:

[0121] An acquisition module 102, configured to acquire a target code stream in 256B / 257B format;

[0122] A rate adjustment module 104, configured to adjust the rate of the target code stream by adding or deleting 257b idle code blocks.

[0123] In some embodiments, the rate adjustment module 104 includes an insertion module and a deletion module; the insertion module is configured to insert the 257b idle code block after the 257b termination code block or the 257b idle code block in the target code stream; the deletion module is configured to delete the 257b idle code block from the target code stream.

[0124] In this embodiment, the 257b idle code block is used as the basic unit for adjusting the bitstream rate, which can reduce the complexity of the rate adaptation mechanism in hardware implementation. Deleting the 257b idle code block in the target bitstream can increase the bitstream rate, and adding a new 257b idle code block to the target bitstream can decrease the bitstream rate.

[0125] In some embodiments, the target bitstream in 256B / 257B format consists of multiple 257b encoded blocks, and each 257b encoded block is formed by transcoding 4 66b encoded blocks in 256B / 257B format.

[0126] In some embodiments, the 257b idle code block (I) is formed by transcoding 4 66b idle code blocks; the 257b end code block is formed by transcoding a first quantity of 66b data code blocks (D), 1 66b end code block (T), and a second quantity of 66b idle code blocks (I), where the first quantity and the second quantity are greater than or equal to zero, and the sum of the first quantity and the second quantity is equal to 3.

[0127] In an exemplary embodiment, each 257b encoded block can be represented by the symbols of 4 66b encoded blocks, where the combination modes of the 4 66b encoded blocks in the 257b end code block include: TIII, DTII, DDTI, and DDDT.

[0128] In some embodiments, the node further includes: an identification module, configured to identify the 257b idle code block in the target bitstream through a first mode before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks.

[0129] Exemplarily, the first mode includes: the first bit is 0, the second to fifth bits are 0000, and a first preset pattern; the first preset pattern includes at least one of the following: the sixth to ninth bits are 0111, and the tenth to sixty-fifth bits are all 0; the sixth to thirteenth bits are 01110000.

[0130] In some embodiments, the identification module is further configured to identify the 257b end code block in the target bitstream through a second mode before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks.

[0131] Exemplarily, the second mode includes at least one of the following:

[0132] The first bit is 0, the second to fifth bits are 0000, and the sixth to ninth bits are of a preset type;

[0133] The first bit is 0, and the second to fifth bits are 1000 or 1110;

[0134] The first bit is 0, the second to fifth bits are 1100, and the 202nd to 257th bits are all 0.

[0135] In some embodiments, the 257b encoding block further includes: a 257b start code block, where the 257b start code block is transcoded from 1 66b start code block and 3 66b data code blocks. Exemplarily, the 257b start code block can be represented as SDDD.

[0136] In some embodiments, the 257b encoding block further includes: a 257b connection code block, where the 257b connection code block is transcoded from one 66b end code block, one 66b start code block, and 2 66b data code blocks, and the 66b end code block is located before the 66b start code block.

[0137] In some embodiments, the 257b connection code block is transcoded from any of the following combinations:

[0138] The 66b data code block, the 66b data code block, the 66b end code block, and the 66b start code block;

[0139] The 66b data code block, the 66b end code block, the 66b start code block, and the 66b data code block;

[0140] The 66b end code block, the 66b start code block, the 66b data code block, and the 66b data code block.

[0141] In an exemplary embodiment, the 257b connection code block can be represented as DDTS, DTSD, or TSDD. The 257b connection code block is used to connect two data packets. The T code block in the 257b connection code block is the tail of the previous data packet, and the S code block is the head of the next data packet.

[0142] In some embodiments, the acquisition module 102 includes a forwarding module and a receiving module; a transcoding module, configured to perform 64B / 66B encoding on the Ethernet MAC packet to obtain a first code stream in 64B / 66B format, and perform 256B / 257B transcoding on the first code stream to obtain the target code stream; a receiving module, configured to receive the target code stream sent by the previous node, where the target code stream is formed by performing 64B / 66B encoding and 256B / 257B transcoding on the Ethernet MAC packet.

[0143] In some embodiments, the first code stream is composed of multiple 66b encoding blocks, and the 66b encoding block includes: a 66b start code block, a 66b data code block, and a 66b end code block, and the first code stream does not include 66b idle code blocks.

[0144] In this embodiment, each Ethernet MAC packet can be transcoded to form a set of 66b encoded blocks. Each set of 66b encoded blocks consists of a 66b start code block (S), several 66b data code blocks (D), and a 66b end code block (T). It does not include 66b idle code blocks (I).

[0145] Exemplarily, during the 64B / 66B encoding process of the Ethernet MAC packet, 8 consecutive Interpacket Gap (IPG) bytes will not be encoded into a 66b idle code block.

[0146] In this embodiment, the transcoding module is further configured to, when the number of remaining 66b encoded blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet has not been received, insert at least one 66b idle code block into the 66b end code block corresponding to the current MAC packet and then perform 256B / 257B transcoding to obtain the 257b end code block in the target code stream.

[0147] In some embodiments, when the number of remaining 66b encoded blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet has been received, a 257b connection code block is used to connect two Ethernet MAC packets. The 257b connection code block can be transcoded from the remaining 66b encoded blocks of the current MAC packet and the 66b encoded blocks at the head of the next MAC packet.

[0148] In some embodiments, the transcoding module is further configured to, when the next Ethernet MAC packet has not been received within a preset first threshold after the transcoding of the current MAC packet is completed, insert a 257b idle code block into the target code stream, where the 257b idle code block is transcoded from 4 66b idle code blocks.

[0149] In some embodiments, the receiving module includes a receiving unit and a decoding unit; the receiving unit is configured to receive the data stream obtained by performing forward error correction coding FEC on the target code stream sent by the previous node; the decoding unit is configured to perform forward error correction decoding processing on the data stream to obtain the target code stream; in the case where FEC cannot correct errors, all 257b encoded blocks in the corresponding FEC codeword in the target code stream are replaced with 257b error code blocks.

[0150] In some embodiments, the FEC codeword is 255 bytes long and consists of 239 bytes of normal data and 16 bytes of redundant overhead. If a certain FEC codeword decoding fails, all 257b encoded blocks in the FEC codeword need to be replaced with 257b error code blocks.

[0151] In some embodiments, the 257b error code block is transcoded from 4 66b error code blocks.

[0152] In some embodiments, the 257b error code block may be identified through a preset third mode. Exemplarily, the third mode includes that the first bit is 0, the second to fifth bits are 0000, and a second preset pattern; wherein, the second preset pattern includes at least one of the following: the sixth to ninth bits are 0111, the tenth to sixty-fifth bits are eight 0111100; the sixth to thirteenth bits are 01110111.

[0153] In some embodiments, when the current node is an intermediate node supporting 257b coded block swapping, the rate adjustment module 104 includes:

[0154] A 257b swapping unit, configured to perform swapping processing on the target bitstream based on 257b coded blocks to obtain a target bitstream after the swapping processing;

[0155] A 257b rate adjustment unit, configured to adjust the rate of the target bitstream after the swapping processing by adding or deleting the 257b idle code blocks.

[0156] In some embodiments, when the current node is an intermediate node supporting 66b coded block swapping, the rate adjustment module 104 includes:

[0157] A 66b transcoding unit, configured to transcode the target bitstream to obtain a second bitstream in 64B / 66B format, wherein the second bitstream includes 66b idle code blocks;

[0158] A 66b swapping unit, configured to perform swapping processing on the second bitstream based on 66b coded blocks to obtain a second bitstream after the swapping processing;

[0159] A 66b rate adjustment unit, configured to adjust the rate of the second bitstream after the swapping processing by adding or deleting the 66b idle code blocks to obtain a second bitstream after the rate adjustment;

[0160] A 257b transcoding unit, configured to perform 256B / 257B transcoding on the second bitstream after the rate adjustment, and perform shifting, adding or deleting processing on the 66b idle code blocks in the second bitstream after the rate adjustment during the transcoding process to obtain a target bitstream after the rate adjustment in 256B / 257B format, wherein the 257b coded blocks in the target bitstream after the rate adjustment are of the same type as the 257b coded blocks in the target bitstream.

[0161] In some embodiments, when the current node is an intermediate node supporting 66b coded block swapping, the rate adjustment module 104 includes:

[0162] A speed reduction unit, configured to delete some 257b idle code blocks in the target bitstream according to a preset proportional coefficient, so as to obtain a speed-reduced target bitstream;

[0163] A 66b transcoding unit, configured to transcode the speed-reduced target bitstream to obtain a second bitstream in 64B / 66B format, where the second bitstream includes 66b idle code blocks;

[0164] A 66b swapping unit, configured to perform a swapping process on the second bitstream based on 66b encoded blocks to obtain a second bitstream after the swapping process;

[0165] A 257b transcoding unit, configured to perform 256B / 257B transcoding on the second bitstream after the swapping process to obtain a target bitstream after the swapping process;

[0166] A 257b rate adjustment unit, configured to adjust the rate of the target bitstream after the swapping process by adding or deleting the 257b idle code blocks.

[0167] Through the embodiments of the present application, a rate adaptation mechanism based on 257b bitstreams can be implemented, reducing the hardware implementation complexity of rate adaptation under high-speed interfaces, and thus solving the problem of high implementation complexity of the rate adaptation mechanism of high-speed Ethernet as the rate increases, and better supporting the development of high-speed Ethernet technology.

[0168] The embodiments of the present application further provide a computer-readable storage medium, in which a computer program is stored, where the computer program, when run by a processor, executes the steps in any one of the above method embodiments.

[0169] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc, and other various media that can store computer programs.

[0170] The embodiments of the present application further provide an electronic device, including a memory and a processor, where a computer program is stored in the memory, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0171] In an exemplary embodiment, the above electronic device may further include a transmission device and an input / output device, where the transmission device is connected to the above processor, and the input / output device is connected to the above processor.

[0172] For the specific examples in this embodiment, reference may be made to the examples described in the above embodiments and exemplary embodiments, and details thereof will not be repeated here.

[0173] Obviously, those skilled in the art should understand that the various modules or steps of the present application described above can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed over a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device. Thus, they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order than here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module for implementation. In this way, the present application is not limited to any specific combination of hardware and software.

[0174] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application shall be included in the protection scope of the present application.

Claims

1. A rate adjustment method, characterized in that, The method includes: Obtaining a target bitstream in 256B / 257B format; Adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks.

2. The method according to claim 1, characterized in that Adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks includes: Inserting the 257b idle code block after a 257b termination code block or the 257b idle code block in the target bitstream; Or, deleting the 257b idle code block from the target bitstream.

3. The method according to claim 2, wherein The 257b idle code block is transcoded from 4 66b idle code blocks; The 257b termination code block is transcoded from a first quantity of 66b data code blocks, 1 66b termination code block, and a second quantity of 66b idle code blocks, wherein the first quantity and the second quantity are greater than or equal to zero, and the sum of the first quantity and the second quantity is equal to 3.

4. The method according to claim 2, wherein Before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks, the method further includes: Identifying the 257b idle code block in the target bitstream through a first pattern; Wherein, the first pattern includes: the first bit is 0, the second to fifth bits are 0000, and a first preset pattern; Wherein, the first preset pattern includes at least one of the following: The sixth to ninth bits are 0111, and the tenth to 65th bits are all 0; The sixth to 13th bits are 01110000.

5. The method according to claim 2, characterized in that, Before adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks, the method further includes: Identifying the 257b termination code block in the target bitstream through a second pattern; Wherein, the second pattern includes at least one of the following: The first bit is 0, the second to fifth bits are 0000, and the sixth to ninth bits are of a preset type; The first bit is 0, the second to fifth bits are 1000 or 1110; The first bit is 0, the second to fifth bits are 1100, and the 202nd to 257th bits are all 0.

6. The method according to claim 1, characterized in that, The target bitstream is composed of multiple 257b coding blocks, and the 257b coding block further includes: a 257b start code block, wherein the 257b start code block is transcoded from 1 66b start code block and 3 66b data code blocks.

7. The method according to claim 1, characterized in that, The target bitstream is composed of multiple 257b coding blocks, and the 257b coding block further includes: a 257b connection code block, wherein the 257b connection code block is transcoded from one 66b termination code block, one 66b start code block, and 2 66b data code blocks, and the 66b termination code block is located before the 66b start code block.

8. The method according to claim 1, wherein Obtaining a target bitstream in 256B / 257B format includes: Performing 64B / 66B encoding on an Ethernet MAC packet to obtain a first bitstream in 64B / 66B format, and performing 256B / 257B transcoding on the first bitstream to obtain the target bitstream.

9. The method according to claim 1, characterized in that Obtain the target code stream in 256B / 257B format, including: receiving the target code stream sent by the previous node, where the target code stream is formed by performing 64B / 66B encoding and 256B / 257B transcoding on the Ethernet MAC packet.

10. The method according to claim 8, wherein When performing 64B / 66B encoding on the Ethernet MAC packet, the inter-frame gap bytes in the Ethernet MAC packet are not encoded into 66b idle code blocks. The first code stream includes 66b start code blocks, 66b data code blocks, and 66b end code blocks, and the 66b idle code blocks are not included in the first code stream.

11. The method according to claim 8, wherein Perform 256B / 257B transcoding on the first code stream to obtain the target code stream, including: transcoding the 66b end code block of the current MAC packet and the 66b start code block of the next MAC packet in the first code stream into a 257b connection code block, where the 257b connection code block does not contain 66b idle code blocks.

12. The method according to claim 8, wherein Perform 256B / 257B transcoding on the first code stream to obtain the target code stream, including: When the number of remaining 66b encoded blocks of the current MAC packet in the first code stream is less than 4 and the next Ethernet MAC packet has not been received, insert at least one 66b idle code block into the 66b end code block corresponding to the current MAC packet and then perform 256B / 257B transcoding.

13. The method according to claim 8, characterized in that Perform 256B / 257B transcoding on the first code stream to obtain the target code stream, further including: When the next Ethernet MAC packet has not been received within a preset first threshold after the transcoding of the current MAC packet in the first code stream is completed, insert 257b idle code blocks into the target code stream, where the 257b idle code blocks are formed by transcoding 4 66b idle code blocks.

14. The method according to claim 9, wherein Receive the target code stream sent by the previous node, including: Receive the data stream obtained by performing forward error correction coding FEC on the target code stream sent by the previous node; Perform forward error correction decoding processing on the data stream to obtain the target code stream; In the case where FEC cannot correct errors, replace all 257b encoded blocks in the corresponding FEC codeword in the target code stream with 257b error code blocks.

15. According to the method described in claim 14, characterized in that, The 257b error code block is formed by transcoding 4 66b error code blocks; The 257b error code block is identified through a preset third mode, where the third mode includes that the first bit is 0, the second to fifth bits are 0000, and a second preset pattern; Wherein, the second preset pattern includes at least one of the following: The sixth to ninth bits are 0111, and the tenth to sixty-fifth bits are 8 0111100s; The sixth to thirteenth bits are 01110111.

16. The method according to claim 1, wherein In the case where the current node is an intermediate node supporting 257b code block exchange, perform rate adjustment on the target code stream by adding or deleting 257b idle code blocks, including: Perform exchange processing on the target code stream based on 257b code blocks to obtain the target code stream after exchange processing; The rate of the target bitstream after the swapping process is adjusted by adding or deleting the 257b idle code blocks.

17. The method according to claim 1, characterized in that, When the current node is an intermediate node supporting 66b coded block swapping, adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks includes: Transcoding the target bitstream to obtain a second bitstream in 64B / 66B format, where the second bitstream includes 66b idle code blocks; Performing a swapping process on the second bitstream based on 66b coded blocks to obtain a swapped second bitstream; Adjusting the rate of the swapped second bitstream by adding or deleting the 66b idle code blocks to obtain a rate-adjusted second bitstream; Performing 256B / 257B transcoding on the rate-adjusted second bitstream, and during the transcoding process, performing shifting, adding, or deleting operations on the 66b idle code blocks in the rate-adjusted second bitstream to obtain a rate-adjusted target bitstream in 256B / 257B format, where the 257b coded blocks in the rate-adjusted target bitstream are of the same type as the 257b coded blocks in the target bitstream.

18. The method according to claim 1, characterized in that, When the current node is an intermediate node supporting 66b coded block swapping, adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks includes: Deleting some of the 257b idle code blocks in the target bitstream according to a preset proportional coefficient to obtain a rate-reduced target bitstream; Transcoding the rate-reduced target bitstream to obtain a second bitstream in 64B / 66B format, where the second bitstream includes 66b idle code blocks; Performing a swapping process on the second bitstream based on 66b coded blocks to obtain a swapped second bitstream; Performing 256B / 257B transcoding on the swapped second bitstream to obtain a swapped target bitstream; Adjusting the rate of the swapped target bitstream by adding or deleting the 257b idle code blocks.

19. A node, characterized in that, The node includes: An acquisition module for acquiring a target bitstream in 256B / 257B format; A rate adjustment module for adjusting the rate of the target bitstream by adding or deleting 257b idle code blocks.

20. A computer-readable storage medium, characterized in that, The computer program is stored in the storage medium, where the computer program, when run by the processor, executes the method described in any one of claims 1 to 18.

21. An electronic device, comprising a memory and a processor, characterized in that, The computer program is stored in the memory, and the processor is configured to run the computer program to execute the method described in any one of claims 1 to 18.

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