Display panel driving method and display device

Abstract

The embodiment of the invention provides a display panel driving method and a display device. The display panel driving method comprises the following steps: generating a light-emitting control time sequence signal comprising a plurality of light-emitting sub-time sequences; wherein for each light-emitting sub-time sequence, the light-emitting sub-time sequence comprises at least one first-type pulse and a plurality of second-type pulses, the first-type pulses are located before the second-type pulses, and the time length of the first-type pulses is larger than that of the second-type pulses; the first type of pulse and the second type of pulse are effective levels; and scanning a pixel circuit of the display panel by using the light-emitting control time sequence signal. By increasing the time duration of the first type of pulses, improving the peak current density of the first type of pulses, improving the current ratio of a normal light-emitting path and reducing the current ratio of a micro-short-circuit path, brightness overshoot can be weakened, the trailing problem is further improved, and the display quality is improved.

Description

Technical Field

[0001] The present application relates to the technical field of displays, and particularly to a display panel driving method and a display device. Background Art

[0002] Current Tandem OLED (Tandem Organic Light-Emitting Diode, where "Tandem" refers to a double-layer tandem structure design) devices can meet the peak brightness requirement of over 3000 nits (nit, a unit of brightness), and have the characteristics of low power consumption and long lifespan. However, the display quality is poor. Specifically, as Figure 1a shown, in a low-brightness / low-gray-scale dynamic application scenario, when switching from the L0 (gray-scale level) to the L32 screen, there is an obvious brightness overshoot from the 2nd frame to the 5th frame, which further leads to an obvious trailing problem.

[0003] The root cause of the above problem lies in the structure of the Tandem OLED device. As Figure 1b shown, the core structure of Tandem OLED is to vertically stack multiple independent light-emitting units (light-emitting layer + functional layer), and the light-emitting units are connected by a charge generation layer CGL (Charge Generation Layer, including P-CGL and N-CGL). Each light-emitting unit contains a complete light-emitting structure, such as a hole transport layer (Hole Transport Layer, HTL), a light-emitting layer EL, an electron transport layer (Electron Transport Layer, ETL), etc. There are capacitances in the upper and lower light-emitting layers of the Tandem OLED device (the upper light-emitting layer is the light-emitting layer close to the cathode Cathode, and the lower light-emitting layer is the light-emitting layer close to the anode Anode). In the case of low brightness / low gray scale, the equivalent internal resistances R1 and R2 of the light-emitting layer (Emission Layer, EL) increase significantly. At this time, the short-circuit path resistance R3 of the charge generation layer CGL (the charge generation layer CGL is short-circuited with the cathode Cathode) is close to the internal resistance of the light-emitting layer EL. As Figure 1c shown, the current will pass through both path 1 and path 2 simultaneously (path 1 is the normal light-emitting path, which needs to charge the capacitance first and then drive the light-emitting layer EL, with a slow response but a stable current; path 2 is a micro-short-circuit path, which does not need to charge the capacitance, that is, it directly conducts bypassing the capacitance, with a fast response but an instantaneous increase in current). In the case of low brightness / low gray scale, the charging speed of the capacitance in path 1 is slow (the equivalent internal resistance is large), and the conduction ratio of path 2 increases. At this time, the higher the current ratio of path 2, the greater the total current, and the brightness far exceeds the expectation, resulting in a brightness overshoot phenomenon, which further leads to a trailing problem.

[0004] To solve the above problems, in related technologies, voltage optimization schemes such as increasing the L0 coefficient (gray-scale voltage adjustment parameter), increasing Vini3 (voltage signal for resetting the transistor gate in the initialization stage), increasing the voltage difference between Vini2 (voltage signal for resetting the transistor drain in the initialization stage) and ELVSS (source reference voltage signal of the reset transistor), and ODC (OverDriving Compensation) compensation (which can only adjust the brightness of the first frame) are usually adopted, but there is no obvious improvement. Summary of the Invention

[0005] The purpose of the embodiments of the present application is to provide a display panel driving method and a display device to improve the display quality. The specific technical solutions are as follows:

[0006] In a first aspect, the embodiments of the present application provide a display panel driving method, and the method includes:

[0007] Generating a light-emitting control timing signal including multiple light-emitting sub-timings; wherein, for each light-emitting sub-timing, the light-emitting sub-timing includes at least one first type of pulse and multiple second type of pulses, the first type of pulse is located before the second type of pulses, the time length of the first type of pulse is greater than the time length of the second type of pulses, and the first type of pulse and the second type of pulses are effective levels;

[0008] Scanning the pixel circuit of the display panel by using the light-emitting control timing signal.

[0009] In a possible implementation manner, the method further includes:

[0010] Generating a reset control timing signal including multiple third type of pulses; wherein, in the time sequence, there is a third type of pulse before each first type of pulse / second type of pulse, and the third type of pulse is an effective level;

[0011] Scanning the pixel circuit by using the reset control timing signal.

[0012] In a possible implementation manner, the time length of the first type of pulse is Nd, where the value range of N is 64 ≤ N ≤ 88, and d represents the clock cycle unit.

[0013] In a possible implementation manner, the time length of the second type of pulse is Md, where the value range of M is 4 ≤ M ≤ 16, and d represents the clock cycle unit.

[0014] In a possible implementation manner, the time length of the third type of pulse is Qd, where the value range of Q is 4 ≤ Q ≤ 16, and d represents the clock cycle unit.

[0015] In a possible implementation, for each light-emitting sub-timing, the light-emitting sub-timing includes a plurality of first-type pulses and a plurality of second-type pulses. For any two adjacent first-type pulses, the time length of the first-type pulse farther from the second-type pulse is greater than the time length of the first-type pulse closer to the second-type pulse;

[0016] For any two adjacent second-type pulses, the time length of the second-type pulse closer to the first-type pulse is greater than the time length of the second-type pulse farther from the first-type pulse.

[0017] In a possible implementation, for each light-emitting sub-timing, the light-emitting sub-timing includes one first-type pulse and a plurality of second-type pulses, and the time length of each of the second-type pulses is less than a preset duration threshold.

[0018] In a possible implementation, the time lengths of all the third-type pulses are the same.

[0019] In a second aspect, an embodiment of the present application provides a display device, and the display device includes a display panel and a display driving chip;

[0020] The display panel includes multiple rows of pixel rows; each of the pixel rows includes a plurality of pixel circuits;

[0021] The display driving chip is configured to: generate a light-emitting control timing signal including a plurality of light-emitting sub-timings; wherein, for each light-emitting sub-timing, the light-emitting sub-timing includes at least one first-type pulse and a plurality of second-type pulses, the first-type pulse is located before the second-type pulse, the time length of the first-type pulse is greater than the time length of the second-type pulse, and the first-type pulse and the second-type pulse are valid levels; use the light-emitting control timing signal to scan the pixel circuits of the display panel.

[0022] In a possible implementation, the display device further includes a timing control circuit;

[0023] The timing control circuit is configured to: generate a reset control timing signal including a plurality of third-type pulses; wherein, in chronological order, there is a third-type pulse before each first-type pulse / second-type pulse, and the third-type pulse is a valid level; use the reset control timing signal to scan the pixel circuits.

[0024] Advantageous effects of the embodiments of the present application:

[0025] A display panel driving method and a display device provided by an embodiment of the present application. The driving method includes: generating a light-emitting control timing signal including a plurality of light-emitting sub-timings; wherein, for each light-emitting sub-timing, the light-emitting sub-timing includes at least one first type of pulse and a plurality of second type of pulses, the first type of pulse is located before the second type of pulses, the time length of the first type of pulse is greater than the time length of the second type of pulses, and the first type of pulse and the second type of pulses are at an effective level; using the light-emitting control timing signal to scan the pixel circuits of the display panel. By increasing the time length of the first type of pulse, the peak current density of the light-emitting layer can be increased, the current ratio of the normal light-emitting path can be increased, and the current ratio of the micro-short circuit path can be reduced, so as to weaken the brightness overshoot, and further improve the trailing problem, thereby improving the display quality.

[0026] Of course, when implementing any product or method of the present application, it is not necessarily required to achieve all the above-mentioned advantages at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are only some embodiments of the present application, and those of ordinary skill in the art can also obtain other embodiments based on these drawings.

[0028] Figure 1a It is a schematic diagram of the brightness waveform when switching from L0 to L32 in the related art;

[0029] Figure 1b It is a schematic diagram of the structure of a Tandem OLED device in the related art;

[0030] Figure 1c It is a schematic diagram of the normal light-emitting path and the micro-short circuit path in the related art;

[0031] Figure 2a It is the first flow schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0032] Figure 2b It is a schematic diagram of the timing waveforms of the EM signal and the Reset-H signal when switching from L0 to L32 in the related art;

[0033] Figure 2c It is a schematic diagram of the improved timing waveforms of the EM signal and the Reset-H signal in the embodiment of the present application;

[0034] Figure 2d It is a schematic diagram of the brightness waveform when switching from L0 to L32 in the embodiment of the present application;

[0035] Figure 3The second process schematic diagram of the display panel driving method provided by the embodiment of the present application;

[0036] Figure 4 The first structural schematic diagram of the display device provided by the embodiment of the present application;

[0037] Figure 5 The second structural schematic diagram of the display device provided by the embodiment of the present application;

[0038] Figure 6 A structural schematic diagram of the pixel circuit of the display device provided by the embodiment of the present application. Detailed implementation manners

[0039] Next, the technical solutions in the embodiments of the present application will be clearly and completely described in conjunction with the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art based on the present application belong to the protection scope of the present application.

[0040] The current Tandem OLED (Tandem Organic Light-Emitting Diode, "Tandem" refers to the double-layer series structure design) device can meet the peak brightness requirement of more than 3000 nits (nit, luminance unit), and has the characteristics of low power consumption and high lifespan, but the display quality is poor. Specifically, as Figure 1a shown, in the low-brightness / low-gray-scale dynamic application scenario, when switching from L0 (gray-scale level) to the L32 screen, there is an obvious brightness overshoot in the 2nd to 5th frames, which further leads to an obvious trailing problem. Figure 1a In [the figure], the abscissa represents time, with the unit of s (second), and the ordinate represents luminance, with the unit of nit (nit).

[0041] The root cause of the above problem lies in the structure of the Tandem OLED device, as Figure 1bAs shown in the figure, the core structure of the Tandem OLED is to vertically stack multiple independent light-emitting units (light-emitting layer + functional layer). The light-emitting units are connected by a charge generation layer CGL (Charge Generation Layer, including P-CGL and N-CGL). Each light-emitting unit contains a complete light-emitting structure, such as a hole transport layer (Hole Transport Layer, HTL), a light-emitting layer (Emission Layer, EL, including organic materials of red RED, green GREEN, and blue BLUE sub-pixels, where holes and electrons recombine to emit light), an electron transport layer (Electron Transport Layer, ETL), etc. There are capacitances in the upper and lower light-emitting layers of the Tandem OLED device (the upper light-emitting layer is the light-emitting layer close to the cathode Cathode, and the lower light-emitting layer is the light-emitting layer close to the anode Anode). In the case of low brightness / low gray scale, the equivalent internal resistances R1 and R2 of the light-emitting layer EL increase significantly. At this time, the short-circuit path resistance R3 of the charge generation layer CGL (the charge generation layer CGL is short-circuited with the cathode Cathode) is close to the internal resistance of the light-emitting layer EL, as Figure 1c shown in the figure, the current will pass through path 1 and path 2 simultaneously (path 1 is the normal light-emitting path, which needs to charge the capacitance first and then drive the light-emitting layer EL, with a slow response but a stable current; path 2 is the micro-short-circuit path, which does not need to charge the capacitance, that is, it bypasses the capacitance and conducts directly, with a fast response but an instantaneous increase in current). In the case of low brightness / low gray scale, the capacitance charging speed of path 1 is slow (the equivalent internal resistance is large), and the conduction ratio of path 2 increases. At this time, the higher the current ratio of path 2, the greater the total current, and the brightness far exceeds the expectation, resulting in a brightness overshoot phenomenon, which further leads to the trailing problem.

[0042] To solve the above problems, in related technologies, voltage optimization schemes such as increasing the L0 coefficient (gray-scale voltage adjustment parameter), increasing Vini3 (the voltage signal used to reset the transistor gate in the initialization stage), increasing the voltage difference between Vini2 (the voltage signal used to reset the transistor drain in the initialization stage) and ELVSS (the source reference voltage signal of the reset transistor), and ODC (OverDriving Compensation) compensation (which can only adjust the brightness of the first frame) are usually adopted, but there is no obvious improvement.

[0043] In order to improve at least one of the above problems, an embodiment of the present application provides a display panel driving method and a display device.

[0044] Next, the display panel driving method provided by the embodiment of the present application will be described in detail. Refer to Figure 2a , which is the first flow schematic diagram of the display panel driving method provided by the embodiment of the present application, including the following steps:

[0045] Step S201: Generate a light-emitting control timing signal including multiple light-emitting sub-timings. For each light-emitting sub-timing, the light-emitting sub-timing includes at least one first-type pulse and multiple second-type pulses. The first-type pulse is located before the second-type pulses. The time length of the first-type pulse is greater than the time length of the second-type pulses. The first-type pulse and the second-type pulses are at an active level.

[0046] The light-emitting control timing signal EM (Emission) signal is the core timing signal for controlling the light-emitting stage in the OLED pixel circuit. Its core functions include switch control and brightness adjustment. Switch control means that it acts on the gate of the light-emitting control transistor. By adjusting the gate voltage, it controls the on and off of the transistor, thereby determining whether the OLED emits light. When the light-emitting control transistor is a P-type transistor, when the light-emitting control timing signal EM signal is at a low level, the light-emitting control transistor is turned on and the OLED emits light. When the light-emitting control timing signal EM signal is at a high level, the light-emitting control transistor is turned off and the OLED does not emit light. Brightness adjustment means that in combination with the PWM (Pulse Width Modulation) dimming technology, gray-scale control is achieved by adjusting the duty cycle (the ratio of the light-emitting time) of the EM signal pulse.

[0047] In the related art, when switching from L0 to the L32 screen, the timing waveform of the light-emitting control timing signal EM signal can be seen in Figure 2b , the 12 low-level pulses (active levels) of the EM signal in one frame are set with equal widths, that is, evenly distributed among 12 pulses for light emission. The peak current density of the light-emitting layer EL is low, so the current in the micro-short circuit path dominates, resulting in a brightness overshoot phenomenon.

[0048] Taking the example that the EM signal in one frame in the related art includes 12 pulses, the equal-width setting of the high and low levels of the 12 pulses in the related art can be adjusted to a differential setting of the high and low level widths. See Figure 2c And Figure 2d , the 12 pulses can be divided into 3 groups (3 light-emitting sub-timings). Each group includes 4 pulses (the first-type pulse and the second-type pulses). The setting method of increasing the time length of the first pulse to obtain the first-type pulse and reducing the time length of other pulses to obtain the second-type pulse can be adopted. In addition to Figure 2cFor the shown setting method, it is also possible to adopt the setting method of increasing the time lengths of the first two pulses to obtain the first type of pulses and decreasing the time lengths of other pulses to obtain the second type of pulses (increasing the time lengths of the first two pulses can more effectively improve the overshoot phenomenon of brightness), or other setting methods can also be adopted. In one example, the time lengths of the 4 pulses can be sequentially set to 88d, 4d, 4d, 4d. It is necessary to ensure that the sum of the time lengths of the 4 pulses is equal to the total time length of the original 4 equal-width pulses (100d), where d represents the clock cycle unit. In one example, the time lengths of the 4 pulses can be sequentially set to 76d, 12d, 8d, 4d. In one example, the time lengths of the 4 pulses can be sequentially set to 64d, 28d, 4d, 4d. Sequentially decreasing the time lengths of the 4 pulses can better ensure brightness stability.

[0049] For the case where the time lengths of the 4 pulses are sequentially set to 88d, 4d, 4d, 4d, the time length of the first pulse in each light-emitting sub-timing is increased to the limit, and the time lengths of other pulses are decreased to the limit. That is to say, by concentrating the light emission on the first pulse in each light-emitting sub-timing, the light-emitting peak current density of the normal light-emitting path is increased (similar to quickly charging a capacitor with more force), the current ratio of the normal light-emitting path is increased, and the current ratio of the micro-short circuit path is decreased, which can weaken the overshoot of brightness, and then improve the trailing problem to improve the display quality.

[0050] Step S202: Scan the pixel circuits of the display panel by using the light-emitting control timing signal.

[0051] Use the light-emitting control timing signal EM signal to scan the gates of the light-emitting control transistors of the pixel circuits of the display panel.

[0052] In the embodiments of the present application, by increasing the time length of the first type of pulses, the light-emitting peak current density of the light-emitting layer is increased, the current ratio of the normal light-emitting path is increased, and the current ratio of the micro-short circuit path is decreased, which can weaken the overshoot of brightness, and then improve the trailing problem to improve the display quality.

[0053] In a possible implementation manner, refer to Figure 3 , which is the second flow schematic diagram of the display panel driving method provided by the embodiments of the present application. Based on Figure 2a , the display panel driving method further includes the following steps:

[0054] Step S301: Generate a reset control timing signal including a plurality of third type of pulses; among them, in the time sequence, there is a third type of pulse before each first type of pulse / second type of pulse, and the third type of pulse is an effective level.

[0055] The reset control timing signal Reset-H is a reset signal in display driving, similar to a "forced clear" operation. The function of the reset control timing signal Reset-H is to quickly clear the residual charge in the pixels before each frame of display, ensuring the accurate pixel state during each refresh.

[0056] In the related art, when switching from L0 to the L32 screen, in the case where the reset transistor is a P-type transistor, the timing waveform of the reset control timing signal Reset-H can be seen in Figure 2b , in one frame, the reset control timing signal Reset-H only includes 3 low-level pulses (effective levels), which may cause incomplete reset and residual charge to trigger a smear phenomenon.

[0057] Based on Figure 2b the timing waveform in, the number of low-level pulses of the Reset-H signal in one frame can be adjusted from only 3 to 12, which can be seen in Figure 2c , that is, at the high-level moment (invalid level, the light-emitting control transistor is in the off state) of each light-emitting control timing signal EM, the reset control timing signal reset-H is reset once, equivalent to changing from "coarse adjustment" to "fine adjustment". Each time the light-emitting control timing signal EM is at a high level, the reset-H signal is triggered once, and the charge residue is cleared at a high frequency before the pixel emits light. The high-frequency reset operation reduces the charge residue in the initial stage of each frame, enabling the pixel to reach the target brightness faster when the first frame (the first frame) is displayed, avoiding the "draggy" brightness climb process, thereby reducing the smear phenomenon.

[0058] When the reset control timing signal reset-H is reset, the display screen will briefly dim (brightness drop), but the reset interval of the original 3 low-level pulses is long, resulting in a large brightness drop amplitude. The adjusted 12 low-level pulses make the brightness change of each reset smaller through a more uniform distribution of the reset operation, and the overall average brightness is improved. At the same time, the SVM (Stroboscopic Motion Visibility) can also be improved. SVM is used to measure the clarity of dynamic images. The high-frequency pulses make the charge release more thorough, the pixel response speed faster, and the afterimage and blurring in dynamic images are reduced.

[0059] Step S302: Scan the pixel circuit by using the reset control timing signal.

[0060] Use the reset control timing signal Reset-H to scan the gate of the reset transistor of the pixel circuit; wherein, the reset transistor is used to transmit the reset signal to the gate of the driving transistor of the pixel circuit through its own conduction state.

[0061] In the embodiment of the present application, at the high-level moment of each emission control timing signal EM signal (invalid level, the emission control transistor is in the off state), the reset control timing signal reset-H signal is reset once, that is, through precise reset of "high frequency and small amplitude", the smear phenomenon is improved, the problem of large brightness drop during the reset of the reset-H signal is improved, and the display smoothness and picture clarity are enhanced.

[0062] In a possible implementation manner, the time length of the first type of pulse is Nd, the value range of N is 64 ≤ N ≤ 88, and d represents the clock cycle unit.

[0063] In a possible implementation manner, the time length of the second type of pulse is Md, the value range of M is 4 ≤ M ≤ 16, and d represents the clock cycle unit.

[0064] In a possible implementation manner, the time length of the third type of pulse is Qd, the value range of Q is 4 ≤ Q ≤ 16, and d represents the clock cycle unit.

[0065] In a possible implementation manner, for each emission sub-timing, the emission sub-timing includes a plurality of first type of pulses and a plurality of second type of pulses. For any two adjacent first type of pulses, the time length of the first type of pulse farther from the second type of pulse is greater than the time length of the first type of pulse closer to the second type of pulse;

[0066] For any two adjacent second type of pulses, the time length of the second type of pulse closer to the first type of pulse is greater than the time length of the second type of pulse farther from the first type of pulse.

[0067] By setting the time lengths of the pulses in each emission sub-timing to decrease in sequence, the brightness stability can be improved. In an example, the emission control timing signal EM signal in one frame includes 12 low-level pulses. The 12 pulses are divided into 3 groups (3 emission sub-timings), and each group includes 4 pulses (the first type of pulse and the second type of pulse). The time lengths of the 4 pulses can be set to 76d, 12d, 8d, and 4d in sequence (the total time length of the original 4 equal-width pulses is 100d).

[0068] In the embodiment of the present application, by setting the time lengths of the pulses in each emission sub-timing to decrease in sequence, the brightness stability can be improved.

[0069] In a possible implementation manner, for each emission sub-timing, the emission sub-timing includes one first type of pulse and a plurality of second type of pulses, and the time lengths of all the second type of pulses are less than a preset duration threshold.

[0070] The preset duration threshold is the time length of the low-level equal-width pulse of the light emission control timing signal EM signal in the related art. The time length of each second-type pulse is less than the preset duration threshold. That is to say, the time length of the first pulse in each light emission sub-timing is increased, and the time lengths of other pulses are reduced. By concentrating the light emission on the first pulse in each light emission sub-timing, the light emission peak current density of the normal light emission path is increased (similar to quickly charging a capacitor with more force), the current proportion of the normal light emission path is increased, the current proportion of the micro-short circuit path is reduced, the brightness overshoot can be weakened, and then the trailing problem can be improved to improve the display quality.

[0071] In the embodiment of the present application, by concentrating the light emission on the first pulse in each light emission sub-timing, the light emission peak current density of the normal light emission path is increased (similar to quickly charging a capacitor with more force), the current proportion of the normal light emission path is increased, the current proportion of the micro-short circuit path is reduced, the brightness overshoot can be weakened, and then the trailing problem can be improved to improve the display quality.

[0072] In a possible implementation manner, the time lengths of all the third-type pulses are the same.

[0073] In one example, the time length of each of the third-type pulses may be 4d.

[0074] The embodiment of the present application further provides a display device 1. Refer to Figure 4 , the display device 1 includes a display panel 11 and a display driving chip 12;

[0075] The display panel 11 includes multiple pixel rows; each pixel row includes multiple pixel circuits;

[0076] The display driving chip 12 is configured to: generate a light emission control timing signal including multiple light emission sub-timings; wherein, for each light emission sub-timing, the light emission sub-timing includes at least one first-type pulse and multiple second-type pulses, the first-type pulse is located before the second-type pulses, the time length of the first-type pulse is greater than the time length of the second-type pulses, and the first-type pulse and the second-type pulses are valid levels; use the light emission control timing signal to scan the pixel circuits of the display panel.

[0077] The specific analysis is the same as above and will not be elaborated here.

[0078] In the embodiment of the present application, by increasing the time length of the first-type pulse, the light emission peak current density of the light emitting layer is increased, the current proportion of the normal light emission path is increased, the current proportion of the micro-short circuit path is reduced, the brightness overshoot can be weakened, and then the trailing problem can be improved to improve the display quality.

[0079] In a possible implementation manner, refer toFigure 5 , the display device 1 further includes a timing control circuit 13;

[0080] The timing control circuit 13 is configured to: generate a reset control timing signal including a plurality of third - type pulses; wherein, in chronological order, there is a third - type pulse before each first - type pulse / second - type pulse, and the third - type pulse is at an effective level; and scan the pixel circuit by using the reset control timing signal.

[0081] The specific analysis is the same as above, and will not be elaborated here.

[0082] In the embodiment of the present application, at the high - level moment (invalid level, the light - emitting control transistor is in the off state) of each light - emitting control timing signal EM signal, the reset control timing signal reset - H signal is reset once. That is, through the precise reset of "high frequency, small amplitude", the ghosting phenomenon is improved, the problem of large brightness drop when the reset - H signal is reset is improved, and the display smoothness and picture clarity are enhanced.

[0083] In order to more clearly understand the solution of the present application, a simple description is given below by taking the 5T1C (5 transistors, 1 storage capacitor) pixel circuit structure as an example, which can be referred to Figure 6 . The 5T1C pixel circuit structure includes: a data writing transistor T1, a driving transistor T2, a compensating transistor T3, a reset transistor T4, a light - emitting control transistor T5, and 1 storage capacitor Cst. D1 is a light - emitting device OLED, VDD is the positive - power supply signal line, VSS is the negative - power supply signal line, EM is the light - emitting control timing signal, Gate(n) is the gate scan signal line of the current pixel row, Gate(n - 1) is the gate scan signal line of the previous pixel row, Vinit is the reset signal, Reset - H is the reset control timing signal, and Data is the data signal line.

[0084] The gate of the reset transistor T4 is connected to the reset control timing signal Reset-H signal. The first end of the reset transistor T4 is connected to the second node N2. The second end of the reset transistor T4 is connected to the reset signal Vinit. The first plate of the storage capacitor Cst is connected to the positive power supply signal line VDD. The second plate of the storage capacitor Cst is connected to the second node N2. The gate of the light-emitting control transistor T5 is connected to the light-emitting control timing signal EM signal. The first end of the light-emitting control transistor T5 is connected to the positive power supply signal line VDD. The second end of the light-emitting control transistor T5 is connected to the first node N1. The gate of the driving transistor T2 is connected to the second node N2. The first end of the driving transistor T2 is connected to the first node N1. The second end of the driving transistor T2 is connected to the third node N3. The gate of the compensation transistor T3 is connected to the gate scan signal line Gate(n - 1) of the previous pixel row. The first end of the compensation transistor T3 is connected to the second node N2. The second end of the compensation transistor T3 is connected to the third node N3. The gate of the data writing transistor T1 is connected to the gate scan signal line Gate(n) of the current pixel row. The first end of the data writing transistor T1 is connected to the first node N1. The second end of the data writing transistor T1 is connected to the data signal line Data. The positive electrode of the light-emitting device D1 is connected to the third node N3. The negative electrode of the light-emitting device D1 is connected to the negative power supply signal line VSS.

[0085] Among them, the data writing transistor T1 is a P-type transistor, the driving transistor T2 is a P-type transistor, the compensation transistor T3 is an N-type transistor, the reset transistor T4 is a P-type transistor, and the light-emitting control transistor T5 is a P-type transistor.

[0086] It can be understood that for any transistor in the pixel circuit of the present application, the first end of the transistor is the source or drain, and the second end of the transistor is the drain or source corresponding to the first end.

[0087] It can be understood that the transistors used in the pixel circuit of the present application can be TFTs (Thin Film Transistors), or MOS transistors (Metal-Oxide-Semiconductor Field-Effect Transistors), or other types of transistors, which can be specifically selected according to the actual situation.

[0088] It should be noted that in this document, relational terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the term "comprising", "including" or any other variation thereof is intended to cover non-exclusive inclusion, such that a process, method, article or device comprising a series of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such process, method, article or device. Without further limitation, an element defined by the phrase "comprising an..." does not exclude the presence of additional identical elements in the process, method, article or device comprising the element.

[0089] Each embodiment in this specification is described in a related manner. For the same or similar parts among the embodiments, reference can be made to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and reference can be made to the relevant part of the method embodiment for the relevant content.

[0090] The above description is only the preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are all included in the protection scope of the present application.

Claims

1. A display panel driving method, characterized in that, The method includes: Generating a light emission control timing signal including a plurality of light emission sub-timings; wherein, for each light emission sub-timing, the light emission sub-timing includes at least one first type of pulse and a plurality of second type of pulses, the first type of pulse is located before the second type of pulses, the time length of the first type of pulse is greater than the time length of the second type of pulses, and the first type of pulse and the second type of pulses are at an active level; Scanning the pixel circuits of the display panel by using the light emission control timing signal.

2. The method according to claim 1, characterized in that, The method further includes: Generating a reset control timing signal including a plurality of third type of pulses; wherein, in chronological order, there is a third type of pulse before each first type of pulse / second type of pulse, and the third type of pulse is at an active level; Scanning the pixel circuits by using the reset control timing signal.

3. The method according to claim 1, wherein The time length of the first type of pulse is Nd, where N ranges from 64 ≤ N ≤ 88, and d represents a clock cycle unit.

4. The method according to claim 1, characterized in that, The time length of the second type of pulse is Md, where M ranges from 4 ≤ M ≤ 16, and d represents a clock cycle unit.

5. The method according to claim 2, wherein The time length of the third type of pulse is Qd, where Q ranges from 4 ≤ Q ≤ 16, and d represents a clock cycle unit.

6. The method according to claim 1, characterized in that For each light emission sub-timing, the light emission sub-timing includes a plurality of first type of pulses and a plurality of second type of pulses. For any two adjacent first type of pulses, the time length of the first type of pulse farther from the second type of pulses is greater than the time length of the first type of pulse closer to the second type of pulses; For any two adjacent second type of pulses, the time length of the second type of pulse closer to the first type of pulse is greater than the time length of the second type of pulse farther from the first type of pulse.

7. The method according to claim 1, characterized in that, For each light emission sub-timing, the light emission sub-timing includes one first type of pulse and a plurality of second type of pulses, and the time length of each of the second type of pulses is less than a preset duration threshold.

8. The method according to claim 2, characterized in that, The time lengths of all the third type of pulses are the same.

9. A display device, characterized in that, The display device includes a display panel and a display driving chip; The display panel includes multiple rows of pixel rows; each of the pixel rows includes a plurality of pixel circuits; The display driving chip is configured to: generate a light emission control timing signal including a plurality of light emission sub-timings; wherein, for each light emission sub-timing, the light emission sub-timing includes at least one first type of pulse and a plurality of second type of pulses, the first type of pulse is located before the second type of pulses, the time length of the first type of pulse is greater than the time length of the second type of pulses, and the first type of pulse and the second type of pulses are at an active level; scan the pixel circuits of the display panel by using the light emission control timing signal.

10. The display device according to claim 9, wherein The display device further includes a timing control circuit; The timing control circuit is configured to: generate a reset control timing signal including a plurality of third type of pulses; wherein, in chronological order, there is a third type of pulse before each first type of pulse / second type of pulse, and the third type of pulse is at an active level; scan the pixel circuits by using the reset control timing signal.

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