Display device and method of manufacturing same

Abstract

The invention relates to a display device and a method of manufacturing the same. According to an embodiment, the display device includes: a base layer; a pixel defining layer including a pixel opening corresponding to the pixel region; a light emitting unit overlapping the pixel region and including a charge generating layer; and a separation pattern overlapping the valley region, in which the separation pattern includes: a first pattern portion protruding from an upper surface of the pixel defining layer to a first height; a second pattern portion protruding from the upper surface of the pixel defining layer to a second height substantially the same as the first height; and a third pattern portion disposed between the first pattern portion and the second pattern portion and recessed from the first pattern portion and the second pattern portion toward the upper surface of the pixel defining layer, and the charge generating layer is broken on the third pattern portion.

Description

[0001] Cross - Reference to Related Applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10-2024-0002039, filed with the Korean Intellectual Property Office on January 5, 2024, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The embodiments described herein relate to a display device and a method of manufacturing a display device, and more particularly, to a display device including a charge generation layer. Background Art

[0004] Electronic devices that provide images to users, such as smart phones, tablet personal computers (PCs), digital cameras, laptop computers, navigation devices, and televisions, include a display panel for displaying an image.

[0005] For color display, the display panel is formed by dividing pixels into red pixels, green pixels, and blue pixels and forming a light-emitting layer having the color of the corresponding pixel in each pixel. Generally, a deposition method using a shadow mask is used for the light-emitting layer, but defects such as mask sag may occur, and thus a process of forming the light-emitting layer and other organic layers commonly for the entire pixel through an aperture mask has been formed or developed.

[0006] However, in the case of forming the organic layer commonly, since the organic layer is provided commonly between adjacent pixels, lateral leakage current may occur, and thus color mixing and brightness defects may occur between adjacent pixels. Summary of the Invention

[0007] Embodiments provide a display panel in which color mixing between adjacent pixels can be prevented and a decrease in brightness can be prevented by preventing lateral leakage current from occurring between adjacent pixels.

[0008] However, the embodiments are not limited to the embodiments set forth herein. By referring to the detailed description of the present disclosure given below, the above and other embodiments will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0009] According to an embodiment, a display device includes: a substrate layer including a pixel region and a non-pixel region; a pixel defining layer disposed on the substrate layer and including a pixel opening corresponding to the pixel region; a light-emitting unit disposed on the pixel defining layer, overlapping with the pixel region, and including a charge generation layer; and a separation pattern disposed on the pixel defining layer and overlapping with a valley region among a valley region and a non-valley region disposed on a virtual line surrounding the pixel opening, wherein the separation pattern includes: a first pattern portion protruding from an upper surface of the pixel defining layer to a first height; a second pattern portion protruding from the upper surface of the pixel defining layer to a second height substantially the same as the first height; and a third pattern portion disposed between the first pattern portion and the second pattern portion, and the third pattern portion is recessed from the first pattern portion and the second pattern portion toward the upper surface of the pixel defining layer, and the charge generation layer is disconnected on the third pattern portion.

[0010] The third pattern portion may protrude from the upper surface of the pixel defining layer to a third height, and the third height is less than the first height and the second height.

[0011] The separation pattern may be made of an organic photosensitive material.

[0012] The valley region may include: a first-1 valley portion surrounding a part of the pixel opening; a first-2 valley portion spaced farther from the pixel opening than the first-1 valley portion and having a shape corresponding to the shape of the first-1 valley portion; and an overlapping portion disposed between the first-1 valley portion and the first-2 valley portion, and the first pattern portion may overlap with the first-1 valley portion, the second pattern portion may overlap with the first-2 valley portion, and the third pattern portion may overlap with the overlapping portion.

[0013] In a cross-section, the separation pattern may have a shape in which two protruding portions convexly protruding from the upper surface of the pixel defining layer partially overlap in the overlapping portion.

[0014] The lowest point of the third pattern portion may be positioned at a central portion of the overlapping portion.

[0015] The charge generation layer may be disconnected at a position corresponding to the lowest point closest to the upper surface of the pixel defining layer of the third pattern portion.

[0016] The separation pattern may include a material that cures when irradiated with light.

[0017] The pixel region may include a first pixel region and a second pixel region spaced apart from the first pixel region. The pixel opening may include a first pixel opening corresponding to the first pixel region and a second pixel opening corresponding to the second pixel region. The non-valley region may include a first non-valley region provided on a part of a first virtual line surrounding the first pixel opening and a second non-valley region provided on a part of a second virtual line surrounding the second pixel opening, and the first non-valley region and the second non-valley region may not face each other.

[0018] The light-emitting unit may include: a first light-emitting stack provided on a lower surface of the charge generation layer; and a second light-emitting stack provided on an upper surface of the charge generation layer, and each of the first light-emitting stack and the second light-emitting stack may include a light-emitting layer that emits light.

[0019] An angle formed between a tangent to an outer surface of the third pattern portion and the upper surface of the pixel defining layer may increase as a position where the angle is located is closer to a lowest point of the third pattern portion.

[0020] The display device may further include: a common electrode provided on the light-emitting unit and overlapping with the pixel region and the non-pixel region, wherein the common electrode may not be disconnected on the third pattern portion.

[0021] According to an embodiment, a display device includes: a substrate layer including a pixel region and a non-pixel region; a pixel defining layer provided on the substrate layer and including a pixel opening corresponding to the pixel region; and a light-emitting unit provided on the pixel defining layer, overlapping with the pixel region, and including a charge generation layer, wherein a recess overlapping with the valley region among a valley region and a non-valley region arranged on a virtual line surrounding the pixel opening is defined in the pixel defining layer, and the charge generation layer is disconnected at a position corresponding to a lowest point of the recess closest to a lower surface of the pixel defining layer.

[0022] The pixel defining layer may include a material that cures when irradiated with light.

[0023] The pixel defining layer may include: a first portion, the maximum height of the first portion from the lower surface of the pixel defining layer to the upper surface of the pixel defining layer being a first height; a second portion, the maximum height of the second portion from the lower surface of the pixel defining layer to the upper surface of the pixel defining layer being a second height substantially the same as the first height; and a third portion, disposed between the first portion and the second portion, and the maximum height of the third portion from the lower surface of the pixel defining layer to the upper surface of the pixel defining layer being a third height less than the first height and the second height.

[0024] The angle formed between the tangent of the outer surface of the recessed portion and the lower surface of the pixel defining layer may increase as the position where the angle is located is closer to the lowest point of the recessed portion.

[0025] According to an embodiment, a method of manufacturing a display device includes: forming a preliminary separation pattern layer on a preliminary display device including a substrate layer and a pixel defining layer, the substrate layer including a pixel region and a non-pixel region, the pixel defining layer being disposed on the substrate layer and including a pixel opening corresponding to the pixel region; forming a separation pattern by exposing light to the preliminary separation pattern layer using a mask including a transmissive region, a non-transmissive region, and a semi-transmissive region; and forming a light-emitting unit including a charge generation layer on the separation pattern, wherein the charge generation layer is disconnected at a portion of the separation pattern corresponding to the semi-transmissive region.

[0026] The separation pattern may include: a first pattern portion protruding from the upper surface of the pixel defining layer to a first height; a second pattern portion protruding from the upper surface of the pixel defining layer to a second height substantially the same as the first height; and a third pattern portion disposed between the first pattern portion and the second pattern portion and recessed from the first pattern portion and the second pattern portion toward the upper surface of the pixel defining layer, the first pattern portion and the second pattern portion may correspond to the transmissive region, and the third pattern portion may correspond to the semi-transmissive region, and the charge generation layer may be disconnected on the third pattern portion.

[0027] The charge generation layer may be disconnected at a position corresponding to the lowest point of the third pattern portion closest to the upper surface of the pixel defining layer.

[0028] The preliminary separation pattern layer may include a material that cures upon irradiation with light. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and other objects and features of the present disclosure will become apparent by referring to the embodiments of the present disclosure described in detail with reference to the accompanying drawings.

[0030] Figure 1 is a schematic perspective view of a coupling state of an electronic device according to an embodiment.

[0031] Figure 2 is an exploded schematic perspective view of an electronic device according to an embodiment.

[0032] Figure 3A is a schematic cross-sectional view of a display module according to an embodiment.

[0033] Figure 3B is an enlarged schematic cross-sectional view of a part of a display panel according to an embodiment.

[0034] Figure 3C is an enlarged schematic cross-sectional view of a part of a light-emitting element according to an embodiment.

[0035] Figure 3D is an enlarged schematic cross-sectional view of a part of a light-emitting element according to an embodiment.

[0036] Figure 4A is an enlarged schematic plan view of a part of a display panel according to an embodiment.

[0037] Figure 4B is according to an embodiment Figure 4A an enlarged schematic plan view of portion BB' of

[0038] Figure 5A is according to an embodiment along Figure 4B line I-I' of

[0039] Figure 5B is according to an embodiment Figure 5A an enlarged schematic cross-sectional view of portion CC' of

[0040] Figure 6 is according to an embodiment along Figure 4B line I-I' of

[0041] Figure 7 is according to an embodiment Figure 4A an enlarged schematic plan view of portion BB' of

[0042] Figure 8 is according to an embodiment along Figure 7 line II-II' of

[0043] Figure 9 is according to an embodiment Figure 8 an enlarged schematic cross-sectional view of portion DD' of

[0044] Figure 10A and Figure 10B andFigure 10C and Figure 10D is a schematic cross-sectional view showing a part of a method of manufacturing a display device according to an embodiment.

[0045] Figure 11A 、 Figure 11B 、 Figure 11C and Figure 11D is a schematic cross-sectional view showing a part of a method of manufacturing a display device according to an embodiment. DETAILED DESCRIPTION

[0046] In the following description, for purposes of explanation, numerous specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words as non-limiting examples of the devices or methods disclosed herein. However, it is apparent that the various embodiments may be practiced without these specific details or with one or more equivalent arrangements. Here, the various embodiments are not necessarily exclusive and do not limit the present disclosure. For example, the specific shapes, configurations, and characteristics of an embodiment may be used or implemented in another embodiment.

[0047] Unless otherwise specified in detail, the illustrated embodiments should be understood to provide features of the present invention. Thus, unless otherwise specified in detail, without departing from the scope of the present invention, the features, components, modules, layers, films, panels, regions, and / or aspects, etc. (hereinafter individually referred to as or collectively referred to as "elements") of the various embodiments may be combined, separated, interchanged, and / or rearranged in other ways.

[0048] The use of cross-hatching and / or shading in the drawings generally serves to clarify the boundaries between adjacent elements. Thus, unless specified in detail, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, size, ratio, commonality between the elements shown, and / or any other characteristics, attributes, properties, etc. of the elements. In addition, in the drawings, for clarity and / or description purposes, the dimensions and relative dimensions of the elements may be exaggerated. When an embodiment can be implemented differently, a specific process order may be performed differently from the described order. For example, two consecutively described processes may be performed substantially simultaneously or in an order opposite to the described order. Additionally, the same reference numerals denote the same elements.

[0049] When an element or layer is referred to as being "on", "connected to", or "coupled to" another element or layer, the element or layer can be directly on, connected to, or coupled to the other element or layer, or there can be intervening elements or intervening layers. However, when an element or layer is referred to as being "directly on", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or intervening layers. For this reason, the term "connected" can refer to physical connection, electrical connection, and / or fluid connection with or without intervening elements or intervening layers. In addition, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 are not limited to the three axes of a rectangular coordinate system (such as the X-axis, Y-axis, and Z-axis), and can be interpreted in a broader sense. For example, the axes of the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. For the purposes of the present disclosure, "at least one of A and B" can be understood to mean only A, only B, or any combination of A and B. In addition, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z. As used herein, the term "and / or" includes any combination and all combinations of one or more of the associated listed items.

[0050] Although terms such as "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another. Thus, the first element discussed later can be referred to as the second element without departing from the teachings of the present disclosure.

[0051] Spatial relative terms (such as "below", "beneath", "under", "lower", "above", "upper", "on (over)", "higher", and "side" (e.g., as in "sidewall") etc.) may be used herein for descriptive purposes and thus to describe the relationship of one element to another element (or elements) as shown in the figures. In addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device during use, operation, and / or manufacture. For example, if the device in the figures is flipped, an element described as being "below" or "beneath" another element or feature will then be oriented "above" the other element or feature. Thus, the term "below" can encompass both the above and below orientations. Additionally, the device can be oriented in other ways (e.g., rotated 90 degrees or at other orientations), and thus, the spatial relative terms used herein should be interpreted accordingly.

[0052] The terms used herein are for the purpose of describing particular embodiments and are not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are also intended to include the plural forms unless the context clearly dictates otherwise. Further, when used in this specification, the terms "comprises", "comprising", "includes" and / or "including" specify the presence of the stated features, integers, steps, operations, elements, components and / or groups thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should also be noted that as used herein, the terms "substantially", "about" and other similar terms are used as approximate terms and not as terms of degree, and are thus used to account for the inherent deviations in measured, calculated and / or provided values that would be recognized by one of ordinary skill in the art.

[0053] Various embodiments are described herein with reference to sectional views and / or exploded views as schematic illustrations of embodiments and / or intermediate structures. Accordingly, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances are to be expected. Thus, the embodiments disclosed herein are not necessarily to be construed as limited to the particular shapes shown in the regions, but include deviations in shapes due to, for example, manufacturing. In this manner, the regions shown in the drawings may be schematic in nature and the shapes of these regions may not reflect the actual shapes of the regions of the device and, thus, are not necessarily intended to be limiting.

[0054] In accordance with the convention in the art, some embodiments are described and illustrated in the drawings in terms of functional blocks, units and / or modules. Those skilled in the art will appreciate that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits (such as logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, and wiring connections, etc.) that may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where the blocks, units and / or modules are implemented by a microprocessor or other similar hardware, they may be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein and may optionally be driven by firmware and / or software. It is also contemplated that each block, unit and / or module may be implemented by dedicated hardware or as a combination of dedicated hardware for performing some functions and a processor (e.g., one or more programmed microprocessors and associated circuitry) for performing other functions. Additionally, without departing from the scope of the present invention, each block, unit and / or module of some embodiments may be physically divided into two or more interacting and discrete blocks, units and / or modules. Further, without departing from the scope of the present invention, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules.

[0055] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0056] Figure 1 is a schematic perspective view of a coupling state of an electronic device according to an embodiment. Figure 2 is an exploded schematic perspective view of the electronic device according to an embodiment.

[0057] Referring to Figure 1 , the electronic device ED may be a device activated according to an electrical signal. The electronic device ED may display an image IM and sense an external input. The electronic device ED may include various embodiments. For example, the electronic device ED may include a computer (e.g., a tablet personal computer (PC), a laptop computer), a smart phone, or a television set, etc. In an embodiment, the electronic device ED is illustratively shown as a tablet PC. However, the embodiment is not limited thereto, and the electronic device ED according to the embodiment may be a smart phone, or the electronic device ED according to the embodiment may be a large-sized display device such as a laptop computer, a monitor, or a television set.

[0058] The electronic device ED may display the image IM in a third direction DR3 in a display surface DS parallel to a first direction DR1 and a second direction DR2. The display surface DS on which the image IM is displayed may correspond to the front surface of the electronic device ED and correspond to the front surface FS of the window WM (see Figure 2 ). Hereinafter, the same reference numerals will be used for the front surface of the electronic device ED and the front surface of the window WM. The image IM may include a still image as well as a moving image. In Figure 2 ), an icon is shown as an example of the image IM. Figure 1

[0059] In an embodiment, the front surface (or upper surface) and the rear surface (or lower surface) of each component may be defined with respect to the direction of the displayed image IM. The front surface and the rear surface may face away from each other in the third direction DR3, and the normal direction of each of the front surface and the rear surface may be parallel to the third direction DR3. The separation distance in the third direction DR3 between the front surface and the rear surface may correspond to the thickness of the electronic device ED in the third direction DR3. For example, the directions indicated by the first direction DR1, the second direction DR2, and the third direction DR3 are relative concepts and may be changed to other directions. In addition, in the description, the phrase "on a plane" or "in a plan view" may mean a state of observing a component on a plane defined by the first direction DR1 and the second direction DR2.

[0060] An electronic device ED according to an embodiment can sense a user input applied from the outside. The user input can include various types of external inputs, such as a part of the user's body, light, heat, or pressure. The user input can be provided in various forms, and depending on the structure of the electronic device ED, the electronic device ED can sense the user input applied to the side surface or the rear surface of the electronic device ED, but the embodiment is not limited thereto.

[0061] As Figure 2 shown, the electronic device ED can include a window WM, a display module DM, and a housing EDC. In an embodiment, the window WM and the housing EDC can be coupled to each other to form the appearance of the electronic device ED. In an embodiment, the housing EDC, the display module DM, and the window WM can be sequentially stacked in a third direction DR3.

[0062] The window WM can include an optically transparent material. The window WM can include an insulating panel. For example, the window WM can be made of glass, plastic, or a combination thereof.

[0063] As described above, the front surface FS of the window WM can define the front surface FS of the electronic device ED.

[0064] The window WM can include a border region and a transmissive region. The transmissive region can be an optically transparent region. For example, the transmissive region can be a region having a visible light transmittance of about 90% or more.

[0065] Compared with the transmissive region, the border region can be a region having a relatively low light transmittance. The border region can define the shape of the transmissive region. The border region can be adjacent to the transmissive region and surround the transmissive region. The border region can have a selected color. The border region can overlap with a non-display region DP-NDA of a display panel DP to be described later. The border region can cover the non-display region DP-NDA of the display panel DP and prevent the non-display region DP-NDA from being visually recognized from the outside. For example, this is an illustrative description, and in the window WM according to an embodiment, the border region can be omitted.

[0066] The display module DM can at least include a display panel DP. Although Figure 2 only the display panel DP among the stacked structures of the display module DM is shown, basically, the display module DM can also include components arranged on the display panel DP and components arranged under the display panel DP. The stacked structure of the display module DM will be described later.

[0067] The display panel DP can include a display region DP-DA corresponding to a display region DA of the electronic device ED (see Figure 1 ), and a non-display region NDA corresponding to a non-display region NDA of the electronic device ED (see Figure 1)'s non-display area DP-NDA. In the description, the expression "region / section and region / section correspond to each other" means that the region / section and the region / section overlap with each other, and is not limited to the same region. The display module DM may include a driving chip DIC disposed on the non-display area DP-NDA. The display module DM may further include a printed circuit board PCB coupled to the non-display area DP-NDA. The printed circuit board PCB may be electrically connected to pads disposed in the non-display area DP-NDA of the display panel DP through an anisotropic conductive adhesive layer.

[0068] The driving chip DIC may include driving elements (e.g., data driving circuits) for driving pixels of the display panel DP. Although Figure 2 a structure in which the driving chip DIC is mounted on the display panel DP is shown, the embodiment is not limited thereto. For example, the driving chip DIC may be mounted on the printed circuit board PCB.

[0069] The outer casing EDC may accommodate the display module DM and may be coupled to the window WM. The outer casing EDC may protect components (such as the display module DM) accommodated inside the outer casing EDC.

[0070] Figure 3A is a schematic cross-sectional view of a display module according to an embodiment. Figure 3B is an enlarged schematic cross-sectional view of a part of a display panel according to an embodiment. Figure 3C and Figure 3D is an enlarged schematic cross-sectional view of a part of a light-emitting element according to an embodiment. Figure 3B Illustratively shows a light-emitting element OLED and a transistor TR included in one pixel included in the display panel DP of the embodiment.

[0071] Referring to Figure 3A , the display module DM may include a display panel DP and an input sensing unit ISU. The display panel DP may be a component that substantially generates an image IM (see Figure 1 ). The image IM (see Figure 1 ) generated by the display panel DP may be visually recognized by a user from the outside through the display area DA (see Figure 1 ).

[0072] The display panel DP may be a light-emitting display panel. For example, the display panel DP may be an organic light-emitting display panel or an inorganic light-emitting display panel. The organic light-emitting display panel may be a display panel in which the light-emitting layer includes an organic light-emitting material. The inorganic light-emitting display panel may be a display panel in which the light-emitting layer includes an inorganic light-emitting material. In addition, the display panel DP may be a quantum dot light-emitting display panel in which the light-emitting layer includes quantum dots or quantum rods, or a micro light-emitting display panel or a nano light-emitting display panel using a micro light-emitting diode (LED) or a nano light-emitting diode (LED). Hereinafter, the display panel DP is described as an organic light-emitting display panel.

[0073] The input sensing unit ISU may be disposed on the display panel DP. The input sensing unit ISU may sense an external input applied from the outside. The external input may include various types of inputs externally provided from the electronic device ED (see Figure 1 ). The input applied from the outside may be provided in various forms. For example, the external input may include contact through a part of the user's body (such as a hand), and an external input (such as hovering) applied to be close to the electronic device ED (see Figure 1 ) or adjacent to the electronic device ED at a selected distance. In addition, the external input may have various forms (such as force (e.g., pressure) and light), and these embodiments are not limited to one embodiment.

[0074] The input sensing unit ISU may be formed on the display panel DP through a continuous process. For example, the input sensing unit ISU may be disposed (e.g., directly disposed) on the display panel DP. For example, in the description, the phrase "component B is directly disposed on component A" may mean that no third component is disposed between component A and component B. For example, an adhesive layer may not be disposed between the input sensing unit ISU and the display panel DP.

[0075] The display panel DP may include a substrate layer BL, and a circuit element layer DP-CL, a display element layer DP-OLED, and an upper insulating layer TFL disposed on the substrate layer BL.

[0076] The substrate layer BL may provide a substrate surface on which the circuit element layer DP-CL, the display element layer DP-OLED, and the upper insulating layer TFL are disposed. The substrate layer BL may be a rigid substrate or a flexible substrate that can be bent, folded, and curled. The substrate layer BL may be a glass substrate, a metal substrate, or a polymer substrate, etc. However, the embodiments are not limited thereto, and the substrate layer BL may include an inorganic layer, an organic layer, or a composite material layer.

[0077] The substrate layer BL may have a multi-layer structure. For example, the substrate layer BL may include a first synthetic resin layer, a multi-layer or single-layer inorganic layer, and a second synthetic resin layer provided on the multi-layer or single-layer inorganic layer. Each of the first synthetic resin layer and the second synthetic resin layer may include a polyimide-based resin, but the embodiments are not particularly limited thereto.

[0078] The circuit element layer DP-CL may be provided on the substrate layer BL. The circuit element layer DP-CL may include an insulating layer, a conductive layer, and a semiconductor layer. The conductive layer of the circuit element layer DP-CL may constitute a signal line or a control circuit of a pixel.

[0079] The display element layer DP-OLED may be provided on the circuit element layer DP-CL. The display element layer DP-OLED may include a light-emitting element. The display element layer DP-OLED may include, for example, an organic light-emitting element. However, this is illustrative, and the display element layer DP-OLED according to the embodiments may include an inorganic light-emitting element, an organic-inorganic light-emitting element, or a liquid crystal layer.

[0080] The upper insulating layer TFL may include a coating layer and a thin film encapsulation layer (encapsulation layer) to be described later. The upper insulating layer TFL may include an organic layer and an inorganic layer that seals the organic layer.

[0081] The upper insulating layer TFL may be provided on the display element layer DP-OLED and may protect the display element layer DP-OLED from foreign substances such as moisture, oxygen, and dust particles. The upper insulating layer TFL may seal the display element layer DP-OLED to block the inflow of moisture and oxygen into the display element layer DP-OLED. The upper insulating layer TFL may include at least one inorganic layer. The upper insulating layer TFL may include an organic layer and an inorganic layer that seals the organic layer. The upper insulating layer TFL may include a stacked structure of an inorganic layer / an organic layer / an inorganic layer in sequence.

[0082] The input sensing unit ISU may be provided on the upper insulating layer TFL. The input sensing unit ISU may be formed on the upper insulating layer TFL by a continuous process. The input sensing unit ISU may be provided (for example, directly provided) on the display panel DP. For example, a separate adhesive member may not be provided between the input sensing unit ISU and the display panel DP. The input sensing unit ISU may be arranged to contact the inorganic layer provided on the uppermost side of the upper insulating layer TFL.

[0083] For example, the display module DM according to the embodiments may further include a protection member provided on the lower surface of the display panel DP, and an anti-reflection member provided on the upper surface of the input sensing unit ISU. The anti-reflection member may reduce the reflectance of external light. The anti-reflection member may be provided (for example, directly provided) on the input sensing unit ISU by a continuous process.

[0084] The antireflection member may include a light-shielding pattern overlapping with a reflection structure disposed below the antireflection member. The antireflection member may further include a color filter. The color filter may be disposed between the light-shielding patterns and may include a first color filter, a second color filter, and a third color filter corresponding to a first color pixel, a second color pixel, and a third color pixel, respectively.

[0085] As Figure 3A shown, in a plan view or on a plane, the display panel DP may be divided into a display area DP-DA and a non-display area DP-NDA. The display area DP-DA of the display panel DP may be an area where an image is displayed, and the non-display area DP-NDA may be an area where a driving circuit or driving wirings are disposed, etc. The light-emitting elements of the pixels may be arranged in the display area DP-DA. The display area DP-DA may overlap at least a part of a transmissive area of the window WM (see Figure 2 ), and the non-display area DP-NDA may be covered by a border area of the window WM. The display area DP-DA and the non-display area DP-NDA of the display panel DP may correspond to the display area DA and the non-display area NDA of the electronic device ED shown in Figure 1 respectively.

[0086] Hereinafter, the configurations of the circuit element layer DP-CL, the display element layer DP-OLED, and the upper insulating layer TFL will be described in detail through Figure 3B and Figure 3C .

[0087] Referring to Figure 3B , the circuit element layer DP-CL may include at least one insulating layer and circuit elements. The circuit elements may include signal lines and driving circuits of pixels, etc. The circuit element layer DP-CL may be formed through processes of forming an insulating layer, a semiconductor layer, and a conductive layer by coating or deposition, etc., and processes of patterning the insulating layer, the semiconductor layer, and the conductive layer by a photolithography process.

[0088] The buffer layer BFL may include at least one stacked inorganic layer. A semiconductor pattern may be disposed on the buffer layer BFL. The buffer layer BFL may improve the coupling force between the substrate layer BL and the semiconductor pattern.

[0089] The semiconductor pattern may include polysilicon. However, the embodiments are not limited thereto, and the semiconductor pattern may include amorphous silicon or metal oxide. Figure 3B A part of the semiconductor pattern is shown, and in a plan view or on a plane, the semiconductor pattern may be further disposed in another area of the pixel. The semiconductor pattern may be disposed across the pixel in a specific rule.

[0090] Depending on whether the semiconductor pattern is doped, the semiconductor pattern can have different electrical properties. The semiconductor pattern can include a first region A1 having a low doping concentration and low conductivity, and second regions SN1 and DN1 having a relatively high doping concentration and relatively high conductivity. The second region SN1 can be disposed on one side of the first region A1, and the second region DN1 can be disposed on the other side of the first region A1. The second regions SN1 and DN1 can be doped with an N-type dopant or a P-type dopant. The P-type transistor can include a doped region doped with a P-type dopant. The first region A1 can be an undoped region or can be doped at a concentration lower than that of the second regions SN1 and DN1.

[0091] The second regions SN1 and DN1 can be used as electrodes or signal lines. The second region (e.g., a single second region) SN1 can correspond to the source of the transistor TR, and the second region DN1 can correspond to the drain of the transistor TR. Figure 3B A part of the connection signal line SCL formed of the semiconductor pattern is shown. For example, in a plan view or on a plane, the connection signal line SCL can be connected to the drain of the transistor TR.

[0092] The first insulating layer 10 can be disposed on the buffer layer BFL. The first insulating layer 10 can commonly overlap with the pixels arranged in the display area DP-DA (see Figure 3A ) and cover the semiconductor pattern. The first insulating layer 10 can be an inorganic layer and / or an organic layer and can have a single-layer structure or a multi-layer structure. The first insulating layer 10 can include at least one of aluminum oxide, titanium oxide, silicon oxide, silicon oxynitride, zirconium oxide, and hafnium oxide. The insulating layer of the circuit element layer DP-CL to be described later and the first insulating layer 10 can be an inorganic layer and / or an organic layer and can have a single-layer structure or a multi-layer structure.

[0093] The gate G1 can be disposed on the first insulating layer 10. The gate G1 can be a part of a metal pattern. The gate G1 can overlap with the first region A1. The gate G1 can be used as a mask in the process of doping the semiconductor pattern.

[0094] The second insulating layer 20 can be disposed on the first insulating layer 10 and cover the gate G1. The second insulating layer 20 can commonly overlap with the pixels. The upper electrode UE can be disposed on the second insulating layer 20. The upper electrode UE can overlap with the gate G1. The upper electrode UE can include a multi-layer metal layer. In an embodiment, the upper electrode UE can be omitted.

[0095] The third insulating layer 30 may be disposed on the second insulating layer 20 and cover the upper electrode UE. The first connection electrode CNE1 may be disposed on the third insulating layer 30. The first connection electrode CNE1 may be connected to the connection signal line SCL through a contact hole CNT-1 that penetrates the first insulating layer 10 to the third insulating layer 30.

[0096] The fourth insulating layer 40 may be disposed on the third insulating layer 30, and the fifth insulating layer 50 may be disposed on the fourth insulating layer 40. The fourth insulating layer 40 may be an organic layer. The second connection electrode CNE2 may be disposed on the fourth insulating layer 40. The second connection electrode CNE2 may be connected to the first connection electrode CNE1 through a contact hole CNT-2 that penetrates the fourth insulating layer 40.

[0097] The fifth insulating layer 50 may be disposed on the fourth insulating layer 40 and cover the second connection electrode CNE2. The fifth insulating layer 50 may be an organic layer.

[0098] The light-emitting element OLED may be disposed on the fifth insulating layer 50. The first electrode AE may be disposed on the fifth insulating layer 50. The first electrode AE may be connected to the second connection electrode CNE2 through a contact hole CNT-3 that penetrates the fifth insulating layer 50. The pixel opening OP may be formed (or defined) in the pixel defining layer PDL, and at least a portion of the first electrode AE may be exposed through the pixel defining layer PDL. The pixel defining layer PDL may be an organic layer.

[0099] The display area DP-DA may include a pixel area PXA and a non-pixel area NPXA adjacent to the pixel area PXA. The non-pixel area NPXA may surround the pixel area PXA. In an embodiment, the pixel area PXA may be formed (or defined) to correspond to a partial area of the first electrode AE exposed by the pixel opening OP.

[0100] Refer to Figure 3C , the light-emitting element OLED may include a first electrode AE, a first light-emitting stack ST1, a charge generation layer CGL, a second light-emitting stack ST2, and a second electrode CE (or a common electrode CE) that are sequentially stacked in a third direction DR3. The light-emitting element OLED may be a light-emitting element having a tandem structure including light-emitting stacks ST1 and ST2 each including a light-emitting layer.

[0101] The first light-emitting stack ST1 may include a first light-emitting layer EML1, a first hole control layer HTR1, and a first electron control layer ETR1, and the first light-emitting layer EML1 is interposed between the first hole control layer HTR1 and the first electron control layer ETR1.

[0102] The first hole control layer HTR1 may include at least one of a first hole injection layer HIL1 and a first hole transport layer HTL1. The first hole transport layer HTL1 may include at least one of a first hole buffer layer and a first electron blocking layer.

[0103] The first electron control layer ETR1 may include at least one of a first electron injection layer EIL1 and a first electron transport layer ETL1. The first electron control layer ETR1 may further include a first hole blocking layer.

[0104] The second light-emitting stack ST2 may include a second light-emitting layer EML2, a second hole control layer HTR2, and a second electron control layer ETR2, and the second light-emitting layer EML2 is interposed between the second hole control layer HTR2 and the second electron control layer ETR2.

[0105] The second hole control layer HTR2 may include at least one of a second hole injection layer HIL2 and a second hole transport layer HTL2. The second electron control layer ETR2 may include at least one of a second electron injection layer EIL2 and a second electron transport layer ETL2. The description of the first hole control layer HTR1 and the first electron control layer ETR1 may be equally (or similarly) applied to the description of the second hole control layer HTR2 and the second electron control layer ETR2.

[0106] In an embodiment, all the light emitted from the light-emitting stacks ST1 and ST2 may have the same wavelength. For example, the light emitted from the light-emitting stacks ST1 and ST2 may be blue light. However, the embodiment is not limited thereto, and the wavelength ranges of the light emitted from the light-emitting stacks ST1 and ST2 may be different from each other. For example, at least one of the light-emitting stacks ST1 and ST2 may emit blue light, and the other of the light-emitting stacks ST1 and ST2 may emit green light. A light-emitting element OLED including the light-emitting stacks ST1 and ST2 that emit light having different wavelength ranges may emit white light.

[0107] A charge generation layer CGL may be disposed between the first light-emitting stack ST1 and the second light-emitting stack ST2. In the case of applying a voltage, the charge generation layer CGL may generate charges (electrons and holes) by forming a complex via a redox reaction. In addition, the charge generation layer CGL may supply the generated charges to the light-emitting stacks ST1 and ST2. The charge generation layer CGL may double the current efficiency generated in the light-emitting stacks ST1 and ST2 and may be used to balance the charges between the first light-emitting stack ST1 and the second light-emitting stack ST2.

[0108] More specifically, the charge generation layer CGL may have a layer structure in which a lower charge generation layer CGL-1 and an upper charge generation layer CGL-2 are joined to each other. The lower charge generation layer CGL-1 may be an N-type charge generation layer disposed adjacent to the first light-emitting stack ST1, and may supply electrons to the first light-emitting stack ST1. The lower charge generation layer CGL-1 may include an arylamine-based organic compound.

[0109] The upper charge generation layer CGL-2 may be a P-type charge generation layer disposed adjacent to the second light-emitting stack ST2, and may supply holes to the second light-emitting stack ST2. The upper charge generation layer CGL-2 may include a charge generation compound made of a metal, a metal oxide, a carbide, a fluoride, or a mixture thereof.

[0110] A buffer layer may be further disposed between the lower charge generation layer CGL-1 and the upper charge generation layer CGL-2.

[0111] According to an embodiment, the first light-emitting stack ST1, the charge generation layer CGL, and the second light-emitting stack ST2 may be commonly formed in a pixel using an opening mask. However, the embodiment is not limited thereto, and at least one of the first hole control layer HTR1 and the second hole control layer HTR2, the first light-emitting layer EML1 and the second light-emitting layer EML2, and the first electron control layer ETR1 and the second electron control layer ETR2 may be patterned and formed through a mask. For example, the first light-emitting layer EML1 and the second light-emitting layer EML2 may be disposed in a region corresponding to the pixel opening OP (see Figure 3B ). For example, the first light-emitting layer EML1 and the second light-emitting layer EML2 may be separately formed in the pixel.

[0112] The second electrode CE may be disposed on the second light-emitting stack ST2. The second electrode CE may have an integral shape and may be commonly disposed in the pixel.

[0113] Returning to Figure 3B , the upper insulating layer TFL may be disposed on the display element layer DP-OLED and include a thin film. According to an embodiment, the upper insulating layer TFL may include a coating layer CPL and a packaging layer TFE disposed on the coating layer CPL. The coating layer CPL may be disposed on the second electrode CE and may be in contact with the second electrode CE. The coating layer CPL may include an organic material.

[0114] The encapsulation layer TFE may include a first inorganic encapsulation layer TIOL1, an organic encapsulation layer TOL disposed on the first inorganic encapsulation layer TIOL1, and a second inorganic encapsulation layer TIOL2 disposed on the organic encapsulation layer TOL. The first inorganic encapsulation layer TIOL1 and the second inorganic encapsulation layer TIOL2 may protect the display element layer DP-OLED from moisture / oxygen, and the organic encapsulation layer TOL may protect the display element layer DP-OLED from foreign substances such as dust particles.

[0115] Referring to Figure 3D , the light-emitting element OLED-1 according to an embodiment may include a first electrode AE, a first light-emitting stack ST1, a first charge generation layer CGL1, a second light-emitting stack ST2, a second charge generation layer CGL2, a third light-emitting stack ST3, and a second electrode CE. In the embodiment, the light-emitting element OLED-1 may include three light-emitting stacks ST1, ST2, and ST3 and two charge generation layers CGL1 and CGL2 disposed between adjacent light-emitting stacks ST1, ST2, and ST3. The same / similar reference numerals are used for Figure 3B and Figure 3C the same / similar components described in

[0116] The third light-emitting stack ST3 may have a structure similar to that of the first light-emitting stack ST1 and the second light-emitting stack ST2 described above in Figure 3C . The third light-emitting stack ST3 may include a third hole control layer, a third light-emitting layer, and a third electron control layer sequentially stacked on the second charge generation layer CGL2 in a third direction DR3.

[0117] In addition, the first charge generation layer CGL1 and the second charge generation layer CGL2 may have a structure similar to that of the charge generation layer CGL described above in Figure 3C . The first charge generation layer CGL1 may have a layer structure in which a first lower charge generation layer CGL-1 and a first upper charge generation layer CGL-2 are joined to each other, and the second charge generation layer CGL2 may have a layer structure in which a second lower charge generation layer CGL-3 and a second upper charge generation layer CGL-4 are joined to each other.

[0118] For example, the number of the light-emitting stacks ST1, ST2, and ST3 and the charge generation layers CGL1 and CGL2 is not limited to Figure 3C and Figure 3D shown in

[0119] Figure 4AIt is an enlarged schematic plan view of a part of a display panel according to an embodiment. Figure 4A is Figure 2 An enlarged schematic view of the arrangement of pixels, valley regions VA1, VA2, and VA3, and non-valley regions NVA1, NVA2, and NVA3 defined adjacent thereto in region AA' inside the display panel DP shown in

[0120] Referring to Figure 4A , in the display module DM (see Figure 2 ) of the embodiment, the display area DP-DA (see Figure 2 ) may include pixel regions PXA-B, PXA-R, and PXA-G and a non-pixel region NPXA surrounding the pixel regions PXA-B, PXA-R, and PXA-G. In the description, the substrate layer BL (see Figure 2 ) of the display panel DP (see Figure 3B ) may include pixel regions PXA-B, PXA-R, and PXA-G and a non-pixel region NPXA, and the remaining components (see Figure 3B ) provided on the substrate layer BL of the display panel DP may overlap with the pixel regions PXA-B, PXA-R, and PXA-G and / or the non-pixel region NPXA.

[0121] The pixel regions PXA-B, PXA-R, and PXA-G may include a first pixel region PXA-B, a second pixel region PXA-R, and a third pixel region PXA-G. The first pixel region PXA-B, the second pixel region PXA-R, and the third pixel region PXA-G may emit light having different wavelengths. The first pixel region PXA-B may emit first light having a blue wavelength, the second pixel region PXA-R may emit second light having a red wavelength, and the third pixel region PXA-G may emit third light having a green wavelength.

[0122] The first pixel region PXA-B may be arranged in a first direction DR1' and a third direction DR3'. The first pixel region PXA-B may form pixel rows arranged in the first direction DR1'. The pixel rows may be spaced apart from each other in the third direction DR3'. The second pixel region PXA-R may be arranged between the first pixel regions PXA-B in a fifth direction DR5' or a fourth direction DR4'. The third pixel region PXA-G may be arranged between the first pixel regions PXA-B in a fifth direction DR5' or a fourth direction DR4'.

[0123] For example, the first direction DR1', the second direction DR2', the third direction DR3', the fourth direction DR4', and the fifth direction DR5' may represent different from Figures 1 to 3DThe directions of the first direction DR1, the second direction DR2, and the third direction DR3 described in. The first direction DR1’, the second direction DR2’, the third direction DR3’, the fourth direction DR4’, and the fifth direction DR5’ are not absolute directions but relative directions for description and can be interchanged.

[0124] Each of the pixel regions PXA - B, PXA - R, and PXA - G can be a region defined by a pixel defining layer PDL. The non - pixel region NPXA can be the region between adjacent pixel regions PXA - B, PXA - R, and PXA - G and can be a region corresponding to the pixel defining layer PDL.

[0125] In the pixel defining layer PDL, a first pixel opening OP - B corresponding to the first pixel region PXA - B, a second pixel opening OP - R corresponding to the second pixel region PXA - R, and a third pixel opening OP - G corresponding to the third pixel region PXA - G can be defined.

[0126] Each of the plurality of first pixel regions PXA - B can correspond to a first electrode AE exposed from the pixel defining layer PDL through the corresponding first pixel opening OP - B (see Figure 3B ). Each of the plurality of second pixel regions PXA - R can correspond to a first electrode AE exposed from the pixel defining layer PDL through the corresponding second pixel opening OP - R (see Figure 3B ). Each of the plurality of third pixel regions PXA - G can correspond to a first electrode AE exposed from the pixel defining layer PDL through the corresponding third pixel opening OP - G (see Figure 3B ).

[0127] According to the wavelength of the emitted light, the first pixel region PXA - B, the second pixel region PXA - R, and the third pixel region PXA - G can have different areas. For example, the first pixel region PXA - B emitting the first light can have the largest area. The second pixel region PXA - R emitting the second light and the third pixel region PXA - G emitting the third light can have substantially the same area. However, the embodiments are not limited thereto, and the first pixel region PXA - B, the second pixel region PXA - R, and the third pixel region PXA - G can have the same area, or the first pixel region PXA - B, the second pixel region PXA - R, and the third pixel region PXA - G can be defined with an area ratio different from that shown in Figure 4A . In another example, in addition to the light having a green wavelength, the light having a blue wavelength, and the light having a red wavelength, the first pixel region PXA - B, the second pixel region PXA - R, and the third pixel region PXA - G can emit light having other colors.

[0128] Each of the first pixel region PXA-B, the second pixel region PXA-R, and the third pixel region PXA-G may have a rectangular shape with rounded corners in a plan view or on a plane. However, the shapes of the first pixel region PXA-B, the second pixel region PXA-R, and the third pixel region PXA-G are illustratively shown, and the first pixel region PXA-B, the second pixel region PXA-R, and the third pixel region PXA-G may be modified into various shapes as needed.

[0129] In an embodiment, the first virtual line L1, the second virtual line L2, and the third virtual line L3 may be defined in the pixel defining layer PDL. Each of the plurality of first virtual lines L1 may be formed (or defined) as a line surrounding (e.g., completely surrounding) the corresponding first pixel opening OP-B. Each of the plurality of second virtual lines L2 may be formed (or defined) as a line surrounding (e.g., completely surrounding) the corresponding second pixel opening OP-R. Each of the plurality of third virtual lines L3 may be formed (or defined) as a line surrounding (e.g., completely surrounding) the corresponding third pixel opening OP-G.

[0130] The pixel defining layer PDL may include at least one first valley region VA1 and at least one first non-valley region NVA1 disposed on the first virtual line (e.g., a single first virtual line) L1, at least one second valley region VA2 and at least one second non-valley region NVA2 disposed on the second virtual line (e.g., a single second virtual line) L2, and at least one third valley region VA3 and at least one third non-valley region NVA3 disposed on the third virtual line (e.g., a single third virtual line) L3.

[0131] In an embodiment, the first valley region VA1 may be provided on the first virtual line L1. The first valley region VA1 may include a 1-1 valley region VA1-1 and a 1-2 valley region VA1-2 on the first virtual line L1. The 1-1 valley region VA1-1 and the 1-2 valley region VA1-2 may be spaced apart from each other. Except for the 1-1 non-valley region NVA1-1 and the 1-2 non-valley region NVA1-2, the 1-1 valley region VA1-1 and the 1-2 valley region VA1-2 may surround the remaining part of the periphery of the first pixel region PXA-B. The 1-1 valley region VA1-1 and the 1-2 valley region VA1-2 may face each other in the third direction DR3'.

[0132] In an embodiment, the first non-valley region NVA1 may be provided on the first virtual line L1, and the first non-valley region NVA1 may include a 1-1 non-valley region NVA1-1 and a 1-2 non-valley region NVA1-2.

[0133] The first non-valley region NVA1-1 and the first non-valley region NVA1-2 can be arranged between the first valley regions VA1 on the first virtual line L1. The first non-valley region NVA1-1 can extend parallel to the fourth direction DR4'. The first non-valley region NVA1-2 can extend parallel to the fifth direction DR5'.

[0134] In an embodiment, the second virtual line L2 can surround the second pixel region PXA-R. The second valley region VA2 can be provided on the second virtual line L2. The second valley region VA2 can surround the long side (e.g., a single long side) of the second pixel region PXA-R that extends in the fourth direction DR4' or the fifth direction DR5', and the two short sides of the second pixel region PXA-R that extend in the fifth direction DR5' or the fourth direction DR4'.

[0135] In an embodiment, the second non-valley region NVA2 can be provided on the second virtual line L2. The second non-valley region NVA2 can be provided on the long side (e.g., a single long side) of the second pixel region PXA-R that extends in the fourth direction DR4' or the fifth direction DR5'. The second non-valley region NVA2 can be provided at the central portion of the long side of the second pixel region PXA-R that extends in the fourth direction DR4' or the fifth direction DR5'.

[0136] The second non-valley region NVA2 can face the adjacent first valley region VA1 in the fourth direction DR4' or the fifth direction DR5'. The second non-valley region NVA2 does not face the first non-valley region NVA1 in the fourth direction DR4' or the fifth direction DR5'. The second non-valley region NVA2 can be arranged adjacent to the first pixel region PXA-B. The second non-valley region NVA2 can be provided on the long side of the second pixel region PXA-R that is adjacent to the first pixel region PXA-B among the long sides.

[0137] In an embodiment, the third valley region VA3 can be provided on the third virtual line L3. The third valley region VA3 can include a 3-1 valley region VA3-1 and a 3-2 valley region VA3-2 on the third virtual line L3. The 3-1 valley region VA3-1 and the 3-2 valley region VA3-2 can be spaced apart from each other.

[0138] In an embodiment, the 3-1 valley region VA3-1 can surround the first short side of the third pixel region PXA-G, a part of the first long side adjacent to the first short side, and a part of the second long side adjacent to the first short side. The 3-2 valley region VA3-2 can surround the second short side of the third pixel region PXA-G, a part of the first long side adjacent to the second short side, and a part of the second long side adjacent to the second short side.

[0139] In an embodiment, the third non-valley region NVA3 may be provided on the third virtual line L3, and the third non-valley region NVA3 may include a 3-1 non-valley region NVA3-1 and a 3-2 non-valley region NVA3-2.

[0140] Each of the 3-1 non-valley region NVA3-1 and the 3-2 non-valley region NVA3-2 may extend in a fourth direction DR4' or a fifth direction DR5'. The 3-1 non-valley region NVA3-1 and the 3-2 non-valley region NVA3-2 may be disposed adjacent to a first long side and a second long side of the third pixel region PXA-G, respectively. The 3-1 non-valley region NVA3-1 may face an adjacent first valley region VA1 in the fourth direction DR4' or the fifth direction DR5'. The 3-2 valley region VA3-2 may face an adjacent second valley region VA2 in the fourth direction DR4' or the fifth direction DR5'.

[0141] In an embodiment, the length of the 3-1 non-valley region NVA3-1 in the fourth direction DR4' or the fifth direction DR5' may be substantially the same as the length of the 3-2 non-valley region NVA3-2 in the fourth direction DR4' or the fifth direction DR5'. For example, the 3-1 non-valley region NVA3-1 and the 3-2 non-valley region NVA3-2 may be arranged to face each other in the fourth direction DR4' or the fifth direction DR5'. When observed in the fourth direction DR4' or the fifth direction DR5', the 3-1 non-valley region NVA3-1 and the 3-2 non-valley region NVA3-2 may overlap each other.

[0142] In the display panel DP according to an embodiment, the valley regions VA1, VA2, and VA3 surrounding portions of the pixel regions PXA-B, PXA-R, and PXA-G may be defined to prevent lateral leakage current from occurring between adjacent pixels. For example, in the specification, "lateral leakage current" means a current flowing in another direction crossing the third direction DR3 (see Figure 3C and Figure 3D ), rather than a current flowing in the third direction DR3 (see Figure 3C and Figure 3D ) which is the stacking direction of the light-emitting elements OLED and OLED-1 (see Figure 3C and Figure 3D ), for example, in the direction of displaying an image. The lateral leakage current may mean a current flowing in a direction parallel to the plane defined by the first direction DR1 (see Figure 3A and Figure 3B ) and the second direction DR2 (see Figure 3A and Figure 3B ).

[0143] According to an embodiment, the separation pattern HSP (see Figure 5A) can be set in the valley regions VA1, VA2, and VA3. The separation pattern HSP corresponding to the valley regions VA1, VA2, and VA3 can be defined (see Figure 5A ). Accordingly, lateral leakage current can be prevented, color mixing between adjacent pixels can be prevented, and reduction in luminance can be prevented. A detailed description of the separation pattern HSP (see Figure 5A ) will be made later with reference to Figure 5A , Figure 5B and Figure 6 .

[0144] According to an embodiment, as described above, the separation pattern HSP (see Figure 5A ) may not be set in the valley regions VA1, VA2, and VA3. For example, the recessed portions GRU2 corresponding to the valley regions VA1, VA2, and VA3 (see Figure 9 ) can be defined in the pixel defining layer PDL. Accordingly, lateral leakage current can be prevented, color mixing between adjacent pixels can be prevented, and reduction in luminance can be prevented. A detailed description of the recessed portions GRU2 (see Figure 9 ) will be made later with reference to Figures 7 to 9 .

[0145] According to an embodiment, the pixel defining layer PDL may include non-valley regions NVA1, NVA2, and NVA3 defined as regions where no valley pattern is formed so that a driving voltage can be transmitted to the second electrode CE (see Figure 3B ). In an embodiment, at least one first non-valley region NVA1, at least one second non-valley region NVA2, and at least one third non-valley region NVA3 may be arranged not to face each other. In the description, the phrase "arranged not to face each other" means that different non-valley patterns do not overlap with each other in a portion defining the shortest distance between adjacent pixel regions. In the description, the phrase "different non-valley regions" means a plurality of non-valley regions respectively arranged on different virtual lines.

[0146] The first non-valley region NVA1, the second non-valley region NVA2, and the third non-valley region NVA3 may be arranged not to face each other. In the case where the first non-valley region NVA1, the second non-valley region NVA2, and the third non-valley region NVA3 are defined to face each other, lateral leakage current may occur between adjacent pixels through the first non-valley region NVA1, the second non-valley region NVA2, and the third non-valley region NVA3 facing each other. According to an embodiment, the first non-valley region NVA1, the second non-valley region NVA2, and the third non-valley region NVA3 are arranged not to face each other, and thus lateral leakage current between adjacent pixels through the first non-valley region NVA1, the second non-valley region NVA2, and the third non-valley region NVA3 facing each other can be prevented.

[0147] Figure 4B is according to an embodiment Figure 4A is an enlarged schematic plan view of part BB'. In Figure 4B it, the first valley region VA1-1 may have been descriptively described, but the following description of the first valley region VA1-1 may equally apply to Figure 4A the first valley region VA1, the second valley region VA2, and the third valley region VA3 of

[0148] Referring to Figure 4B , the first valley region VA1-1 may extend in the fifth direction DR5', and may be separated from the first pixel region PXA-B by a selected distance in the fourth direction DR4'. The first valley region VA1-1 may surround a part of the first pixel opening OP-B. The first valley region VA1 may include the first valley part PVA1-1, the overlapping part HVA, and the second valley part PVA1-2.

[0149] The first valley part PVA1-1 may be adjacent to the first pixel region PXA-B and may extend along the periphery of the first pixel region PXA-B. The first valley part PVA1-1 may have a constant width in a plan view or on a plane and may extend in the fifth direction DR5'. The first valley part PVA1-1 may be closer to the first pixel region PXA-B than the second pixel region PXA-R.

[0150] The second valley part PVA1-2 may be farther from the first pixel opening OP-B than the first valley part PVA1-1. The second valley part PVA1-2 may have a shape corresponding to that of the first valley part PVA1-1. The second valley part PVA1-2 may have a constant width in a plan view or on a plane and may extend in the fifth direction DR5'. The second valley part PVA1-2 may be closer to the first pixel region PXA-B than the second pixel region PXA-R. The second valley part PVA1-2 may be separated from the first valley part PVA1-1 by a selected distance in the fourth direction DR4'. The width of the second valley part PVA1-2 in the fourth direction DR4' in a plan view or on a plane may be substantially the same as the width of the first valley part PVA1-1 in the fourth direction DR4' in a plan view or on a plane.

[0151] The overlapping portion HVA can be provided between the first valley portion PVA1-1 and the first second valley portion PVA1-2. Similar to the first valley portion PVA1-1 and the first second valley portion PVA1-2, the overlapping portion HVA can also extend in the fifth direction DR5'. Among the long sides of the overlapping portion HVA, the first long side adjacent to the first pixel region PXA-B can contact the first valley portion PVA1-1. Among the long sides of the overlapping portion HVA, the second long side adjacent to the second pixel region PXA-R can contact the first second valley portion PVA1-2. The first valley portion PVA1-1, the first second valley portion PVA1-2, and the overlapping portion HVA can together constitute the first valley region (e.g., a single first valley region) VA1-1 that extends in the fifth direction DR5'.

[0152] The overlapping portion HVA can be line-symmetric with respect to a line defined by the lowest point SP, which will be described later. The line defined by the lowest point SP can extend in the fifth direction DR5'. The line defined by the lowest point SP can overlap the overlapping portion HVA in a plan view or on a plane.

[0153] Figure 5A is a schematic cross-sectional view along line I-I' according to an embodiment. Hereinafter, the description of the first valley region VA1-1 can be equally applied to Figure 4B the first valley region VA1, the second valley region VA2, and the third valley region VA3 shown in Figure 4A .

[0154] Referring to Figure 5A , a display panel DP according to an embodiment can include a substrate layer BL, a circuit element layer DP-CL provided on the substrate layer BL, and a light-emitting element OLED provided on the circuit element layer DP-CL. For example, an upper insulating layer TFL (see Figure 3B ) can be further provided on the light-emitting element OLED.

[0155] The light-emitting element OLED provided on the circuit element layer DP-CL can include a first electrode AE, a light-emitting unit EP, and a second electrode CE that are sequentially stacked. The light-emitting unit EP can be provided on a pixel defining layer PDL and can overlap the first pixel region PXA-B and the second pixel region PXA-R. Figure 5A The light-emitting unit EP in Figure 3C can include the first light-emitting stack ST1, the charge generation layer CGL, and the second light-emitting stack ST2 described above in Figure 3C . The first light-emitting stack ST1 can include at least a first light-emitting layer EML1 (see Figure 3C ), and the second light-emitting stack ST2 can include at least a second light-emitting layer EML2 (see Figure 3C ).

[0156] The pixel defining layer PDL may be disposed on the circuit element layer DP-CL. A first pixel opening OP-B and a second pixel opening OP-R (a part of the first electrode AE is exposed through the first pixel opening OP-B and the second pixel opening OP-R) may be defined in the pixel defining layer PDL.

[0157] The separation pattern HSP may be disposed on the pixel defining layer PDL. The separation pattern HSP may overlap with the 1-1 valley region VA1-1. The separation pattern HSP may include a first pattern portion HSP1, a second pattern portion HSP2, and a third pattern portion HSP3. The separation pattern HSP may prevent lateral leakage current that causes color mixing or brightness reduction between adjacent pixels from flowing along the charge generation layer CGL between adjacent pixels (see Figure 3C ) and thus may improve the display quality of the display panel DP. This will be described later with reference to Figure 5B for description.

[0158] The separation pattern HSP may include an organic photosensitive material. Thus, in the case of forming the separation pattern HSP, the organic photosensitive material may be cured or decomposed by irradiating light. The separation pattern HSP may include a material that cures when irradiated with light. For example, the separation pattern HSP may include a negative photosensitive material. In the case of using a negative photosensitive material and in the case of performing development by irradiating light, the angle formed between the outer surface of the separation pattern HSP and the upper surface PDL-US of the pixel defining layer PDL may increase.

[0159] The separation pattern HSP may have a shape in a cross section in which two protrusions protruding convexly from the upper surface PDL-US of the pixel defining layer PDL partially overlap in the overlapping portion HVA. This is because the angle of the separation pattern HSP in the overlapping portion HVA changes abruptly, and the charge generation layer CGL (see Figure 5B ) on the separation pattern HSP may be disconnected, and thus, lateral leakage current between adjacent pixels may be prevented.

[0160] The first pattern portion HSP1 may overlap with the 1-1 valley portion PVA1-1. The second pattern portion HSP2 may overlap with the 1-2 valley portion PVA1-2. The third pattern portion HSP3 may overlap with the overlapping portion HVA. The first pattern portion HSP1 and the second pattern portion HSP2 may have a symmetrical shape with respect to the third pattern portion HSP3.

[0161] The first pattern portion HSP1 may be a portion that protrudes from the upper surface PDL-US of the pixel defining layer PDL to a first height HI1 which is the maximum height of the first pattern portion HSP1. The distance from the first highest point HP1 of the first pattern portion HSP1 to the upper surface PDL-US of the pixel defining layer PDL in the second direction DR2' may be the first height HI1. The first pattern portion HSP1 may be a portion that protrudes convexly from the upper surface PDL-US of the pixel defining layer PDL. The second pattern portion HSP2 may protrude from the upper surface PDL-US of the pixel defining layer PDL to a second height HI2 which is the maximum height of the second pattern portion HSP2. The distance from the second highest point HP2 of the second pattern portion HSP2 to the upper surface PDL-US of the pixel defining layer PDL in the second direction DR2' may be the second height HI2. For example, the first height HI1 and the second height HI2 may be substantially the same as each other. For example, the first pattern portion HSP1 and the second pattern portion HSP2 may be portions that protrude convexly from the upper surface PDL-US of the pixel defining layer PDL.

[0162] The third pattern portion HSP3 may protrude from the upper surface PDL-US of the pixel defining layer PDL to a third height HI3 (see Figure 5B ) which is less than the first height HI1 and the second height HI2 and which is the maximum height of the third pattern portion HSP3. The third pattern portion HSP3 may be a portion that is curved from the upper surfaces of the first pattern portion HSP1 and the second pattern portion HSP2 toward the upper surface PDL-US of the pixel defining layer PDL. Thus, the third height HI3 (see Figure 5B ) which is the maximum height of the third pattern portion HSP3 may be less than the first height HI1 and the second height HI2.

[0163] The third pattern portion HSP3 may be provided between the first pattern portion HSP1 and the second pattern portion HSP2. The third pattern portion HSP3 may be a portion that is recessed from the upper surfaces of the first pattern portion HSP1 and the second pattern portion HSP2 toward the upper surface PDL-US of the pixel defining layer PDL.

[0164] The angles AN1-1 and AN1-2 formed between the tangents to the outer surface of the third pattern portion HSP3 and the upper surface PDL-US of the pixel defining layer PDL may increase as the positions where the angles AN1-1 and AN1-2 are located are closer to the lowest point SP of the third pattern portion HSP3. The lowest point SP of the third pattern portion HSP3 may be positioned at the central portion of the overlapping portion HVA. Thus, at the lowest point SP, the sum of the angles AN1-1 and AN1-2 formed between the tangents to the outer surface of the third pattern portion HSP3 and the upper surface PDL-US of the pixel defining layer PDL may increase. This will be described later with reference to Figure 5B for details.

[0165] The light-emitting unit EP may be disposed on the separation pattern HSP and the pixel definition layer PDL. The light-emitting unit EP may cover the separation pattern HSP. The light-emitting unit EP may overlap with the pixel regions PXA-R and PXA-B and the non-pixel region NPXA. As described above in Figure 3C as described, the light-emitting unit EP may include a first light-emitting stack ST1, a charge generation layer CGL, and a second light-emitting stack ST2, and as described above in Figure 3D as described, the light-emitting unit EP may include three light-emitting stacks ST1, ST2, and ST3 and two charge generation layers CGL1 and CGL2.

[0166] The second electrode CE may be disposed on the light-emitting unit EP and cover the light-emitting unit EP. The second electrode CE may overlap with the pixel regions PXA-R and PXA-B and the non-pixel region NPXA.

[0167] The highest points of the first pattern portion HSP1 and the second pattern portion HSP2 may be spaced apart from each other by a first distance D1 in the fourth direction DR4'. As the first distance D1 increases, the minimum height LHI3 of the lowest point SP may decrease. Accordingly, portions of the outer surface of the third pattern portion HSP3 having a large slope may meet at the lowest point SP, and the 1-1 angle AN1-1 and the 1-2 angle AN1-2 may increase. This means that the change in slope at the lowest point SP increases, and thus, the charge generation layer CGL (see Figure 5B ) may be disconnected. However, when the first distance D1 is too large, the protrusions may not overlap with each other, and thus, the overlapping portion HVA and the third pattern portion HSP3 corresponding to the overlapping portion HVA may disappear. Since the third pattern portion HSP3 (the slope of the third pattern portion HSP3 changes abruptly) disappears, the charge generation layer CGL may not be disconnected, and thus, a lateral leakage current may flow between adjacent pixels. The first distance D1 may be in the range of about 3 μm to about 5 μm.

[0168] Figure 5B is an enlarged schematic cross-sectional view of the portion CC' according to an embodiment of Figure 5A of.

[0169] Referring to Figure 5B , the light-emitting unit EP may include a first light-emitting stack ST1, a charge generation layer CGL, and a second light-emitting stack ST2. The first light-emitting stack ST1 may be disposed on the lower surface of the charge generation layer CGL. The second light-emitting stack ST2 may be disposed on the upper surface of the charge generation layer CGL. The first light-emitting stack ST1 and the second light-emitting stack ST2 may respectively include light-emitting layers EML1 and EML2 that emit light (see Figure 3C)。The light-emitting unit EP may have a shape corresponding to the upper surface of the third pattern portion HSP3. The second electrode CE may have a shape corresponding to the upper surface of the third pattern portion HSP3.

[0170] A recessed portion GRU1 recessed toward the upper surface PDL-US of the pixel defining layer PDL may be defined on the upper surface of the third pattern portion HSP3. As the recessed portion GRU1 approaches the first pattern portion HSP1 or the second pattern portion HSP2, the recessed portion GRU1 may move away from the upper surface PDL-US of the pixel defining layer PDL. The light-emitting unit EP may be disposed along the upper surface of the first pattern portion HSP1, the upper surface of the second pattern portion HSP2, and the recessed portion GRU1.

[0171] The charge generation layer CGL may be disconnected near the lowest point SP of the third pattern portion HSP3 closest to the upper surface PDL-US of the pixel defining layer PDL. The charge generation layer CGL may be disconnected at a position ASP corresponding to the lowest point SP of the third pattern portion HSP3. The lowest point SP of the third pattern portion HSP3 may be a point where the slope of the outer surface of the third pattern portion HSP3 changes abruptly. For example, the charge generation layer CGL may be disconnected due to the abruptly changing slope of the outer surface of the third pattern portion HSP3. For example, the charge generation layer CGL disposed at the lowest point SP of the third pattern portion HSP3 may be sharply bent and broken. Accordingly, it is possible to prevent the lateral leakage current from flowing through the charge generation layer CGL in the fourth direction DR4'.

[0172] The common electrode CE disposed on the light-emitting unit EP may not be disconnected on the third pattern portion HSP3. Accordingly, the common electrode CE may supply a common voltage to adjacent pixels.

[0173] As the positions where the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 are located are closer to the lowest point SP of the third pattern portion HSP3, the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 formed between the tangent to the outer surface of the third pattern portion HSP3 and the upper surface PDL-US of the pixel defining layer PDL may increase. For example, the first - 1 angle AN1 - 1 may be an angle formed between the tangent to the outer surface of the third pattern portion HSP3 near the first pattern portion HSP1 and the upper surface PDL-US of the pixel defining layer PDL. The first - 2 angle AN1 - 2 may be an angle formed between the tangent to the outer surface of the third pattern portion HSP3 near the second pattern portion HSP2 and the upper surface PDL-US of the pixel defining layer PDL.

[0174] As the sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 increases, the change in the slope of the outer surface of the third pattern portion HSP3 can increase. Since the sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 is maximum at the lowest point SP, the charge - generating layer CGL can be disconnected at the position ASP corresponding to the lowest point SP.

[0175] The first - 1 angle AN1 - 1 can be about 30 degrees or greater, and the first - 2 angle AN1 - 2 can be about 30 degrees or greater. The sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 can be about 60 degrees or greater. When the sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 is less than about 60 degrees, the change in the slope of the third pattern portion HSP3 may not be large enough, and thus the charge - generating layer CGL may not be disconnected near the lowest point SP. In addition, when the sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 is too large, there may be a risk of disconnection of the common electrode CE.

[0176] The sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 can be changed according to the height LHI3 (hereinafter referred to as the minimum height LHI3) of the lowest point SP from the upper surface PDL - US of the pixel - defining layer PDL. As the minimum height LHI3 decreases, the sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 can increase. As the minimum height LHI3 increases, the sum of the first - 1 angle AN1 - 1 and the first - 2 angle AN1 - 2 can decrease.

[0177] Figure 6 is a schematic cross - sectional view along line I - I’ according to an embodiment. Hereinafter, the same reference numerals are used for components identical to those described in Figure 4B and their descriptions will be omitted. Figure 5A and Figure 5B The second distance D2 of the display panel DP in

[0178] Referring to Figure 6 can be less than the first distance D1 of the display panel DP in Figure 6 . Thus, the first pattern portion HSP1 and the second pattern portion HSP2 are positioned closer to each other, and the minimum height HI4 of the lowest point SP can be greater than Figure 5A the minimum height LHI3 in Figure 5A .

[0179] The minimum height HI4 can be greater than Figure 5A the minimum height LHI3 of the display panel DP in Figure 5Athe first - 1 angle AN1 - 1, and the second - 2 angle AN2 - 2 can be less than Figure 5A the first - 2 angle AN1 - 2. For example, the change in the slope at the lowest point SP of the outer surface of the third pattern portion HSP3 is reduced, which may lead to the possibility that the charge generation layer CGL does not break. Therefore, Figure 5A the display panel DP of Figure 6 is more suitable than the display panel DP of

[0180] Figure 7 is according to the embodiment Figure 4A an enlarged schematic plan view of the portion BB’ of Figure 7 In Figure 4A the first valley region VA1 - 1 has been descriptively described, but the following description of the first valley region VA1 - 1 can be equally applied to

[0181] Referring to Figure 7 , the first valley region VA1 - 1 can extend in the fifth direction DR5’ and can be separated from the first pixel region PXA - B by a selected distance in the fourth direction DR4’. The first valley region VA1 - 1 can surround a part of the first pixel opening OP - B. The first valley region VA1 - 1 can be line - symmetric with respect to the line defined by the lowest point SPP. The line defined by the lowest point SPP can extend in the fifth direction DR5’. The line defined by the lowest point SPP can overlap with the first valley region VA1 - 1 in the plan view or on the plane.

[0182] Figure 8 is a schematic cross - sectional view according to the embodiment along Figure 7 the line II - II’ of

[0183] Referring to Figure 8 , a recessed portion GRU2 (see Figure 9 ) overlapping with the first valley region VA1 - 1 can be defined in the pixel - defining layer PDL. The pixel - defining layer PDL can include a first portion P1 - PDL, a second portion P2 - PDL, and a third portion P3 - PDL. The maximum height of the first portion P1 - PDL from the lower surface PDL - LS to the upper surface PDL - US of the pixel - defining layer PDL can be the first height HI1’. The maximum height of the second portion P2 - PDL from the lower surface PDL - LS to the upper surface PDL - US of the pixel - defining layer PDL can be the second height HI2’. The first height HI1’ and the second height HI2’ can be substantially the same as each other.

[0184] The third portion P3-PDL can be disposed between the first portion P1-PDL and the second portion P2-PDL, and the maximum height of the third portion P3-PDL from the lower surface PDL-LS to the upper surface PDL-US of the pixel defining layer PDL can be a third height HI3'. The third height HI3' can be less than the first height HI1' and the second height HI2'. The third portion P3-PDL can be a portion that is recessed from the first portion P1-PDL and the second portion P2-PDL toward the lower surface PDL-LS of the pixel defining layer PDL.

[0185] The change in the slope of the outer surface of the third portion P3-PDL can be large at the lowest point SPP of the third portion P3-PDL. Accordingly, the charge generation layer CGL (see Figure 9 ) disposed near the lowest point SPP can be disconnected.

[0186] The pixel defining layer PDL can include an organic photosensitive material. The pixel defining layer PDL can include a photocurable material. For example, the pixel defining layer PDL can include a negative photosensitive material. In the case of using a negative photosensitive material and in the case of performing development by irradiating light, the angle formed between the outer surface of the pixel defining layer PDL and the lower surface PDL-LS of the pixel defining layer PDL can increase.

[0187] Figure 9 is a schematic enlarged cross-sectional view of the portion DD' according to an embodiment Figure 8 of.

[0188] Referring to Figure 9 , a recessed portion GRU2 recessed toward the lower surface PDL-LS of the pixel defining layer PDL can be defined on the upper surface of the third portion P3-PDL. The light emitting unit EP can be disposed along the upper surface of the first portion P1-PDL, the upper surface of the second portion P2-PDL, and the recessed portion GRU2.

[0189] The charge generation layer CGL can be disconnected near the lowest point SPP closest to the lower surface PDL-LS of the pixel defining layer PDL in the third portion P3-PDL among the recessed portion GRU2. The charge generation layer CGL can be disconnected at a position ASP corresponding to the lowest point SPP of the third portion P3-PDL. The lowest point SPP of the third portion P3-PDL can be a point at which the slope of the outer surface of the third portion P3-PDL changes abruptly. For example, the charge generation layer CGL can be disconnected due to the abruptly changing slope of the outer surface of the third portion P3-PDL. For example, the charge generation layer CGL disposed at the lowest point SPP of the third portion P3-PDL can be abruptly bent and broken. Accordingly, lateral leakage current can be prevented from flowing through the charge generation layer CGL in the fourth direction DR4'.

[0190] The common electrode CE provided on the light-emitting unit EP may not be disconnected on the third part P3-PDL. Therefore, the common electrode CE can supply a common voltage to adjacent pixels.

[0191] As the positions where the 3-1 angle AN3-1 and the 3-2 angle AN3-2 are located are closer to the lowest point SPP of the third part P3-PDL, the 3-1 angle AN3-1 and the 3-2 angle AN3-2 formed between the tangent of the outer surface of the third part P3-PDL and the lower surface PDL-LS of the pixel defining layer PDL can increase. For example, the 3-1 angle AN3-1 can be the angle formed between the tangent of the outer surface of the third part P3-PDL close to the first part P1-PDL and the lower surface PDL-LS of the pixel defining layer PDL. The 3-2 angle AN3-2 can be the angle formed between the tangent of the outer surface of the third part P3-PDL close to the second part P2-PDL and the lower surface PDL-LS of the pixel defining layer PDL.

[0192] As the sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 increases, the change in the slope of the outer surface of the third part P3-PDL can increase. Since the sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 is the largest at the lowest point SPP, the charge generation layer CGL can be disconnected at the position ASP corresponding to the lowest point SPP.

[0193] The 3-1 angle AN3-1 can be about 30 degrees or greater, and the 3-2 angle AN3-2 can be about 30 degrees or greater. The sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 can be about 60 degrees or greater. When the sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 is less than about 60 degrees, the change in the slope of the third part P3-PDL may not be large enough, and thus, the charge generation layer CGL may not be disconnected near the lowest point SPP. In addition, when the sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 is too large, there may be a risk of the common electrode CE being disconnected.

[0194] The sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 can change according to the height LHI3’ (hereinafter referred to as the minimum height LHI3’) of the lowest point SPP from the lower surface PDL-LS of the pixel defining layer PDL. As the minimum height LHI3’ decreases, the sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 can increase. As the minimum height LHI3’ increases, the sum of the 3-1 angle AN3-1 and the 3-2 angle AN3-2 can decrease.

[0195] Figures 10A to 10DIt is a schematic cross-sectional view showing a part of a method of manufacturing a display device according to an embodiment. Hereinafter, the same reference numerals are used for the same components as those described above, and their descriptions will be omitted.

[0196] Referring to Figure 10A , a preliminary separation pattern layer P-HSP can be formed on a preliminary display device P-DP, the preliminary display device P-DP including a substrate layer BL and a pixel defining layer PDL, the substrate layer BL including pixel regions PXA-B and PXA-R and a non-pixel region NPXA, the pixel defining layer PDL being disposed on the substrate layer BL and defining pixel openings OP-B and OP-R corresponding to the pixel regions PXA-B and PXA-R, respectively. The preliminary separation pattern layer P-HSP can be disposed (e.g., directly disposed) on the upper surface of the pixel defining layer PDL. The preliminary separation pattern layer P-HSP can overlap with the non-pixel region NPXA. The preliminary separation pattern layer P-HSP can overlap with the pixel defining layer PDL.

[0197] Referring to Figure 10B , a separation pattern HSP (see Figure 10C ) can be formed by exposing light to the preliminary separation pattern layer P-HSP using a mask MK, the mask MK including transmissive regions TA and TA', a non-transmissive region NTA, and a half-transmissive region HTA disposed between the transmissive regions TA and TA'. For example, the mask MK can be a halftone mask. The preliminary separation pattern layer P-HSP can include a material that cures upon irradiation with light.

[0198] The non-transmissive region NTA of the mask MK can be a region through which light cannot pass. The transmissive region TA of the mask MK can be a region through which light can pass. The half-transmissive region HTA can be a region through which a smaller amount of light passes than the amount of light passing through the transmissive region TA.

[0199] Since the preliminary separation pattern layer P-HSP contains a negative photosensitive material (which is a material that cures upon irradiation with light), the part of the preliminary separation pattern layer P-HSP corresponding to the non-transmissive region NTA can be removed. The preliminary separation pattern layer P-HSP at the part corresponding to the transmissive region TA can be cured and retained. The preliminary separation pattern layer P-HSP at the part corresponding to the half-transmissive region HTA can be partially cured and retained. The preliminary separation pattern layer P-HSP at the part corresponding to the transmissive region TA can form a first pattern portion HSP1 (see Figure 10C ) and a second pattern portion HSP2 (see Figure 10C ). The preliminary separation pattern layer P-HSP at the part corresponding to the half-transmissive region HTA can form a third pattern portion HSP3 (see Figure 10C ).

[0200] Reference Figure 10C , the separated pattern HSP can be formed by exposing using a mask MK (see Figure 10B ) and then developing. The separated pattern HSP can include a first pattern portion HSP1, a second pattern portion HSP2, and a third pattern portion HSP3 provided between the first pattern portion HSP1 and the second pattern portion HSP2. During development, flow occurs in the preliminary separated pattern layer P-HSP (see Figure 10B ), and thus the separated pattern HSP can be formed in a continuously curved shape without steps in the cross section.

[0201] Reference Figure 10D , a light-emitting unit EP including a charge generation layer CGL (see Figure 5B ) can be formed on the separated pattern HSP. The charge generation layer CGL (see Figure 5B ) can be disconnected near the lowest point SP of the third pattern portion HSP3 corresponding to the semi-transmissive region HTA (see Figure 10B ) of the separated pattern HSP. For example, the charge generation layer CGL (see Figure 5B ) can be disconnected due to a sudden change in the slope at the lowest point SP. This has been described in detail above, and its description will be omitted.

[0202] A display panel DP can be formed by forming a common electrode CE covering the light-emitting unit EP and a pixel defining layer PDL on the light-emitting unit EP. The common electrode CE can overlap with a non-pixel region NPXA and pixel regions PXA-B and PXA-R, and can be continuously formed without disconnection.

[0203] As described above with reference to Figures 10A to 10D , the separated pattern HSP can be formed using a halftone mask MK. Compared with the related art, this can simplify the manufacturing process and reduce the manufacturing cost. In the related art, in order to form a separator on the pixel defining layer, a separate metal layer is formed on the pixel defining layer, a photoresist is exposed and developed on the pixel defining layer, the metal layer is wet-etched, the pixel defining layer is dry-etched, the photoresist is removed, and then the remaining metal layer is wet-etched. In addition, in the case of the method of manufacturing a display device according to an embodiment, a separate wet-etching process is not required, and thus pixels can be prevented from being damaged in the wet-etching process.

[0204] Figures 11A to 11D is a schematic cross-sectional view showing a part of the method of manufacturing a display device according to an embodiment. Hereinafter, the same reference numerals are used for the same components as those described above, and their descriptions will be omitted.

[0205] Reference Figure 11A, a preliminary display device P-DP including a substrate layer BL and a preliminary pixel definition layer P-PDL can be fabricated. The substrate layer BL includes pixel regions PXA-B and PXA-R and a non-pixel region NPXA. The preliminary pixel definition layer P-PDL is disposed on the substrate layer BL and defines pixel openings OP-B and OP-R corresponding to the pixel regions PXA-B and PXA-R, respectively. For example, the preliminary pixel definition layer P-PDL may include an organic photosensitive material. The preliminary pixel definition layer P-PDL may include a material that cures upon irradiation with light.

[0206] Referring to Figure 11B , the preliminary pixel definition layer P-PDL can be exposed using a mask MK. The mask MK may include a transmissive region TA through which light passes and a semi-transmissive region HTA through which light partially passes. A third portion P3-PDL (see Figure 11C ) in which a recess GRU2 (see Figure 11C ) is defined can be formed by exposing and developing the preliminary pixel definition layer P-PDL using the mask MK.

[0207] Referring to Figure 11B and Figure 11C , since the preliminary pixel definition layer P-PDL contains a negative photosensitive material (which is a material that cures upon irradiation with light), the preliminary pixel definition layer P-PDL at the portion corresponding to the transmissive region TA can be cured and retained. The preliminary pixel definition layer P-PDL at the portion corresponding to the semi-transmissive region HTA can be partially cured and retained. The preliminary pixel definition layer P-PDL at the portion corresponding to the transmissive region TA can form a first portion P1-PDL and a second portion P2-PDL. The preliminary pixel definition layer P-PDL at the portion corresponding to the semi-transmissive region HTA can form a third portion P3-PDL.

[0208] Referring to Figure 11D , a light-emitting unit EP including a charge generation layer CGL (see Figure 9 ) can be formed on the pixel definition layer PDL. The charge generation layer CGL (see Figure 9 ) can be disconnected near the lowest point SPP of the third portion P3-PDL corresponding to the semi-transmissive region HTA (see Figure 11B ) of the pixel definition layer PDL. For example, the charge generation layer CGL (see Figure 9 ) can be disconnected due to a sharp change in the slope at the lowest point SPP.

[0209] The display panel DP can be formed by forming a common electrode CE on the light-emitting unit EP to cover the light-emitting unit EP and the pixel-defining layer PDL. The common electrode CE can overlap with the non-pixel region NPXA and the pixel regions PXA-B and PXA-R, and can be continuously formed without disconnection.

[0210] The display device according to an embodiment can include a separation pattern surrounding a part of the pixel region, and the charge generation layer can be disconnected on the separation pattern. Accordingly, lateral leakage current can be prevented, color mixing between adjacent pixels can be prevented, and thus display quality can be improved and a reduction in brightness can be prevented.

[0211] In a method of manufacturing a display device according to an embodiment, by using a halftone mask including a semi-transmissive region to form the separation pattern, a partition can be formed without a separate additional process, and thus the manufacturing process can be simplified and the manufacturing cost can be reduced.

[0212] In summarizing the detailed description, those skilled in the art will appreciate that many variations and modifications can be made to the embodiments without substantially departing from the principles, spirit, and scope of the present disclosure. Accordingly, the disclosed embodiments are for general and descriptive purposes only and not for purposes of limitation.

Claims

1. A display device, wherein, The display device includes: a substrate layer including a pixel region and a non-pixel region; a pixel defining layer disposed on the substrate layer and including a pixel opening corresponding to the pixel region; a light-emitting unit disposed on the pixel defining layer, overlapping with the pixel region, and including a charge generation layer; and a separation pattern disposed on the pixel defining layer and overlapping with a valley region among a valley region and a non-valley region disposed on a virtual line surrounding the pixel opening, wherein the separation pattern includes: a first pattern portion protruding from an upper surface of the pixel defining layer to a first height; a second pattern portion protruding from the upper surface of the pixel defining layer to a second height same as the first height; and a third pattern portion disposed between the first pattern portion and the second pattern portion, and the third pattern portion being recessed from the first pattern portion and the second pattern portion toward the upper surface of the pixel defining layer, and the charge generation layer is disconnected on the third pattern portion.

2. The display device according to claim 1, wherein, The third pattern portion protrudes from the upper surface of the pixel defining layer to a third height, and the third height is less than the first height and the second height.

3. The display device according to claim 1, wherein, The separation pattern is made of an organic photosensitive material.

4. The display device according to claim 1, wherein the valley region includes: a first-1 valley portion surrounding a part of the pixel opening; a first-2 valley portion spaced farther from the pixel opening than the first-1 valley portion and having a shape corresponding to the shape of the first-1 valley portion; and an overlapping portion disposed between the first-1 valley portion and the first-2 valley portion, and the first pattern portion overlaps with the first-1 valley portion, the second pattern portion overlaps with the first-2 valley portion, and the third pattern portion overlaps with the overlapping portion.

5. The display device according to claim 4, wherein, The separation pattern has a shape in a cross section where two protruding portions convexly protruding from the upper surface of the pixel defining layer partially overlap in the overlapping portion.

6. The display device according to claim 4, wherein, The lowest point of the third pattern portion is positioned at a central portion of the overlapping portion.

7. The display device according to claim 1, wherein, The charge generation layer is disconnected at a position corresponding to the lowest point closest to the upper surface of the pixel defining layer of the third pattern portion.

8. The display device according to claim 1, wherein The separation pattern includes a material that cures under irradiation of light.

9. The display device according to claim 1, wherein the pixel region includes a first pixel region and a second pixel region spaced apart from the first pixel region, the pixel opening includes a first pixel opening corresponding to the first pixel region and a second pixel opening corresponding to the second pixel region, the non-valley region includes a first non-valley region disposed on a part of a first virtual line surrounding the first pixel opening and a second non-valley region disposed on a part of a second virtual line surrounding the second pixel opening, and the first non-valley region and the second non-valley region do not face each other.

10. The display device according to claim 1, wherein the light-emitting unit includes: a first light-emitting stack disposed on a lower surface of the charge generation layer; and A second light-emitting stack is disposed on an upper surface of the charge generation layer, and each of the first light-emitting stack and the second light-emitting stack includes a light-emitting layer that emits light.

11. The display device according to claim 1, wherein, An angle formed between a tangent to an outer surface of the third pattern portion and the upper surface of the pixel defining layer increases as a position where the angle is located gets closer to a lowest point of the third pattern portion.

12. The display device according to claim 1, wherein, The display device further includes: a common electrode disposed on the light-emitting unit and overlapping the pixel region and the non-pixel region, wherein the common electrode is not disconnected on the third pattern portion.

13. A display device, wherein, The display device includes: a substrate layer including a pixel region and a non-pixel region; a pixel defining layer disposed on the substrate layer and including a pixel opening corresponding to the pixel region; and a light-emitting unit disposed on the pixel defining layer, overlapping the pixel region, and including a charge generation layer, wherein a recess overlapping the valley region among a valley region and a non-valley region disposed on a virtual line surrounding the pixel opening is defined in the pixel defining layer, and the charge generation layer is disconnected at a position corresponding to a lowest point of the recess closest to a lower surface of the pixel defining layer.

14. The display device according to claim 13, wherein, The pixel defining layer includes a material that cures upon irradiation with light.

15. The display device according to claim 13, wherein, The pixel defining layer includes: a first portion, a maximum height of which from the lower surface of the pixel defining layer to the upper surface of the pixel defining layer is a first height; a second portion, a maximum height of which from the lower surface of the pixel defining layer to the upper surface of the pixel defining layer is a second height that is the same as the first height; and a third portion disposed between the first portion and the second portion, and a maximum height of which from the lower surface of the pixel defining layer to the upper surface of the pixel defining layer is a third height that is less than the first height and the second height.

16. The display device according to claim 13, wherein, An angle formed between a tangent to an outer surface of the recess and the lower surface of the pixel defining layer increases as a position where the angle is located gets closer to the lowest point of the recess.

17. A method of manufacturing a display device, wherein, The method includes: forming a preliminary separation pattern layer on a preliminary display device including a substrate layer and a pixel defining layer, the substrate layer including a pixel region and a non-pixel region, the pixel defining layer being disposed on the substrate layer and including a pixel opening corresponding to the pixel region; forming a separation pattern by exposing light to the preliminary separation pattern layer by using a mask including a transmissive region, a non-transmissive region, and a semi-transmissive region; and forming a light-emitting unit including a charge generation layer on the separation pattern, wherein the charge generation layer is disconnected on a portion of the separation pattern corresponding to the semi-transmissive region.

18. The method according to claim 17, wherein the separation pattern includes: a first pattern portion protruding from the upper surface of the pixel defining layer to a first height; a second pattern portion protruding from the upper surface of the pixel defining layer to a second height that is the same as the first height; and A third pattern portion is disposed between the first pattern portion and the second pattern portion and is recessed from the first pattern portion and the second pattern portion toward the upper surface of the pixel defining layer. The first pattern portion and the second pattern portion correspond to the transmissive region, and the third pattern portion corresponds to the semi-transmissive region, and The charge generation layer is disconnected on the third pattern portion.

19. The method according to claim 18, wherein The charge generation layer is disconnected at a position corresponding to the lowest point of the third pattern portion closest to the upper surface of the pixel defining layer.

20. The method according to claim 17, wherein The preliminary separation pattern layer includes a material that cures upon irradiation with light.

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