Display device

Abstract

A display device is provided. The display device includes: a pixel having a transmissive region for transmitting external light and a non-transmissive region for blocking the external light, and including emission regions, a first non-emission region between adjacent emission regions, and a second non-emission region between adjacent transmissive regions; driving scan lines connected to the pixels; sensing scan lines connected to the pixels; and a horizontal voltage line connected to the pixel, in which the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at a first interval in the first non-emission region, and in which the driving scan line, the sensing scan line, and the horizontal voltage line overlap each other in the second non-emission region, or spaced apart from each other by a second interval smaller than the first interval.

Description

Technical Field

[0001] Embodiments of the present disclosure described herein relate to a transparent display device. Background Art

[0002] Among display devices, emissive display devices use light-emitting diodes that generate light through recombination of electrons and holes to display images. Emissive display devices have a high response speed and are driven at low power consumption.

[0003] An emissive display device includes a display panel in which pixels connected to data lines and scan lines are arranged. Generally, each of the pixels includes a light-emitting diode and a pixel circuit unit for controlling the amount of current flowing into the light-emitting diode. The pixel circuit unit controls the amount of current flowing through the light-emitting diode in response to a data signal. At this time, light having a corresponding brightness is generated according to the amount of current flowing through the light-emitting diode.

[0004] An emissive display device can have transmissive characteristics by adopting a transparent display panel. In the transparent display panel, a light-transmitting region may be defined in each pixel to transmit light. Accordingly, a user can not only visually recognize an image displayed through the pixels of the display panel, but also visually recognize an object or an image behind the display panel by the light transmitted through the light-emitting region. Summary of the Invention

[0005] Embodiments of the present disclosure provide a display device having improved transmittance.

[0006] According to one or more embodiments, a display device includes: pixels having a transmissive region configured to transmit external light and a non-transmissive region configured to block external light, the non-transmissive region including an emission region, a first non-emission region between two adjacent emission regions, and a second non-emission region between two adjacent transmissive regions; a driving scan line connected to the pixels and extending in a first direction; a sensing scan line connected to the pixels and extending in the first direction; and a horizontal voltage line connected to the pixels and extending in the first direction, wherein in a partial region of the first non-emission region, the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at a first interval in a second direction crossing the first direction, and wherein in the second non-emission region, the driving scan line, the sensing scan line, and the horizontal voltage line are stacked on one another or spaced apart from each other at a second interval smaller than the first interval in the second direction.

[0007] The first non-emission region may include: a first sub-region in which the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at the first interval; and a second sub-region in which the driving scan line, the sensing scan line, and the horizontal voltage line are stacked on one another or spaced apart from each other at the second interval.

[0008] The second sub-region may be between the first sub-region and the second non-emission region.

[0009] The horizontal voltage line may be between the driving scan line and the sensing scan line in the plan view, wherein, in the second non-emission region, when the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at a second interval in a second direction, the separation distance between the driving scan line and the sensing scan line is greater than the width of the horizontal voltage line.

[0010] The horizontal voltage line may be in a different layer from the driving scan line and the sensing scan line.

[0011] The gate pattern layer may include the driving scan line and the sensing scan line, wherein the data pattern layer includes the horizontal voltage line.

[0012] The horizontal voltage line may be between the driving scan line and the sensing scan line in the plan view, wherein, in the second non-emission region, when the driving scan line, the sensing scan line, and the horizontal voltage line are stacked on top of each other, the separation distance between the driving scan line and the sensing scan line is less than the width of the horizontal voltage line.

[0013] The display device may further include: a first voltage line connected to the pixel and extending in a second direction; and a second voltage line connected to the pixel, extending in the second direction, and spaced apart from the first voltage line in a first direction, wherein the horizontal voltage line is connected to the first voltage line or the second voltage line.

[0014] The horizontal voltage line may be between the driving scan line and the sensing scan line in the plan view, wherein the driving scan line includes a first line portion and a second line portion, the first line portion is in the same layer as the horizontal voltage line in the first non-emission region, the second line portion is in a different layer from the horizontal voltage line in the second non-emission region, and wherein the sensing scan line includes a third line portion and a fourth line portion, the third line portion is in the same layer as the horizontal voltage line in the first non-emission region, and the fourth line portion is in a different layer from the horizontal voltage line in the second non-emission region.

[0015] The separation distance between the second line portion and the fourth line portion may be less than the separation distance between the first line portion and the third line portion.

[0016] The first line portion may be connected to the second line portion through a first contact hole, wherein the third line portion is connected to the fourth line portion through a second contact hole.

[0017] The pixel may include: a first sub-pixel configured to output light of a first color; a second sub-pixel configured to output light of a second color; and a third sub-pixel configured to output light of a third color.

[0018] The display device may further include: a first data line connected to the first sub-pixel and extending in a second direction; a second data line connected to the second sub-pixel and extending in the second direction; and a third data line connected to the third sub-pixel and extending in the second direction, wherein the first data line, the second data line, and the third data line are superimposed on the first non-emitting region.

[0019] The first data line, the second data line, and the third data line may be in different layers from the driving scan line, the sensing scan line, and the horizontal voltage line.

[0020] The driving scan line and the horizontal voltage line may be in different layers from the first data line, the second data line, and the third data line, wherein the sensing scan line includes: a third line portion in the same layer as the driving scan line in the first non-emitting region; and a fourth line portion in the same layer as the first data line, the second data line, and the third data line in the second non-emitting region, and wherein the third line portion is connected to the fourth line portion through a second contact hole.

[0021] The fourth line portion of the sensing scan line, the driving scan line, and the horizontal voltage line may be superimposed on each other.

[0022] The display device may further include: a first voltage line connected to the pixel and extending in the second direction; and a second voltage line connected to the pixel, extending in the second direction, and spaced apart from the first voltage line in a first direction, wherein the first voltage line and the second voltage line are in the same layer as the first data line, the second data line, and the third data line.

[0023] The display device may further include: a first connection line connecting the driving scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel; and a second connection line connecting the sensing scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

[0024] The first connection line and the second connection line may be in the same layer as the driving scan line and the sensing scan line, wherein the first connection line and the second connection line are in different layers from the horizontal voltage line.

[0025] According to one or more embodiments, a display device includes: a substrate layer; a buffer layer above the substrate layer; an interlayer insulating layer above the buffer layer; pixels above the substrate layer and having a non-transmissive region for blocking external light and a transmissive region for transmitting external light; a driving scan line connected to the pixels and extending in a first direction; a sensing scan line connected to the pixels and extending in the first direction; a horizontal voltage line connected to the pixels and extending in the first direction; a data line connected to the pixels and extending in a second direction intersecting the first direction; a light-blocking pattern layer above the substrate layer and including the data line; a gate pattern layer above the buffer layer configured to cover the light-blocking pattern layer and including two of the driving scan line, the sensing scan line, or the horizontal voltage line; and a data pattern layer above the interlayer insulating layer configured to cover the gate pattern layer and including the remaining one of the driving scan line, the sensing scan line, or the horizontal voltage line.

[0026] The horizontal voltage line may be between the driving scan line and the sensing scan line in a plan view, wherein a separation distance between the driving scan line and the sensing scan line is greater than a width of the horizontal voltage line in the second direction.

[0027] The horizontal voltage line may be in a different layer from the driving scan line and the sensing scan line.

[0028] The gate pattern layer may include the driving scan line and the sensing scan line, wherein the data pattern layer includes the horizontal voltage line.

[0029] The horizontal voltage line may be between the driving scan line and the sensing scan line in a plan view, wherein a separation distance between the driving scan line and the sensing scan line is less than a width of the horizontal voltage line in the second direction.

[0030] The display device may further include: a first voltage line connected to the pixels and extending in the second direction; and a second voltage line connected to the pixels, extending in the second direction, and spaced apart from the first voltage line in the first direction, wherein the horizontal voltage line is connected to the first voltage line or the second voltage line.

[0031] The pixels may include: a first sub-pixel configured to output light of a first color; a second sub-pixel configured to output light of a second color; and a third sub-pixel configured to output light of a third color.

[0032] The display device may further include: a first data line connected to the first sub-pixel and extending in the second direction; a second data line connected to the second sub-pixel and extending in the second direction; and a third data line connected to the third sub-pixel and extending in the second direction, wherein the first data line, the second data line, and the third data line are superimposed on the non-transmissive region.

[0033] The first data line, the second data line, and the third data line may be in different layers from the driving scan line, the sensing scan line, and the horizontal voltage line.

[0034] The display device may further include: a first voltage line connected to the pixel and extending in a second direction; and a second voltage line connected to the pixel, extending in the second direction, and spaced apart from the first voltage line in a first direction, wherein the first voltage line and the second voltage line are in the same layer as the first data line, the second data line, and the third data line.

[0035] The display device may further include: a first connection line connecting the driving scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel; and a second connection line connecting the sensing scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel, wherein the first connection line and the second connection line are in the same layer as the driving scan line and the sensing scan line, and wherein the first connection line and the second connection line are in different layers from the horizontal voltage line. Description of the Drawings

[0036] The above and other aspects of the present disclosure will become apparent by describing embodiments of the present disclosure in detail with reference to the drawings.

[0037] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure.

[0038] Figure 2 is a schematic cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0039] Figure 3 is a plan view showing a transmissive region and a non-transmissive region in a pixel according to one or more embodiments of the present disclosure.

[0040] Figure 4 is a plan view showing a connection relationship between the first sub-pixel to the third sub-pixel and lines according to one or more embodiments of the present disclosure.

[0041] Figure 5 is a circuit diagram showing the first sub-pixel to the third sub-pixel according to one or more embodiments of the present disclosure.

[0042] Figure 6 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0043] Figure 7 is a plan view showing a layout of pixels according to one or more embodiments of the present disclosure.

[0044] Figure 8A is Figure 7 an enlarged view of part AA of

[0045] Figure 8B is a cross-sectional view taken along the Figure 8A line I-I' shown in

[0046] Figure 8C is of a part AA according to one or more embodiments of the present disclosure Figure 7 and is an enlarged view of part AA

[0047] Figure 8D is a cross-sectional view taken along the Figure 8C line II-II' shown in

[0048] Figure 9A is of a part AA according to one or more embodiments of the present disclosure Figure 7 and is an enlarged view of part AA

[0049] Figure 9B is a cross-sectional view taken along the Figure 9A line III-III' shown in

[0050] Figure 9C is of a part AA according to one or more embodiments of the present disclosure Figure 7 and is an enlarged view of part AA

[0051] Figure 10A is of a part AA according to one or more embodiments of the present disclosure Figure 7 and is an enlarged view of part AA

[0052] Figure 10B is a cross-sectional view taken along the Figure 10A line IV-IV' shown in

[0053] Figures 11A to 11F is a process diagram showing the manufacturing process of a display panel according to one or more embodiments of the present disclosure DETAILED DESCRIPTION

[0054] Aspects of some embodiments of the present disclosure and methods of implementing them can be more easily understood by referring to the detailed description of the embodiments and the accompanying drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, redundant, irrelevant to the description of the embodiments, or unnecessary for those of ordinary skill in the art to fully understand the aspects of the present disclosure, processes, elements, and techniques may be omitted. Unless otherwise noted, the same reference numerals, characters, or combinations thereof represent the same elements throughout the drawings and the written description, and thus, their repeated description may be omitted

[0055] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as limited to the embodiments shown herein. The use of "may", "can", or "may not" in describing the embodiments corresponds to one or more embodiments of the present disclosure.

[0056] Taking the whole of the present disclosure into consideration, those of ordinary skill in the art will understand that the respective suitable features of the various embodiments of the present disclosure can be combined, or partially or wholly combined with each other, and can be technically interlocked and operated in various suitable ways, and unless otherwise stated or implied, each embodiment can be implemented independently of each other or in combination with each other in any suitable way.

[0057] In the drawings, for clarity and / or descriptive purposes, the relative dimensions of elements, layers, and regions may be exaggerated. In other words, since the dimensions and thicknesses of the elements in the drawings are arbitrarily shown for convenience of description, the disclosure is not limited thereto. Additionally, the use of cross-hatching and / or shading in the drawings is generally provided to make the boundaries between adjacent elements clear. Thus, unless stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc.

[0058] Various embodiments are described herein with reference to cross-sectional views that are schematic diagrams of embodiments and / or intermediate structures. Thus, variations in the shapes illustrated due to, for example, manufacturing techniques and / or tolerances are to be expected. In addition, for the purpose of describing embodiments in accordance with the concepts of the present disclosure, the specific structural or functional descriptions disclosed herein are merely illustrative. Accordingly, the embodiments disclosed herein should not be construed as limited to the shapes shown for the elements, layers, or regions, but include shape deviations resulting from, for example, manufacturing.

[0059] For example, an implantation region shown as rectangular will generally have rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0060] For ease of explanation, spatial relative terms such as "under", "below", "lower", "lower side", "beneath", "above", "upper", "upon", "higher", "upper side", "side (e.g., as in "side wall")" etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature. It will be understood that the spatial relative terms are intended to cover different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "under", "below" or "beneath" another element or feature will then be oriented "above" the said other element or feature. Thus, the example terms "under" and "beneath" can cover both an upper and a lower orientation. The device may be otherwise oriented (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first component is described as being disposed "on" a second component, this means that the first component is disposed at the upper side or the lower side (but not limited to its upper side) of the second component based on the direction of gravity.

[0061] In addition, the phrase "in a plan view" means when viewing the object portion from above, and the phrase "in a schematic cross-sectional view" means when viewing a schematic cross-section taken by vertically cutting the object portion from the side. The term "superposed" or its variants means that a first object may be above or below or on one side of a second object, and vice versa. Additionally, the term "superposed" may include laminating, facing or facing towards, extending over, covering or partially covering, or any other suitable term as would be appreciated and understood by those of ordinary skill in the art. The expression "not superposed" may include meanings such as "spaced apart from", "placed beside", "offset from", and any other suitable equivalents as would be appreciated and understood by those of ordinary skill in the art. The terms "facing" and "facing towards" may mean that a first object may be directly or indirectly opposite a second object. In the case where a third object is between the first object and the second object, the first object and the second object may be understood to be indirectly opposite each other although they still face each other.

[0062] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, the element, layer, region or component may be directly formed on, directly on, directly connected to or directly coupled to the other element, layer, region or component, or may be indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to the other element, layer, region or component such that there may be one or more intervening elements, layers, regions or components. Additionally, this may be collectively referred to as direct (or indirect) coupling (or connection) and integral (or non-integral) coupling (or connection). For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, the layer, region or component may be directly electrically connected or directly coupled to the other layer, region and / or component, or there may be one or more intervening layers, regions or components. One or more intervening components may include switches, resistors, capacitors, etc. When describing embodiments, unless explicitly described as a direct connection, the expression of connection refers to an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or directly coupled to another component, or directly on or indirectly on another component without an intervening component.

[0063] In addition, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction, but includes forming the part on a side surface or in a downward direction. Conversely, when a part of a layer, film, region, plate, etc. is formed "under" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is yet another part between the part and the other part. At the same time, other expressions such as "between", "immediately between" or "adjacent to" and "directly adjacent to" describing the relationship between components can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, the element or layer may be the only element or layer between the two elements or layers, or there may also be one or more intervening elements or layers.

[0064] For the purposes of the present disclosure, when a phrase such as "at least one of...", "any one of...", or "one or more of..." follows a list of elements, it modifies the entire list of elements and not individual elements in the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted to mean only X, only Y, only Z, or any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XYY, YZ, and ZZ or any variations thereof). Similarly, the phrase "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any combination and all combinations of one or more of the associated listed items. For example, the phrase "A and / or B" can include A, B, or A and B. Similarly, when phrases such as "at least one of...", "a plurality of...", "one of...", and other prepositional phrases precede (or follow) a list of elements, they modify the entire list of elements and not individual elements in the list. When stating "C to D", unless otherwise specified, it means greater than C and less than D.

[0065] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, and are only used to distinguish one element, member, component, region, zone, layer, section, or part from another element, member, component, region, zone, layer, section, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer, or first section described below may be referred to as a second element, second component, second region, second layer, or second section. Describing an element as a "first" element does not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or groups of elements. For the sake of brevity, the terms "first", "second", etc. may respectively represent "first category (or first group)", "second category (or second group)", etc.

[0066] In an example, the x-direction, y-direction, and / or z-direction are not limited to the directions corresponding to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the x-direction, y-direction, and z-direction can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, second direction, and / or third direction.

[0067] The terms used herein are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, unless the context clearly indicates otherwise, the singular forms "a", "an", and "the" are also intended to include the plural forms, and the plural forms are also intended to include the singular form. It will also be understood that when the terms "comprises", "comprising", "has", "having", and "includes", and variations thereof are used in this specification, it is meant that the stated features, integers, steps, operations, elements, and / or components are present, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0068] When one or more embodiments can be implemented differently, a specific process order can be performed differently from the described order. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described order.

[0069] As used herein, the terms "substantially", "about", "approximate", and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations of measured or calculated values that would be recognized by a person of ordinary skill in the art. For example, "substantially" can include a range of + / - 5% of the corresponding value. As used herein, "about" or "approximate" includes the stated value and means within an acceptable deviation of the specific value as determined by a person of ordinary skill in the art considering the measurement in question and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system). For example, "about" can mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value. Additionally, when describing embodiments of the present disclosure, the use of "may" refers to "one or more embodiments of the present disclosure".

[0070] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by a person of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms (such as those defined in a common dictionary) should be interpreted as having a meaning consistent with their meaning in the context of the relevant art and / or in this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0071] Figure 1 is a perspective view of a display device according to one or more embodiments of the present disclosure, Figure 2 is a schematic cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0072] Refer to Figure 1, the display device DD according to one or more embodiments of the present disclosure can be used not only for large electronic devices (such as televisions, monitors, and billboards), but also for medium and small-sized electronic devices (such as personal computers, laptop computers, personal digital terminals, car navigation units, game consoles, portable electronic devices, and cameras). However, these devices are merely illustrative, and without departing from the spirit and scope of the present disclosure, the display device DD can be used for other electronic devices.

[0073] The display device DD can be a transparent display device. That is, the display device DD can have a high transmittance sufficient to allow an object or background located behind to be visible. Figure 1 An example is shown in which the user's hand UH located behind the display device DD is visually recognized.

[0074] The display device DD can have a display area DA and a non-display area NDA defined therein. The display area DA is the area where the image IM is displayed, and the non-display area NDA is the area adjacent to the display area DA and where the image IM is not displayed. Therefore, the user can visually recognize the image IM displayed in the display area DA. An object or image located behind the display device DD can be visible in the display area DA.

[0075] The border area of the display device DD can be defined by the non-display area NDA. An object or image located behind the display device DD is not visible in the non-display area NDA. The non-display area NDA can surround the display area DA. However, this is illustrative, and the non-display area NDA can be adjacent to only a part of the periphery of the display area DA. Optionally, the non-display area NDA can be omitted. However, the present disclosure is not limited to any of the embodiments.

[0076] Refer to Figure 1 and Figure 2 , the display device DD can include a display panel DP. The display panel DP can be an emissive display panel. For example, the display panel DP can be an organic light-emitting display panel, an inorganic light-emitting display panel, or a quantum dot light-emitting display panel. The emission layer of the organic light-emitting display panel can include an organic light-emitting material. The emission layer of the inorganic light-emitting display panel can include an inorganic light-emitting material. The emission layer of the quantum dot light-emitting display panel can include quantum dots and quantum rods.

[0077] The display panel DP includes a substrate layer BS, a circuit layer DP_CL, and an element layer DP_ED. The display panel DP according to the present disclosure can be a flexible display panel. However, the present disclosure is not limited thereto. For example, the display panel DP can be a foldable display panel foldable about a folding axis, or can be a rigid display panel.

[0078] The substrate layer BS may include a synthetic resin layer. The synthetic resin layer may be a polyimide-based resin layer, and its material is not particularly limited. Additionally, the substrate layer BS may include a glass substrate, a metal substrate, or an organic / inorganic composite substrate.

[0079] The circuit layer DP_CL is located on the substrate layer BS. The circuit layer DP_CL is located between the substrate layer BS and the element layer DP_ED. The circuit layer DP_CL includes at least one insulating layer and circuit elements. Hereinafter, the insulating layer included in the circuit layer DP_CL is referred to as an intermediate insulating layer. The intermediate insulating layer includes at least one intermediate inorganic film and at least one intermediate organic film. The circuit elements may include pixel driving circuits included in each of the plurality of pixels for displaying an image.

[0080] The element layer DP_ED may include light-emitting elements included in each of the pixels. In one or more embodiments of the present disclosure, the light-emitting element may be an organic light-emitting diode. The light-emitting elements are arranged to correspond to the emission regions EA. Accordingly, the display panel DP may display an image through the plurality of emission regions EA. Additionally, the display panel DP may transmit external light through the transmission region TA. Accordingly, the display panel DP may use the light generated from the emission regions EA to display an image and may allow an object or background located behind to be visible through the transmission region TA.

[0081] A non-transmission region NTA (refer to Figure 3 ) in which various elements and lines are provided and thus the transmittance of external light is extremely low or external light hardly transmits may be defined in the display panel DP. The emission regions EA may be included in the non-transmission region NTA. Since various elements and lines are not provided in the transmission region TA, the transmission region TA may have a relatively high transmittance of external light. When the area occupied by the transmission region TA in the display panel DP increases, the transmittance of external light may be increased.

[0082] The display panel DP may further include a packaging layer that seals the element layer DP_ED. The packaging layer may include at least one organic film and at least one inorganic film. The inorganic film may include an inorganic material and may protect the element layer DP_ED from the effects of moisture / oxygen. The inorganic film may include a silicon nitride layer, a silicon oxynitride layer, a silicon oxide layer, a titanium oxide layer, or an aluminum oxide layer, but is not particularly limited thereto. The organic film may include an organic material and may protect the element layer DP_ED from foreign substances such as dust particles.

[0083] Figure 3 is a plan view showing a transmission region and a non-transmission region in a pixel according to one or more embodiments of the present disclosure.

[0084] Refer to Figure 3, the display panel DP may include a plurality of pixels PX. The plurality of pixels PX may have the same structure. Each of the plurality of pixels PX may include a non-transmissive region NTA and a transmissive region TA. The non-transmissive region NTA may be formed (e.g., in a plan view) to surround the transmissive region TA. In one or more embodiments of the present disclosure, the non-transmissive region NTA may include an emission region EA and a non-emission region NEA. The non-emission region NEA may surround (e.g., in a plan view) the emission region EA and the transmissive region TA.

[0085] Among the plurality of pixels PX, Figure 3 two adjacent pixels PX are shown. Each of the pixels PX may include a plurality of sub-pixels. The emission region EA includes a plurality of emission regions EA1, EA2, and EA3 corresponding to the plurality of sub-pixels, respectively.

[0086] In one or more embodiments of the present disclosure, each pixel PX may include a first sub-pixel that outputs a first color light R (or red light), a second sub-pixel that outputs a second color light G (or green light), and a third sub-pixel that outputs a third color light B (or blue light). The first emission region EA1 is defined in the first sub-pixel, the second emission region EA2 is defined in the second sub-pixel, and the third emission region EA3 is defined in the third sub-pixel. At least one of the first sub-pixel to the third sub-pixel may have a different size from the remaining sub-pixels. For example, the third sub-pixel may have a size larger than the sizes of the first sub-pixel and the second sub-pixel. In this case, the third emission region EA3 corresponding to the third sub-pixel may have a size larger than the sizes of the first emission region EA1 and the second emission region EA2 corresponding to the first sub-pixel and the second sub-pixel, respectively. Optionally, the first sub-pixel to the third sub-pixel may have the same size.

[0087] The transmissive region TA may have a size larger than the sum of the sizes of the first sub-pixel to the third sub-pixel. However, this is not limited thereto, and the size of the transmissive region TA may vary according to the desired transmittance of the display device DD.

[0088] Although Figure 3 a structure in which each pixel PX has one transmissive region TA is shown, the present disclosure is not limited thereto. That is, each pixel PX may have a plurality of transmissive regions TA. For example, each pixel PX may include three transmissive regions adjacent to the first sub-pixel to the third sub-pixel, respectively.

[0089] Although Figure 3A structure is shown in which each of the emission regions EA1 to EA3 has a quadrilateral shape defined in a first direction DR1 and a second direction DR2, but the shape of the emission regions EA1 to EA3 is not limited thereto. For example, each of the emission regions EA1 to EA3 may have a rhombus shape. Although the transmission region TA is also shown as having a quadrilateral shape defined in the first direction DR1 and the second direction DR2, the shape of the transmission region TA may vary according to the shape of the emission regions EA1 to EA3.

[0090] Figure 4 is a plan view showing the connection relationship between the first sub-pixel to the third sub-pixel and the lines according to one or more embodiments of the present disclosure. Figure 5 is a circuit diagram showing the first sub-pixel to the third sub-pixel according to one or more embodiments of the present disclosure.

[0091] Referring to Figure 4 and Figure 5 , each pixel PX includes a first sub-pixel SPX1, a second sub-pixel SPX2, and a third sub-pixel SPX3. The first sub-pixel SPX1 includes a first pixel circuit SPC1 and a first light-emitting element ED1, the second sub-pixel SPX2 includes a second pixel circuit SPC2 and a second light-emitting element ED2, and the third sub-pixel SPX3 includes a third pixel circuit SPC3 and a third light-emitting element ED3. In one or more embodiments of the present disclosure, the first pixel circuit SPC1 to the third pixel circuit SPC3 may have the same circuit configuration.

[0092] Each pixel PX may be connected to two scan lines (hereinafter referred to as the j-th driving scan line SCLj and the j-th sensing scan line SSLj), three data lines (hereinafter referred to as the i-th data line DLi, the i + 1-th data line DLi+1, and the i + 2-th data line DLi+2), a first driving voltage line (or referred to as the first voltage line) VL1 and a second driving voltage line (or referred to as the second voltage line) VL2, and an initialization voltage line VIL. Here, j and i are integers greater than or equal to 1.

[0093] The j-th driving scan line SCLj and the j-th sensing scan line SSLj may extend in a first direction DR1, the i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2 may extend in a second direction DR2, and may intersect with the j-th driving scan line SCLj and the j-th sensing scan line SSLj. The first driving voltage line VL1, the second driving voltage line VL2, and the initialization voltage line VIL may extend in the second direction DR2, and may be spaced apart from the i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2 in the first direction DR1. The first driving voltage line VL1, the second driving voltage line VL2, and the initialization voltage line VIL may intersect with the j-th driving scan line SCLj and the j-th sensing scan line SSLj.

[0094] When viewed from above the plane, the j-th driving scan line SCLj and the j-th sensing scan line SSLj may be located at the lower side and the upper side of the pixel PX, respectively. The j-th driving scan line SCLj is commonly connected to the first pixel circuit SPC1, the second pixel circuit SPC2, and the third pixel circuit SPC3 through a first connection line CCL1, and the j-th sensing scan line SSLj is commonly connected to the first pixel circuit SPC1, the second pixel circuit SPC2, and the third pixel circuit SPC3 through a second connection line CCL2.

[0095] The i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2 may be connected to the first pixel circuit SPC1, the second pixel circuit SPC2, and the third pixel circuit SPC3, respectively. That is, the i-th data line DLi is connected to the first pixel circuit SPC1, the (i + 1)-th data line DLi+1 is connected to the second pixel circuit SPC2, and the (i + 2)-th data line DLi+2 is connected to the third pixel circuit SPC3. The i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2 may be respectively referred to as the first data line, the second data line, and the third data line.

[0096] The (j - 1)-th horizontal voltage line HVLj-1 is located between the (j - 1)-th driving scan line SCLj-1 and the j-th sensing scan line SSLj, and the j-th horizontal voltage line HVLj is located between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1. Each of the (j - 1)-th horizontal voltage line HVLj-1 and the j-th horizontal voltage line HVLj extends in a first direction DR1. In one or more embodiments of the present disclosure, the (j - 1)-th horizontal voltage line HVLj-1 may be connected to a first driving voltage line VL1, and the j-th horizontal voltage line HVLj may be connected to a second driving voltage line VL2. Accordingly, the (j - 1)-th horizontal voltage line HVLj-1 may serve as the first driving voltage line VL1, and the j-th horizontal voltage line HVLj may serve as the second driving voltage line VL2.

[0097] Each of the first pixel circuit SPC1 to the third pixel circuit SPC3 may include three transistors and one capacitor. Each of the first pixel circuit SPC1 to the third pixel circuit SPC3 includes a first transistor T1, a second transistor T2, and a third transistor T3, and a capacitor Cst. At least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be an oxide transistor having an oxide semiconductor layer. Each of the first transistor T1, the second transistor T2, and the third transistor T3 may be an N-type transistor. However, the present disclosure is not limited thereto. For example, each of the first transistor T1, the second transistor T2, and the third transistor T3 may be a P-type transistor. Alternatively, one or more of the first transistor T1, the second transistor T2, and the third transistor T3 may be N-type transistors, and the other transistors may be P-type transistors. Additionally, at least one of the first transistor T1, the second transistor T2, and the third transistor T3 may be a transistor having a low temperature polycrystalline silicon (LTPS) semiconductor layer.

[0098] The first transistor T1 is connected between the first driving voltage line VL1 that receives the first driving voltage ELVDD and one of the first light-emitting element ED1, the second light-emitting element ED2, and the third light-emitting element ED3 (hereinafter referred to as the corresponding light-emitting element). The first transistor T1 includes a first electrode connected to the first driving voltage line VL1, a second electrode electrically connected to the anode of the corresponding light-emitting element, and a third electrode connected to one end of the capacitor Cst. Here, the contact point where the anode of the corresponding light-emitting element is connected to the second electrode of the first transistor T1 may be referred to as the first node N1. As used herein, the expression "a transistor is connected to a signal line" means that one of the first to third electrodes of the transistor has a shape of a single body with the signal line or is formed integrally with the signal line, or is connected to the signal line through a connecting electrode. Additionally, as used herein, the expression "one transistor is electrically connected to another transistor" means that one of the first to third electrodes of one transistor has a shape of a single body with one of the first to third electrodes of the other transistor or is integral with one of the first to third electrodes of the other transistor, or is connected to one of the first to third electrodes of the other transistor through a connecting electrode.

[0099] The first transistor T1 can receive the data voltage transmitted according to the switching operation of the second transistor T2 from at least one of the i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2 (hereinafter referred to as the corresponding data line), and can supply a driving current to the corresponding light-emitting element.

[0100] The second transistor T2 is connected between the corresponding data line and the third electrode of the first transistor T1. The second transistor T2 includes a first electrode connected to the corresponding data line, a second electrode connected to the third electrode of the first transistor T1, and a third electrode connected to the j-th driving scan line SCLj. Here, the contact point where the second electrode of the second transistor T2 is connected to the third electrode of the first transistor T1 may be referred to as the second node N2. The second transistor T2 can be turned on according to the j-th driving scan signal transmitted through the j-th driving scan line SCLj, and can transmit the data voltage transmitted from the corresponding data line to the third electrode of the first transistor T1.

[0101] The third transistor T3 is connected between the second electrode of the first transistor T1 and the initialization voltage line VIL. The third transistor T3 includes a first electrode connected to the first node N1, a second electrode connected to the initialization voltage line VIL, and a third electrode connected to the j-th sensing scan line SSLj. The third transistor T3 can be turned on according to the j-th sensing scan signal transmitted through the j-th sensing scan line SSLj, and can electrically connect the initialization voltage line VIL and the first node N1.

[0102] One end of the capacitor Cst is connected to the second node N2, and the opposite end of the capacitor Cst is connected to the first node N1. The cathode of the corresponding light-emitting element may be connected to the second driving voltage line VL2 that transmits the second driving voltage ELVSS. The second driving voltage ELVSS may have a voltage level lower than the voltage level of the first driving voltage ELVDD.

[0103] The configurations of the first pixel circuit SPC1 to the third pixel circuit SPC3 according to the present disclosure are not limited to the embodiments corresponding to Figure 5 The first pixel circuit SPC1 to the third pixel circuit SPC3 shown in Figure 5 are merely illustrative, and various changes and modifications can be made to the configurations of the first pixel circuit SPC1 to the third pixel circuit SPC3. For example, the third transistor T3 can be omitted from each of the first pixel circuit SPC1 to the third pixel circuit SPC3.

[0104] Each of the first light-emitting element ED1 to the third light-emitting element ED3 may include an anode connected to the second electrode (or the first node N1) of the first transistor T1 and a cathode that receives the second driving voltage ELVSS. Each of the first light-emitting element ED1 to the third light-emitting element ED3 may generate light corresponding to the amount of current supplied from the first transistor T1.

[0105] The j-th driving scan line SCLj and the j-th sensing scan line SSLj are located in the non-transmissive region NTA and do not overlap with the transmissive region TA. The i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2 are located in the non-transmissive region NTA and do not overlap with the transmissive region TA.

[0106] As described above, the signal lines SSLj, SCLj, DLi, DLi+1, and DLi+2 are positioned so as not to pass through the transmissive region TA and not to overlap with the transmissive region TA. Therefore, the possibility of the following phenomenon can be reduced or prevented: external light incident on the transmissive region TA is reflected by the signal lines SSLj, SCLj, DLi, DLi+1, and DLi+2, resulting in deterioration of the transmittance of the display panel DP. Therefore, the user can clearly identify an object or an image located behind the display panel DP.

[0107] Figure 6 is a cross-sectional view of a display panel according to one or more embodiments of the present disclosure.

[0108] Referring to Figure 4 and Figure 6 , the light-blocking pattern layer BML (refer to Figure 11A)(is) located on the upper surface of the substrate layer BS. In one or more embodiments of the present disclosure, the light blocking pattern layer BML may include a shielding electrode BSE, data lines (i.e., the i-th data line DLi, the (i + 1)-th data line DLi+1, and the (i + 2)-th data line DLi+2), a first driving voltage line VL1, a second driving voltage line VL2, and an initialization voltage line VIL. The shielding electrode BSE may be positioned in the form of an island. Additionally, the shielding electrode BSE may be electrically connected to one of the first driving voltage line VL1, the second driving voltage line VL2, and the initialization voltage line VIL.

[0109] A buffer layer BFL is located on the substrate layer BS to cover the light blocking pattern layer BML (as used herein, "located on" may mean "above"). The buffer layer BFL may include a silicon oxide layer or a silicon nitride layer. Optionally, the buffer layer BFL may have a structure in which the silicon oxide layer and the silicon nitride layer are stacked alternately with each other.

[0110] A semiconductor pattern OSL is located on the buffer layer BFL. The semiconductor pattern OSL may correspond to one of a plurality of patterns of a semiconductor layer located on the buffer layer BFL. When viewed from above the plane, the semiconductor pattern OSL may be superimposed on the shielding electrode BSE. Thus, the shielding electrode BSE may block light so that light is not provided toward the semiconductor pattern OSL.

[0111] The semiconductor pattern OSL may include a metal oxide. The metal oxide semiconductor may include a crystalline or amorphous oxide semiconductor. For example, the oxide semiconductor may include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Optionally, the oxide semiconductor may include a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and its oxide. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), or zinc tin oxide (ZTO).

[0112] The semiconductor pattern OSL may include a plurality of regions distinguished according to whether the metal oxide included in the semiconductor pattern OSL is reduced. The region where the metal oxide is reduced (hereinafter, referred to as the reduced region) has a higher conductivity than the region where the metal oxide is not reduced (hereinafter, referred to as the non-reduced region). The reduced region basically serves as the source / drain of a transistor or a signal line. The non-reduced region basically corresponds to the semiconductor region (or channel region) of the transistor. In other words, a part of the semiconductor pattern may be the channel region of the transistor, and another part of the semiconductor pattern may be the source region or the drain region of the transistor.

[0113] The gate insulating pattern GIL is located on the semiconductor pattern OSL or the buffer layer BFL. A part of the gate insulating pattern GIL may overlap with the channel region. The gate insulating pattern GIL does not need to be completely formed on the substrate layer BS, but may be formed to overlap only with the corresponding conductive pattern layer (for example, the gate pattern layer GAT (see Figure 11C )) described below. However, the present disclosure is not limited thereto, and in one or more embodiments of the present disclosure, the gate insulating pattern GIL may completely overlap with the substrate layer BS.

[0114] The gate pattern layer GAT (refer to Figure 11C ) may be located on the gate insulating pattern GIL. The gate pattern layer GAT may include third electrodes (or gates) GE of each of the first transistor T1 to the third transistor T3 (refer to Figure 5 ) and the first connection line CCL1 and the second connection line CCL2. In one or more embodiments of the present disclosure, the gate pattern layer GAT may further include the j-th driving scan line SCLj and the j-th sensing scan line SSLj.

[0115] The interlayer insulating layer ILD is located on the buffer layer BFL to cover the gate pattern layer GAT. The data pattern layer SD (refer to Figure 11D ) may be located on the interlayer insulating layer ILD. The data pattern layer SD may include the first connection electrode CCE1 and the second connection electrode CCE2, the (j - 1)-th horizontal voltage line HVLj - 1, and the j-th horizontal voltage line HVLj. The first connection electrode CCE1 and the second connection electrode CCE2 may be connected to the source region and the drain region of the semiconductor pattern OSL through contact holes penetrating the interlayer insulating layer ILD, respectively. However, the embodiments are not limited thereto, and the gate pattern layer GAT may include two of the driving scan lines (for example, the (j - 1)-th driving scan line SCLj - 1 and the j-th driving scan line SCLj), the sensing scan lines (for example, the j-th sensing scan line SSLj and the (j + 1)-th sensing scan line SSLj + 1), and the horizontal voltage lines (for example, the (j - 1)-th horizontal voltage line HVLj - 1 and the j-th horizontal voltage line HVLj), and the data pattern layer SD may include the remaining one of them.

[0116] The protective layer PVX is located on the interlayer insulating layer ILD to cover the data pattern layer SD. The via layer VIA may be located on the protective layer PVX. Anodes AE of each of the light-emitting elements ED1, ED2, and ED3 may be located on the via layer VIA. The anode AE may be connected to the second connection electrode CCE2 through contact holes penetrating the via layer VIA and the protective layer PVX. Here, the second connection electrode CCE2 may be a connection electrode connected to the drain region of the first transistor T1.

[0117] The pixel defining layer PDL may be located on the via layer VIA and may cover a part of the anode AE. An opening PDL_OP is defined in the pixel defining layer PDL. The opening PDL_OP of the pixel defining layer PDL exposes at least a part of the anode AE.

[0118] The emission layer may be located on the anode AE. The emission layer may be located in a region corresponding to the opening PDL_OP. That is, the emission layer may be formed separately for each of the sub-pixels. When the emission layer is formed separately for each of the pixels, the emission layers may each emit at least one of blue light, red light, and green light. However, not limited thereto, the emission layers may be connected together to have an integral / one-body shape and may be provided commonly for a plurality of pixels. In this case, the emission layer provided in the shape of one body may provide blue light or white light.

[0119] The cathode may be located on the emission layer. The cathode may have a one-body shape and may be positioned commonly for a plurality of pixels.

[0120] Figure 7 is a plan view showing the layout of pixels according to one or more embodiments of the present disclosure. Figure 8A is Figure 7 an enlarged view of part AA of Figure 8B is a cross-sectional view taken along the line I-I' shown in Figure 8A

[0121] Referring to Figure 4 , Figure 6 , Figure 7 and Figure 8A , each of the plurality of pixels PX may include a non-transmissive region NTA and a transmissive region TA. The non-transmissive region NTA may be formed to surround the transmissive region TA. In one or more embodiments of the present disclosure, the non-transmissive region NTA may include an emission region EA and a non-emission region NEA. The non-emission region NEA may surround (e.g., in a plan view) the emission region EA and the transmissive region TA. In one or more embodiments of the present disclosure, the non-emission region NEA may include a first non-emission region (or first region) A1 and a second non-emission region (or second region) A2. The first non-emission region A1 is a region located between two emission regions EA adjacent to each other in the second direction DR2, and the second non-emission region A2 is a region located between two transmissive regions TA adjacent to each other in the second direction DR2. The first data line DLi, the second data line DLi+1, and the third data line DLi+2 may be superimposed on the first non-emission region A1.

[0122] In a partial region of the first non-emission region A1, the (j-1)-th driving scan line SCLj-1, the j-th sensing scan line SSLj, and the (j-1)-th horizontal voltage line HVLj-1 are spaced apart from each other in the second direction DR2 by a first interval d1. In the second non-emission region A2, the (j-1)-th driving scan line SCLj-1, the j-th sensing scan line SSLj, and the (j-1)-th horizontal voltage line HVLj-1 are spaced apart from each other in the second direction DR2 by a second interval d2. Here, the second interval d2 is smaller than the first interval d1.

[0123] Similarly, in a partial region of the first non-emission region A1, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj are spaced apart from each other in the second direction DR2 by a first interval d1. In the second non-emission region A2, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj are spaced apart from each other in the second direction DR2 by a second interval d2. Here, the second interval d2 is smaller than the first interval d1.

[0124] The first non-emission region A1 may include a first sub-region SA1 and a second sub-region SA2. The first sub-region SA1 is a region where the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj are spaced apart from each other by a first interval d1. The second sub-region SA2 is a region where the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj are spaced apart from each other by a second interval d2. However, this is not limited thereto. In the second sub-region SA2, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj may also overlap each other. In one or more embodiments of the present disclosure, the second sub-region SA2 may be located between the first sub-region SA1 and the second non-emission region A2.

[0125] As Figure 8B shown, the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 are located on the buffer layer BFL, and the j-th horizontal voltage line HVLj is located on the interlayer insulating layer ILD. However, the present disclosure is not limited thereto. The j-th horizontal voltage line HVLj may be located on the buffer layer BFL, and the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 may be located on the interlayer insulating layer ILD.

[0126] The j-th horizontal voltage line HVLj may be located (e.g., in a plan view) between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1. A separation distance ds1 between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 (i.e., a separation distance in the second direction DR2) may be greater than a width w1 of the j-th horizontal voltage line HVLj in the second direction DR2. Accordingly, when viewed from above the plane, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj do not overlap with each other (hereinafter, referred to as a "non-overlapping structure"). However, the present disclosure is not limited thereto. For example, when viewed from above the plane, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj may overlap with each other (hereinafter, referred to as having an "overlapping structure").

[0127] Figure 8C is according to one or more embodiments of the present disclosure Figure 7 an enlarged view of portion AA of Figure 8D is a cross-sectional view taken along line II-II' shown in Figure 8C

[0128] Referring to Figure 8C and Figure 8D , in the second non-emission region A2, when viewed from above the plane, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj may overlap with each other. In contrast, in the first non-emission region A1, when viewed from above the plane, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj do not overlap with each other.

[0129] The j-th horizontal voltage line HVLj may be located (e.g., in a plan view) between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1. A separation distance ds2 between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 (i.e., a separation distance in the second direction DR2) may be less than a width w1 of the j-th horizontal voltage line HVLj in the second direction DR2. Accordingly, when viewed from above the plane, the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj may overlap with each other.

[0130] When the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 overlap with the j-th horizontal voltage line HVLj, an area of the transmissive region TA may be greater than an area of the transmissive region TA in the case of the non-overlapping structure, and thus, a transmittance of the display device DD may be improved.

[0131] ​When the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 and the j-th horizontal voltage line HVLj are in different layers, the intervals between the signal lines SCLj, HVLj, and SSLj+1 can be reduced, or the signal lines SCLj, HVLj, and SSLj+1 can be positioned to overlap each other. Accordingly, the area occupied by the signal lines SCLj, HVLj, and SSLj+1 in the display panel DP can be reduced. Accordingly, the area of the transmissive region TA can be increased, and the transmittance of the display panel DP can be improved.

[0132] Figure 9A is an enlarged view of a partial AA of Figure 7 according to one or more embodiments of the present disclosure. Figure 9B is a cross-sectional view taken along line III-III' shown in Figure 9A . Figure 9C is an enlarged view of a partial AA of Figure 7 according to one or more embodiments of the present disclosure.

[0133] Referring to Figure 9A and Figure 9B , the j-th driving scan line SCLj, the (j + 1)-th sensing scan line SSLj+1, and the j-th horizontal voltage line HVLj extend in a first direction DR1 and are spaced apart from each other in a second direction DR2. In one or more embodiments of the present disclosure, the j-th horizontal voltage line HVLj is located between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1.

[0134] The j-th driving scan line SCLj includes a first line portion SCL_LP1 and a second line portion SCL_LP2. The first line portion SCL_LP1 overlaps with a first non-emission region A1 and is positioned in the same layer as the layer in which the j-th horizontal voltage line HVLj is positioned. The second line portion SCL_LP2 overlaps with a second non-emission region A2 and is positioned in a layer different from the layer in which the j-th horizontal voltage line HVLj is positioned. The first line portion SCL_LP1 and the second line portion SCL_LP2 may be connected through a first contact hole CNT1. In one or more embodiments of the present disclosure, the first line portion SCL_LP1 may be located on an interlayer insulating layer ILD, the second line portion SCL_LP2 may be located on a buffer layer BFL, and the first line portion SCL_LP1 and the second line portion SCL_LP2 may be connected through a first contact hole CNT1 formed through the interlayer insulating layer ILD.

[0135] The (j + 1)-th sensing scan line SSLj+1 includes a third line portion SSL_LP3 and a fourth line portion SSL_LP4. The third line portion SSL_LP3 overlaps with the first non-emission region A1 and is positioned in the same layer as the layer where the j-th horizontal voltage line HVLj is positioned. The fourth line portion SSL_LP4 overlaps with the second non-emission region A2 and is positioned in a layer different from the layer where the j-th horizontal voltage line HVLj is positioned. The third line portion SSL_LP3 and the fourth line portion SSL_LP4 can be connected through a second contact hole CNT2. In one or more embodiments of the present disclosure, the third line portion SSL_LP3 can be located on the interlayer insulating layer ILD, the fourth line portion SSL_LP4 can be located on the buffer layer BFL, and the third line portion SSL_LP3 and the fourth line portion SSL_LP4 can be connected through the second contact hole CNT2 formed by penetrating the interlayer insulating layer ILD.

[0136] In the first non-emission region A1, the first line portion SCL_LP1 and the third line portion SSL_LP3 are spaced apart from each other in the second direction DR2 by a third interval. In the second non-emission region A2, the second line portion SCL_LP2 and the fourth line portion SSL_LP4 are spaced apart from each other in the second direction DR2 by a fourth interval. Here, the fourth interval is smaller than the third interval.

[0137] In Figure 9B is shown a structure in which the first line portion SCL_LP1 is located on the interlayer insulating layer ILD and the second line portion SCL_LP2 is located on the buffer layer BFL. However, the present disclosure is not limited thereto. For example, the first line portion SCL_LP1 and the third line portion SSL_LP3 can be located on the buffer layer BFL, and the second line portion SCL_LP2 and the fourth line portion SSL_LP4 can be located on the interlayer insulating layer ILD.

[0138] In addition, in Figure 9A is shown a structure in which the j-th horizontal voltage line HVLj does not overlap with the second line portion SCL_LP2 and the fourth line portion SSL_LP4 when viewed from above the plane. However, the present disclosure is not limited thereto. For example, when viewed from above the plane, the j-th horizontal voltage line HVLj can overlap with the second line portion SCL_LP2 and the fourth line portion SSL_LP4.

[0139] Referring to Figure 9C , in the second non-emission region A2, when viewed from above the plane, the j-th horizontal voltage line HVLj can overlap with the second line portion SCL_LP2 and the fourth line portion SSL_LP4. On the contrary, in the first non-emission region A1, when viewed from above the plane, the j-th horizontal voltage line HVLj does not overlap with the first line portion SCL_LP1 and the third line portion SSL_LP3.

[0140] The separation distance between the second line portion SCL_LP2 and the fourth line portion SSL_LP4 (i.e., the separation distance in the second direction DR2) can be less than the width w1 of the j-th horizontal voltage line HVLj in the second direction DR2 (see Figure 8B ). When the second line portion SCL_LP2 and the fourth line portion SSL_LP4 are superimposed on the j-th horizontal voltage line HVLj, the area of the transmission region TA can be greater than the area of the transmission region TA in the case of a non-superimposed structure, and thus the transmittance of the display device DD can be improved.

[0141] Figure 10A is an enlarged view of a part AA according to one or more embodiments of the present disclosure Figure 7 and Figure 10B is a cross-sectional view taken along the line IV-IV' shown in Figure 10A .

[0142] Referring to Figure 10A and Figure 10B , the j-th horizontal voltage line HVLj is located between the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1. The j-th horizontal voltage line HVLj is positioned in a layer different from the layers in which the j-th driving scan line SCLj and the (j + 1)-th sensing scan line SSLj+1 are positioned.

[0143] In one or more embodiments of the present disclosure, the j-th driving scan line SCLj is located on the buffer layer BFL, and the j-th horizontal voltage line HVLj is located on the interlayer insulating layer ILD. The (j + 1)-th sensing scan line SSLj+1 includes a third line portion SSL_LP3a and a fourth line portion SSL_LP4a. The third line portion SSL_LP3a is superimposed on the first non-emission region A1 and is positioned in the same layer as the layer in which the j-th driving scan line SCLj is positioned (e.g., located on the buffer layer BFL). The fourth line portion SSL_LP4a is superimposed on the second non-emission region A2 and is positioned in a layer different from the layers in which the j-th driving scan line SCLj and the j-th horizontal voltage line HVLj are positioned. In one or more embodiments of the present disclosure, the fourth line portion SSL_LP4a can be located on the substrate layer BS. The fourth line portion SSL_LP4a and the first data line DLi, the second data line DLi+1, and the third data line DLi+2 can be located in the same layer.

[0144] The third line portion SSL_LP3a and the fourth line portion SSL_LP4a can be connected through the second contact hole CNT2a. In one or more embodiments of the present disclosure, the third line portion SSL_LP3a and the fourth line portion SSL_LP4a can be connected through the second contact hole CNT2a formed by passing through the buffer layer BFL.

[0145] When viewed from above the plane, the fourth line portion SSL_LP4a can be completely superimposed on the j-th driving scan line SCLj and the j-th horizontal voltage line HVLj. Therefore, when the fourth line portion SSL_LP4a, the j-th driving scan line SCLj, and the j-th horizontal voltage line HVLj are located in different layers, the three signal lines SCLj, HVLj, and SSLj+1 can be located in an area occupied by one signal line. Therefore, the area of the transmissive region TA can be increased, and the transmittance of the display panel DP can be improved.

[0146] Figures 11A to 11F is a process diagram showing a manufacturing process of a display panel according to one or more embodiments of the present disclosure.

[0147] Referring to Figure 6 and Figure 11A , a light-blocking pattern layer BML is formed on the substrate layer BS. In one or more embodiments of the present disclosure, the light-blocking pattern layer BML may include a conductive material having light-blocking properties. The light-blocking pattern layer BML may include a shielding electrode BSE. The shielding electrode BSE may be superimposed on a semiconductor pattern of at least one of the transistors (i.e., the first transistor T1 to the third transistor T3 (refer to Figure 5 )) included in each of the first pixel circuit SPC1 to the third pixel circuit SPC3.

[0148] The light-blocking pattern layer BML may further include a first data line DLi, a second data line DLi+1, and a third data line DLi+2. The first data line DLi, the second data line DLi+1, and the third data line DLi+2 may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The light-blocking pattern layer BML may include a first vertical voltage line B_VL1, a second vertical voltage line B_VL2, and a first initialization voltage line B_VIL. The first vertical voltage line B_VL1, the second vertical voltage line B_VL2, and the first initialization voltage line B_VIL may extend in the second direction DR2 and may be spaced apart from each other in the first direction DR1. The shielding electrode BSE may be located between the first vertical voltage line B_VL1 and the first data line DLi. The first vertical voltage line B_VL1 may be included in the first voltage line VL1 shown in Figure 4 , the second vertical voltage line B_VL2 may be included in the second voltage line VL2 shown in Figure 4 , and the first initialization voltage line B_VIL may be included in the initialization voltage line VIL shown in Figure 4 .

[0149] Referring to Figure 6 , Figure 11A and Figure 11B, a light-blocking pattern layer BML is covered by a buffer layer BFL, and a semiconductor pattern layer is formed on the buffer layer BFL. The semiconductor pattern layer may include a plurality of semiconductor patterns OSL. Each of the semiconductor patterns OSL may be a semiconductor pattern of at least one of the first transistor T1 to the third transistor T3 (refer to Figure 5 ).

[0150] Each of the semiconductor patterns OSL may include an oxide semiconductor. For example, the oxide semiconductor may include a metal oxide of zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti). Optionally, the oxide semiconductor may include a mixture of a metal such as zinc (Zn), indium (In), gallium (Ga), tin (Sn), or titanium (Ti) and its oxide. The oxide semiconductor may include indium tin oxide (ITO), indium gallium zinc oxide (IGZO), zinc oxide (ZnO), indium zinc oxide (IZO), zinc indium oxide (ZIO), indium oxide (InO), titanium oxide (TiO), indium zinc tin oxide (IZTO), or zinc tin oxide (ZTO).

[0151] Refer to Figure 6 , Figure 11B and Figure 11C , a gate insulating pattern GIL is positioned on the semiconductor pattern OSL or the buffer layer BFL. A part of the gate insulating pattern GIL may overlap with the channel region of the semiconductor pattern OSL.

[0152] A gate pattern layer GAT may be positioned on the gate insulating pattern GIL. The gate pattern layer GAT may include a third electrode (or gate) GE of each of the first transistor T1 to the third transistor T3 (refer to Figure 5 ), a first intermediate voltage line G_VL2, and a first connection line CCL1 and a second connection line CCL2. The first intermediate voltage line G_VL2 and the first connection line CCL1 and the second connection line CCL2 may extend in a second direction DR2. In one or more embodiments of the present disclosure, the gate pattern layer GAT may further include a (j - 1)th driving scan line SCLj - 1, a jth driving scan line SCLj, a jth sensing scan line SSLj, and a (j + 1)th sensing scan line SSLj + 1. The first connection line CCL1 branches from the jth driving scan line SCLj, and the second connection line CCL2 branches from the jth sensing scan line SSLj. When viewed from above the plane, the first intermediate voltage line G_VL2 overlaps with the second vertical voltage line B_VL2. The first intermediate voltage line G_VL2 may be electrically connected to the second vertical voltage line B_VL2 to form a second voltage line VL2 (refer to Figure 4 ).

[0153] Refer to Figure 6 , Figure 11C and Figure 11D, an interlayer insulating layer ILD is positioned on a buffer layer BFL to cover a gate pattern layer GAT. A data pattern layer SD may be positioned on the interlayer insulating layer ILD. The data pattern layer SD may include a connection electrode CCE, a j-1th horizontal voltage line HVLj-1, and a jth horizontal voltage line HVLj. The connection electrode CCE may be connected to source and drain regions of a semiconductor pattern OSL through a contact hole penetrating the interlayer insulating layer ILD. The connection electrode CCE may include Figure 6 a first connection electrode CCE1 and a second connection electrode CCE2 shown in

[0154] . The data pattern layer SD may further include a second intermediate voltage line S_VL1, a third intermediate voltage line S_VL2, and a second initialization voltage line S_VIL. When viewed from above the plane, the second intermediate voltage line S_VL1 overlaps with a first vertical voltage line B_VL1. The second intermediate voltage line S_VL1 may be electrically connected to the first vertical voltage line B_VL1 to form a first voltage line VL1 (refer to Figure 4 ). The third intermediate voltage line S_VL2 may be electrically connected to a second vertical voltage line B_VL2 and a first intermediate voltage line G_VL2 to form a second voltage line VL2 (refer to Figure 4 ). The second initialization voltage line S_VIL may be electrically connected to a first initialization voltage line B_VIL to form an initialization voltage line VIL (refer to Figure 4 ).

[0155] Refer to Figure 6 , Figure 11D and Figure 11E . A protective layer PVX may be positioned on the interlayer insulating layer ILD to cover the data pattern layer SD, and a via layer VIA may be positioned on the protective layer PVX. A first anode AE1, a second anode AE2, and a third anode AE3 of a first light-emitting element ED1, a second light-emitting element ED2, and a third light-emitting element ED3 (refer to Figure 5 ) may be positioned on the via layer VIA. The first anode AE1, the second anode AE2, and the third anode AE3 may be connected to the connection electrode CCE through contact holes penetrating the via layer VIA and the protective layer PVX. The first anode AE1, the second anode AE2, and the third anode AE3 may be spaced apart from each other in a second direction DR2 and may be electrically insulated from each other.

[0156] A cathode connection electrode C_CNE may be positioned on the via layer VIA. The cathode connection electrode C_CNE may be an electrode for electrically connecting a cathode and the second voltage line VL2. In one or more embodiments of the present disclosure, the cathode connection electrode C_CNE may be connected to the third intermediate voltage line S_VL2 through contact holes penetrating the via layer VIA and the protective layer PVX.

[0157] Refer toFigure 6 , Figure 11E and Figure 11F , the pixel defining layer PDL can be positioned on the via layer VIA, and the pixel defining layer PDL can cover a part of each of the first anode AE1, the second anode AE2, and the third anode AE3. The first opening PDL_OP1, the second opening PDL_OP2, and the third opening PDL_OP3 are defined in the pixel defining layer PDL. The first opening PDL_OP1, the second opening PDL_OP2, and the third opening PDL_OP3 of the pixel defining layer PDL expose at least a part of the first anode AE1, the second anode AE2, and the third anode AE3, respectively.

[0158] The pixel defining layer PDL may further include an opening C_OP that exposes a part of the cathode connection electrode C_CNE. The opening C_OP may be a part where a laser drilling process for connecting the cathode and the second voltage line VL2 is performed.

[0159] According to the present disclosure, when the driving scan line and the sensing scan line are positioned in a layer different from the layer in which the horizontal voltage line is positioned, the interval between the signal lines can be reduced, or the signal lines can be positioned to overlap each other. Accordingly, the area occupied by the signal lines in the display panel can be reduced. Accordingly, the area of the transmissive region can be increased, and the transmittance of the display panel can be improved.

[0160] Although the present disclosure has been described with reference to the embodiments of the present disclosure, it will be apparent to those of ordinary skill in the art that various changes and modifications can be made thereto without departing from the spirit and scope of the present disclosure as set forth in the claims and their functional equivalents to be included therein.

Claims

1. A display device, the display device comprising: Pixels, having a transmissive region configured to transmit external light and a non - transmissive region, the non - transmissive region being configured to block external light and including an emission region, a first non - emission region between two adjacent emission regions, and a second non - emission region between two adjacent transmissive regions; A driving scan line, connected to the pixel and extending in a first direction; A sensing scan line, connected to the pixel and extending in the first direction; And A horizontal voltage line, connected to the pixel and extending in the first direction, wherein, in a partial region of the first non - emission region, the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at a first interval in a second direction intersecting the first direction, and wherein, in the second non - emission region, the driving scan line, the sensing scan line, and the horizontal voltage line are stacked on each other or spaced apart from each other at a second interval smaller than the first interval in the second direction.

2. The display device according to claim 1, wherein The first non - emission region includes: A first sub - region, in which the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at the first interval; and A second sub - region, in which the driving scan line, the sensing scan line, and the horizontal voltage line are stacked on each other or spaced apart from each other at the second interval.

3. The display device according to claim 2, wherein, The second sub - region is between the first sub - region and the second non - emission region.

4. The display device according to claim 1, wherein, The horizontal voltage line is between the driving scan line and the sensing scan line in a plan view, and wherein, in the second non - emission region, when the driving scan line, the sensing scan line, and the horizontal voltage line are spaced apart from each other at the second interval in the second direction, the separation distance between the driving scan line and the sensing scan line is greater than the width of the horizontal voltage line.

5. The display device according to claim 4, wherein, The horizontal voltage line is in a different layer from the driving scan line and the sensing scan line.

6. The display device according to claim 5, wherein, A gate pattern layer includes the driving scan line and the sensing scan line, and wherein, a data pattern layer includes the horizontal voltage line.

7. The display device according to claim 1, wherein, The horizontal voltage line is between the driving scan line and the sensing scan line in a plan view, and wherein, in the second non - emission region, when the driving scan line, the sensing scan line, and the horizontal voltage line are stacked on each other, the separation distance between the driving scan line and the sensing scan line is less than the width of the horizontal voltage line.

8. The display device according to claim 1, the display device further comprising: A first voltage line, connected to the pixel and extending in the second direction; And A second voltage line, connected to the pixel, extending in the second direction, and spaced apart from the first voltage line in the first direction, wherein, the horizontal voltage line is connected to the first voltage line or the second voltage line.

9. The display device according to claim 1, wherein, The horizontal voltage line is between the driving scan line and the sensing scan line in a plan view, Wherein, the driving scan line includes a first line portion and a second line portion. The first line portion is in the same layer as the horizontal voltage line in the first non-emission region, and the second line portion is in a different layer from the horizontal voltage line in the second non-emission region, and Wherein, the sensing scan line includes a third line portion and a fourth line portion. The third line portion is in the same layer as the horizontal voltage line in the first non-emission region, and the fourth line portion is in a different layer from the horizontal voltage line in the second non-emission region.

10. The display device according to claim 9, wherein, The separation distance between the second line portion and the fourth line portion is smaller than the separation distance between the first line portion and the third line portion.

11. The display device according to claim 9, wherein, The first line portion is connected to the second line portion through a first contact hole, and Wherein, the third line portion is connected to the fourth line portion through a second contact hole.

12. The display device according to claim 1, wherein, The pixel includes: A first sub-pixel configured to output light of a first color; A second sub-pixel configured to output light of a second color; and A third sub-pixel configured to output light of a third color.

13. The display device according to claim 12, wherein the display device further includes: A first data line connected to the first sub-pixel and extending in the second direction; A second data line connected to the second sub-pixel and extending in the second direction; And A third data line connected to the third sub-pixel and extending in the second direction, Wherein, the first data line, the second data line, and the third data line are stacked with the first non-emission region.

14. The display device according to claim 13, wherein, The first data line, the second data line, and the third data line are in different layers from the driving scan line, the sensing scan line, and the horizontal voltage line.

15. The display device according to claim 13, wherein, The driving scan line and the horizontal voltage line are in different layers from the first data line, the second data line, and the third data line, Wherein, the sensing scan line includes: a third line portion in the same layer as the driving scan line in the first non-emission region; and a fourth line portion in the same layer as the first data line, the second data line, and the third data line in the second non-emission region, and Wherein, the third line portion is connected to the fourth line portion through a second contact hole.

16. The display device according to claim 15, wherein, The fourth line portion of the sensing scan line, the driving scan line, and the horizontal voltage line are stacked with each other.

17. The display device according to claim 13, wherein the display device further includes: A first voltage line connected to the pixel and extending in the second direction; And A second voltage line connected to the pixel, extending in the second direction, and spaced apart from the first voltage line in the first direction, Wherein, the first voltage line and the second voltage line are in the same layer as the first data line, the second data line, and the third data line.

18. The display device according to claim 12, wherein the display device further includes: A first connection line connecting the driving scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel; And A second connection line connects the sensing scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel.

19. The display device according to claim 18, wherein, The first connection line and the second connection line are on the same layer as the driving scan line and the sensing scan line, and wherein the first connection line and the second connection line are on different layers from the horizontal voltage line.

20. A display device, the display device comprising: A substrate layer; A buffer layer above the substrate layer; An interlayer insulating layer above the buffer layer; Pixels above the substrate layer and having a non-transmissive region for blocking external light and a transmissive region for transmitting external light; A driving scan line connected to the pixels and extending in a first direction; A sensing scan line connected to the pixels and extending in the first direction; A horizontal voltage line connected to the pixels and extending in the first direction; A data line connected to the pixels and extending in a second direction intersecting the first direction; A light-blocking pattern layer above the substrate layer and including the data line; A gate pattern layer above the buffer layer, configured to cover the light-blocking pattern layer and including two of the driving scan line, the sensing scan line, and the horizontal voltage line; And A data pattern layer above the interlayer insulating layer, configured to cover the gate pattern layer and including the remaining one of the driving scan line, the sensing scan line, and the horizontal voltage line.

21. The display device according to claim 20, wherein, The horizontal voltage line is between the driving scan line and the sensing scan line in a plan view, and wherein a separation distance between the driving scan line and the sensing scan line is greater than a width of the horizontal voltage line in the second direction.

22. The display device according to claim 21, wherein, The horizontal voltage line is on a different layer from the driving scan line and the sensing scan line.

23. The display device according to claim 22, wherein, The gate pattern layer includes the driving scan line and the sensing scan line, and wherein the data pattern layer includes the horizontal voltage line.

24. The display device according to claim 20, wherein, The horizontal voltage line is between the driving scan line and the sensing scan line in a plan view, and wherein a separation distance between the driving scan line and the sensing scan line is less than a width of the horizontal voltage line in the second direction.

25. The display device according to claim 20, the display device further comprising: A first voltage line connected to the pixels and extending in the second direction; And A second voltage line connected to the pixels, extending in the second direction, and spaced apart from the first voltage line in the first direction, wherein the horizontal voltage line is connected to the first voltage line or the second voltage line.

26. The display device according to claim 20, wherein, The pixel includes: A first sub-pixel configured to output light of a first color; A second sub-pixel configured to output light of a second color; and A third sub-pixel configured to output light of a third color.

27. The display device according to claim 26, the display device further comprising: A first data line connected to the first sub-pixel and extending in the second direction; A second data line connected to the second sub-pixel and extending in the second direction; And A third data line is connected to the third sub-pixel and extends in the second direction. Among them, the first data line, the second data line, and the third data line are superimposed on the non-transmissive region.

28. The display device according to claim 27, wherein, The first data line, the second data line, and the third data line are in different layers from the driving scan line, the sensing scan line, and the horizontal voltage line.

29. The display device according to claim 27, wherein the display device further comprises: A first voltage line is connected to the pixel and extends in the second direction; And A second voltage line is connected to the pixel, extends in the second direction, and is spaced apart from the first voltage line in the first direction. Among them, the first voltage line and the second voltage line are in the same layer as the first data line, the second data line, and the third data line.

30. The display device according to claim 26, wherein the display device further comprises: A first connection line connects the driving scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel; And A second connection line connects the sensing scan line to the first sub-pixel, the second sub-pixel, and the third sub-pixel. Among them, the first connection line and the second connection line are in the same layer as the driving scan line and the sensing scan line, and Among them, the first connection line and the second connection line are in different layers from the horizontal voltage line.

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