Display panel and display device

Abstract

The invention provides a display panel and a display device, relates to the technical field of display, and aims to solve the problem of winding coupling. The display panel comprises a hole area, a winding area and a first display area. A pixel circuit; the data line partially comprises a first wire, a data winding wire and a second wire, and the data winding wire is located in the winding area; the scanning line partially comprises a third wire, a scanning winding wire and a fourth wire which are connected, and the scanning winding wire is located in the winding area; the data line comprises a first data line and a second data line, the first data line and the second data line are electrically connected with different pixel circuits respectively, data signals are written in the first data line and the second data line in a time-sharing manner, a data winding in the first data line is a first winding, and a data winding in the second data line is a second winding; the scanning lines comprise first scanning lines, and scanning winding lines in the first scanning lines are third winding lines; the metal layer where the third winding is located is located between the metal layer where the first winding is located and the metal layer where the second winding is located.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a display panel and a display device. Background Art

[0002] Currently, a display panel can have a hole dug in the screen to achieve a full-screen design. In such a display panel, some signal lines need to be routed in the routing area around the light-transmitting hole. However, there is coupling between the routed lines, which will have an adverse effect on the overall performance of the display panel. Summary of the Invention

[0003] Embodiments of the present invention provide a display panel and a display device for improving the problem of routing coupling.

[0004] In a first aspect, embodiments of the present invention provide a display panel, including: a hole area, a routing area surrounding the hole area, and at least a part of a first display area surrounding the routing area; a pixel circuit, at least located in the first display area; data lines electrically connected to the pixel circuit, a part of the data lines including a connected first trace, a data routing, and a second trace. The first trace and the second trace are located in the first display area and on both sides of the routing area in a first direction, and the data routing is located in the routing area; scan lines electrically connected to the pixel circuit, a part of the scan lines including a connected third trace, a scan routing, and a fourth trace. The third trace and the fourth trace are located in the first display area and on both sides of the routing area in a second direction, and the scan routing is located in the routing area. The second direction intersects with the first direction; wherein, the data lines include a first data line and a second data line, the first data line and the second data line are electrically connected to different pixel circuits and write data signals in a time-division manner. The data routing in the first data line is a first routing, and the data routing in the second data line is a second routing; the scan lines include a first scan line, and the scan routing in the first scan line is a third routing; wherein, the metal layer where the third routing is located is between the metal layer where the first routing is located and the metal layer where the second routing is located.

[0005] In a second aspect, based on the same inventive concept, embodiments of the present invention further provide a display device including the above display panel.

[0006] The technical solutions provided by the embodiments of the present invention have the following beneficial effects: In the technical solution provided by the embodiments of the present invention, when designing the winding in the winding area, the third winding of the first scanning line is spaced between the first winding of the first data line and the second winding of the second data line.

[0007] The pixel circuit performs operations such as reset, bias adjustment, charging, and light emission control under the drive of various scanning signals. However, according to the working principle of the pixel circuit, within one frame time, the level switching of various scanning signals is not frequent. For example, some scanning signals only need to provide an effective level within one frame time, and are in a stable non-enabling level at other times. Therefore, when there is a third winding between the first winding and the second winding, the third winding can act as a shield wire to play an electric field shielding role, thereby reducing the coupling capacitance between the second winding and the first winding. Then, when a data signal is written to the second data line, the influence of the voltage jump on the second winding on the signal on the first winding can be effectively reduced.

[0008] On the other hand, there is at least the metal layer where the third winding is located between the metal layers where the first winding and the second winding are located. This means that the first winding and the second winding are longitudinally separated by a relatively large distance. Increasing the longitudinal distance between the first winding and the second winding can also reduce the coupling capacitance between the second winding and the first winding to a certain extent, thereby reducing the mutual interference between the second winding and the first winding.

[0009] In summary, the embodiments of the present invention can effectively reduce the coupling between the first winding and the second winding. For example, compared with the existing structure, its coupling capacitance can be reduced by more than half, thereby significantly improving the signal interference between the first winding and the second winding and effectively improving the longitudinal split screen phenomenon of the display panel. In addition, the embodiments of the present invention utilize the original third winding in the winding area to act as the shield wire between the first winding and the second winding, without the need to additionally set other shield traces. Therefore, the number of traces in the winding area will not be increased, avoiding increasing the wiring difficulty in the winding area. Description of the Drawings

[0010] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative efforts.

[0011] Figure 1 It is a schematic diagram of an area division of a display panel provided by an embodiment of the present invention; Figure 2 It is a schematic diagram of a structure of a display panel provided by an embodiment of the present invention; Figure 3Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 4 A schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention; Figure 5 Another schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention; Figure 6 Another schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention; Figure 7 Another schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention; Figure 8 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 9 A schematic structural diagram of the pixel circuit 4 provided by the embodiment of the present invention; Figure 10 A timing diagram provided by the embodiment of the present invention; Figure 11 is Figure 10 The timing diagram of some signals in; Figure 12 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 13 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 14 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 15 is Figure 14 A cross-sectional view along the A1 - A2 direction; Figure 16 A schematic structural diagram of the first scan line provided by the embodiment of the present invention; Figure 17 A schematic structural diagram of the second scan line and the third scan line provided by the embodiment of the present invention; Figure 18 Another schematic structural diagram of the display panel provided by the embodiment of the present invention; Figure 19 is Figure 18 A cross-sectional view along the B1 - B2 direction; Figure 20 Another schematic structural diagram of the first scan line, the second scan line and the third scan line provided by the embodiment of the present invention; Figure 21 A schematic structural diagram of the fourth scan line provided by the embodiment of the present invention; Figure 22Another schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention; Figure 23 A schematic structural diagram of the display device provided by the embodiment of the present invention. Detailed implementation manners

[0012] To better understand the technical solution of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0013] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0014] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise.

[0015] It should be understood that the term " / and" used herein is only a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this article generally represents an "or" relationship between the front and rear associated objects.

[0016] Before elaborating on the technical solution provided by the embodiments of the present invention, the present invention first explains the problems existing in the related technologies.

[0017] In the related technology, the display panel can be perforated in the screen, and then optical components such as cameras are arranged at the perforated positions to achieve the purpose of increasing the screen-to-body ratio of the screen.

[0018] In this type of display panel, some data lines need to be disconnected on both sides of the hole, and the two disconnected traces are connected by data winding lines around the hole.

[0019] Currently, the data lines in the display panel generally adopt a gating design. That is, the gating unit is used to control different data lines to write data signals at different times. For example, when driving a row of pixel circuits, first, the first gating switch in the gating unit is turned on, and the source signal line is controlled to write a data signal to the first data line. Then, the first gating switch is turned off, and the second gating switch is turned on, and the source signal line is controlled to write a data signal to the second data line.

[0020] The inventors' research found that in the above process, when the second data line starts to write a data signal, the first data line is in a floating state. Then, when the second data line starts to write a data signal and a voltage jump occurs on the second data line, this voltage jump will couple to the signal on the first data line. For example, when a lower data voltage is written to the second data line, it will also couple and pull down the signal on the first data line, thereby affecting the charging of the pixel circuit connected to the first data line.

[0021] This problem is particularly obvious at the winding position. The data windings at the winding position are arranged more densely, so the voltage jump of the data windings in the second data line has a greater impact on the signal of the data windings in the first data line, which in turn causes obvious color deviation in the display areas on both sides of the hole, resulting in a vertical split screen phenomenon in the display panel.

[0022] In response to this, an embodiment of the present invention provides a display panel, which can effectively improve the above-mentioned vertical split screen problem caused by large data winding coupling.

[0023] As Figure 1 shown, Figure 1 is a schematic diagram of an area division of the display panel provided by an embodiment of the present invention. The display panel includes a hole area 1, a winding area 2, and a first display area 3. Among them, an optical component such as a camera is provided at the position of the hole area 1; the winding area 2 surrounds the hole area 1, for example, it can be a border area; the first display area 3 at least partially surrounds the winding area 2 and is a conventional display area.

[0024] Combined with Figure 1 as Figures 2 to 4 shown, Figure 2 is a schematic structural diagram of the display panel provided by an embodiment of the present invention. Figure 3 is another schematic structural diagram of the display panel provided by an embodiment of the present invention. Figure 4 is a schematic cross-sectional structural diagram of the display panel provided by an embodiment of the present invention. The display panel further includes at least a pixel circuit 4 located in the first display area 3, and a data line D and a scan line S electrically connected to the pixel circuit 4.

[0025] Among them, some data lines D include a connected first trace d1, a data winding d0, and a second trace d2. The first trace d1 and the second trace d2 are located in the first display area 3 and on both sides of the winding area 2 in the first direction x, and the data winding d0 is located in the winding area 2. That is, the first trace d1 and the second trace d2 are the parts of this part of the data line D that are disconnected on both longitudinal sides of the hole area 1, and the first trace d1 and the second trace d2 are connected by the data winding d0.

[0026] The partial scan line S includes a connected third trace s1, a scan winding s0, and a fourth trace s2. The third trace s1 and the fourth trace s2 are located in the first display area 3 and on both sides of the winding area 2 in the second direction y. The scan winding s0 is located in the winding area 2, and the second direction y intersects with the first direction x. That is, the third trace s1 and the fourth trace s2 are the parts of this partial scan line S that are disconnected on both lateral sides of the hole area 1, and the third trace s1 and the fourth trace s2 are connected by the scan winding s0.

[0027] Among them, the data line D includes a first data line D1 and a second data line D2. The first data line D1 and the second data line D2 are respectively electrically connected to different pixel circuits 4 and write data signals in a time-division manner. The data winding d0 in the first data line D1 is the first winding d01, and the data winding d0 in the second data line D2 is the second winding d02.

[0028] The following explains "the first data line D1 and the second data line D2 write data signals in a time-division manner": See Figure 2 , the display panel further includes a plurality of gating units 5. The gating unit 5 includes a first gating switch 6 and a second gating switch 7. Among them, the control terminals of the first gating switches 6 in the plurality of gating units 5 are all electrically connected to a first control line mux1, and the control terminals of the second gating switches 7 in the plurality of gating units 5 are all electrically connected to a second control line mux2. The input terminals of the first gating switch 6 and the second gating switch 7 in the same gating unit 5 are electrically connected to the same source signal line source. The output terminal of one first gating switch 6 is electrically connected to a first data line D1, and the output terminal of one second gating switch 7 is electrically connected to a second data line D2.

[0029] When driving a row of pixel circuits 4, the gating unit 5 controls the source signal line source to write data signals to the first data line D1 and the second data line D2 in a time-division manner. Taking the source signal line source writing data signals to the first data line D1 first as an example, first, the first control line mux1 provides an enabling level (such as a low level) to control the first gating switches 6 in the plurality of gating units 5 to turn on, so that the data signals on the source signal line source are written to the first data line D1. Then, the first control line mux1 controls the first gating switches 6 to turn off, and the first data line D1 floats. The second control line mux2 starts to provide an enabling level (such as a low level) to control the second gating switches 7 in the plurality of gating units 5 to turn on, so that the data signals on the source signal line source are written to the second data line D2.

[0030] In the above process, when the pixel circuit 4 starts to perform a charging operation, the data signals on the first data line D1 are written into the corresponding pixel circuits 4, and the data line D signals on the second data line D2 are written into the corresponding pixel circuits 4.

[0031] The scan line S includes a first scan line S1, and the scan winding s0 in the first scan line S1 is the third winding s01.

[0032] Wherein, the metal layer where the third winding s01 is located is between the metal layer where the first winding d01 is located and the metal layer where the second winding d02 is located.

[0033] In the technical solution provided by the embodiment of the present invention, when designing the windings in the winding area 2, the third winding s01 of the first scan line S1 is spaced between the first winding d01 of the first data line D1 and the second winding d02 of the second data line D2.

[0034] The pixel circuit performs operations such as reset, bias adjustment, charging, and light emission control under the drive of various scan signals. However, according to the working principle of the pixel circuit 4, within one frame time, the level switching of various scan signals is not frequent. For example, some scan signals only need to provide an effective level within one frame time, and are in a stable non-enabled level at other times. Therefore, when the third winding s01 is spaced between the first winding d01 and the second winding d02, the third winding s01 can act as a shield wire to play an electric field shielding role, thereby reducing the coupling capacitance between the second winding d02 and the first winding d01. Then, when a data signal is written to the second data line D2, the influence of the voltage jump on the second winding d02 on the signal on the first winding d01 can be effectively reduced.

[0035] On the other hand, there is at least the metal layer where the third winding s01 is located between the metal layers where the first winding d01 and the second winding d02 are located, which means that the first winding d01 and the second winding d02 are longitudinally separated by a relatively large distance. Increasing the longitudinal distance between the first winding d01 and the second winding d02 can also reduce the coupling capacitance between the second winding d02 and the first winding d01 to a certain extent, thereby reducing the mutual interference between the second winding d02 and the first winding d01.

[0036] In summary, the embodiment of the present invention can effectively reduce the coupling between the first winding d01 and the second winding d02. For example, compared with the existing structure, its coupling capacitance can be reduced by more than half, thereby significantly improving the signal interference between the first winding d01 and the second winding d02, and effectively improving the longitudinal split screen phenomenon of the display panel. In addition, the embodiment of the present invention uses the originally existing third winding s01 in the winding area 2 to act as a shield wire between the first winding d01 and the second winding d02, without additionally setting other shield traces, so the number of traces in the winding area 2 will not be increased, avoiding increasing the wiring difficulty in the winding area 2.

[0037] In a feasible implementation manner, refer to Figure 4, in a direction perpendicular to the plane where the display panel is located: the third winding s01 and the first winding d01 at least partially overlap, and / or the third winding s01 and the second winding d02 at least partially overlap, and / or the third winding s01 and the interval between adjacent first windings d01 at least partially overlap, and / or the third winding s01 and the interval between adjacent second windings d02 at least partially overlap.

[0038] In the above structure, the third winding s01 and the data winding d0 are interspersed. The third winding s01 is dispersedly arranged around each first winding d01 and second winding d02, which can play a stronger shielding role.

[0039] In a feasible implementation manner, refer to Figure 3 and Figure 4 , in a direction perpendicular to the plane where the display panel is located, the first winding d01 and the second winding d02 at least partially overlap, which can compress the wiring width occupied by the overall data winding d0 and help narrow the winding area 2.

[0040] It should be noted that when there is at least a third winding s01 between the first winding d01 and the second winding d02, it means that the metal layers where the first winding d01 and the second winding d02 are located are longitudinally far apart. Coupled with the shielding effect of the third winding s01, even if the first winding d01 and the second winding d02 at least partially overlap, the coupling between the two is still small.

[0041] Furthermore, refer to Figure 3 and Figure 4 , in a direction perpendicular to the plane where the display panel is located, the third winding s01 and the facing area between the first winding d01 and the second winding d02 at least partially overlap.

[0042] The facing area of the first winding d01 and the second winding d02 refers to the overlapping area of the two. In another expression, the first winding d01 includes a first sub - part, the second winding d02 includes a second sub - part. In a direction perpendicular to the plane where the display panel is located, the first sub - part and the second sub - part overlap, and the third winding s01 overlaps with both the first sub - part and the second sub - part at the same time.

[0043] The coupling at the facing position of the first winding d01 and the second winding d02 is slightly larger. Spacing at least a part of the third winding s01 at the facing position of the first winding d01 and the second winding d02 has a better shielding effect and can reduce the signal influence between the second winding d02 and the first winding d01 to a greater extent.

[0044] In a feasible implementation manner, refer to Figure 2, the pixel circuit 4 includes a first pixel circuit 41 electrically connected to a red light-emitting element, a second pixel circuit 42 electrically connected to a green light-emitting element, and a third pixel circuit 43 electrically connected to a blue light-emitting element.

[0045] Among them, the first data line D1 is electrically connected to the first pixel circuit 41 and the third pixel circuit 43, and the second data line D2 is electrically connected to the second pixel circuit 42.

[0046] In a more specific structure, the display panel includes a first circuit column 8 and a second circuit column 9 alternately arranged along the second direction y. Among them, the first circuit column 8 includes the first pixel circuit 41 and the third pixel circuit 43 alternately arranged along the first direction x, and the second circuit column 9 includes a plurality of second pixel circuits 42 arranged along the first direction x. And, in two adjacent first circuit columns 8, the first pixel circuit 41 in one first circuit column 8 and the third pixel circuit 43 in the other first circuit column 8 are aligned and arranged in the second direction y.

[0047] The first data line D1 is electrically connected to the first pixel circuit 41 and the third pixel circuit 43 in the first circuit column 8, and the second data line D2 is electrically connected to the second pixel circuit 42 in the second circuit column 9.

[0048] Generally, the green light-emitting element needs to emit stronger green light to synthesize the required color together with the red light emitted by the red light-emitting element and the blue light emitted by the blue light-emitting element. This requires a higher luminous brightness of the green light-emitting element, and the data voltage required by the second pixel circuit 42 is lower than the data voltages required by the first pixel circuit 41 and the third pixel circuit 43.

[0049] In the related art, when a lower data voltage is written to the second data line D2, the data voltage on the first data line D1 will be pulled down under the coupling effect, and then the data voltages finally written to the first pixel circuit 41 and the third pixel circuit 43 are on the low side, resulting in the display areas on both sides of the hole region 1 being reddish. After adopting the technical solution provided by the embodiment of the present invention, the coupling between the first winding d01 and the second winding d02 becomes lower, and the phenomenon of red bias in the display panel under heavy load can be effectively improved, and the display uniformity is better.

[0050] Furthermore, in the embodiment of the present invention, as Figure 5 shown, Figure 5 is another schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention. The display panel further includes a substrate 10. The metal layer where the second winding d02 is located is on the side away from the substrate 10 of the metal layer where the first winding d01 is located, and a planarization layer 11 is included between the metal layer where the second winding d02 is located and the substrate 10.

[0051] Exemplarily, the display panel includes a first semiconductor layer cl1, a first metal layer m1, a second metal layer mc, a second semiconductor layer cl2, a third metal layer mg, a fourth metal layer sd1, and a fifth metal layer sd2 that are stacked in a direction away from the substrate 10.

[0052] The pixel circuit 4 includes a first transistor T1, a second metal layer T2, and a capacitor Cst. The first transistor T1 is a silicon transistor, such as a low temperature poly silicon (LTPS) transistor, and the second transistor is an oxide transistor, such as an indium gallium zinc oxide (IGZO) transistor.

[0053] Among them, the first semiconductor layer cl1 includes a silicon semiconductor material and includes the active layer ac1 of the first transistor T1; the first metal layer m1 includes the gate g1 of the first transistor T1 and the first electrode plate c1 of the capacitor; the second metal layer mc includes the second electrode plate c2 of the capacitor; the second semiconductor layer cl2 includes an oxide semiconductor material and includes the active layer ac2 of the second transistor T2; the third metal layer mg includes the gate g2 of the second transistor T2; the fourth metal layer includes a connection electrode 12, and part of the connection electrode 12 is connected to the active layer ac1 of the first transistor T1 through a via, and part of the connection electrode 12 is connected to the active layer ac2 of the second transistor T2 through a via.

[0054] An inorganic insulating layer 13 is respectively provided between the first semiconductor layer cl1 and the first metal layer m1, between the first metal layer m1 and the second metal layer mc, between the second metal layer mc and the second semiconductor layer cl2, between the second semiconductor layer cl2 and the third metal layer mg, and between the third metal layer mg and the fourth metal layer sd1, and a planarization layer 11 is provided between the fourth metal layer sd1 and the fifth metal layer sd2.

[0055] In a setting manner, the first winding d01 is located in the third metal layer mg, the third winding s01 is located in the fourth metal layer sd1, and the second winding d02 is located in the fifth metal layer sd2.

[0056] As described above, the second winding d02 is electrically connected to the second pixel circuit 42, and green light contributes more to the brightness. The planarization layer 11 is included between the metal layer where the second winding d02 is located and the substrate 10, which means that the second winding d02 is located in a metal layer farther from the substrate 10, and the metal layer where the second winding d02 is located is higher, so that the coupling between the second winding d02 and the traces in other metal layers below is smaller, and the signal transmission on the second winding d02 is more stable, ensuring the luminous reliability of the green sub-pixels.

[0057] In a feasible implementation manner, asFigure 6 and Figure 7 as shown Figure 6 This is yet another schematic cross-sectional structure diagram of the display panel provided by an embodiment of the present invention Figure 7 This is yet another schematic cross-sectional structure diagram of the display panel provided by an embodiment of the present invention. The first winding d01 includes opposite first side 14 and second side 15, and the second side 15 is located on the side of the first side 14 close to the hole region 1

[0058] The third winding s01 includes opposite third side 16 and fourth side 17, and the fourth side 17 is located on the side of the third side 16 close to the hole region 1

[0059] The display panel further includes a substrate 10. The metal layer where the second winding d02 is located is on the side away from the substrate 10 of the metal layer where the first winding d01 is located. In the direction perpendicular to the plane where the substrate 10 is located, at least part of the second winding d02 overlaps with the second side 15 and the third side 16, and / or at least part of the second winding d02 overlaps with the fourth side 17 and the first side 14

[0060] See Figure 6 and Figure 7 , there may be some slope angles A in the insulating layer below the metal layer where the second winding d02 is located due to the elevation of the first winding d01 and the third winding s01. The positions of at least part of the slope angles A correspond to the positions of the sides of the first winding d01 and the third winding s01. When etching to form the second winding d02 above this insulating layer, if the position of the second winding d02 does not overlap with the slope angle A, etching residues are likely to occur in the angular gaps at the positions of the slope angles A, and then a short circuit is likely to occur between the metal residues at the positions of the slope angles A and the second winding d02

[0061] However, in the above structure, the second winding d02 straddles between the third winding s01 and the first winding d01, and the position of the second winding d02 will cover these slope angles A, thus avoiding the above problems

[0062] In a feasible implementation manner, in combination with Figure 2 , the display panel includes a plurality of circuit rows 18 arranged along the first direction x, and the circuit rows 18 include a plurality of pixel circuits 4 arranged along the second direction y

[0063] When charging the same circuit row 18, the second data line D2 writes a data signal later than the first data line D1. Combining the foregoing analysis, when charging the same circuit row 18, the fact that the second data line D2 writes a data signal later than the first data line D1 means that the first control line mux1 first provides an enabling level to control the data signal on the source signal line source to be written into the first data line D1, and then the second control line mux2 provides an enabling level to control the data signal on the source signal line source to be written into the second data line D2.

[0064] Among them, referring to Figure 10 , there is a time interval between the moment when the second data line D2 starts to write a data signal and the moment when the voltage jumps in the signal of the first scan line S1.

[0065] It can be understood that the moment when the second data line D2 starts to write a data signal refers to the moment when the signal on the second control line mux2 jumps from a non-enabling level to an enabling level. Combining Figure 2 and Figure 10 , the embodiments of the present invention are illustrated by taking the first selection switch 6 and the second selection switch 7 as P-type transistors and the enabling levels of the first control signal and the second control signal as low levels. Therefore, the moment when the second data line D2 starts to write a data signal is also the moment when the signal on the second control line mux2 jumps from a high level to a low level.

[0066] There is a time interval between the moment when the second data line D2 starts to write a data signal and the moment when the voltage jumps in the signal of the first scan line S1, that is, the two moments are staggered from each other. When the second data line D2 starts to write a data signal, there is no voltage jump on each third winding s01. Either a stable high level or a stable low level is transmitted on the third winding s01. Therefore, the signal interference of the second winding d02 to the first winding d01 can be reliably shielded.

[0067] Define the moment when the data signal starts to be written on the second data line D2 as the first moment. Taking the enabling level provided by the first scan line S1 as a high level as an example: In one case, the time when the first scan line S1 outputs a high level can be located between two adjacent first moments. When the second data line D2 starts to write a data signal, the signals on each third winding s01 are all low levels and the levels are consistent. In this case, the pulse width of the high level in the first scan signal is small. Or, in another case, referring to Figure 10 , the time when the first scan line S1 outputs a high level can cover multiple first moments. In this case, the high level in the first scan signal covers multiple low levels in the second control signal, and the pulse width of the high level in the first scan signal is large.

[0068] It can be understood that the pixel circuit 4 is electrically connected to multiple types of scan lines S, and the scan signals output by different types of scan lines S have different functions. In an embodiment of the present invention, at least one of the scan lines S can be selected as the first scan line S1.

[0069] Before describing which scan line S is selected as the first scan line S1, the embodiment of the present invention first introduces the structure of the pixel circuit 4 and the multiple scan lines S connected thereto.

[0070] In a feasible implementation manner, as Figures 8 to 10 shown, Figure 8 is another schematic structural diagram of the display panel provided by the embodiment of the present invention, Figure 9 is a schematic structural diagram of a pixel circuit 4 provided by the embodiment of the present invention, Figure 10 is a timing diagram provided by the embodiment of the present invention. The pixel circuit 4 includes: A driving transistor T00, the gate of the driving transistor T00 is electrically connected to the first node N1, the second pole is electrically connected to the second node N2, and the second pole is electrically connected to the third node N3.

[0071] A first reset transistor T01, its gate is electrically connected to the first reset scan line s1n, the first pole is electrically connected to the first reset line Ref1, and the second pole is electrically connected to the first node N1.

[0072] A data writing transistor T02, its gate is electrically connected to the data writing scan line sp, the first pole is electrically connected to the data line D, and the second pole is electrically connected to the second node N2.

[0073] A threshold compensation transistor T03, its gate is electrically connected to the threshold compensation scan line s2n, the first pole is electrically connected to the third node N3, and the second pole is electrically connected to the first node N1.

[0074] A bias transistor T04, its gate is electrically connected to the bias scan line spx, the first pole is electrically connected to the bias line DVH, and the second pole is electrically connected to the driving transistor T00, for example, the second pole is electrically connected to the second node N2.

[0075] A first light-emitting control transistor T05, its gate is electrically connected to the light-emitting control scan line Emit, the first pole is electrically connected to the power supply line PVDD, and the second pole is electrically connected to the second node N2.

[0076] A second light-emitting control transistor T06, its gate is electrically connected to the light-emitting control scan line Emit, the first pole is electrically connected to the third node N3, and the second pole is electrically connected to the fourth node N4. The fourth node is electrically connected to the light-emitting element 19.

[0077] A second reset transistor T04, having a gate electrically connected to a bias scan line spx, a first pole electrically connected to a second reset line Ref2, and a second pole electrically connected to a fourth node N4.

[0078] A capacitor Cst, having a first plate electrically connected to a first node N1 and a second plate electrically connected to a power supply line PVDD.

[0079] In one structure, the first reset transistor T01 and the threshold compensation transistor T03 include an oxide semiconductor active layer. For example, both are IGZO transistors. The data writing transistor T02, the bias transistor T04, the first light-emitting control transistor T05, the second light-emitting control transistor T06, and the second reset transistor T04 include a silicon semiconductor active layer. For example, these transistors are all LTPS transistors.

[0080] In one structure, referring to Figure 8 , the first reset scan line s1n, the threshold compensation scan line s2n, the light-emitting control scan line Emit, and the bias scan line spx can all be designed with one driving m, where m≥2. In the embodiments of the present invention, m = 2 is taken as an example for illustration. That is, among these scan lines S, each is electrically connected to the pixel circuits 4 in m circuit rows 18. The data writing scan line sp is designed with one driving one, that is, each data writing scan line sp is only electrically connected to the pixel circuits 4 in one circuit row 18.

[0081] Combined with Figure 9 and Figure 10 , the working process of the pixel circuit 4 includes: In a first time period t1, the bias transistor T04 is turned on in response to the low level provided by the bias scan line spx, and the threshold compensation transistor T03 is turned on in response to the high level provided by the compensation signal line s2n. The bias voltage is written into the first node N1 via the bias transistor T04 and the threshold compensation transistor T03 to bias the driving transistor T00. At the same time, the second reset transistor T07 is turned on in response to the low level provided by the bias scan line spx, and the fourth node N4 is reset using the second reset voltage.

[0082] In a second time period t2, the first reset transistor T01 is turned on in response to the high level provided by the first reset scan line s1n, and the first node N1 is reset using the first reset voltage.

[0083] In a third time period t3, the data writing transistor T02 is turned on in response to the low level provided by the data writing scan line sp, and the threshold compensation transistor T03 is turned on in response to the high level provided by the compensation signal line s2n. The first node N1 is charged using the data voltage and the threshold of the driving transistor T00 is compensated.

[0084] In the fourth time period t4, the bias transistor T04 is turned on in response to the low level provided by the bias scan line spx, and the bias voltage is written to the second node N1 to bias the driving transistor T00. At the same time, the second reset transistor T07 is turned on in response to the low level provided by the bias scan line spx, and the fourth node N4 is reset using the second reset voltage.

[0085] In the fifth time period t5, the first light-emitting control transistor T05 and the second light-emitting control transistor T06 are turned on in response to the low level provided by the light-emitting control scan line Emit, and the driving voltage converted by the driving transistor T00 is written to the fourth node N4 to drive the light-emitting element to emit light.

[0086] Taking the i-th circuit row 18 as an example, during the driving process of the same circuit row 18, combined with Figure 2 , as Figure 11 shown, Figure 11 is Figure 10 a timing diagram of some signals in. In the t6 time period, the first control line mux1 provides a low level to control the first strobe switch 6 to conduct, and the data signal on the source signal line source is written into the first data line D1. In the t7 time period, the second control line mux2 provides a low level to control the second strobe switch 7 to conduct, and the data signal on the source signal line source is written into the second data line D2. In the third time period t3, the data writing transistor T02 of the pixel circuit 4 in the i-th circuit row 18 is turned on in response to the low level provided by the data writing scan line sp(i), and the data signal on the first data line D1 is written into the first pixel circuit 41 or the third pixel circuit 43 in the i-th circuit row 18, and the data signal on the second data line D2 is written into the second pixel circuit 42 in the i-th circuit row 18.

[0087] Among them, the third time period t3 can have no overlap with the t6 time period and overlap with the t7 time period. At this time, the first data line D1 only performs line charging. After the data signal is written on the first data line D1, it floats, and waits until the third time period t3 to write the data signal into the corresponding pixel circuit 4. The second data line D2 performs line charging + direct charging. The second data line D2 enters the third time period t3 during the process of writing the data signal, and the data signal on the second data line D2 is synchronously written into the corresponding pixel circuit 4.

[0088] In a feasible implementation manner, combined with Figures 8 to 10 , as Figure 12 shown, Figure 12Another structural schematic diagram of the display panel provided by the embodiment of the present invention. The pixel circuit 4 includes a driving transistor T00 and a first reset transistor T01. Among them, the first reset transistor T01 includes an oxide semiconductor active layer, whose gate is electrically connected to the first reset scan line s1n, the first pole is electrically connected to the first reset line Ref1, and the second pole is electrically connected to the gate of the driving transistor T00.

[0089] Among them, the first scan line S1 includes the first reset scan line s1n.

[0090] Combined with the foregoing description of the working principle of the pixel circuit 4, it can be seen that within one frame time, the first reset scan line s1n only provides a high level once, and the voltage jump of its signal is not frequent, and the signal is more stable. Therefore, when the first reset scan line s1n is selected as the first scan line S1, the shielding effect of the third winding s01 is better.

[0091] In a feasible implementation manner, combined with Figures 8 to 10 , as Figure 13 shown, Figure 13 Another structural schematic diagram of the display panel provided by the embodiment of the present invention. The pixel circuit 4 includes a driving transistor T00 and a bias transistor T04. The gate of the bias transistor T04 is electrically connected to the bias scan line spx, the first pole is electrically connected to the bias line DVH, and the second pole is electrically connected to the driving transistor T00. Exemplarily, the second pole of the bias transistor T04 is electrically connected to the first pole of the driving transistor T00.

[0092] Among them, the first scan line S1 includes the bias scan line spx.

[0093] Combined with the foregoing description of the working principle of the pixel circuit 4, it can be seen that compared with other scan signals, the bias scan line spx is only used to control the bias of the driving transistor T00 and the reset of the fourth node N4. Therefore, the timing design of the bias scan signal can be more flexible, with fewer limiting factors. The bias scan signal can either jump once before and after the third period t3 as Figure 10 shown, or only jump once before or after the third period t3. Therefore, when the bias scan line spx is selected as the first scan line S1, the third winding s01 can achieve a better shielding effect.

[0094] In a feasible implementation manner, combined with Figure 8 , as Figures 14 to 16 shown, Figure 14 Another structural schematic diagram of the display panel provided by the embodiment of the present invention, Figure 15 is Figure 14 a cross-sectional view along the A1-A2 direction, Figure 16A schematic structural diagram of a first scan line S1 provided by an embodiment of the present invention. The display panel further includes a plurality of circuit rows 18 arranged along a first direction x, and the circuit rows 18 include a plurality of pixel circuits 4 arranged along a second direction y.

[0095] Among them, m first scan lines S1 connected to m circuit rows 18 receive the same signal, that is, the m first scan lines S1 connected to the m circuit rows 18 are electrically connected to the same stage of shift register, and m≥2. The circuit row 18 includes a first circuit row 20. Some of the pixel circuits 4 in the first circuit row 20 are located on one side of the winding area 2 in the second direction y, and some of the pixel circuits 4 are located on the other side of the winding area 2 in the second direction y. Among the first scan lines S1 connected to the first circuit row 20, the third traces s1 in different first scan lines S1 are connected to the fourth trace s2 through different third windings s01.

[0096] When the m first scan lines S1 connected to the m circuit rows 18 receive the same signal, in the embodiment of the present invention, the m first scan lines S1 are not merged in the winding area 2, but the third traces s1 of the m first scan lines S1 are respectively connected to the fourth trace s2 through a third winding s01. In this way, there are a sufficient number of third windings s01 in the winding area 2, and the shielding strength of the third winding s01 is greater.

[0097] In a feasible embodiment, in combination with Figure 14 、 Figure 15 and Figure 17 , Figure 17 A schematic structural diagram of a second scan line S2 and a third scan line S3 provided by an embodiment of the present invention. The display panel further includes a plurality of circuit rows 18 arranged along a first direction x, and the circuit rows 18 include a plurality of pixel circuits 4 arranged along a second direction y. The display panel further includes a plurality of circuit row groups 20 arranged along the first direction x, and the circuit row groups 20 include adjacent m circuit rows 18, m≥2.

[0098] The scan line S further includes a second scan line S2 and a third scan line S3. The scan winding s0 in the second scan line S2 is a fourth winding s02, and the scan winding s0 in the third scan line S3 is a fifth winding s03.

[0099] Among them, m second scan lines S2 connected to the same circuit row group 22 receive the same signal, that is, the m second scan lines S2 connected to the same circuit row group 22 are electrically connected to the same stage of shift register, and the third traces s1 in different second scan lines S2 are connected to the fourth trace s2 through the same fourth winding s02.

[0100] The m third scan lines S3 connected to the same circuit row group 22 receive the same signal, that is, the m third scan lines S3 connected to the same circuit row group 22 are electrically connected to the same stage of shift register, and the third traces s1 in different third scan lines S3 are connected to the fourth trace s2 through the same fifth winding s03.

[0101] Among them, the fourth winding s02 and the fifth winding s03 are arranged on the same layer.

[0102] When the m second scan lines S2 connected to the same circuit row group 22 receive the same signal and the m third scan lines S3 connected thereto receive the same signal, in the embodiment of the present invention, the m second scan lines S2 are designed for wire merging in the winding area 2, so that the third traces s1 in the m second scan lines S2 are connected to the fourth trace s2 through the same fourth winding s02, and the m third scan lines S3 are designed for wire merging in the winding area 2, so that the third traces s1 in the m third scan lines S3 are connected to the fourth trace s2 through the same fifth winding s03, which can reduce the number of scan windings s0 in the winding area 2 and help reduce the width of the winding area 2. Further, in the embodiment of the present invention, the fourth winding s02 and the fifth winding s03 are arranged in the same metal layer, which can also reduce the number of film layers occupied by this part of the scan windings s0. Further, referring to Figure 9 , the pixel circuit 4 includes a driving transistor T00, a first reset transistor T01, a first light-emitting control transistor T05, a second light-emitting control transistor T06, and a bias transistor T04.

[0103] Among them, the first reset transistor T01 includes an oxide semiconductor active layer, whose gate is electrically connected to the first reset scan line s1n, the first pole is electrically connected to the first reset line Ref1, and the second pole is electrically connected to the gate of the driving transistor T00. The gate of the first light-emitting control transistor T05 is electrically connected to the light-emitting control scan line Emit, the first pole is electrically connected to the power supply line PVDD, and the second pole is electrically connected to the gate of the driving transistor T00. The gate of the second light-emitting control transistor T06 is electrically connected to the light-emitting control scan line Emit, the first pole is electrically connected to the second pole of the driving transistor T00, and the second pole is electrically connected to the light-emitting element. The gate of the bias transistor T04 is electrically connected to the bias scan line spx, the first pole is electrically connected to the bias line DVH, and the second pole is electrically connected to the driving transistor T00.

[0104] Among them, the third scan line S3 includes the light-emitting control scan line S. The first scan line S1 includes one of the first reset scan line s1n and the bias scan line spx, and the second scan line S2 includes the other of the first reset scan line s1n and the bias scan line spx.

[0105] Exemplarily, referring toFigure 14 and Figure 15 The first scan line S1 includes a first reset scan line s1n, and the second scan line S2 includes a bias scan line spx.

[0106] In this structure, the m bias scan lines spx are subjected to a wire merging design in the winding area 2, and the m light emission control scan lines S are subjected to a wire merging design in the winding area 2, reducing the number of scan windings s0 in the bias scan lines spx and the light emission control scan line Emit. Moreover, the scan windings s0 in the bias scan lines spx and the light emission control scan line S are arranged on the same layer, which can also reduce the number of film layers occupied by this part of the scan windings s0.

[0107] Or, as Figures 18 to 20 shown, Figure 18 FIG. is another structural schematic diagram of the display panel provided by the embodiment of the present invention. Figure 19 is Figure 18 a cross-sectional view along the B1-B2 direction, Figure 20 and is another structural schematic diagram of the first scan line S1, the second scan line S2, and the third scan line S3 provided by the embodiment of the present invention. The first scan line S1 includes a bias scan line spx, and the second scan line S2 includes a first reset scan line s1n. In this structure, the m first reset scan lines s1n are subjected to a wire merging design in the winding area 2, and the m light emission control scan lines Emit are subjected to a wire merging design in the winding area 2, reducing the number of scan windings s0 in the first reset scan lines s1n and the light emission control scan line Emit. Moreover, the scan windings s0 in the bias scan lines spx and the light emission control scan line S are arranged on the same layer, which can also reduce the number of film layers occupied by this part of the scan windings s0.

[0108] In a feasible implementation manner, in combination with Figure 14 , Figure 15 and Figure 21 , Figure 21 FIG. is a structural schematic diagram of a fourth scan line S4 provided by the embodiment of the present invention. The scan line S further includes a fourth scan line S4, and the scan winding s0 in the fourth scan line S4 is a sixth winding s04.

[0109] Among them, the m fourth scan lines S4 connected by the same circuit row group 22 receive the same signal, that is, these m fourth scan lines S4 are electrically connected to the same-stage shift register, and the third traces s1 in different fourth scan lines S4 are connected to the fourth traces s2 through different sixth windings s04. Moreover, different sixth windings s04 are arranged on the same layer.

[0110] When the m fourth scan lines S4 connected to the m circuit rows 18 receive the same signal, in the embodiments of the present invention, the m fourth scan lines S4 are not merged in the winding area 2. Instead, the third traces s1 of the m fourth scan lines S4 are respectively connected to the fourth traces s2 through a third winding s01. In the embodiments of the present invention, some more important scan lines S can be set as the fourth scan lines S4. The fourth scan lines S4 on both sides of the hole area 1 are not merged, and the load consistency of the fourth scan lines S4 is better.

[0111] Further, referring to Figure 9 , the pixel circuit 4 includes a driving transistor T00 and a threshold compensation transistor T03. The threshold compensation transistor T03 includes an oxide semiconductor active layer, whose gate is electrically connected to the threshold compensation scan line s2n, the first pole is electrically connected to the first pole of the driving transistor T00, and the second pole is electrically connected to the gate of the driving transistor T00.

[0112] Among them, the fourth scan line S4 includes the threshold compensation scan line s2n.

[0113] The threshold compensation scan signal is used to control the writing of the data signal into the gate of the driving transistor T00, which is directly related to the charging of the driving transistor T00 and has a greater impact on the display. Therefore, using the threshold compensation scan line s2n as the fourth scan line S4 and not merging the threshold compensation scan line s2n can improve the charging consistency of the pixel circuits 4 at different positions and improve the display uniformity.

[0114] In a feasible implementation manner, referring again to Figure 14 and Figure 15 、and referring to Figure 18 and Figure 19 , the display panel further includes a first circuit column 8 and a second circuit column 9 arranged alternately along the second direction y. The first circuit column 8 and the second circuit column 9 respectively include a plurality of pixel circuits 4 arranged along the first direction x. The first circuit column 8 is electrically connected to the first data line D1, and the second circuit column 9 is electrically connected to the second data line D2.

[0115] The display panel further includes a plurality of circuit column groups 21 arranged along the second direction y. The circuit column group 21 includes four adjacent first circuit columns 8 and second circuit columns 9.

[0116] The display panel further includes a circuit row 18 arranged along the first direction x. The circuit row 18 includes a plurality of pixel circuits 4 arranged along the second direction y.

[0117] The display panel further includes a plurality of circuit row groups 22 arranged along the first direction x. The circuit row group 22 includes m adjacent circuit rows 18, m≥2, and the embodiments of the present invention are illustrated by taking m = 2 as an example.

[0118] The winding area 2 includes a plurality of winding units 23. Each winding unit 23 includes a data winding d0 connected to a circuit column group 21 and a scan winding s0 connected to a circuit row group 22.

[0119] The winding area 2 includes a plurality of winding units 23. The number of windings included in different winding units 23 is the same, and the overlapping manner between different windings in different winding units 23 can follow the same design, making the winding arrangement in the entire winding area 2 more regular and the coupling more uniform.

[0120] Combined with the foregoing description of the setting method of the scan winding s0 in different scan lines S, in one structure, a winding unit 23 includes two first windings d01, two second windings d02, two third windings s01, two sixth windings s04, one fourth winding s02, and one fifth winding s05.

[0121] Next, refer to Figure 15 and Figure 19 to schematically illustrate the film layer positions of the scan winding s0 and the data winding d0.

[0122] The second winding d02 is located in the fifth metal layer sd2, the third winding s01 is located in the fourth metal layer sd1, the first winding d01 is located in the third metal layer mg, the sixth winding s04 is located in the second metal layer mc, and the fourth winding s02 and the fifth winding s03 are located in the first metal layer m1.

[0123] In the direction perpendicular to the plane of the substrate 10, any one of the windings can overlap at least with another winding to optimize the wiring width required for multiple windings and reduce the width of the winding area 2.

[0124] Moreover, as Figure 22 shown, Figure 22 FIG. is another schematic cross-sectional structure diagram of the display panel provided by the embodiment of the present invention. In the direction perpendicular to the plane of the substrate 10, the first winding d01 can overlap with the side surface of the sixth winding s04 opposite to the fourth winding s02, that is, the first winding d01 straddles between the sixth winding s04 and the fourth winding s02, or the first winding d01 can overlap with the side surface of the sixth winding s04 opposite to the fifth winding s03, that is, the first winding d01 straddles between the sixth winding s04 and the fifth winding s03.

[0125] At this time, the setting method of the first winding d01 is the same as that of Figure 6 and Figure 7The setting method of the second winding d02 is similar. When forming the first winding d01 above the insulating layer on the sixth winding s04, it is possible to prevent etching residues from existing at the slope angle at the middle position between the sixth winding s04 and the fourth winding s02 (or the fifth winding s03).

[0126] In addition, the data writing scan line sp can be driven bilaterally, that is, the data writing scan line sp is electrically connected to a shift register at both ends respectively. Therefore, referring again to Figure 14 and Figure 18 , the data writing scan line sp can not wind in the winding area 2. The data writing scan line sp is disconnected on both sides of the winding area 2, and the disconnected parts on both sides are respectively connected to a shift register.

[0127] Based on the same inventive concept, an embodiment of the present invention also provides a display device, as Figure 23 shown, Figure 23 is a schematic structural diagram of the display device provided by the embodiment of the present invention. The display device includes the above-mentioned display panel 100. Of course, Figure 23 the display device shown is only for schematic illustration. The display device can be any electronic device with a display function such as a mobile phone, a tablet computer, a notebook computer, an e-book or a television, etc.

[0128] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0129] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A display panel, characterized in that, Comprising: a hole region, a winding region surrounding the hole region, and a first display region at least partially surrounding the winding region; a pixel circuit, at least located in the first display region; data lines electrically connected to the pixel circuit, a part of the data lines including a connected first trace, a data winding, and a second trace, the first trace and the second trace being located in the first display region and on both sides of the winding region in a first direction, and the data winding being located in the winding region; scan lines electrically connected to the pixel circuit, a part of the scan lines including a connected third trace, a scan winding, and a fourth trace, the third trace and the fourth trace being located in the first display region and on both sides of the winding region in a second direction, the scan winding being located in the winding region, and the second direction intersecting the first direction; wherein, the data lines include a first data line and a second data line, the first data line and the second data line are respectively electrically connected to different pixel circuits and write data signals in a time-sharing manner, the data winding in the first data line is a first winding, and the data winding in the second data line is a second winding; the scan lines include a first scan line, and the scan winding in the first scan line is a third winding; wherein, the metal layer where the third winding is located is between the metal layer where the first winding is located and the metal layer where the second winding is located.

2. The display panel according to claim 1, wherein in a direction perpendicular to the plane where the display panel is located, the third winding at least partially overlaps with the first winding, and / or the third winding at least partially overlaps with the second winding, and / or the third winding at least partially overlaps with the interval between adjacent first windings, and / or the third winding at least partially overlaps with the interval between adjacent second windings.

3. The display panel according to claim 1, wherein in a direction perpendicular to the plane where the display panel is located, the first winding and the second winding at least partially overlap.

4. The display panel according to claim 3, wherein in a direction perpendicular to the plane where the display panel is located, the third winding at least partially overlaps with the facing region between the first winding and the second winding.

5. The display panel according to claim 1, wherein the pixel circuit includes a first pixel circuit electrically connected to a red light-emitting element, a second pixel circuit electrically connected to a green light-emitting element, and a third pixel circuit electrically connected to a blue light-emitting element; wherein, the first data line is electrically connected to the first pixel circuit and the third pixel circuit, and the second data line is electrically connected to the second pixel circuit; the display panel further includes a substrate, the metal layer where the second winding is located is on the side away from the substrate of the metal layer where the first winding is located, and a planarization layer is included between the metal layer where the second winding is located and the substrate.

6. The display panel according to claim 1, wherein The first winding includes opposite first and second side surfaces, and the second side surface is located on the side of the first side surface close to the hole region; The third winding includes opposite third and fourth side surfaces, and the fourth side surface is located on the side of the third side surface close to the hole region; The display panel further includes a substrate, and the metal layer where the second winding is located is on the side away from the substrate of the metal layer where the first winding is located. In a direction perpendicular to the plane where the substrate is located, at least part of the second winding overlaps with the second side surface and the third side surface, and / or at least part of the second winding overlaps with the fourth side surface and the first side surface.

7. The display panel according to claim 1, wherein The display panel includes a plurality of circuit rows arranged along the first direction, and each circuit row includes a plurality of the pixel circuits arranged along the second direction; When charging the same circuit row, the second data line writes a data signal later than the first data line; Among them, there is a time interval between the moment when the second data line starts to write the data signal and the moment when the voltage jumps in the signal of the first scan line.

8. The display panel according to claim 1, wherein The pixel circuit includes: A driving transistor; A first reset transistor, including an oxide semiconductor active layer, whose gate is electrically connected to the first reset scan line, the first pole is electrically connected to the first reset line, and the second pole is electrically connected to the gate of the driving transistor; Among them, the first scan line includes the first reset scan line.

9. The display panel according to claim 1, wherein The pixel circuit includes: A driving transistor; A bias transistor, whose gate is electrically connected to the bias scan line, the first pole is electrically connected to the bias line, and the second pole is electrically connected to the driving transistor; Among them, the first scan line includes the bias scan line.

10. The display panel according to claim 1, wherein The display panel further includes a plurality of circuit rows arranged along the first direction, and each circuit row includes a plurality of the pixel circuits arranged along the second direction; among them, m first scan lines connected to m circuit rows receive the same signal, m≥2; The circuit row includes a first circuit row, and part of the pixel circuits in the first circuit row are located on one side of the winding region in the second direction, and part of the pixel circuits are located on the other side of the winding region in the second direction; Among the first scan lines connected to the first circuit row, the third traces in different first scan lines are connected to the fourth traces through different third windings.

11. The display panel according to claim 1, wherein The display panel further includes: A first circuit column and a second circuit column arranged alternately along the second direction, the first circuit column and the second circuit column respectively include a plurality of the pixel circuits arranged along the first direction, the first circuit column is electrically connected to the first data line, and the second circuit column is electrically connected to the second data line; A plurality of circuit column groups arranged along the second direction, where each circuit column group includes four adjacent first circuit columns and the second circuit column; A circuit row arranged along the first direction, where the circuit row includes a plurality of pixel circuits arranged along the second direction; A plurality of circuit row groups arranged along the first direction, where each circuit row group includes m adjacent circuit rows, m≥2; The routing area includes a plurality of routing units, and each routing unit includes a data routing connected to one circuit column group and a scan routing connected to one circuit row group.

12. The display panel according to claim 1, wherein The display panel further includes: A circuit row arranged along the first direction, where the circuit row includes a plurality of pixel circuits arranged along the second direction; A plurality of circuit row groups arranged along the first direction, where each circuit row group includes m adjacent circuit rows, m≥2; The scan line further includes a second scan line and a third scan line. The scan routing in the second scan line is a fourth routing, and the scan routing in the third scan line is a fifth routing; Wherein, m second scan lines connected to the same circuit row group receive the same signal, and the third traces in different second scan lines are connected to the fourth trace through the same fourth routing; m third scan lines connected to the same circuit row group receive the same signal, and the third traces in different third scan lines are connected to the fourth trace through the same fifth routing; The fourth routing and the fifth routing are arranged on the same layer.

13. The display panel according to claim 12, wherein The pixel circuit includes: A driving transistor; A first reset transistor, including an oxide semiconductor active layer, whose gate is electrically connected to a first reset scan line, a first pole is electrically connected to a first reset line, and a second pole is electrically connected to the gate of the driving transistor; A first light-emitting control transistor, whose gate is electrically connected to a light-emitting control scan line, a first pole is electrically connected to a power supply line, and a second pole is electrically connected to the gate of the driving transistor; A second light-emitting control transistor, whose gate is electrically connected to the light-emitting control scan line, a first pole is electrically connected to the second pole of the driving transistor, and a second pole is electrically connected to a light-emitting element; A bias transistor, whose gate is electrically connected to a bias scan line, a first pole is electrically connected to a bias line, and a second pole is electrically connected to the driving transistor; Wherein, the third scan line includes the light-emitting control scan line; The first scan line includes one of the first reset scan line and the bias scan line, and the second scan line includes the other of the first reset scan line and the bias scan line.

14. The display panel according to claim 1, wherein The display panel further includes: A circuit row arranged along the first direction, where the circuit row includes a plurality of pixel circuits arranged along the second direction; A plurality of circuit row groups arranged along the first direction, where each circuit row group includes m adjacent circuit rows, m≥2; The scan line further includes a fourth scan line, and the scan routing in the fourth scan line is a sixth routing; Among them, m fourth scan lines connected to the same circuit row group receive the same signal, and third traces in different fourth scan lines are connected to the fourth trace through different sixth winding lines; The different sixth winding lines are arranged in the same layer.

15. The display panel according to claim 14, wherein The pixel circuit includes: A driving transistor; A threshold compensation transistor, including an oxide semiconductor active layer, whose gate is electrically connected to the threshold compensation scan line, the first pole is electrically connected to the first pole of the driving transistor, and the second pole is electrically connected to the gate of the driving transistor; The fourth scan line includes a threshold compensation scan line.

16. A display device, characterized in that, Including the display panel according to any one of claims 1 to 15.

Images