Coding method, decoding method and device

Abstract

The invention relates to a coding method, a decoding method and a device, in the coding method, first equipment can determine a second bit sequence and a third bit sequence based on a first bit sequence, and the third bit sequence comprises a bit sequence of which the weight is higher than a first threshold in a base graph corresponding to the first bit sequence. That is, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Furthermore, the first device can perform polar code coding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with lower weight in a polar code coding mode, so as to improve the error correction performance. And for the third bit sequence with relatively high weight, LDPC coding can be performed on the third bit sequence and a polarization code coding result (namely, a fourth bit sequence obtained by performing polarization code coding on the second bit sequence). The error floor of LDPC decoding is reduced, and the error correction performance of LDPC codes is improved.

Description

Technical Field

[0001] This application relates to the field of communication technologies, and in particular, to an encoding method, a decoding method, and a device. Background Art

[0002] The low density parity check (LDPC) code is a channel coding scheme that is very close to the Shannon limit, and has characteristics such as good performance and low complexity. Currently, it has been determined by the 3rd generation partnership project (3GPP) to be the data channel coding scheme for the fifth generation (5G) communication technology.

[0003] However, in the case where the signal-to-noise ratio (SNR) is relatively high, the LDPC code may have an error floor due to the influence of the trap set, and its block error rate (BLER) no longer decreases as the SNR increases. Among them, the trap set is a set of bit serial numbers that cannot be correctly decoded and output after a large fixed number of iterations, and the error floor is mainly determined by the size and distribution of the trap set. Therefore, how to reduce the error floor of the LDPC code has become an urgent problem to be solved at the current stage. Summary of the Invention

[0004] This application provides an encoding method, a decoding method, and a device, which can reduce the error floor and the block error rate of the LDPC code, thereby improving the error correction performance.

[0005] In a first aspect, an encoding method is provided. This method can be executed by a first device, or by a module (such as a processor, a chip, or a chip system, etc.) applied to the first device, or by a logical node, a logical module, or software that can implement all or part of the functions of the first device. In this encoding method, a second bit sequence and a third bit sequence can be determined based on a first bit sequence, and the third bit sequence includes the bit sequence in the base graph corresponding to the first bit sequence with a weight higher than a first threshold. The second bit sequence can also be encoded by a polar code to obtain a fourth bit sequence. Thus, the third bit sequence and the fourth bit sequence can be encoded by a low density parity check (LDPC) code to obtain a fifth bit sequence.

[0006] It can be seen that in the above embodiments, the first device can determine a second bit sequence and a third bit sequence based on the first bit sequence. The third bit sequence includes the bit sequence in the base graph corresponding to the first bit sequence with a weight higher than the first threshold. That is to say, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Further, the first device can perform polar code encoding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with a lower weight by means of polar code encoding to improve the error correction performance. For the third bit sequence with a higher weight, it can be LDPC-encoded together with the result of the polar code encoding (i.e., the fourth bit sequence obtained by performing polar code encoding on the second bit sequence). In this way, the error floor of LDPC decoding can be reduced, thereby improving the error correction performance of the LDPC code. At the same time, the LDPC encoding load caused by Polar outer code encoding can also be reduced, thereby reducing the code rate of the LDPC code and improving the waterfall region performance.

[0007] In a possible implementation manner, determining the second bit sequence and the third bit sequence based on the first bit sequence includes: determining a first value based on the first number of columns in the base graph with a weight higher than the first threshold; determining the third bit sequence from the first bit sequence based on the first value and the lifting factor corresponding to the first bit sequence; and determining the second bit sequence based on the third bit sequence and the first bit sequence.

[0008] It can be seen that in the above embodiments, the first device can determine a first value based on the first number of columns in the base graph with a weight higher than the first threshold, so that the third bit sequence can be determined from the first bit sequence based on the first value and the lifting factor corresponding to the first bit sequence. In this way, the bit sequence with a larger column weight in the first bit sequence can be determined more precisely, and then the bit sequence with a non-large column weight, that is, the second bit sequence, can be determined more precisely.

[0009] In a possible implementation manner, the first number of columns is an integer greater than or equal to 1. For example, the first number of columns can be 2 or 3.

[0010] In a possible implementation manner, determining the first value based on the first number of columns in the base graph with a weight higher than the first threshold includes: determining the second number of columns with the highest reliability from the other columns in the base graph except those with a weight higher than the first threshold; and determining the first value based on the first number of columns and the second number of columns.

[0011] It can be seen that in the above embodiments, the first device can also determine the first value based on the first number of columns and the second number of columns. The first value can be used to determine the third bit sequence from the first bit sequence, which is equivalent to increasing the number of bits that do not undergo polar code encoding. Therefore, this can reduce the LDPC encoding load caused by Polar outer code encoding, thereby reducing the code rate of the LDPC code and improving the waterfall region performance.

[0012] In a possible implementation, polar code encoding is performed on the second bit sequence to obtain a fourth bit sequence, including: performing parity check encoding on the second bit sequence to obtain a sixth bit sequence; performing polar code encoding on the sixth bit sequence to obtain the fourth bit sequence. Among them, the parity check encoding can be parity check (PC) encoding and / or cyclic redundancy check (CRC) encoding.

[0013] It can be seen that in the above embodiments, the first device can first perform parity check encoding on the second bit sequence and then perform polar code encoding. It is equivalent to that the parity check only checks the bits with non-large column weight. This is because the bits with large column weight are almost error-free. If an error occurs, then the bits with non-large column weight are very likely to be in error. The parity check can correct the bits with non-large column weight. In addition, the parity check can be used for error correction, so that the performance of the polar code under SCL decoding can be improved when using SCL decoding.

[0014] In a possible implementation, the method further includes: performing parity check encoding on the seventh bit sequence to obtain a first bit sequence.

[0015] It can be seen that in the above embodiments, the first device can perform parity check encoding on the seventh bit sequence to obtain a first bit sequence. The seventh bit sequence contains the bits with large column weight. That is to say, the bits with large column weight can also be checked by the parity check, so that a lower false alarm rate (FAR) can be obtained.

[0016] In a possible implementation, the method further includes: segmenting the initial bit sequence based on the first segmentation length to obtain X bit sequences, where the X bit sequences include the first bit sequence or the seventh bit sequence, and X is an integer greater than 1; among them, the first segmentation length is determined based on the first value and the boosting factor.

[0017] It can be seen that in the above embodiments, the first device can segment the initial bit sequence based on the first segmentation length, and the first segmentation length is determined based on the first value and the boosting factor. That is to say, this provides a segmentation method adapted to this solution, reducing the problem of encoding errors caused by segmentation mistakes.

[0018] In a possible implementation, the first segmentation length is determined based on the first value and the boosting factor, including: the first segmentation length is determined based on the first value, the boosting factor and the second value; among them, the second value is determined based on the total number of columns of the base graph and the first value.

[0019] In a possible implementation, the first segmentation length satisfies the following conditions: Wherein, a is the first value, b is the second value, R is the third value, and Z is the boosting factor.

[0020] In a possible implementation manner, determining the second bit sequence based on the third bit sequence and the first bit sequence includes: segmenting other bit sequences of the first bit sequence except the third bit sequence based on the second segment length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence, and Y is an integer greater than 1; wherein, the second segment length is determined based on the maximum length supported by polar code encoding and the third value.

[0021] It can be seen that in the above embodiments, the first device can segment other bit sequences of the first bit sequence except the third bit sequence based on the second segment length (determined based on the maximum length supported by polar code encoding and the third value) to obtain Y bit sequences, and the Y bit sequences may include the second bit sequence. This can prevent errors when encoding the second bit sequence with polar codes and better be compatible with the current polar code method.

[0022] In a possible implementation manner, the second segment length satisfies the following conditions: Wherein, Nm is the maximum length supported by polar code encoding, and R is the third value.

[0023] In a possible implementation manner, the method further includes: sending a symbol sequence based on the third bit sequence.

[0024] In a second aspect, a decoding method is provided. This method can be executed by a second device, or by a module (such as a processor, a chip, or a chip system, etc.) applied to the second device, or by a logical node, a logical module, or software that can implement all or part of the functions of the second device. In this decoding method, a symbol sequence can be obtained, so that a fifth bit sequence can be determined based on the symbol sequence, and then the fifth bit sequence is decoded by LDPC to obtain the third bit sequence and the fourth bit sequence. In this way, the fourth bit sequence can be decoded by polar codes to obtain the second bit sequence, and the first bit sequence is determined based on the third bit sequence and the second bit sequence.

[0025] It can be seen that in the above embodiments, the second device may first determine the fifth bit sequence based on the symbol sequence, and then perform LDPC decoding on the fifth bit sequence to obtain the third bit sequence and the fourth bit sequence. Thus, polar code decoding can be performed on the fourth bit sequence to obtain the second bit sequence. In this way, the first bit sequence can be determined based on the third bit sequence and the second bit sequence. This can be used to reduce the error floor of LDPC decoding, and further improve the error correction performance of the LDPC code. At the same time, the LDPC coding payload brought by Polar outer code encoding can also be reduced, thereby reducing the code rate of the LDPC code and improving the performance in the waterfall region. In addition, the second device performs polar code decoding on a partial bit sequence (such as the fourth bit sequence) in the LDPC decoding result, reducing the decoding delay and improving the decoding efficiency.

[0026] In a third aspect, a communication device is provided, including units or modules for implementing the method described in any one of the first aspect to the second aspect. The communication device may be the first device or the second device, or a module of the first device or the second device (such as a processor, a chip, or a chip system, etc.), or a logical node, a logical module, or software capable of implementing all or part of the functions of the first device or the second device.

[0027] In a fourth aspect, a communication device is provided. The communication device includes at least one processor; wherein, the at least one processor is configured to execute the method described in any one of the first aspect to the second aspect. The communication device may be the first device or the second device, or a module of the first device or the second device (such as a processor, a chip, or a chip system, etc.), or a logical node, a logical module, or software capable of implementing all or part of the functions of the first device or the second device. The at least one processor may execute computer programs or instructions in a memory to cause the above method to be executed. The memory may be included in the communication device or located outside the communication device. In addition, the communication device may further include an interface.

[0028] In a fifth aspect, a communication system is provided. The communication system includes a first device and a second device; the first device is configured to execute the method described in any one of the first aspect; the second device is configured to execute the method described in any one of the second aspect.

[0029] In a sixth aspect, a computer-readable storage medium is provided. The computer-readable storage medium stores computer instructions, which when executed by a computer, cause the computer to execute the method described in any one of the first aspect to the second aspect.

[0030] In a seventh aspect, there is provided a computer program product, which includes computer program code. When the computer program code is run by a computer, the computer is caused to execute the method described in any one of the first aspect to the second aspect. Description of the Drawings

[0031] Figure 1 This is the infrastructure of a communication system provided by an embodiment of the present application;

[0032] Figure 2 This is a schematic diagram of the communication process between communication devices;

[0033] Figure 3 This is a schematic diagram of polar code encoding;

[0034] Figure 4 This is a schematic diagram of a parity check matrix;

[0035] Figure 5 This is a schematic flowchart of an encoding method provided by an embodiment of the present application;

[0036] Figure 6 This is a schematic flowchart of a decoding method provided by an embodiment of the present application;

[0037] Figure 7 This is a schematic flowchart of another encoding method provided by an embodiment of the present application;

[0038] Figure 8 This is a schematic flowchart of another decoding method provided by an embodiment of the present application;

[0039] Figure 9 This is an example of encoding and decoding provided by an embodiment of the present application;

[0040] Figure 10 This is a comparison diagram of beneficial effects provided by an embodiment of the present application;

[0041] Figure 11 This is another example of encoding and decoding provided by an embodiment of the present application;

[0042] Figure 12 This is another comparison diagram of beneficial effects provided by an embodiment of the present application;

[0043] Figure 13 This is a schematic structural diagram of a communication device provided by an embodiment of the present application;

[0044] Figure 14 This is a schematic structural diagram of another communication device provided by an embodiment of the present application. Detailed Embodiments

[0045] The following will describe the technical solutions in the embodiments of the present application in conjunction with the accompanying drawings in the embodiments of the present application. Among them, the terms "system" and "network" in the embodiments of the present application can be used interchangeably. Unless otherwise specified, " / " indicates that the objects associated before and after are in an "or" relationship. For example, A / B can represent A or B; "and / or" in the present application is only a description of the association relationship of the associated objects, indicating that there can be three relationships. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, and B exists alone. These three situations, where A and B can be singular or plural. And, in the description of the present application, unless otherwise specified, "a plurality of" means two or more than two. "At least one (item)" or similar expressions below refer to any combination of these items, including any combination of single items (items) or plural items (items). For example, at least one (item) of a, b, or c can represent: a, b, c, a - b, a - c, b - c, or a - b - c, where a, b, c can be one or multiple. In addition, in order to clearly describe the technical solutions in the embodiments of the present application, in the embodiments of the present application, terms such as "first" and "second" are used to distinguish the same items or similar items with basically the same functions of network elements. Those skilled in the art can understand that the terms such as "first" and "second" do not limit the quantity and execution order, and the terms such as "first" and "second" do not necessarily limit to be different.

[0046] Reference to "one embodiment" or "some embodiments" etc. described in the embodiments of the present application means that a specific feature, structure, or characteristic described in conjunction with the embodiment is included in one or more embodiments of the present application. Thus, statements such as "in one embodiment", "in some embodiments", "in other some embodiments", "in still other embodiments" etc. that appear in different places in this specification do not necessarily all refer to the same embodiment, but mean "one or more but not all embodiments", unless otherwise specifically emphasized in another way. The terms "include", "comprise", "have" and their variants all mean "including but not limited to", unless otherwise specifically emphasized in another way.

[0047] The following specific implementation manners further elaborate on the objectives, technical solutions, and beneficial effects of the present application. It should be understood that the following is only the specific implementation manners of the present application and is not used to limit the protection scope of the present application. Any modifications, equivalent replacements, improvements, etc. made on the basis of the technical solutions of the present application should be included in the protection scope of the present application.

[0048] In various embodiments of the present application, if there is no special description and logical conflict, the terms and / or descriptions between different embodiments are consistent and can be cross-referenced to each other. The technical features in different embodiments can be combined to form new embodiments according to their internal logical relationships.

[0049] It should be understood that the technical solutions of the embodiments of the present application can be applied to long term evolution (LTE) architectures, 5th generation mobile networks (5G), wireless local area networks (WLAN) systems, vehicle to everything (V2X) communication systems, LTE-vehicle (LTE-V), vehicle to vehicle (V2V), vehicle networking, machine type communications (MTC), and so on. The technical solutions of the embodiments of the present application can also be applied to other future communication systems, such as 6G communication systems, etc. In future communication systems, the functions may remain the same, but the names may change.

[0050] The following introduces the basic architecture of the communication system provided by the embodiments of the present application. The communication system provided by the present application may include one or more network devices and one or more terminal devices. The following uses Figure 1 the shown system architecture for exemplary explanation. As Figure 1 shown, the communication system includes a network device 10 and one or more terminal devices communicating with the network device 10 (such as Figure 1 the terminal device 20 in

[0051] It should be noted that Figure 1 the number of network devices and terminal devices in

[0052] I. Terminal Devices

[0053] A terminal device is an entity on the user side that is used to receive signals, or send signals, or receive and send signals. The terminal device is used to provide one or more of voice services and data connectivity services to users. The terminal device can be a device that includes wireless transceiver functions and can cooperate with network devices to provide communication services to users. Specifically, the terminal device can refer to user equipment (UE), access terminal, user unit, user station, mobile station, mobile device, remote station, remote terminal, mobile device, terminal, wireless communication device, user agent, user device, or roadside unit (RSU). The terminal device can also be a drone, an Internet of Things (IoT) device, a station (ST) in a wireless local area network (WLAN), a cellular phone, a smart phone, a cordless phone, a wireless data card, a tablet computer, a Session Initiation Protocol (SIP) phone, a wireless local loop (WLL) station, a personal digital assistant (PDA) device, a laptop computer, a machine type communication (MTC) terminal, a handheld device with wireless communication functions, a computing device, or other processing devices connected to a wireless modem, an in-vehicle device, a wearable device (which can also be called a wearable intelligent device), a virtual reality (VR) terminal, an augmented reality (AR) terminal, a wireless terminal in remote medical, a wireless terminal in industrial control, a wireless terminal in self-driving, a wireless terminal in a smart grid, a wireless terminal in transportation safety, a wireless terminal in a smart city, a wireless terminal in a smart home, etc. The terminal device can also be a terminal in a 5G system or a terminal in a next-generation communication system, which is not limited in the embodiments of this application.

[0054] Embodiments of this application do not limit the form of the terminal device. The device for implementing the functions of the terminal device may be the terminal device; or it may be a device capable of supporting the terminal device to implement the functions, such as a chip system. This device may be installed in the terminal device or used in matching with the terminal device. In the embodiments of this application, the chip system may be composed of chips or may include chips and other discrete devices.

[0055] II. Network device

[0056] A network device is an entity on the network side for sending signals, or receiving signals, or sending and receiving signals. The network device may be a device deployed in a radio access network (RAN) to provide wireless communication functions for the terminal device.

[0057] In a possible scenario, the network device can be a device with base station functions, such as an evolved NodeB (eNodeB), a transmitting and receiving point (TRP), a transmitting point (TP), a next generation NodeB (gNB), a next generation base station in a 6G mobile communication system, an integrated access and backhaul (IAB) node, a non-terrestrial network device in NTN, i.e., a device that can be deployed on a high-altitude platform or a satellite, etc. The network device can be a transmission reception point (TRP), a base station, or various forms of control nodes. For example, a network controller, a radio controller, etc. Specifically, the network device can be various forms of macro base stations, micro base stations (also known as small stations) in a heterogeneous network (HetNet) scenario, relay stations, access points (APs), radio network controllers (RNCs), Node Bs (NBs), base station controllers (BSCs), base transceiver stations (BTSs), home base stations (e.g., home evolved nodeB, or home node B, HNB), baseband units (BBUs) and remote radio units (RRUs) in a distributed base station scenario, transmitting and receiving points (TRPs), transmitting points (TPs), mobile switching centers, etc., or can also be the antenna panel of a base station. The control node can be connected to multiple base stations and configure resources for multiple terminals covered by the multiple base stations. In systems adopting different radio access technologies, the names of the devices with base station functions may vary. For example, it can be a gNB in 5G, or a network-side device in a network after 5G or a network device in a future-evolved public land mobile network (PLMN), or a device that undertakes base station functions in device-to-device (D2D) communication, machine-to-machine (M2M) communication, vehicle-to-everything (V2X) communication, etc. The present application does not limit the specific name of the network device.The network device can also be a baseband unit pool (BBU pool) and RRU under an open radio access network (openRAN, O-RAN or ORAN), a cloud radio access network (CRAN), etc.

[0058] All or part of the functions of the network device in this application can also be implemented by software functions running on hardware, or by virtualized functions instantiated on a platform (such as a cloud platform). The network device in this application can also be a logical node, logical module or software that can implement all or part of the network device functions.

[0059] In another possible scenario, multiple network devices cooperate to assist the terminal device in achieving wireless access, and different network devices respectively implement part of the functions of the base station. For example, the network device can include a central unit (CU), a distributed unit (DU), a CU-control plane (CP), a CU-user plane (UP), or a radio unit (RU), etc. The CU and DU can be set separately, or can also be included in the same network element, such as a baseband unit (BBU). The RU can be included in a radio frequency device or radio frequency unit, such as included in a remote radio unit (RRU), an active antenna unit (AAU), or a remote radio head (RRH). It can be understood that the network device can be a CU node, or a DU node, or a device including a CU node and a DU node. In addition, the CU can be classified as a network device in the radio access network RAN, or the CU can be classified as a network device in the core network CN, which is not limited here.

[0060] In different systems, the CU (or CU-CP and CU-UP), DU or RU may also have different names, but those skilled in the art can understand their meanings. For example, in the ORAN system, the CU can also be called O-CU (open CU), the DU can also be called O-DU, the CU-CP can also be called O-CU-CP, the CU-UP can also be called O-CU-UP, and the RU can also be called O-RU. For the convenience of description, the CU, CU-CP, CU-UP, DU and RU are used as examples in this application. Any one of the CU (or CU-CP, CU-UP), DU and RU in this application can be implemented by a software module, a hardware module, or a combination of a software module and a hardware module.

[0061] In the embodiments of the present application, the form of the network device is not limited. The device for implementing the functions of the network device may be a network device; it may also be a device capable of supporting the network device to implement the functions, such as a chip system. This device may be installed in the network device or used in matching with the network device.

[0062] To facilitate the understanding of the content of this solution, some terms involved in the embodiments of the present application are further explained below for the convenience of those skilled in the art to understand. This part is only for the convenience of understanding and cannot be regarded as a specific limitation to the present application.

[0063] I. Communication process between communication devices

[0064] For example, in Figure 2 , the first device can transmit information to the second device through a channel after sequentially performing source coding, channel coding, rate matching, and modulation on the bit stream generated by the information source. Correspondingly, after receiving the information, the second device sequentially performs demodulation, derate matching, channel decoding, and source decoding on the information to obtain the destination, that is, to recover the bit stream generated by the information source. The channel may be an additive white Gaussian noise (AWGN) channel. Among them, at least one of the first device and the second device may be Figure 1 the terminal device or the network device in

[0065] II. Polar code

[0066] The polar code is a known channel coding scheme that can be strictly proved to "achieve" the channel capacity. It has characteristics such as high performance and low complexity. At present, it has been determined by 3GPP to be the control channel coding scheme for the enhanced mobile broadband (eMBB) scenario (uplink / downlink) of the 5G control channel.

[0067] The polar code is a linear block code, and its encoding process can be x N = u N G N , where u N = {u0, u1,..., u N-1} is a binary row vector with a length of N, is the encoding matrix, The Kronecker power represented by can be defined as For example, when n = 2, the polar code encoding matrix with a code length of N = 4 can be obtained

[0068] During the encoding process of polar codes, u N can be divided into two parts. One part of the bits carries information and is called information bits. The index set of these bits can be denoted as A. The other part of the bits has fixed values and is called frozen bits, usually set to 0. When the frozen bits are set to 0, the encoding process of polar codes can be simplified to x A = u A GN(A), where u A is the set of information bits in u N , and its length can be denoted as K; GN(A) is a submatrix of GN composed of the rows corresponding to the indices in set A. GN(A) is a K×N matrix. Among them, the selection of set A will affect the performance of polar codes.

[0069] Figure 3 shows a schematic diagram of polar code encoding. As Figure 3 shown, u8 = {u0, u0,.., u7} is a binary row vector with a length of 8. This binary row vector can include frozen bits and information bits, and the frozen bits and information bits can be adjacent or interleaved. For example: u0, u1, u2, and u4 are frozen bits and can all be 0. u3, u5, u6, and u7 are information bits. Figure 3 The circle-plus symbol shown in it represents the exclusive OR operation. u0, u1, u2, and u4 are the four bits with lower reliability, and u3, u5, u6, and u7 are the four bits with higher reliability. Among them, Figure 3 the intermediate results in the shown encoding process are only an example, and the embodiments of the present application do not limit this. In the present application, polar code encoding and polar outer code encoding can be replaced with each other.

[0070] In the present application, polar codes can include at least one of the following: Arikan Polar code, Parity Check Polar (PC-Polar) code, Cyclic Redundancy Check Polar (CA-Polar) code, or Parity Check - Cyclic Redundancy Check Polar - Polar (PC-CA-Polar) code, etc. Arikan Polar refers to the original polar code without being concatenated with other codes, including information bits and / or frozen bits. PC-Polar is a polar code concatenated with a PC code. CA-Polar is a polar code concatenated with a CRC code. PC-CA-Polar code is a polar code concatenated with both a PC code and a CRC code.

[0071] Among them, the CRC code, as a commonly used error detection code, is the most common outer code concatenated with the polar code. In this application, the length of the CRC code can be R bits, and R can be a positive integer, such as 4, 6, 8, 11, 16, or 24. This application does not limit its length. It should be understood that the CRC code can be obtained based on the generating polynomial, and the power of the generating polynomial of the R-bit CRC code can be R. Different polynomials are used for CRC codes of different lengths. For example, taking the CRC code with a length of 24 bits as an example, the polynomial it uses can be CRC24. This application does not limit the specific polynomial used for the CRC code.

[0072] There are various possible implementation methods for polar code decoding. For example, successive cancellation decoding (SC) decoding, successive cancellation list decoding (SCL), successive cancellation stack (SCS) decoding, CRC-aided successive cancellation list (CA-SCL) decoding, belief propagation (BP) decoding, and soft cancellation (SCAN) decoding, etc. This application does not limit the decoding method of the polar code. Exemplarily, for the Arikan Polar code, SC decoding, SCL decoding, SCS decoding, BP decoding, or SCAN decoding, etc. can be used. For the PC-Polar code, CA-Polar code, or PC-CA-Polar code, CA-SCL decoding, etc. can be used.

[0073] III. LDPC Code

[0074] The LDPC code is a class of linear block codes with a sparse parity-check matrix, that is, the density of non-zero elements in the parity-check matrix (which can also be called the parity-check matrix or LDPC matrix) is relatively low, that is, it is required that the number of zero elements in the parity-check matrix is much more than the number of non-zero elements. The LDPC code can be represented by the parity-check matrix or the Tanner graph. This application does not limit the specific representation form of the LDPC code. For the convenience of understanding, the following takes the LDPC code represented by the parity-check matrix as an example for introduction, which should not be regarded as a limitation of this application.

[0075] The parity-check matrix of the LDPC code can be referred to Figure 4 . In Figure 4Among them, the parity-check matrix includes a high-rate region, an incremental redundancy region, and a raptor-like region. The region enclosed by the dotted line represents the code rate. The main characteristic of the parity-check matrix is nesting, that is, the low-rate region can contain the high-rate region, and the high-rate region can be used as a sub-matrix of the low-rate region. In one possible implementation, different matrix regions can be selected according to the code rate as the parity-check matrix. For example, from the upper left region to the lower right region of the matrix, such as from row 0 to row M0 and from column 0 to column N0, etc. M0 and N0 can be integers greater than 0.

[0076] Optionally, the parity-check matrix of the LDPC code can be obtained from a base graph (BG) and a shifting value. The base graph can be determined based on the length of the information bits and the code rate. The code rate refers to the proportion of the bits before encoding (i.e., information bits) in the bits after encoding. Among them, the base graph can be divided into BG1 and BG2. Exemplarily, the applicable code length of the information bits for BG1 is from 308 bits to 8448 bits, and the code rate is from 0.25 to 0.95. The applicable code length of the information bits for BG2 is from 40 bits to 3840 bits, and the code rate is from 0.20 to 0.95.

[0077] It should be noted that in this application, the row numbers and column numbers of the base graph can be numbered starting from 0, and the row numbers and column numbers of the matrix can be numbered starting from 0. This application does not limit specifically from which value the row numbers and column numbers start to be numbered.

[0078] Generally, the base graph can include m×n matrix elements (entries) and can be represented by an m-row and n-column matrix. The value of the matrix element can be 0 or 1. Among them, the element with a value of 0 can be called a zero element, indicating that this element can be replaced by a Z*Z all-zero matrix (zero matfix). The element with a value of 1 can be called a non-zero element, indicating that this element can be replaced by a Z*Z circulant permutation matrix (circulant permutation matrix). That is to say, each matrix element represents an all-zero matrix or a circulant permutation matrix.

[0079] Among them, Z can be a positive integer, which can be called a lifting factor, or can also be called a liftingsize or a lifting factor, etc. For example, it can be determined according to the length of the information bits. Exemplarily, Z can be a j ∈{2, 3, 5, 7, 9, 11, 13, 15}, max(k j) ∈ {7, 7, 6, 5, 5, 5, 4, 4}. j is an integer greater than or equal to 0. For example, Z can be For example, Z can be For example, Z can be For example, Z can be For example, Z can be The rest are similar and will not be listed one by one here.

[0080] Optionally, there is an association relationship between Z and the translation value. For example, the set composed of multiple Zs (which can be called the set of lifting sizes, and will be introduced below with the set of lifting sizes as an example) can correspond to the translation value, such as the row number of the set of lifting sizes corresponding to the column number of the translation value. Optionally, the column number of the translation value can be described as a set index. Specifically, in Table 1, the set of lifting sizes can correspond to the set index. For example, {2, 4, 8, 16, 32, 64, 128, 256} corresponds to 0, and the rest are similar and will not be elaborated here.

[0081] Table 1 Set of lifting sizes (setofLDPCliftingsizeZ) in LDPC

[0082] <![CDATA[setindex(i Ls )]]> Set of lifting sizes (Z) 0 {2,4,8,16,32,64,128,256} 1 {3,6,12,24,48,96,192,384} 2 {5,10,20,40,80,160,320} 3 {7,14,28,56,112,224} 4 {9,18,36,72,144,288} 5 {11,22,44,88,176,352} 6 {13,26,52,104,208} 7 {15,30,60,120,240}

[0083] Next, a specific example is combined to describe the process of replacing the elements in the base graph with a Z*Z matrix. Specifically: Assume that the element value at the i-th row and j-th column in the base graph is 1, and its translation value is P i,j , P i,j is an integer greater than or equal to 0. The element with a value of 1 at the i-th row and j-th column in the base graph can be replaced by the Z*Z cyclic permutation matrix corresponding to P i,j , and this cyclic permutation matrix can be obtained by performing P i,j times of right cyclic shift on the Z*Z identity matrix. It can be seen that by replacing each element with a value of 0 in the base graph with a Z*Z all-zero matrix, and each element with a value of 1 with the Z*Z cyclic permutation matrix corresponding to its translation value, the parity-check matrix of the LDPC code can be obtained. The base graph can be used to indicate the position of the offset value, and the non-zero elements in the base graph correspond to the offset value. It can be seen that the size of the parity-check matrix H is (m*Z)*(n*Z). For example, assume Z = 4, each zero element is replaced by a 4*4 all-zero matrix, and assume P 2,3 = 2, then the non-zero element at the 2nd row and 3rd column is replaced by a 4*4 cyclic permutation matrix, which is obtained by performing 2 times of right cyclic shift on the 4*4 identity matrix. It should be noted that only an example is given here and is not limited thereto.

[0084] Among them, there are multiple possible implementation manners for LDPC codes. For example, Minimum Sum (MS) algorithm decoding or BP decoding, etc. The decoding manner of LDPC codes is not limited in this application. Optionally, MS decoding can be further divided into Offset-Minimum Sum (Offset-MS) decoding and Normalized-Minimum Sum (Normalized-MS) decoding. Offset-Minimum Sum decoding can be, for example, layered offset min-sum (LOMS) decoding.

[0085] The following will Figure 5 introduce the embodiments of this application in detail. It should be noted that the execution subject of the method provided in this application can be Figure 2 the first device and the second device in Figures 5 to 8 . Taking the first device as a terminal device and the second device as a network device as an example for introduction, it should not be regarded as a limitation to this application. Among them, the processing performed by a single execution subject (terminal device or network device) shown in the embodiments of this application can also be divided into being performed by multiple execution subjects, and these execution subjects can be logically and / or physically separated. For example, the processing performed by the network device can be divided into being performed by at least one of CU, DU, and RU. In addition, each embodiment of this application is only described by taking all steps included in it as an example, and should not be regarded as a specific limitation to this application. That is to say, the steps included in the embodiments of this application (such as Figures 5 to 8 any one of the embodiments) can be partially executed or all executed without logical conflict.

[0086] As Figure 5 shown, a coding method provided by an embodiment of this application includes but is not limited to the following steps:

[0087] 501. The terminal device performs polar code encoding on the first bit sequence to obtain a second bit sequence.

[0088] Among them, the first bit sequence may include at least one of the following: an information bit sequence, a frozen bit sequence, or a check bit sequence. The information bit sequence is a sequence composed of information bits, and the frozen bit sequence is a sequence composed of frozen bits. The check bit sequence may include a PC code and / or a CRC code. The following will introduce the first bit sequence in two cases, which should not be regarded as a limitation to this application. Specifically:

[0089] The first case: The first bit sequence includes an information bit sequence.

[0090] The second case: The first bit sequence includes an information bit sequence and a check bit sequence.

[0091] Among them, the second bit sequence can be a polar code. For example, for the first case above, the second bit sequence can be an Arikan Polar code. For the second case above, the second bit sequence can be a PC-Polar code, a CA-Polar code, or a PC-CA-Polar code.

[0092] In a possible implementation, the length Npolar of the second bit sequence can be determined according to the length T of the first bit sequence and the code rate R corresponding to the second bit sequence. For example, the length of the second bit sequence satisfies the following condition:

[0093] Among them, in this application is rounded up. Here, only rounding up is taken as an example, and it should not be regarded as a limitation to this application. For example, rounding up in this application can be replaced by rounding down.

[0094] R can be the code rate corresponding to the second bit sequence. R can be a predefined or preconfigured value greater than 0, or R can be indicated by the network device to the terminal device. For example, R can be 0.9517, or R can be (Nm × 0.9517) / Nm, such as 975 / 1024. Nm is the maximum length supported by polar code encoding. Optionally, Nm can be an integer greater than 0, such as Nm is 1024.

[0095] In a possible implementation, the information bit sequence in the first bit sequence can be part or all of the initial bit sequence. Among them, the initial bit sequence in this application can be called the mother code. The initial bit sequence can include the information bit sequence. Optionally, the initial bit sequence can also include a frozen bit sequence or not include a frozen bit sequence. Here, taking the initial bit sequence not including a frozen bit sequence as an example, the relationship between the first bit sequence and the initial bit sequence is introduced, and it should not be regarded as a limitation to this application. Specifically:

[0096] 1. The information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. For example, when the length of the initial bit sequence is less than the maximum length Kcb supported by LDPC encoding, the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. That is to say, the information bit sequence in the first bit sequence is all the bit sequences of the initial bit sequence, that is, the first bit sequence without cascaded parity check bit sequences is the same as the initial bit sequence.

[0097] Kcb can be determined based on the base graph. For example, when the base graph is BG1, Kcb is 8448. When the base graph is BG2, Kcb is 3840. Among them, the base graph is determined based on the length and code rate of the information bits in the initial bit sequence.

[0098] 2. The terminal device may segment the initial bit sequence based on the first segmentation length to obtain L bit sequences, where L is an integer greater than 1. For example, when the length of the initial bit sequence is greater than Kcb, the terminal device may segment the initial bit sequence based on the first segmentation length to obtain L bit sequences. That is to say, the information bit sequence in the first bit sequence is a partial bit sequence of the initial bit sequence, that is, the first bit sequence without concatenated parity bits is a partial bit sequence of the initial bit sequence.

[0099] Among them, the L bit sequences may include a fourth bit sequence. For example, for the first case above, the fourth bit sequence may be used as the first bit sequence. For the second case above, the terminal device may perform parity code encoding on the fourth bit sequence to obtain the first bit sequence. The parity code encoding may be PC encoding and / or CRC encoding. For example, taking CRC encoding of the fourth bit sequence as an example, the terminal device may concatenate 24-bit CRC code at the end of the fourth bit sequence to obtain the first bit sequence.

[0100] It should be noted that the length of the initial bit sequence being equal to Kcb may be used as a condition for "the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence", or as a condition for "the terminal device segments the initial bit sequence based on the first segmentation length to obtain L bit sequences", which is not limited here.

[0101] In a possible implementation manner, the first segmentation length may be determined based on the first value R and Kcb. For example, the first segmentation length satisfies the following conditions: Exemplarily, assuming R is 0.9517 and Kcb is 3840, K1 may be

[0102] In a possible implementation manner, the lengths of the L bit sequences may be partially the same, completely the same, or completely different. It should be understood that the process of encoding each bit sequence in the L bit sequences is similar. For example, reference may be made to Figure 5 , which will not be elaborated here.

[0103] In a possible implementation manner, the length of the information bit sequence in the first bit sequence may be greater than, equal to, or less than Nm. For example, when the length of the information bit sequence in the first bit sequence is greater than or equal to Nm, the terminal device may further segment the first bit sequence based on the second segmentation length to obtain P bit sequences, where P is an integer greater than 1. In this case, step 501 may include: the terminal device performs polar code encoding on the P bit sequences respectively to concatenate them into a second bit sequence. The present application does not limit the process of concatenating the bit sequences encoded by polar codes.

[0104] Optionally, the length of the second segment may be determined based on Nm and R, for example, satisfying the following conditions: Exemplarily, assuming R is 0.9517 and Nm is 1024, K2 may be

[0105] In a possible implementation, the lengths of the P bit sequences may be partially the same, exactly the same, or completely different. For example, the first bit sequence includes 2924 bits, the length of the second segment is 975, and the terminal device may divide the first bit sequence into 3 bit sequences based on the length of the second segment, with lengths of 975, 975, and 974 respectively. That is, the lengths of 2 of the 3 bit sequences are the same.

[0106] 502. The terminal device performs LDPC encoding on the second bit sequence to obtain a third bit sequence.

[0107] Wherein, the third bit sequence is an LDPC code. It may also be referred to as an LDPC codeword sequence.

[0108] Optionally, after step 502, step 503 may further be included.

[0109] 503. The terminal device sends a symbol sequence based on the third bit sequence.

[0110] Correspondingly, the network device receives the symbol sequence. For example, the network device receives the symbol sequence from the terminal device. Correspondingly, the terminal device sends the symbol sequence to the network device based on the third bit sequence.

[0111] Optionally, step 503 may include: the terminal device modulates the third bit sequence based on the modulation method to obtain a symbol sequence. The modulation method in this application may be quadrature phase shift keying (QPSK), binary phase shift keying (BPSK), 16 - quadrature amplitude modulation (QAM), 64 - QAM, 256 - QAM, 1024 - QAM, or 4096 - QAM, etc. This application does not make a limitation in this regard.

[0112] It can be seen that in the above embodiments, the terminal device may first perform polar code encoding on the first bit sequence to obtain a second bit sequence, and then perform LDPC encoding on the second bit sequence to obtain a third bit sequence, that is, an LDPC code. In this way, without losing the code rate of the LDPC code, the error floor of LDPC decoding can be reduced, and thus the error correction performance of the LDPC code can be improved.

[0113] Such asFigure 6 As shown, it is a decoding method provided by an embodiment of the present application. It should be noted that Figure 5 the shown embodiment or Figure 6 the shown embodiment can be executed alone, or Figure 5 the shown embodiment and Figure 6 the shown embodiment can be combined. For example, Figure 5 the shown embodiment is executed before Figure 6 step 601. The following will elaborate on Figure 6 the shown embodiment. Specifically, the method includes but is not limited to the following steps:

[0114] 601. The network device acquires a symbol sequence.

[0115] For example, the network device receives the symbol sequence from the terminal device.

[0116] 602. The network device determines a third bit sequence based on the symbol sequence.

[0117] Optionally, the network device can demodulate the symbol sequence based on the modulation method to obtain the third bit sequence. Among them, the third bit sequence is an LDPC code. It can also be called an LDPC codeword sequence.

[0118] 603. The network device performs LDPC decoding on the third bit sequence to obtain a second bit sequence.

[0119] Among them, the manner in which the network device performs LDPC decoding on the third bit sequence can refer to the above relevant description and will not be elaborated here. The second bit sequence is similar to the second bit sequence in Figure 5 step 501 and will not be elaborated here.

[0120] 604. The network device performs polar code decoding on the second bit sequence to obtain a first bit sequence.

[0121] Among them, the first bit sequence is similar to the first bit sequence in Figure 5 step 501 and will not be elaborated here. The manner in which the network device performs polar code decoding on the second bit sequence can refer to the above relevant description and will not be elaborated here.

[0122] It can be seen that in the above embodiment, the network device can first determine the third bit sequence based on the symbol sequence, so that the third bit sequence can be subjected to LDPC decoding to obtain the second bit sequence, and then the second bit sequence is subjected to polar code decoding to obtain the first bit sequence. This can be used to reduce the error floor of LDPC decoding, and further improve the error correction performance of the LDPC code.

[0123] Such as Figure 7As shown, another encoding method provided by the present application includes but is not limited to the following steps:

[0124] 701. The terminal device determines a second bit sequence and a third bit sequence based on the first bit sequence, and the third bit sequence includes the bit sequence in the base graph corresponding to the first bit sequence with a weight higher than the first threshold.

[0125] Among them, the first bit sequence may include at least one of the following: an information bit sequence, a frozen bit sequence, or a check bit sequence. The information bit sequence is a sequence composed of information bits, and the frozen bit sequence is a sequence composed of frozen bits. The check bit sequence may include a PC code and / or a CRC code. Hereinafter, the first bit sequence will be introduced in two cases, which should not be regarded as a limitation of the present application. Specifically:

[0126] First, the first bit sequence includes an information bit sequence.

[0127] Second, the first bit sequence includes an information bit sequence and a check bit sequence. In this case, the terminal device can perform check code encoding on the seventh bit sequence to obtain the first bit sequence. The check code encoding may be PC encoding and / or CRC encoding. For example, taking CRC encoding of the seventh bit sequence as an example, the terminal device can concatenate a 24-bit CRC code at the end of the seventh bit sequence to obtain the first bit sequence.

[0128] Optionally, step 701 may include: the terminal device determines a first value based on the first number of columns in the base graph with a weight higher than the first threshold, so that the third bit sequence can be determined from the first bit sequence based on the first value and the lifting factor corresponding to the first bit sequence, and then the second bit sequence can be determined based on the third bit sequence and the first bit sequence.

[0129] Among them, there are several implementation manners for the terminal device to determine the first value based on the first number of columns in the base graph with a weight higher than the first threshold. Specifically:

[0130] 1. The first value is the first number of columns. Among them, the first number of columns is an integer greater than or equal to 1. For example, the first number of columns can be 2 or 3, etc. Generally, the weights of the first T columns in the base graph are higher than the first threshold, and T is the first number of columns. Exemplarily, assuming that the first number of columns is 2, that is, the weights of the 0th column to the 1st column in the base graph are higher than the first threshold. Or, assuming that the first number of columns is 3, that is, the weights of the 0th column to the 2nd column in the base graph are higher than the first threshold. Among them, the first threshold can be a predefined or preconfigured value greater than 0.

[0131] 2. The terminal device determines the second column number with the highest reliability (i.e., the lowest bit error) from the other columns in the base map except those with weights higher than the first threshold, and determines a first value based on the first column number and the second column number. For example, the terminal device sorts the reliabilities of the other columns in ascending or descending order of reliability to count the column number with the highest reliability, obtaining the second column number. Here, the reliability from high to low can be understood as the bit error rate from low to high. Vice versa.

[0132] In a possible implementation manner, the first value can be the sum of the first column number and the second column number. Exemplarily, assume the base map includes 10 columns and the first column number is 2, that is, the weights of columns 0 to 1 in the base map are higher than the first threshold. The terminal device can sort the reliabilities of columns 2 to 9 in ascending or descending order of reliability to count the column number with the highest reliability, obtaining the second column number. For example, the second column number can be an integer greater than or equal to 1.

[0133] 3. The terminal device determines the third column number with a reliability higher than the second threshold from the other columns in the base map except those with weights higher than the first threshold, and determines a first value based on the first column number and the third column number. For example, the first value is the sum of the first column number and the third column number. Here, the third threshold can be a predefined or preconfigured value greater than 0.

[0134] Here, the weight in the base map can be understood as: the weight of the column in the base map. Here, only the column weight is taken as an example for introduction, which should not be regarded as a limitation to this application. It should be noted that in this application, the weight of the base map is determined by the number of non-zero elements. For example, the weight of a row refers to the number of non-zero elements in a row, and the weight of a column refers to the number of non-zero elements in a column. The weight of a row and the weight of a column can be simply referred to as row weight and column weight respectively.

[0135] In a possible implementation manner, the base map can be determined based on the length and code rate of the information bits in the initial bit sequence. The boosting factor corresponding to the first bit sequence can be determined based on the length of the information bits in the initial bit sequence. Here, the information bit sequence in the first bit sequence can be part or all of the bit sequence of the initial bit sequence. The initial bit sequence can include an information bit sequence. Optionally, the initial bit sequence can also include a frozen bit sequence or not include a frozen bit sequence. Here, taking the initial bit sequence not including a frozen bit sequence as an example, the relationship between the first bit sequence and the initial bit sequence is introduced, which should not be regarded as a limitation to this application. Specifically:

[0136] 1. The information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. For example, when the length of the initial bit sequence is less than the maximum length Kcb supported by LDPC coding, the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence. That is to say, the information bit sequence in the first bit sequence is all the bit sequences of the initial bit sequence, that is, the first bit sequence without the concatenated parity bit sequence is the same as the initial bit sequence.

[0137] Kcb can be determined based on the base graph. For example, when the base graph is BG1, Kcb is 8448. When the base graph is BG2, Kcb is 3840. Among them, the base graph is determined based on the length of the information bits and the code rate in the initial bit sequence.

[0138] 2. The terminal device can segment the initial bit sequence based on the first segmentation length to obtain X bit sequences, where X is an integer greater than 1. For example, when the length of the initial bit sequence is greater than Kcb, the terminal device can segment the initial bit sequence based on the first segmentation length to obtain X bit sequences. Among them, the X bit sequences can include the first bit sequence or the seventh bit sequence. For example, for the first case above, the X bit sequences include the first bit sequence. That is to say, the information bit sequence in the first bit sequence is a partial bit sequence of the initial bit sequence. For the second case above, the X bit sequences include the seventh bit sequence. That is to say, the seventh bit sequence is a partial bit sequence of the initial bit sequence.

[0139] It should be noted that the length of the initial bit sequence being equal to Kcb can be used as a condition for "the information bit sequence in the first bit sequence is the information bit sequence in the initial bit sequence", or, as a condition for "the terminal device segments the initial bit sequence based on the first segmentation length to obtain X bit sequences", which is not limited here.

[0140] Optionally, the first segmentation length can be determined based on the first value and the lifting factor. For example, the first segmentation length can be determined based on the first value, the lifting factor, and the second value. The second value is determined based on the total number of columns of the base graph and the first value. For example, the second value is the difference between the total number of columns of the base graph and the first value.

[0141] Optionally, the first segmentation length can also be determined based on the third value. The third value is the code rate corresponding to the second bit sequence. The third value can be a predefined or preconfigured value greater than 0, or, the third value can be indicated by the network device to the terminal device. For example, the third value can be 0.9517, or, the third value can be (Nm × 0.9517) / Nm, such as 975 / 1024. Nm is the maximum length supported by polar code coding. Nm can be an integer greater than 0. For example, Nm is 1024.

[0142] In a possible implementation, the first segment length may satisfy the following conditions: Where a is the first value, b is the second value, R is the third value, and Z is the boosting factor. Exemplarily, assume Z is 384, a is 2, b is 8, and R is 0.9517. Where a×Z = M1. Therefore, K1 = M1 + M2.

[0143] Where the terminal device determines a third bit sequence from the first bit sequence based on the first value and the boosting factor corresponding to the first bit sequence. For example, it may include: The terminal device selects the first Q bits from the first bit sequence as the third bit sequence based on the product Q of the first value and the boosting factor. For example, if the first value is 2 and the boosting factor is 104, Q may be 208.

[0144] Where the terminal device determines a second bit sequence based on the third bit sequence and the first bit sequence. There are several implementation manners as follows. Specifically:

[0145] 1. The second bit sequence is the other bit sequence in the first bit sequence except the third bit sequence. For example, when the length of the other bit sequence is less than Nm, the second bit sequence is the other bit sequence.

[0146] 2. The terminal device segments the other bit sequence based on the second segment length to obtain Y bit sequences, and the Y bit sequences include the second bit sequence. For example, when the length of the other bit sequence is greater than Nm, the terminal device segments the other bit sequence based on the second segment length to obtain Y bit sequences. Where Y is an integer greater than 1. The second segment length may be determined based on Nm and the third value. For example, the second segment length satisfies the following conditions:

[0147] It should be noted that the length of the other bit sequence being equal to Nm can be used as a condition for "the second bit sequence is the other bit sequence", or as a condition for "the terminal device segments the other bit sequence based on the second segment length to obtain Y bit sequences", which is not limited herein.

[0148] 702. The terminal device performs polar code encoding on the second bit sequence to obtain a fourth bit sequence.

[0149] For example, for the first case described above, step 702 can be understood as: the terminal device performs checksum encoding on the second bit sequence to obtain a sixth bit sequence, and then performs polar code encoding on the sixth bit sequence to obtain a fourth bit sequence. The fourth bit sequence can be a polar code, such as a PC-Polar code, a CA-Polar code, or a PC-CA-Polar code, etc.

[0150] In a possible implementation, the length Npolar of the fourth bit sequence can be determined according to the lengths T and R of the second bit sequence.

[0151] For example, the length of the fourth bit sequence satisfies the following conditions:

[0152] 703. The terminal device performs LDPC encoding on the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence.

[0153] The fifth bit sequence is an LDPC code. It can also be called an LDPC codeword sequence. In a possible implementation, step 703 can include: the terminal device performs LDPC encoding on the bit sequence after concatenating the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence. For example, the fourth bit sequence is concatenated at the end of the third bit sequence.

[0154] Optionally, after step 703, step 704 can also be included.

[0155] 704. The terminal device sends a symbol sequence based on the fifth bit sequence.

[0156] Correspondingly, the network device receives the symbol sequence. For example, the network device receives the symbol sequence from the terminal device. Correspondingly, the terminal device sends the symbol sequence to the network device based on the fifth bit sequence.

[0157] Optionally, step 704 can include: the terminal device modulates the fifth bit sequence based on a modulation method to obtain a symbol sequence.

[0158] It can be seen that in the above embodiments, the terminal device can determine a second bit sequence and a third bit sequence based on the first bit sequence. The third bit sequence includes the bit sequence in the base graph corresponding to the first bit sequence with a weight higher than the first threshold. That is to say, the weight corresponding to the second bit sequence is lower than the weight corresponding to the third bit sequence. Further, the terminal device can perform polar code encoding on the second bit sequence, which is equivalent to providing additional protection for the second bit sequence with a lower weight by means of polar code encoding to improve the error correction performance. For the third bit sequence with a higher weight, it can be LDPC-encoded together with the result of polar code encoding (i.e., the fourth bit sequence obtained by performing polar code encoding on the second bit sequence). In this way, the error floor of LDPC decoding can be reduced, thereby improving the error correction performance of the LDPC code. At the same time, the LDPC coding load brought by Polar outer code encoding can also be reduced, thereby reducing the code rate of the LDPC code and improving the waterfall region performance.

[0159] As Figure 8 shown, another decoding method provided by an embodiment of the present application is as follows. It should be noted that Figure 7 the embodiment shown in Figure 8 or the embodiment shown in Figure 7 can be executed alone, or, Figure 8 the embodiment shown in Figure 7 and the embodiment shown in Figure 8 can be combined. For example, Figure 8 the embodiment shown in

[0160] 801. The network device obtains a symbol sequence.

[0161] For example, the network device receives the symbol sequence from the terminal device.

[0162] 802. The network device determines a fifth bit sequence based on the symbol sequence.

[0163] Optionally, the network device can demodulate the symbol sequence based on the modulation method to obtain the fifth bit sequence. Among them, the fifth bit sequence is an LDPC code. It can also be called an LDPC codeword sequence.

[0164] 803. The network device performs LDPC decoding on the fifth bit sequence to obtain a third bit sequence and a fourth bit sequence.

[0165] For example, the network device performs LDPC decoding on the fifth bit sequence to obtain a bit sequence after concatenation of the third bit sequence and the fourth bit sequence. Among them, the method for the network device to perform LDPC decoding on the fifth bit sequence can refer to the above relevant description and will not be elaborated here. The third bit sequence and the fourth bit sequence are respectively Figure 7The third bit sequence and the fourth bit sequence in step 701 are similar and will not be elaborated here. The length of the fourth bit sequence satisfies the following conditions: For example, the last Npolar bits of the bit sequence after concatenating the third bit sequence and the fourth bit sequence can be used as the fourth bit sequence, and the remaining bits can be used as the third bit sequence. That is, the difference between the length of the bit sequence after concatenating the third bit sequence and the fourth bit sequence and Npolar is the length of the third bit sequence.

[0166] 804. The network device decodes the fourth bit sequence using polar codes to obtain the second bit sequence.

[0167] Among them, the second bit sequence is Figure 7 similar to the second bit sequence in step 701 and will not be elaborated here. The method for the network device to decode the fourth bit sequence using polar codes can refer to the above relevant description and will not be elaborated here.

[0168] 805. The network device determines the first bit sequence based on the third bit sequence and the second bit sequence.

[0169] For example, the first bit sequence includes the third bit sequence and the second bit sequence. For example, the bit sequence obtained by concatenating the second bit sequence at the end of the third bit sequence is the first bit sequence. Among them, the first bit sequence is Figure 7 similar to the first bit sequence in step 701 and will not be elaborated here. Optionally, when the first bit sequence includes a check bit sequence, the network device can also perform a check on the first bit sequence. For example, PC checksum and / or CRC check, etc.

[0170] It can be seen that in the above embodiments, the network device can first determine the fifth bit sequence based on the symbol sequence, then perform LDPC decoding on the fifth bit sequence to obtain the third bit sequence and the fourth bit sequence, so as to perform polar code decoding on the fourth bit sequence to obtain the second bit sequence. In this way, the first bit sequence can be determined based on the third bit sequence and the second bit sequence. Since the network device performs polar code decoding on a partial bit sequence (such as the fourth bit sequence) in the LDPC decoding result, the decoding delay is reduced and the decoding efficiency is improved. At the same time, it can also be used to reduce the error floor of LDPC decoding, and thus the error correction performance of LDPC codes can be improved.

[0171] Next, specific examples will be used to Figures 5 to 8 elaborate in detail the beneficial effects of the

[0172] I. Examples of Figure 5 the encoding method and Figure 6 the decoding method shown

[0173] Assume that the length of information bit U is 1000 bits, combined with Figure 5 The encoding method shown and Figure 6 The decoding method shown in the figure can be found in Figure 9 Polar-LDPC encoding and decoding process. For example, the terminal device sequentially performs CRC24 encoding, polar code encoding, LDPC encoding, and QPSK modulation on the information bits, and then sends the information to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device sequentially performs demodulation, LOMS decoding, and polar code decoding on the information to obtain The information bit U is encoded by CRC24 and polar code in turn, which is equivalent to adding polar redundancy check bits to the CRC codeword. The length of the bit sequence after the information bit is encoded by CRC24 is 1024 bits, that is, Figure 9 K_Ca-polar = 1024 bits. After 1024 bits are encoded by polar code, the length of the bit sequence N_polar is N_polar=K_ldpc. Further, after 1076 bits are LDPC-coded, the length of the bit sequence is N_ldpc, such as 3000 bits.

[0174] in, Figure 9 The LDPC encoding and decoding process is as follows: the terminal device performs CRC24 encoding, LDPC encoding, and QPSK modulation on the information bits, and then sends the information to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device demodulates and LOMS decodes the information in turn to obtain in addition, Figure 9 The number of iterations of LOMS decoding can be 15 or 25, the polar code decoding can be SC decoding or SCL decoding, and the path width L can be 8. The length is 1000 bits.

[0175] Below Figure 9 Based on the examples shown, combined with Figure 10 illustrate Figure 5 The encoding method shown and Figure 6 The beneficial effects of the decoding method shown. Specifically, Figure 10 In the figure, the horizontal axis represents SNR, ie, Es / N0, and the vertical axis represents BLER.

[0176] Among them, Figure 10 In 10-1, the number of iterations of LOMS decoding is 15. The curve of Polar-LDPC shows Figure 9 The BLER performance of the Polar-LDPC encoding and decoding process in . The LDPC curve representsFigure 9 The BLER performance corresponding to the LDPC encoding and decoding processes in -6 . It can be seen that when the BLER is less than or equal to 6×10

[0177] In Figure 10 with a value of 10-2, the number of iterations of LOMS decoding is 25. The curve of Polar-LDPC represents Figure 9 the BLER performance corresponding to the Polar-LDPC encoding and decoding processes in Figure 9 . The curve of LDPC represents -6 the BLER performance corresponding to the LDPC encoding and decoding processes in

[0178] II. Examples of the encoding method and Figure 7 the decoding method shown in Figure 8 are as follows

[0179] Suppose the length of the information bit U is 1000 bits. Combining Figure 7 the encoding method shown in Figure 8 and Figure 11 the decoding method shown in

[0180] Figure 11 the process of Polar-LDPC encoding and decoding 1 or Polar-LDPC encoding and decoding 2 in . For example, the terminal device determines the lifting factor Z based on the length of the information bit U. For instance, when the length of the information bit is 1000 bits and the length N_ldpc after LDPC encoding is 3000 bits, BG2 can be selected with a total number of columns of 10 and Z = 104. Since the column weight of the first T columns of BG2 is very large, the corresponding information bits are relatively reliable and not prone to errors. Therefore, no additional protection is required through polar code encoding. That is, the bits that cause the error floor of LDPC are mainly distributed at positions corresponding to non-large column weights. For example, when T is 2, the column weights of the 0th to 1st columns of BG2 are very large, and the bits corresponding to the 2nd to 9th columns (non-large column weights) are prone to errors. The number of bits with large column weights (K_B) is Z×2 = 208.The Polar-LDPC encoding and decoding 1 process is as follows: The terminal device sequentially performs CRC24 encoding and polar code encoding on 792 bits. After CRC24 encoding of 792 bits, the bit sequence length K_S_CRC is 816 bits. After polar code encoding of 816 bits, the bit sequence length N_polar is 858 bits. Further, after concatenating 208 bits and 858 bits (with a length K_ldpc of 1066 bits), LDPC encoding and QPSK modulation are sequentially performed, and then information is sent to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device sequentially demodulates and performs LOMS decoding on the information to obtain the bits that need to be decoded by the polar code, with a length of K_ldpc - K_B = 858 bits. Bits with a large column weight of 208 bits can also be obtained. In this way,

[0181] Figure 11 The Polar-LDPC encoding and decoding 2 process is as follows: The terminal device performs CRC24 encoding on the information bits to obtain a bit length K_CRC of 1024 bits. Among them, the bit sequence length K_polar that needs to be encoded by the polar code is 816 bits, and the bit sequence length K_B that does not need to be encoded by the polar code is 208 bits. Further, 816 bits are encoded by the polar code to obtain a bit sequence length N_polar of 858 bits. In this way, after concatenating 208 bits and 858 bits (with a length K_ldpc of 1066 bits), LDPC encoding and QPSK modulation are sequentially performed, and then information is sent to the network device through the AWGN channel. Correspondingly, after receiving the information, the network device sequentially demodulates and performs LOMS decoding on the information to obtain the bits that need to be decoded by the polar code, with a length of K_ldpc - K_B = 858 bits. Bits with a large column weight of 208 bits can also be obtained. In this way, Among them, Figure 11 the number of iterations of LOMS decoding can be 15 or 25, the polar code decoding can be SC decoding or SCL decoding, and the path width L can be 8. The length is 1000 bits. In addition, Figure 11 the LDPC encoding and decoding process of Figure 9 is similar to the LDPC encoding and decoding process of

[0182] Below, based on the example shown in Figure 11 and combined with Figure 12 it is explained Figure 7 the beneficial effects of the encoding method shown in Figure 8 and the decoding method shown in Specifically, inFigure 12 Among them, the horizontal coordinate represents SNR, i.e., Es / N0, and the vertical coordinate represents BLER.

[0183] In Figure 12 of 12-1, the number of iterations of LOMS decoding is 15, and the large column weight is the first 2 columns of BG2. Figure 9 The curve of the shown Polar-LDPC represents Figure 9 the BLER performance corresponding to the Polar-LDPC encoding and decoding process in Figure 11 The curve of LDPC represents the BLER performance corresponding to the LDPC encoding and decoding process in Figure 11 The curve of the shown Polar-LDPC represents Figure 11 the BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in -6 In the case of Figure 9 the shown Polar-LDPC encoding and decoding, Figure 11 the Polar-LDPC encoding and decoding 1 in

[0184] In Figure 12 of 12-2, the number of iterations of LOMS decoding is 25, and the large column weight is the first 2 columns of BG2. Figure 9 The curve of the shown Polar-LDPC represents Figure 9 the BLER performance corresponding to the Polar-LDPC encoding and decoding process in Figure 11 The curve of LDPC represents the BLER performance corresponding to the LDPC encoding and decoding process in Figure 11 The curve of the shown Polar-LDPC represents Figure 11 the BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in -5 In the case of Figure 9 the shown Polar-LDPC encoding and decoding, Figure 11 the Polar-LDPC encoding and decoding 1 in

[0185] In Figure 12 of 12-3, the number of iterations of LOMS decoding is 15, and the large column weight is the first 3 columns of BG2. The curve of LDPC represents Figure 11 the BLER performance corresponding to the LDPC encoding and decoding process in Figure 11 The curve of the shown Polar-LDPC represents Figure 11The BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in []. It can be seen that when the BLER is less than or equal to 10 -5 In the case of Figure 9 The Polar-LDPC encoding and decoding shown, Figure 11 The Polar-LDPC encoding and decoding 1 in [] and the corresponding error correction performance can still exponentially decrease with the increase of SNR, without error floor.

[0186] In Figure 12 In 12-4 of [], the number of iterations of LOMS decoding is 25, and the first 3 columns with large column weight are those of BG2. The LDPC curve represents Figure 11 The BLER performance corresponding to the LDPC encoding and decoding process in []. Figure 11 The curve of the Polar-LDPC shown represents Figure 11 The BLER performance corresponding to the Polar-LDPC encoding and decoding 1 process in []. It can be seen that when the BLER is less than or equal to 10 -5 In the case of Figure 9 The Polar-LDPC encoding and decoding shown, Figure 11 The Polar-LDPC encoding and decoding 1 in [] and the corresponding error correction performance can still exponentially decrease with the increase of SNR, without error floor.

[0187] In addition, comparing 12-1 of [] with Figure 12 12-3 of [], or comparing 12-2 of [] with Figure 12 12-4 of [], Figure 12 In 12-3 of [] and Figure 12 12-4 of [], for the information bits corresponding to the first 3 columns with large column weight, no polar code encoding is performed, further reducing the redundant bits added by the outer code of the polar code. The performance loss in the waterfall region is reduced from 0.2dB to about 0.1xdB, improving the performance in the waterfall region. Figure 12 Figure 12

[0188]

[0189] It can be understood that in order to implement the above functions, the above device includes the corresponding hardware structure and / or software module for executing each function. Those skilled in the art should easily realize that, combining the units and algorithm steps of each example described in the embodiments disclosed in this article, this application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a certain function is executed in the way of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods for each specific application to implement the described function, but such implementation should not be considered to exceed the scope of this application.

[0189] Embodiments of the present application can divide functional modules for a terminal device or a network device according to the above method examples. For example, each functional module can be divided corresponding to each function, or two or more functions can be integrated into one processing module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. It should be noted that the division of modules in the embodiments of the present application is illustrative, only a logical function division, and there can be other division methods in actual implementation.

[0190] See Figure 13 , Figure 13 which is a schematic structural diagram of a communication device provided by an embodiment of the present application. The communication device 1300 can be applied to the method shown in any of the above Figures 5 to 8 embodiments. As shown in Figure 13 , the communication device 1300 includes: a processing module 1301 and a transceiver module 1302. The processing module 1301 can be one or more processors, and the transceiver module 1302 can be a transceiver or a communication interface. The communication device can be used to implement the terminal device or network device involved in any of the above method embodiments, or to implement the functions of the network element involved in any of the above method embodiments. The network element or network function can be a network element in a hardware device, a software function running on dedicated hardware, or a virtualized function instantiated on a platform (such as a cloud platform). Optionally, the communication device 1300 can further include a storage module 1303 for storing program codes and data of the communication device 1300.

[0191] For example, when the communication device is used as a terminal device or a chip applied to a terminal device and executes the steps performed by the terminal device in the above method embodiments. The transceiver module 1302 is specifically used to perform Figures 5 to 8 the sending and / or receiving actions performed by the terminal device in any of the above embodiments, for example, supporting other processes of the terminal device to execute the technologies described herein. The processing module 1301 can be used to support the communication device 1300 to perform the processing actions in the above method embodiments. For example, it supports the terminal device to execute other processes of the technologies described herein.

[0192] Exemplarily, the processing module 1301 is used to: determine a second bit sequence and a third bit sequence based on a first bit sequence, where the third bit sequence includes the bit sequences in the base graph corresponding to the first bit sequence with weights higher than a first threshold; perform polar code encoding on the second bit sequence to obtain a fourth bit sequence; perform low-density parity-check (LDPC) encoding on the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence.

[0193] In a possible implementation manner, when determining a second bit sequence and a third bit sequence based on a first bit sequence, the processing module 1301 is configured to: determine a first value based on a first number of columns in a base graph whose weight is higher than a first threshold; determine the third bit sequence from the first bit sequence based on the first value and a lifting factor corresponding to the first bit sequence; and determine the second bit sequence based on the third bit sequence and the first bit sequence.

[0194] In a possible implementation manner, when determining the first value based on the first number of columns in the base graph whose weight is higher than the first threshold, the processing module 1301 is configured to: determine a second number of columns with the highest reliability from other columns in the base graph except those whose weight is higher than the first threshold; and determine the first value based on the first number of columns and the second number of columns.

[0195] In a possible implementation manner, when performing polar code encoding on the second bit sequence to obtain a fourth bit sequence, the processing module 1301 is configured to: perform parity check code encoding on the second bit sequence to obtain a sixth bit sequence; and perform polar code encoding on the sixth bit sequence to obtain the fourth bit sequence.

[0196] In a possible implementation manner, the processing module 1301 is further configured to perform parity check code encoding on the sixth bit sequence to obtain a first bit sequence.

[0197] In a possible implementation manner, the processing module 1301 is further configured to segment an initial bit sequence based on a first segmentation length to obtain X bit sequences, where the X bit sequences include the first bit sequence or a seventh bit sequence, and X is an integer greater than 1; wherein, the first segmentation length is determined based on the first value and the lifting factor.

[0198] In a possible implementation manner, when determining the second bit sequence based on the third bit sequence and the first bit sequence, the processing module 1301 is configured to segment other bit sequences in the first bit sequence except the third bit sequence based on a second segmentation length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence, and Y is an integer greater than 1; wherein, the second segmentation length is determined based on the maximum length supported by polar code encoding and a third value.

[0199] In a possible implementation manner, the transceiver module 1302 is further configured to send a symbol sequence based on the third bit sequence.

[0200] An example is that when the communication device is a network device or a chip applied to a network device and executes the steps performed by the network device in the above method embodiments. The transceiver module 1302 is specifically configured to execute Figures 5 to 8Any action of sending and / or receiving performed by a network device in any of the embodiments, such as other processes that support the network device in performing the techniques described herein. The processing module 1301 can be used to support the communication device 1300 in performing the processing actions in the above method embodiments, for example, supporting the network device in performing other processes of the techniques described herein.

[0201] Exemplarily, the processing module 1301 is configured to: obtain a symbol sequence; determine a fifth bit sequence based on the symbol sequence; perform LDPC decoding on the fifth bit sequence to obtain a third bit sequence and a fourth bit sequence; perform polar code decoding on the fourth bit sequence to obtain a second bit sequence; determine a first bit sequence based on the third bit sequence and the second bit sequence.

[0202] In a possible implementation, when the terminal device or the network device is a chip, the transceiver module 1302 can be a communication interface, a pin, a circuit, etc. The communication interface can be used to input data to be processed to the processor and can output the processing result of the processor outward. In a specific implementation, the communication interface can be a general purpose input output (GPIO) interface and can be connected to multiple peripheral devices (such as a display (LCD), a camera, a radio frequency (RF) module, an antenna, etc.). The communication interface is connected to the processor through a bus.

[0203] The processing module 1301 can be a processor that can execute the computer-executable instructions stored in the storage module to cause the chip to execute Figures 5 to 8The method related to any of the illustrated embodiments. Further, the processor may include a controller, an arithmetic unit, and registers. Exemplarily, the controller is mainly responsible for instruction decoding and issuing control signals for the operations corresponding to the instructions. The arithmetic unit is mainly responsible for performing fixed-point or floating-point arithmetic operations, shift operations, and logical operations, etc., and can also perform address operations and conversions. The registers are mainly responsible for storing register operands and intermediate operation results temporarily stored during the execution of instructions, etc. In a specific implementation, the hardware architecture of the processor may be an ASIC architecture, a microprocessor without interlocked piped stages architecture (MIPS), an advanced RISC machines (ARM) architecture, or a network processor (NP) architecture, etc. The processor may be single-core or multi-core. The storage module may be a storage module within the chip, such as registers, caches, etc. The storage module may also be a storage module located outside the chip, such as ROM or other types of static storage devices that can store static information and instructions, RAM, etc.

[0204] It should be noted that the functions corresponding to the processor and the interface can be implemented through hardware design, software design, or a combination of hardware and software, and there is no limitation here.

[0205] Figure 14 This is a schematic structural diagram of another communication device provided by an embodiment of the present application. It can be understood that the communication device 1410 includes means in the form of, for example, modules, units, elements, circuits, or interfaces, etc., which are appropriately configured together to execute the present solution. The communication device 1410 may be the above-mentioned terminal device or network device, or a component (such as a chip) in these devices, to implement the method described in the above method embodiments. The communication device 1410 includes one or more processors 1411. The processor 1411 may be a general-purpose processor or a dedicated processor, etc. For example, it may be a baseband processor or a central processing unit. The baseband processor may be used to process communication protocols and communication data, and the central processing unit may be used to control the communication device (such as a terminal device, a network device, or a chip, etc.), execute software programs, and process the data of the software programs.

[0206] Optionally, in one design, the processor 1411 may include a program 1413 (sometimes also referred to as code or instructions), and the program 1413 may be run on the processor 1411, so that the communication device 1410 executes the method described in the above embodiments. In another possible design, the communication device 1410 includes a circuit (Figure 14 (not shown), the circuit is used to implement the functions of the terminal device, network device, etc. in the above embodiments. Optionally, the communication device 1410 may include one or more memories 1412, on which there is a program 1414 (sometimes also referred to as code or instructions), and the program 1414 can be run on the processor 1411, so that the communication device 1410 executes the method described in the above method embodiments. Optionally, data may also be stored in the processor 1411 and / or the memory 1412. The processor and the memory can be set separately or integrated together.

[0207] Optionally, the communication device 1410 may further include a transceiver 1415 and / or an antenna 1416. The processor 1411 is sometimes also referred to as a processing unit, which controls the communication device (such as a terminal device or a network device). The transceiver 1415 is sometimes also referred to as a transceiver unit, transceiver, transceiver circuit, or transceiver, etc., and is used to implement the transceiver function of the communication device through the antenna 1416.

[0208] The embodiment of the present application also provides a communication device, which includes at least one processor; wherein, the at least one processor is configured to execute Figures 5 to 8 the method described in any item of any embodiment in

[0209] The embodiment of the present application also provides a computer-readable storage medium, which stores computer instructions, and when the computer instructions are executed, the computer is made to execute as Figures 5 to 8 the method described in any item of any embodiment in

[0210] The embodiment of the present application also provides a computer program product, which includes: computer program code, and when the computer program code is run on the computer, the computer is made to execute as Figures 5 to 8 the method described in any item of any embodiment in

[0211] The embodiment of the present application also provides a chip, which includes at least one processor and an interface, and the processor is used to read and execute the instructions stored in the memory. When the instructions are run, the chip is made to execute as Figures 5 to 8 the method described in any item of any embodiment in

[0212] The units described above as separate components may or may not be physically separated. The components shown as units may or may not be physical units, that is, they may be located in one place, or they may be distributed across multiple network units. Some or all of the units can be selected according to actual needs to achieve the objectives of the solution of the embodiments of the present application. In addition, the network element units in the various embodiments of the present application can be integrated in a processing unit, or each unit can exist physically alone, or two or more units can be integrated in one unit. The above-mentioned integrated units can be implemented in the form of hardware or in the form of software network element units.

[0213] If the above-mentioned integrated units are implemented in the form of software network element units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the part that essentially contributes to the technical solution of the present application, or all or part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium and includes several instructions for causing a computer device (which can be a personal computer, a terminal device, a cloud server, or a network device, etc.) to execute all or part of the steps of the above-mentioned methods in the various embodiments of the present application. The foregoing storage medium includes: various media such as USB flash drives, mobile hard disks, read-only memories (ROM, Read-Only Memory), random access memories (RAM, Random Access Memory), magnetic disks, or optical discs that can store program codes. The above is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of various equivalent modifications or substitutions, and these modifications or substitutions should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A coding method, characterized in that, Including: Determining a second bit sequence and a third bit sequence based on a first bit sequence, where the third bit sequence includes a bit sequence in a base graph corresponding to the first bit sequence with a weight higher than a first threshold; Performing polar code encoding on the second bit sequence to obtain a fourth bit sequence; Performing low-density parity-check (LDPC) encoding on the third bit sequence and the fourth bit sequence to obtain a fifth bit sequence.

2. The method according to claim 1, wherein The determining the second bit sequence and the third bit sequence based on the first bit sequence includes: Determining a first value based on a first number of columns in the base graph with a weight higher than the first threshold; Determining the third bit sequence from the first bit sequence based on the first value and a lifting factor corresponding to the first bit sequence; Determining the second bit sequence based on the third bit sequence and the first bit sequence.

3. The method according to claim 1 or 2, characterized in that, The first number of columns is an integer greater than or equal to 1.

4. The method according to any one of claims 1 to 3, characterized in that The determining the first value based on the first number of columns in the base graph with a weight higher than the first threshold includes: Determining a second number of columns with the highest reliability from other columns in the base graph except those with a weight higher than the first threshold; Determining the first value based on the first number of columns and the second number of columns.

5. The method according to any one of claims 1-4, characterized in that The performing polar code encoding on the second bit sequence to obtain a fourth bit sequence includes: Performing check code encoding on the second bit sequence to obtain a sixth bit sequence; Performing polar code encoding on the sixth bit sequence to obtain the fourth bit sequence.

6. The method according to any one of claims 1-4, characterized in that The method further includes: Performing check code encoding on a seventh bit sequence to obtain the first bit sequence.

7. The method according to any one of claims 1-6, characterized in that The method further includes: Segmenting an initial bit sequence based on a first segmentation length to obtain X bit sequences, where the X bit sequences include the first bit sequence or the seventh bit sequence, and X is an integer greater than 1; Wherein, the first segmentation length is determined based on the first value and the lifting factor.

8. The method according to claim 7, characterized in that, The first segmentation length being determined based on the first value and the lifting factor includes: The first segmentation length is determined based on the first value, the lifting factor, and a second value; wherein, the second value is determined based on the total number of columns in the base graph and the first value.

9. The method according to claim 7 or 8, characterized in that The length of the first segment satisfies the following conditions: Wherein, a is the first value, b is the second value, R is a third value, and Z is the lifting factor.

10. The method according to any one of claims 1-9, characterized in that, The determining the second bit sequence based on the third bit sequence and the first bit sequence includes: Segmenting other bit sequences in the first bit sequence except the third bit sequence based on a second segmentation length to obtain Y bit sequences, where the Y bit sequences include the second bit sequence, and Y is an integer greater than 1; Wherein, the second segmentation length is determined based on the maximum length supported by polar code encoding and a third value.

11. The method according to claim 10, characterized in that The second segmented length satisfies the following conditions: Wherein, Nm is the maximum length supported by polar code encoding, and R is the third value.

12. A communication device, characterized in that, Including units or modules for implementing the method according to any one of claims 1 to 11.

13. A communication device, characterized in that, The communication device includes at least one processor; wherein, the at least one processor is configured to execute the method described in any one of claims 1 to 11.

14. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer instructions, and when the computer instructions are executed, the computer is caused to execute the method described in any one of claims 1 to 11.

15. A computer program product, characterized in that, The computer program product includes: computer program code, and when the computer program code is run by a computer, the computer is caused to execute the method described in any one of claims 1 to 11.

16. A chip, characterized in that, The chip includes at least one processor and an interface, the processor is used to read and execute instructions stored in a memory, and when the instructions are run, the chip is caused to execute the method described in any one of claims 1 to 11.

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