High-speed high-voltage PIN large-opening-rate switch driving circuit

Abstract

The invention provides a high-speed high-voltage PIN large-opening-rate switch driving circuit. The high-speed high-voltage PIN large-opening-rate switch driving circuit is formed by connecting a grid driving circuit and a field tube driving circuit. A control signal from the outside is transmitted to the input end of the gate drive circuit, and the output end of the gate drive circuit is connected with the input circuit of the field tube drive circuit. The output end of the field tube driving circuit outputs a driving signal, and the driving signal serves as a final output signal of the driving circuit. The circuit is small in size and wide in applicable voltage range, and has shorter switching time smaller than 15 ns compared with the prior art.

Description

Technical Field

[0001] The present invention relates to the field of electronic technology, and particularly to a high-speed high-voltage PIN large-opening ratio switch drive circuit. Background Art

[0002] The switch drive circuit is a crucial part of electronic devices. It is responsible for controlling the on and off of switch elements, thereby realizing the opening and closing of the circuit.

[0003] The PIN diode can conduct or block current under forward or reverse bias and has the characteristic of fast switching, making it suitable as a high-speed switching electronic switch. When a control signal is input to the drive circuit, after a series of processing and amplification, it drives the PIN diode to conduct or cut off, thereby realizing the control of the load current.

[0004] The existing high-voltage PIN high-power switch drive circuits are large in volume and slow in switching time, with the switching time reaching several microseconds or even more than ten microseconds. Based on this, the present application proposes a drive circuit with a small circuit volume and fast switching time. Summary of the Invention

[0005] The purpose of the present invention is to overcome the shortcomings of the prior art and provide a high-speed high-voltage PIN large-opening ratio switch drive circuit, which is specifically realized through the following technical solutions:

[0006] A high-speed high-voltage PIN large-opening ratio switch drive circuit is composed of a gate drive circuit and a field-effect transistor drive circuit connected. The control signal from the outside is transmitted to the input end of the gate drive circuit, and the output end of the gate drive circuit is connected to the input circuit of the field-effect transistor drive circuit. The output end of the field-effect transistor drive circuit outputs a drive signal, and this drive signal serves as the final output signal of this drive circuit.

[0007] Optionally or preferably, the gate drive circuit receives the control signal and outputs a signal V0 to the field-effect transistor drive circuit. When the control signal is at a low level, the output signal V0 is at a high level; when the control signal is at a high level, the output signal V0 is at a low level.

[0008] Optionally or preferably, the gate drive circuit includes a triode Q1 and a triode Q2. The triode Q1 is a PNP-type triode, and the triode Q2 is an NPN-type triode.

[0009] The control signal from the outside is simultaneously input to the base of the triode Q1 and the base of the triode Q2. The collector of the triode Q1 and the collector of the triode Q2 are connected, and their common end serves as a composite output end and is connected to the input end of the field-effect transistor drive circuit to transmit the output signal V0 to the field-effect transistor drive circuit.

[0010] The gate drive circuit further includes a first positive power supply; the first positive power supply is connected to the emitter of the triode Q1 to provide a high-voltage input to the emitter of the triode Q1; the emitter of the triode Q2 is connected to the reference ground.

[0011] Optionally or preferably, the gate drive circuit further includes a resistor R1 and a capacitor C1; the resistor R1 and the capacitor C1 are connected in parallel, with one common terminal serving as an input terminal to receive a control signal from the outside, and the other common terminal being connected to the bases of the triode Q1 and the triode Q2.

[0012] Optionally or preferably, the field-effect transistor drive circuit receives the output signal V0 of the gate drive circuit and outputs a drive signal; when the output signal V0 is at a low level, the drive signal is at a high level; when the output signal V0 is at a high level, the drive signal is at a low level.

[0013] Optionally or preferably, the field-effect transistor drive circuit includes a PMOS field-effect transistor Q3 and an NMOS field-effect transistor Q4; the field-effect transistor Q3 is a PMOS field-effect transistor; the field-effect transistor Q4 is an NMOS field-effect transistor;

[0014] The output signal V0 is simultaneously input to the gates of the field-effect transistor Q3 and the field-effect transistor Q4; the drains of the field-effect transistor Q3 and the field-effect transistor Q4 are connected to each other, and their common terminal is the output terminal of the field-effect transistor drive circuit to output a drive signal;

[0015] The source of the field-effect transistor Q3 is connected to a second positive power supply; the source of the field-effect transistor Q4 is connected to a negative power supply.

[0016] Optionally or preferably, the field-effect transistor drive circuit further includes a zener diode D1; the zener diode D1 is connected across the gates of the field-effect transistor Q3 and the field-effect transistor Q4 to prevent overvoltage damage to the field-effect transistors.

[0017] Optionally or preferably, the field-effect transistor drive circuit further includes a resistor R2, a resistor R3, a resistor R4, and a resistor R5 to provide current-limiting protection and limit oscillation; the resistor R2 is connected to the gate terminal of the field-effect transistor Q3; the resistor R4 is connected to the drain terminal of the field-effect transistor Q3; the resistor R5 is connected to the drain terminal of the field-effect transistor Q4; both ends of the resistor R3 are respectively connected to the gate and the source of the field-effect transistor Q4.

[0018] Optionally or preferably, it further includes a capacitor C2; the capacitor C2 is connected in parallel with the zener diode D1 to protect the zener diode D1 and improve the transient response.

[0019] Based on the cooperative structure of the gate drive circuit and the field-effect transistor drive circuit, a high-speed and high-voltage PIN large-opening ratio switch drive circuit provided by the present invention can produce the following technical effects:

[0020] (1) The cooperative structure adopted by the present invention can reduce the switching delay, has a shorter switching time compared with the prior art, and the switching time is less than 15 ns;

[0021] (2) The present invention has a wide applicable voltage range and can withstand voltages in the hundreds of volts;

[0022] (3) The circuit structure of the present invention is simple and has a small volume;

[0023] (4) The present invention is applicable to fields such as high-power laser driving, industrial pulse power supplies, and solenoid valve control that require high-speed switching of high-voltage loads. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on the structures shown in these drawings without creative efforts.

[0025] Figure 1 is a schematic diagram of the circuit structure of the present invention;

[0026] Figure 2 is a schematic diagram of the circuit applying the present invention;

[0027] Figure 3 is for applying as Figure 2 shown in the circuit of the policy switching time. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0028] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only some of the embodiments of the present invention, rather than all of them. Without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0029] In a preferred embodiment:

[0030] As Figure 1 shown:

[0031] This embodiment provides a high-speed and high-voltage PIN large-opening ratio switch driving circuit, which is composed of a gate driving circuit and a field-effect transistor driving circuit connected; a control signal from the outside is transmitted to the input end of the gate driving circuit, and the output end of the gate driving circuit is connected to the input circuit of the field-effect transistor driving circuit; the output end of the field-effect transistor driving circuit outputs a driving signal, and this driving signal serves as the final output signal of this driving circuit.

[0032] Specifically, the gate drive circuit includes a triode Q1 and a triode Q2; the triode Q1 is a PNP type triode; the triode Q2 is an NPN type triode;

[0033] The control signal from the outside is simultaneously input to the bases of the triode Q1 and the triode Q2; the collectors of the triode Q1 and the triode Q2 are connected, and their common terminal serves as a composite output terminal and is connected to the input terminal of the field effect transistor drive circuit to transmit the output signal V0 to the field effect transistor drive circuit.

[0034] The gate drive circuit further includes a first positive power supply; the first positive power supply is connected to the emitter of the triode Q1 to provide a high-voltage input to the emitter of the triode Q1; the emitter of the triode Q2 is connected to the reference ground.

[0035] Specifically, the gate drive circuit further includes a resistor R1 and a capacitor C1; the resistor R1 and the capacitor C1 are connected in parallel, one of their common terminals serves as an input terminal to receive the control signal from the outside, and the other common terminal is connected to the bases of the triode Q1 and the triode Q2.

[0036] Specifically, the field effect transistor drive circuit includes a PMOS field effect transistor Q3 and an NMOS field effect transistor Q4; the PMOS field effect transistor Q3 is a PMOS field effect transistor; the NMOS field effect transistor Q4 is an NMOS field effect transistor;

[0037] The output signal V0 is simultaneously input to the gates of the field effect transistor Q3 and the field effect transistor Q4; the drains of the field effect transistor Q3 and the field effect transistor Q4 are connected, and their common terminal is the output terminal of the field effect transistor drive circuit to output a drive signal.

[0038] The source of the field effect transistor Q3 is connected to the second positive power supply; the source of the field effect transistor Q4 is connected to the negative power supply.

[0039] Further, in this embodiment, the field effect transistor drive circuit further includes a zener diode D1; the zener diode D1 is connected across the gates of the field effect transistor Q3 and the field effect transistor Q4 to prevent the field effect transistor from being damaged by overvoltage.

[0040] Further, in this embodiment, the field effect transistor drive circuit further includes a resistor R2, a resistor R3, a resistor R4, and a resistor R5 to provide current limiting protection and limit oscillation; the resistor R2 is connected to the gate terminal of the field effect transistor Q3; the resistor R4 is connected to the drain terminal of the field effect transistor Q3; the resistor R5 is connected to the drain terminal of the field effect transistor Q4; both ends of the resistor R3 are respectively connected to the gate and the source of the field effect transistor Q4.

[0041] Further, it further includes a capacitor C2; the capacitor C2 is connected in parallel with the voltage stabilizing diode D1 for protecting the voltage stabilizing diode D1 and improving the transient response.

[0042] The working principle of this embodiment is as follows:

[0043] (1) When the control signal from the outside is at a low level, the PNP transistor Q1 is turned on and the NPN transistor Q2 is turned off. At this time, the output voltage of the output signal V0 is the first positive power supply VCC; the gate voltage of the PMOS field effect transistor Q3 is VCC, the source voltage is the second positive power supply VCC, the Vgs power supply of the PMOS field effect transistor Q3 is 0V, and the PMOS field effect transistor Q3 is turned off; at this time, the voltage stabilizing diode D1 is turned on, and the voltage of the voltage stabilizing diode D1 is the voltage -VEE of the negative power supply; the gate voltage of the NMOS field effect transistor Q4 is -VEE + VCC, and the source voltage is -VEE. The Vgs power supply of the NMOS field effect transistor Q4 is VCC, and the NMOS transistor Q4 is turned on, and the driving output voltage is -VEE;

[0044] (2) When the control signal from the outside is at a high level, the PNP transistor Q1 is turned off and the NPN transistor Q2 is turned on. At this time, the output voltage of the output signal V0 is 0V; the gate voltage of the PMOS field effect transistor Q3 is 0V, the source voltage is VCC, the Vgs voltage of the PMOS field effect transistor is -VCC, and the PMOS field effect transistor Q3 is turned on; at this time, the voltage stabilizing diode D1 is turned off, the gate voltage of the NMOS field effect transistor Q4 is -VEE, and the source voltage is -VEE. The Vgs power supply of the NMOS field effect transistor is 0V, and the NMOS field effect transistor Q4 is turned off, and the driving output voltage is VCC.

[0045] In application, the circuit can be built in the way as Figure 2 shown to drive the output voltages of +5V and -100V. The PIN diode uses the MA4P504 tube of MACOM. The simulation switching time is as Figure 3 shown. It can be seen that with the driving circuit of the present invention, using the MA4P504 tube as a high-power switch, the switching-on time from 10% to 90% reaches 159ns, and using the MA4P504 tube as a high-power switch, the switching-off time from 90% to 10% reaches 129ns.

[0046] The above are only the preferred embodiments of the present invention. It should be understood that the present invention is not limited to the form disclosed herein, should not be regarded as an exclusion of other embodiments, but can be used in various other combinations, modifications and environments, and can be modified within the scope of the concept described herein through the above teachings or the technology or knowledge in related fields. And the modifications and changes made by those skilled in the art without departing from the spirit and scope of the present invention should all be within the protection scope of the appended claims of the present invention.

Claims

1. A high-speed and high-voltage PIN large-opening ratio switch driving circuit, characterized in that: It is composed of a gate driving circuit and a field-effect transistor driving circuit connected together; a control signal from the outside is transmitted to the input end of the gate driving circuit, and the output end of the gate driving circuit is connected to the input circuit of the field-effect transistor driving circuit; the output end of the field-effect transistor driving circuit outputs a driving signal, and this driving signal serves as the final output signal of this driving circuit.

2. The high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 1, characterized in that: The gate driving circuit receives the control signal and outputs a signal V0 to the field-effect transistor driving circuit; when the control signal is at a low level, the output signal V0 is at a high level; when the control signal is at a high level, the output signal V0 is at a low level.

3. The high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 2, wherein: The gate driving circuit includes a triode Q1 and a triode Q2; the triode Q1 is a PNP type triode; the triode Q2 is an NPN type triode; The control signal from the outside is simultaneously input to the bases of the triode Q1 and the triode Q2; the collectors of the triode Q1 and the triode Q2 are connected, and their common terminal serves as a composite output terminal and is connected to the input end of the field-effect transistor driving circuit to transmit the output signal V0 to the field-effect transistor driving circuit; The gate driving circuit further includes a first positive power supply; the first positive power supply is connected to the emitter of the triode Q1 to provide a high-voltage input to the emitter of the triode Q1; the emitter of the triode Q2 is connected to the reference ground.

4. The high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 1, wherein: The gate driving circuit further includes a resistor R1 and a capacitor C1; the resistor R1 and the capacitor C1 are connected in parallel, one of their common terminals serves as an input end to receive the control signal from the outside, and the other common terminal is connected to the bases of the triode Q1 and the triode Q2.

5. The high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 1, wherein: The field-effect transistor driving circuit receives the output signal V0 of the gate driving circuit and outputs a driving signal; when the output signal V0 is at a low level, the driving signal is at a high level; when the output signal V0 is at a high level, the driving signal is at a low level.

6. A high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 5, characterized in that: The field-effect transistor driving circuit includes a PMOS field-effect transistor Q3 and an NMOS field-effect transistor Q4; the PMOS field-effect transistor Q3 is a PMOS field-effect transistor; the NMOS field-effect transistor Q4 is an NMOS field-effect transistor; The output signal V0 is simultaneously input to the gates of the PMOS field-effect transistor Q3 and the NMOS field-effect transistor Q4; the drains of the PMOS field-effect transistor Q3 and the NMOS field-effect transistor Q4 are connected, and their common terminal is the output end of the field-effect transistor driving circuit to output the driving signal; The source of the PMOS field-effect transistor Q3 is connected to the second positive power supply; the source of the NMOS field-effect transistor Q4 is connected to the negative power supply.

7. A high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 6, characterized in that: The field-effect transistor driving circuit further includes a zener diode D1; the zener diode D1 is connected across the gates of the PMOS field-effect transistor Q3 and the NMOS field-effect transistor Q4 to prevent the field-effect transistors from being damaged by overvoltage.

8. The high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 6, wherein: The field-effect transistor driving circuit further includes a resistor R2, a resistor R3, a resistor R4, and a resistor R5 to provide current-limiting protection and limit oscillation; the resistor R2 is connected to the gate terminal of the PMOS field-effect transistor Q3; the resistor R4 is connected to the drain terminal of the PMOS field-effect transistor Q3; the resistor R5 is connected to the drain terminal of the NMOS field-effect transistor Q4; both ends of the resistor R3 are respectively connected to the gate and the source of the NMOS field-effect transistor Q4.

9. The high-speed and high-voltage PIN large-opening ratio switch driving circuit according to claim 7, wherein: It further includes a capacitor C2; the capacitor C2 is connected in parallel with the zener diode D1 to protect the zener diode D1 and improve the transient response.

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