Self-biased negative threshold voltage comparison method

Abstract

The invention discloses a self-biased negative threshold voltage comparison method, and relates to a self-biased voltage comparison method, and a circuit comprises a starting circuit, a self-biased circuit, a negative threshold voltage lifting circuit, a comparator circuit and a buffer circuit. The starting circuit is used for driving the circuit to get rid of a degenerate working point when the circuit is started, the self-biasing circuit is used for ensuring that follow-up circuits can obtain stable bias current and voltage, the negative threshold voltage boosting circuit is used for inputting negative threshold voltage and boosting the voltage through the circuit for comparison, and the comparator circuit is used for comparing the two voltages. And the buffer circuit enhances the driving capability and ensures that signal transmission is undistorted. The invention provides a method for solving the phenomenon that current flows backward when inductive current drops to zero due to logic delay of an internal circuit module of a converter. According to the invention, after the inductor discharges, the negative threshold voltage is boosted and then compared, so that the circuit is applied to a series of circuits such as a subsequent zero-crossing detector circuit and the like.

Description

Technical Field

[0001] The present invention relates to a self - biasing voltage comparison method, and particularly to a self - biasing negative threshold voltage comparison method. Background Art

[0002] Comparator circuits play a crucial role in the field of analog integrated circuit design and are an indispensable key part. Its core function is to compare the magnitudes of two voltages to prevent damage to the circuit caused by excessive voltage, so it is mostly used in protection circuits.

[0003] With the large - scale application of integrated circuit products in fields such as consumer electronics, communication equipment, and automotive electronics, the requirements for voltage comparison vary significantly in different scenarios. However, traditional comparators cannot directly process the negative voltages generated by current backflow after capacitor discharge. For this reason, the present invention proposes a self - biasing negative threshold voltage comparison method. The core advantage of this circuit lies in accurately and efficiently processing negative voltage signals, especially suitable for scenarios that require direct detection of negative voltages or two - way protection. In addition, its simplified design, noise - immunity characteristics, and fast response ability make it a key component in scenarios such as power management, sensor interfaces, and battery systems. In applications with strict requirements for voltage accuracy, such as portable devices and Internet of Things devices, this circuit can exhibit excellent performance. Summary of the Invention

[0004] The object of the present invention is to propose a self - biasing negative threshold voltage comparison method, which solves the limitation problem that ordinary comparators cannot directly compare negative threshold voltages by raising the negative threshold voltage.

[0005] The technical solution of the present invention is as follows: The present invention proposes a self - biasing negative threshold voltage comparison method, including: Startup circuit: used to drive the circuit to get rid of the degenerate operating point during startup; Self - biasing circuit: ensures that subsequent circuits can obtain stable bias current and voltage; Negative threshold voltage boosting circuit: the input negative threshold voltage is boosted by this circuit for comparison; Comparator circuit: compares two voltages; Buffer circuit: enhances the driving ability to ensure signal transmission without distortion.

[0006] Optionally, the startup circuit includes: PMOS transistors: MP21, MP22, and resistor: R5; the source of the PMOS transistor MP21 is connected to the supply voltage, the drain is connected to the gate of the PMOS transistor MP22 and one end of the resistor R5, the gate of the PMOS transistor MP21 is connected to the gate of the PMOS transistor MP1, the other end of the resistor R5 is grounded, the source of the PMOS transistor MP22 is connected to the supply voltage, and the drain of the PMOS transistor MP22 serves as the output terminal of the startup circuit. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

[0007] Optionally, the self - bias circuit includes: PMOS transistors: MP1, MP2, NMOS transistors: MN1, MN2, and resistor: R6; the source of the PMOS transistor MP1 is connected to the supply voltage, the gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP2, the drain of the PMOS transistor MP2, and the drain of the NMOS transistor MN2, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the gate of the NMOS transistor MN1, and the gate of the NMOS transistor MN2, the source of the PMOS transistor MP2 is connected to the supply voltage, the source of the NMOS transistor MN1 is grounded, the source of the NMOS transistor MN2 is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

[0008] Optionally, the negative threshold voltage boosting circuit includes: PMOS transistors: MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11; NMOS transistor: MN3; resistors: R1, R2. The source of the PMOS transistor MP3 is connected to the supply voltage. The drain of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP3 and the drain of the NMOS transistor MN3. The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN2. The source of the NMOS transistor MN3 is grounded. The source of the PMOS transistor MP4 is connected to the supply voltage. The gate of the PMOS transistor MP4 is connected to the gates of the PMOS transistors MP4, MP6, MP8, and MP10. The drain of the PMOS transistor MP4 is connected to the source of the PMOS transistor MP5 and one end of the resistor R1. The gate of the PMOS transistor MP5 is connected to the external input voltage V1. The drain of the PMOS transistor MP5 is grounded. The other end of the resistor R1 is connected to the gate of the PMOS transistor MP7. The source of the PMOS transistor MP6 is connected to the supply voltage. The drain of the PMOS transistor MP6 is connected to the source of the PMOS transistor MP7 and the gate of the PMOS transistor MP14. The drain of the PMOS transistor MP7 is grounded. The source of the PMOS transistor MP8 is connected to the supply voltage. The drain of the PMOS transistor MP8 is connected to the source of the PMOS transistor MP9 and one end of the resistor R2. The gate of the PMOS transistor MP9 is connected to the external input voltage V2. The drain of the PMOS transistor MP9 is grounded. The other end of the resistor R2 is connected to the gate of the PMOS transistor MP11. The source of the PMOS transistor MP10 is connected to the supply voltage. The drain of the PMOS transistor MP10 is connected to the source of the PMOS transistor MP11 and the gate of the PMOS transistor MP13. The drain of the PMOS transistor MP11 is grounded. The substrates of all the PMOS transistors are connected to VDD, and the substrates of all the NMOS transistors are connected to GND.

[0009] Optionally, the comparator circuit includes: PMOS transistors: MP12, MP13, MP14, MP15, MP16, MP17, MP18; NMOS transistors: MN4, MN5, MN6; resistors: R3, R4. The source of the PMOS transistor MP12 is connected to the supply voltage. The gate of the PMOS transistor MP12 is connected to the gates of the PMOS transistors MP10, MP15, and MP18. The drain of the PMOS transistor MP12 is connected to the sources of the PMOS transistors MP13 and MP14. The drain of the PMOS transistor is connected to the gate of the PMOS transistor MP16 and one end of the resistor R3. The other end of the resistor R3 is grounded. The drain of the PMOS transistor MP14 is connected to the gate of the PMOS transistor MP17 and one end of the resistor R4. The other end of the resistor R4 is grounded. The source of the PMOS transistor MP15 is connected to the supply voltage. The drain of the PMOS transistor MP15 is connected to the sources of the PMOS transistors MP16 and MP17. The drain of the PMOS transistor MP16 is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4, and the gate of the NMOS transistor MN5. The drain of the PMOS transistor MP17 is connected to the drain of the NMOS transistor MN5 and the gate of the NMOS transistor MN6. The source of the NMOS transistor MN4 is grounded. The source of the NMOS transistor MN5 is grounded. The drain of the PMOS transistor MP18 is connected to the drain of the NMOS transistor MN6, the gate of the PMOS transistor MP19, and the gate of the NMOS transistor MN7. The source of the NMOS transistor MN6 is grounded. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

[0010] Optionally, the buffer circuit includes: PMOS transistors: MP19, MP20; NMOS transistors: MN7, MN8. The sources of the PMOS transistors MP19 and MP20 are connected to the supply voltage. The gate of the PMOS transistor MP19 is connected to the gate of the NMOS transistor MN7, the drain of the PMOS transistor MP18, and the drain of the NMOS transistor MN6. The drain of the PMOS transistor MP19 is connected to the drain of the NMOS transistor MN7, the gate of the PMOS transistor MP20, and the gate of the NMOS transistor MN8. The source of the NMOS transistor MN7 is grounded. The source of the NMOS transistor MP20 is connected to the supply voltage. The drain of the NMOS transistor MP20 is connected to the drain of the NMOS transistor MN8 and the output VOUT. The source of the NMOS transistor MN8 is grounded. The substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

[0011] Compared with the prior art, the present invention has better effects: Compared with general comparator circuits, the negative threshold comparator circuit of the present invention applies a self - biasing design, enabling the circuit to have stable bias current and voltage. Moreover, through the voltage - boosting circuit, negative voltages can be compared, while general comparator circuits can only compare positive voltages. The phenomenon of current backflow is common in circuits. If not detected in time, it may cause the entire circuit to malfunction. This circuit can effectively avoid the influence brought by current backflow and improve the stability and safety of the circuit. Description of the Drawings

[0012] Figure 1 It is a design flow chart of a self - biasing negative threshold voltage comparison method of the present invention Figure 2 It is the startup and bias circuit diagrams of the self - biasing negative threshold voltage comparator of the present invention Figure 3 It is the negative threshold voltage - boosting circuit diagram of the self - biasing negative threshold voltage comparator of the present invention Figure 4 It is the comparator circuit diagram of the self - biasing negative threshold voltage comparator of the present invention Figure 5 It is the buffer circuit diagram of the self - biasing negative threshold voltage comparator of the present invention Figure 6 It is the overall circuit diagram of the self - biasing negative threshold voltage comparator of the present invention Explanation of the reference numerals in the figures: 01 startup circuit module, 02 self - biasing circuit module, 03 negative threshold voltage - boosting circuit module, 04 comparator circuit, 05 buffer circuit. Detailed Embodiments

[0013] The present invention will be further described in detail below with reference to examples, but the embodiments of the present invention are not limited thereto.

[0014] To make the purpose, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are some, but not all, of the embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention. Therefore, the following detailed description of the embodiments of the present invention provided in the drawings is not intended to limit the scope of the claimed invention, but merely represents selected embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without creative efforts fall within the scope of protection of the present invention.

[0015] In addition, the illustrations provided in this example only schematically illustrate the basic concept of the present invention. The components shown in the illustrations are only those related to the present invention, rather than being drawn according to the number, shape, and size of the components in actual implementation. The form, quantity, and proportion of each component in actual implementation can be arbitrarily changed, and the layout form of its components may also be more complex.

[0016] Combined with Figure 1 , the design process is as follows: This circuit is powered on by the startup circuit to activate the bias circuit. After the bias circuit is activated, the startup circuit is turned off. The bias circuit provides a stable bias voltage and bias current for the subsequent circuits. Two negative threshold voltages V1 and V2 are input, and positive voltages V1' and V2' are obtained through the negative threshold voltage boosting circuit. Then, the obtained V1' and V2' are input to the comparator for comparison, and finally, the output V OUT .

[0017] This example provides a bias circuit that includes a startup circuit 01 and a self-bias circuit 02, which generates a bias current to ensure the stable operation of semiconductor devices under different working conditions and improve the reliability and accuracy of the circuit.

[0018] As an example, as Figure 2 shown, the startup circuit 01 includes: PMOS transistors: MP21, MP22, and a resistor: R5; the source of the PMOS transistor MP21 is connected to the supply voltage, the drain is connected to the gate of the PMOS transistor MP22 and one end of the resistor R3, the gate of the PMOS transistor MP21 is connected to the gate of the PMOS transistor MP1, the other end of the resistor R5 is grounded, the source of the PMOS transistor MP22 is connected to the supply voltage, and the drain of the PMOS transistor MP22 serves as the output terminal of the startup circuit.

[0019] In this example, the PMOS transistors: MP21, MP22, and the resistor: R5 form the startup circuit. When the power supply voltage VDD is equal to zero, the MP21 transistor operates in the cut-off region, and the current flowing through R5 is equal to zero; when the power supply VDD rises above V TH P22, the MP22 transistor conducts and operates in the deep linear region, causing the startup signal to increase with the increase of the power supply voltage VDD. When the voltage of the startup signal reaches a certain value, MN1 and MN2 conduct, and the power supply voltage VDD flows through the path formed by MP1, MP2, MN1, and the resistor R6 to GND. The MP21 transistor and the MP1 transistor form a current mirror. As the current increases, the mirror current of MP21 also increases, causing the gate voltage of the MP22 transistor to rise; when VG22 > VDD - VTHP22, MP22 enters the cut-off region and the startup unit is turned off.

[0020] As an example, as Figure 2As shown, the self-bias circuit includes: PMOS tubes: MP1, MP2, NMOS tubes: MN1, MN2, and a resistor: R6; the source of the PMOS tube MP1 is connected to the power supply voltage, the gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP2, the drain of the PMOS tube MP2, and the drain of the NMOS tube MN2 are connected, the drain of the PMOS tube MP1 is connected to the drain of the NMOS tube MN1, the gate of the NMOS tube MN1, and the gate of the NMOS tube MN2 are connected, the source of the PMOS tube MP2 is connected to the power supply voltage, the source of the NMOS tube MN1 is grounded, the source of the NMOS tube MN2 is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded.

[0021] In this example, PMOS transistors: MP1, MP2, NMOS transistors: MN1, MN2, and resistor: R6 form a self-bias circuit. Among them, the width-to-length ratio of MP1 and MP2 is equal, and the ratio of the width-to-length ratio of MN1 to MN2 to MN3 is 1:2:1, so K=2, MN1 and MN2 form a current mirror to generate bias current for MP3, MP3 and MP4, MP6, MP8, MP10, MP12, MP15, MP18 have the same width-to-length ratio, MP3 and MP4, MP6, MP8, MP10, MP12, MP15, MP18 form a current mirror, and the drains of MP4, MP6, MP8, MP10, MP12, MP15, MP18 output bias current to provide bias current for subsequent circuits. (1) like Figure 3As shown in the figure, this embodiment provides a negative threshold boost circuit, which includes: PMOS transistors: MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11; NMOS transistor: MN3; resistors: R1, R2. The source of the PMOS transistor MP3 is connected to the supply voltage. The drain of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP3 and the drain of the NMOS transistor MN3. The gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN2, and the source of the NMOS transistor MN3 is grounded. The source of the PMOS transistor MP4 is connected to the supply voltage. The gate of the PMOS transistor MP4 is connected to the gates of the PMOS transistors MP4, MP6, MP8, and MP10. The drain of the PMOS transistor MP4 is connected to the source of the PMOS transistor MP5 and one end of the resistor R1. The gate of the PMOS transistor MP5 is connected to the external input voltage V1, and the drain of the PMOS transistor MP5 is grounded. The other end of the resistor R1 is connected to the gate of the PMOS transistor MP7. The source of the PMOS transistor MP6 is connected to the supply voltage. The drain of the PMOS transistor MP6 is connected to the source of the PMOS transistor MP7 and the gate of the PMOS transistor MP14. The drain of the PMOS transistor MP7 is grounded. The source of the PMOS transistor MP8 is connected to the supply voltage. The drain of the PMOS transistor MP8 is connected to the source of the PMOS transistor MP9 and one end of the resistor R2. The gate of the PMOS transistor MP9 is connected to the external input voltage V2, and the drain of the PMOS transistor MP9 is grounded. The other end of the resistor R2 is connected to the gate of the PMOS transistor MP11. The source of the PMOS transistor MP10 is connected to the supply voltage. The drain of the PMOS transistor MP10 is connected to the source of the PMOS transistor MP11 and the gate of the PMOS transistor MP13. The drain of the PMOS transistor MP11 is grounded.

[0022] (2) (3) As Figure 4As shown, the comparator circuit includes: PMOS transistors: MP12, MP13, MP14, MP15, MP16, MP17, MP18; NMOS transistors: MN4, MN5, MN6; resistors: R3, R4. The source of the PMOS transistor MP12 is connected to the supply voltage. The gate of the PMOS transistor MP12 is connected to the gates of the PMOS transistors MP10, MP15, and MP18. The drain of the PMOS transistor MP12 is connected to the sources of the PMOS transistors MP13 and MP14. The drain of the PMOS transistor is connected to the gate of the PMOS transistor MP16 and one end of the resistor R3. The other end of the resistor R3 is grounded. The drain of the PMOS transistor MP14 is connected to the gate of the PMOS transistor MP17 and one end of the resistor R4. The other end of the resistor R4 is grounded. The source of the PMOS transistor MP15 is connected to the supply voltage. The drain of the PMOS transistor MP15 is connected to the sources of the PMOS transistors MP16 and MP17. The drain of the PMOS transistor MP16 is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4, and the gate of the NMOS transistor MN5. The drain of the PMOS transistor MP17 is connected to the drain of the NMOS transistor MN5 and the gate of the NMOS transistor MN6. The source of the NMOS transistor MN4 is grounded. The source of the NMOS transistor MN5 is grounded. The drain of the PMOS transistor MP18 is connected to the drain of the NMOS transistor MN6, the gate of the PMOS transistor MP19, and the gate of the NMOS transistor MN7. The source of the NMOS transistor MN6 is grounded.

[0023] As Figure 5 shown, this embodiment provides a buffer circuit including: PMOS transistors: MP19, MP20; NMOS transistors: MN7, MN8. The sources of the PMOS transistors MP19 and MP20 are connected to the supply voltage. The gate of the PMOS transistor MP19 is connected to the gate of the NMOS transistor MN7, the drain of the PMOS transistor MP18, and the drain of the NMOS transistor MN6. The drain of the PMOS transistor MP19 is connected to the drain of the NMOS transistor MN7, the gate of the PMOS transistor MP20, and the gate of the NMOS transistor MN8. The source of the NMOS transistor MN7 is grounded. The source of the NMOS transistor MP20 is connected to the supply voltage. The drain of the NMOS transistor MP20 is connected to the drain of the NMOS transistor MN8 and the output VOUT. The source of the NMOS transistor MN8 is grounded.

[0024] In summary, the present invention is a self - biased negative threshold voltage comparison method. By designing and improving the start - up circuit, self - bias circuit, negative threshold voltage boosting circuit, comparator circuit, and buffer circuit, a relatively stable self - bias structure is adopted. Through boosting the negative threshold voltage to compare with positive voltages, the disadvantage that negative threshold voltages cannot be compared is solved.

[0025] The content described above is only the specific implementation manner of the present application, aiming to enable those skilled in the art to understand and implement the present application. For these examples, those skilled in the art can easily make various modifications. The general principles defined herein can be implemented in other examples without departing from the spirit of the present application or exceeding its scope. Therefore, the present application will not be limited to these examples shown herein, but rather conform to the broadest scope consistent with the principles and novel features claimed herein.

Claims

1. A self - biased negative threshold voltage comparison method, characterized in that, The method includes the following circuits: Startup circuit: used to drive the circuit to get rid of the degenerate operating point during startup; Self-biasing circuit: ensures that subsequent circuits can obtain stable bias current and voltage; Negative threshold voltage boosting circuit: the input negative threshold voltage is boosted through this circuit for comparison; Comparator circuit: compares two voltages; Buffer circuit: enhances the driving ability to ensure that signal transmission is distortion-free.

2. The self-biased negative threshold voltage comparison method according to claim 1, wherein The startup circuit includes: PMOS transistors: MP21, MP22, resistor: R5; the source of the PMOS transistor MP21 is connected to the supply voltage, the drain is connected to the gate of the PMOS transistor MP22 and one end of the resistor R5; the gate of the PMOS transistor MP21 is connected to the gate of the PMOS transistor MP1, and the other end of the resistor R5 is grounded; the source of the PMOS transistor MP22 is connected to the supply voltage, and the drain of the PMOS transistor MP22 is used as the output terminal of the startup circuit; the substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

3. A self - biased negative threshold voltage comparison method according to claim 1, characterized in that, The self-biasing circuit includes: PMOS transistors: MP1, MP2, NMOS transistors: MN1, MN2, resistor: R6; the source of the PMOS transistor MP1 is connected to the supply voltage, the gate of the PMOS transistor MP1 is connected to the gate of the PMOS transistor MP2, the drain of the PMOS transistor MP2, and the drain of the NMOS transistor MN2, the drain of the PMOS transistor MP1 is connected to the drain of the NMOS transistor MN1, the gate of the NMOS transistor MN1, and the gate of the NMOS transistor MN2, the source of the PMOS transistor MP2 is connected to the supply voltage, the source of the NMOS transistor MN1 is grounded, the source of the NMOS transistor MN2 is connected to one end of the resistor R6, and the other end of the resistor R6 is grounded; the substrates of all PMOS transistors are connected to VDD, and the substrates of all NMOS transistors are connected to GND.

4. A self - biased negative threshold voltage comparison method according to claim 1, characterized in that The negative threshold voltage boosting circuit includes: PMOS transistors: MP3, MP4, MP5, MP6, MP7, MP8, MP9, MP10, MP11, NMOS transistor: MN3, resistors: R1, R2; the source of the PMOS transistor MP3 is connected to the supply voltage, the drain of the PMOS transistor MP3 is connected to the gate of the PMOS transistor MP3 and the drain of the NMOS transistor MN3; the gate of the NMOS transistor MN3 is connected to the gate of the NMOS transistor MN2, the source of the NMOS transistor MN3 is grounded, the source of the PMOS transistor MP4 is connected to the supply voltage, the gate of the PMOS transistor MP4 is connected to the gates of the PMOS transistors MP4, MP6, MP8, MP10, the drain of the PMOS transistor MP4 is connected to the source of the PMOS transistor MP5 and one end of the resistor R1, the gate of the PMOS transistor MP5 is connected to the external input voltage V1, the drain of the PMOS transistor MP5 is grounded, the other end of the resistor R1 is connected to the gate of the PMOS transistor MP7, the source of the PMOS transistor MP6 is connected to the supply voltage, the drain of the PMOS transistor MP6 is connected to the source of the PMOS transistor MP7 and the gate of the PMOS transistor MP14, the drain of the PMOS transistor MP7 is grounded, the source of the PMOS transistor MP8 is connected to the supply voltage, the drain of the PMOS transistor MP8 is connected to the source of the PMOS transistor MP9 and one end of the resistor R2, the gate of the PMOS transistor MP9 is connected to the external input voltage V2, the drain of the PMOS transistor MP9 is grounded, the other end of the resistor R2 is connected to the gate of the PMOS transistor MP11, the source of the PMOS transistor MP10 is connected to the supply voltage, the drain of the PMOS transistor MP10 is connected to the source of the PMOS transistor MP11 and the gate of the PMOS transistor MP13, the drain of the PMOS transistor MP11 is grounded; the substrates of all the PMOS transistors are connected to VDD, and the substrates of all the NMOS transistors are connected to GND.

5. A self-biased negative threshold voltage comparison method according to claim 1, characterized in that The comparator circuit includes: PMOS transistors: MP12, MP13, MP14, MP15, MP16, MP17, MP18; NMOS transistors: MN4, MN5, MN6; resistors: R3, R4. The source of the PMOS transistor MP12 is connected to the supply voltage. The gate of the PMOS transistor MP12 is connected to the gates of the PMOS transistors MP10, MP15, and MP18. The drain of the PMOS transistor MP12 is connected to the sources of the PMOS transistors MP13 and MP14. The drain of the PMOS transistor is connected to the gate of the PMOS transistor MP16 and one end of the resistor R3. The other end of the resistor R3 is grounded. The drain of the PMOS transistor MP14 is connected to the gate of the PMOS transistor MP17 and one end of the resistor R4. The other end of the resistor R4 is grounded. The source of the PMOS transistor MP15 is connected to the supply voltage. The drain of the PMOS transistor MP15 is connected to the sources of the PMOS transistors MP16 and MP17. The drain of the PMOS transistor MP16 is connected to the drain of the NMOS transistor MN4, the gate of the NMOS transistor MN4, and the gate of the NMOS transistor MN5. The drain of the PMOS transistor MP17 is connected to the drain of the NMOS transistor MN5 and the gate of the NMOS transistor MN6. The source of the NMOS transistor MN4 is grounded. The source of the NMOS transistor MN5 is grounded. The drain of the PMOS transistor MP18 is connected to the drain of the NMOS transistor MN6, the gate of the PMOS transistor MP19, and the gate of the NMOS transistor MN7. The source of the NMOS transistor MN6 is grounded. The substrates of all the PMOS transistors are connected to VDD, and the substrates of all the NMOS transistors are connected to GND.

6. A self - biasing negative threshold voltage comparison method according to claim 1, characterized in that, The buffer circuit includes: PMOS transistors: MP19, MP20; NMOS transistors: MN7, MN8. The sources of the PMOS transistors MP19 and MP20 are connected to the supply voltage. The gate of the PMOS transistor MP19 is connected to the gate of the NMOS transistor MN7, the drain of the PMOS transistor MP18, and the drain of the NMOS transistor MN6. The drain of the PMOS transistor MP19 is connected to the drain of the NMOS transistor MN7, the gate of the PMOS transistor MP20, and the gate of the NMOS transistor MN8. The source of the NMOS transistor MN7 is grounded. The source of the PMOS transistor MP20 is connected to the supply voltage. The drain of the PMOS transistor MP20 is connected to the drain of the NMOS transistor MN8 and the output VOUT. The source of the NMOS transistor MN8 is grounded. The substrates of all the PMOS transistors are connected to VDD, and the substrates of all the NMOS transistors are connected to GND.

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