Heterogeneous computing system, cache consistency maintenance method and device, equipment and medium

Abstract

The invention discloses a heterogeneous computing system, a cache consistency maintenance method and device, equipment and a medium, and relates to the technical field of heterogeneous computing. The method comprises the following steps: determining a hotspot data access path at the current moment according to an access sequence and dependency relationship strength of each data block of the heterogeneous computing system at the current moment; generating current running state information according to the hotspot data access path, the workload information of the heterogeneous computing system at the current moment, the cache effective information and the cross-device communication information; and based on the relationship between the running state of the heterogeneous computing system and the cache coherence protocol type, determining the cache coherence protocol most matched with the current running state of the heterogeneous computing system according to the current running state information. According to the method, the problem that the cache consistency protocol cannot be effectively and dynamically optimized in related technologies can be solved, the cross-device data dependency relationship can be dynamically captured, the dynamic change can be accurately sensed, and the high performance and data consistency of the system can be ensured.

Description

Technical Field

[0001] The present invention relates to the field of heterogeneous computing, and in particular, to a heterogeneous computing system, a method, a device, an electronic device, a non-volatile storage medium, and a computer program product for maintaining cache coherence thereof. Background Art

[0002] A heterogeneous computing system integrates computing units of different architectures. When multiple computing units hold data copies through private caches simultaneously, any modification of data by a computing unit will cause a cache coherence problem.

[0003] In the process of maintaining cache coherence in related technologies, in order to adapt to the load changes of heterogeneous computing systems in real time, a simple read-write ratio threshold is set to dynamically adjust the cache coherence protocol. However, this method cannot accurately capture complex cross-device data dependencies, cannot accurately perceive system dynamic changes, and cannot effectively optimize the cache coherence protocol dynamically. Summary of the Invention

[0004] The present invention provides a heterogeneous computing system, a method, a device, an electronic device, a non-volatile storage medium, and a computer program product for maintaining cache coherence, which can dynamically capture complex cross-device data streams and dependencies, accurately perceive system dynamic changes, realize effective dynamic adjustment of the cache coherence protocol, and ensure high performance and cache data coherence of the heterogeneous computing system.

[0005] To solve the above technical problems, the present invention provides the following technical solutions: On the one hand, the present invention provides a method for maintaining cache coherence, including: Determining a hot data access path of the heterogeneous computing system at the current moment according to the access order and the strength of dependency relationships of each data block of the heterogeneous computing system at the current moment.

[0006] Generating current running state information according to the hot data access path, the current workload information, the cache validity information, and the cross-device communication information of the heterogeneous computing system at the current moment.

[0007] Based on the relationship between the running state of the heterogeneous computing system and the type of cache coherence protocol, determining the cache coherence protocol that best matches the current running state of the heterogeneous computing system according to the current running state information.

[0008] On the other hand, the present invention provides a device for maintaining cache coherence, including: A critical path identification module, configured to determine a hot data access path of the heterogeneous computing system at the current moment according to the access order and the strength of dependency relationships of each data block of the heterogeneous computing system at the current moment.

[0009] A state awareness module, configured to generate current operating state information according to the hot data access path, the workload information, cache validity information, and cross-device communication information of the heterogeneous computing system at the current moment.

[0010] A protocol dynamic selection module, configured to determine the cache coherence protocol that best matches the current operating state of the heterogeneous computing system based on the relationship between the operating state of the heterogeneous computing system and the cache coherence protocol type, according to the current operating state information.

[0011] The present invention also provides an electronic device, including a memory and a processor. When the processor executes the computer program stored in the memory, the steps of any of the above cache coherence maintenance methods are implemented.

[0012] The present invention also provides a non-volatile storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above cache coherence maintenance methods are implemented.

[0013] The present invention also provides a computer program product, including computer programs / instructions. When the computer programs / instructions are executed by a processor, the steps of any of the above cache coherence maintenance methods are implemented.

[0014] Finally, the present invention also provides a heterogeneous computing system, at least including a first computing node, a second computing node, and a cache coherence controller. The cache coherence controller is connected to the first computing node and the second computing node. The first computing node and the second computing node each include at least two computing units. Among them, the cache coherence controller is configured to implement the steps of any of the above cache coherence maintenance methods when executing a computer program.

[0015] The advantages of the technical solution provided by the present invention are as follows: based on the access information between data blocks in a heterogeneous computing system at different times, the data flow and dependency relationships across devices can be dynamically captured, thereby accurately determining the hot data access path that reflects the key links of data access in the heterogeneous computing system. Through the hot data access path, the part that has the greatest impact on the performance of the heterogeneous computing system can be determined, providing accurate data support for the optimization of the cache coherence protocol. By using the current workload information, cache validity information, and cross-device communication information of the heterogeneous computing system, the dynamic changes of the heterogeneous computing system can be accurately and efficiently perceived. Under the relationship between the operating state of the heterogeneous computing system and the type of cache coherence protocol, the cache coherence protocol that best matches the current state of the heterogeneous computing system can be dynamically adjusted through the current state, achieving effective dynamic adjustment of the cache coherence protocol, minimizing communication overhead and latency, improving the system throughput, and ensuring the high performance and cache data consistency of the heterogeneous computing system. In addition, the present invention also provides corresponding implementation devices, electronic devices, non-volatile storage media, computer program products, and heterogeneous computing systems for the cache coherence maintenance method, further making the method more practical, and the devices, electronic devices, non-volatile storage media, computer program products, and heterogeneous computing systems have corresponding advantages. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] To more clearly illustrate the technical solutions of the present invention or related technologies, the following will briefly introduce the drawings required for use in the description of the embodiments or related technologies. Obviously, the drawings described below are only some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0017] Figure 1 Schematic diagram of the hardware composition framework applicable to the cache coherence maintenance method provided by the present invention; Figure 2 Schematic flowchart of a cache coherence maintenance method provided by the present invention; Figure 3 Schematic flowchart of a method for learning the relationship between the operating state and the type of cache coherence protocol provided by the present invention; Figure 4 Schematic structural diagram of a cache coherence maintenance device in an exemplary embodiment provided by the present invention; Figure 5 Schematic structural diagram of an electronic device in an exemplary embodiment provided by the present invention; Figure 6 Schematic structural diagram of a heterogeneous computing system in an exemplary embodiment provided by the present invention; Figure 7 Schematic structural diagram of a cache coherence controller in an exemplary embodiment provided by the present invention. Detailed implementation manners

[0018] To enable those skilled in the art to better understand the technical solutions of the present invention, the present invention will be further described in detail below with reference to the accompanying drawings and specific implementation manners. Among them, the terms "first", "second", "third", "fourth", etc. in the specification and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. The term "exemplary" means "serving as an example, embodiment, or illustration". Any embodiment described herein as "exemplary" does not necessarily need to be construed as superior to or better than other embodiments.

[0019] Heterogeneous computing is a technology that uses multiple different architecture processors to work together in the same computing system to improve computing efficiency and performance. A heterogeneous computing system combines different types of processors such as CPU (Central Processing Unit), GPU (Graphics Processing Unit), TPU (Tensor Processing Unit), and FPGA (Field Programmable Gate Array), giving full play to their respective advantages to achieve parallel computing. Compared with homogeneous systems, it can provide more computing power (i.e., data processing or computing capabilities) resources and is widely used in the field of AI (Artificial Intelligence). It can not only meet the high-efficiency processing requirements of massive data for AI model training and inference but also solve the problem of low energy efficiency ratio in homogeneous computing systems. When dealing with AI tasks, due to architectural limitations, a large amount of energy is consumed to maintain the operation, resulting in high heat dissipation and energy consumption. It can dynamically allocate resources according to the characteristics of tasks, and different processors consume less energy when dealing with suitable tasks, effectively reducing the energy consumption and heat dissipation costs of AI applications. It also supports flexibly selecting and combining different types of processors and architectures according to different AI application scenarios and resource requirements, facilitating expansion and upgrading to adapt to the ever-changing AI technologies and business needs.

[0020] Among them, a heterogeneous computing system integrates multiple heterogeneous processors, accelerators, and memory components, and is usually composed of multiple computing units with significant differences in performance, power consumption, programming models, and memory consistency models, such as CPUs, GPUs, FPGAs, and NPUs (Neural network Processing Units). As the computing power gap between accelerators such as GPUs and NPUs and CPUs shows an order-of-magnitude differentiation, that is, the "memory wall effect" where the data throughput demand of the computing core far exceeds the memory bandwidth supply capacity, it leads to a serious imbalance in the performance of the heterogeneous computing system, such as problems of cross-device data competition, protocol rigidity, and insufficient hardware support. Among them, cross-device data competition refers to the difficulty in coordinating read and write operations across devices due to different memory consistency models of different computing units. For example, CPUs use a strong consistency model, while GPUs use a weak consistency model, which easily leads to data competition and affects the performance and data consistency of the entire system. Protocol rigidity means that traditional cache coherence protocols cannot be dynamically adjusted according to load changes, resulting in a decline in system performance. For example, the directory protocol is prone to directory expansion problems in high-write operation scenarios, and the broadcast protocol has excessive overhead in high-read operation scenarios. Insufficient hardware support means that current cache coherence solutions cannot fully support non-multiple-copy atomicity (non-MCA) hardware, resulting in these hardware being unable to fully utilize their performance advantages and limiting the overall computing power of the system.

[0021] To ensure the stable operation of heterogeneous computing systems, related technologies achieve cache coherence in heterogeneous computing systems through protocol stack innovation and hardware co-design. At the software protocol layer, related technologies maintain cache coherence in read-intensive and low-frequency write operation computing load scenarios of heterogeneous computing systems through the bus snooping protocol, and maintain cache coherence in scenarios with frequent data updates through the directory protocol. Among them, in the bus snooping protocol, the private caches of each processing unit in the heterogeneous computing system continuously monitor bus transactions. When a coherence request broadcast on the bus is detected, a predefined response logic is triggered based on the local cache line state, and the physical characteristics of the bus medium are used to provide transaction atomicity and sequentiality guarantees, enabling the state transition logic to be simplified to a deterministic finite state machine. Cache state synchronization can be achieved with relatively low difficulty through the global broadcast communication mode. However, with the expansion of the scale of multi-core processors, the bus load will increase. The characteristic that only one CPU is allowed to occupy the bus at a single moment leads to frequent blocking of memory access requests, resulting in a significant increase in memory access latency, which is prone to resource waste. In addition, the scalability of the bus snooping protocol is poor and it is difficult to meet the requirements of large-scale processor systems. That is, the cache coherence of a small-scale heterogeneous computing system can be effectively maintained through the bus snooping protocol with relatively low difficulty. Among them, the target protocol achieves cache coherence through a global public directory that records the state information of global cache lines. The global public directory includes the coherence state and a list of replica owners. In the directory protocol, all coherence messages are forwarded through the directory structure, and efficient point-to-point message transmission can be performed by querying the list of replica owners, reducing network communication overhead. In addition, the directory protocol can effectively manage replicas of shared data by establishing a directory to track the storage location and state of data, enabling multiple processors to conveniently access shared data, improving data availability and access efficiency. Large-scale multi-core processor systems can effectively coordinate cache interactions in a multi-core environment through centralized directory management to achieve efficient and reliable cache coherence maintenance. However, both the storage and update operations of the directory consume resources, which may affect the overall performance of the system. In addition, the directory protocol may introduce additional communication latency, reducing the speed of data access, which is not conducive to large-scale heterogeneous computing systems with high real-time requirements and limited resources.

[0022] For the software protocol layer and the hardware layer to jointly implement cache coherence maintenance, a related technology maintains cache coherence in a heterogeneous computing system based on the snooping update strategy. It converts the internal memory coherence model of the cluster into a unified coherence protocol based on the C11 memory coherence model through a translator module. The coherence controller module, as the coherence protocol manager, receives messages sent by each translator, performs unified reordering and routing scheduling on them, and effectively accommodates multiple heterogeneous memory coherence models between clusters by leveraging the loose ordering behavior of heterogeneous clusters. Another related technology is a heterogeneous coherence protocol based on the directory strategy. It designs a method for fusing composite coherence protocols for heterogeneous clusters, follows the global composite coherence model while retaining the coherence models of the original clusters, and fuses the coherence models of different clusters using proxy caches to ensure the coherence of the entire system. To achieve coherence maintenance, these two methods introduce additional translation overhead and fusion overhead, which may affect system performance.

[0023] Although the above methods can alleviate the obstacles in memory access to a certain extent, there are still some problems: The update protocol requires a fixed global directory, cannot dynamically optimize the protocol strategy, has poor flexibility, and performs poorly in complex load scenarios. In addition, protocol synthesis depends on static cluster configurations, lacks runtime adaptability, and cannot dynamically adjust the protocol according to the system state, resulting in suboptimal performance in different load scenarios and being unable to effectively adapt to diverse heterogeneous architectures. To adapt to the dynamic characteristics of task loads and achieve flexible switching of coherence maintenance protocols, it is usually done by simply selecting a protocol based on a read-write ratio threshold. This method cannot accurately capture complex cross-device data dependencies and is difficult to achieve efficient protocol optimization.

[0024] To solve the problem that in the process of maintaining cache coherence in a heterogeneous computing system by related technologies, the cache coherence protocol cannot respond in real time to the dynamic changes of the heterogeneous computing system, resulting in a decline in the performance of the heterogeneous computing system, the present invention can dynamically capture cross-device data streams and dependencies by obtaining access information between data blocks at different times in the heterogeneous computing system, and then determine the critical path of data access. It can perceive the dynamic changes of the heterogeneous computing system in real time and dynamically adjust the cache coherence protocol of the heterogeneous computing system according to the relationship between the running state and the cache coherence protocol type. Combining with the specific application environment architecture or specific hardware architecture on which the execution of the cache coherence maintenance method depends, the specific application environment architecture or specific hardware architecture is described here. The following combines Figure 1 Some possible application scenarios related to the technical solution of the present invention are introduced by way of example, which may include the following content: In this embodiment, the heterogeneous computing system includes multiple servers 1. Each server 1 serves as a computing node of the heterogeneous computing system. Each server includes at least two computing units 10. In addition to the CPU, which is a computing unit itself, it also has at least one type of computing unit built-in that is different from the CPU architecture, such as GPU, FPGA, and ASIC. The communication structure of the heterogeneous computing system is as follows: all the computing units of all the computing nodes are divided according to the type of computing unit. The computing units of the same type of computing unit are divided into a cluster. The computing units in the same cluster can be connected through a tree topology structure, and one of the computing units is selected as the main computing unit. Different clusters interact through the main computing unit, and each cluster is connected through the main computing unit using a ring topology structure.

[0025] To overcome the problems in the related art, such as the difficulty in maintaining consistency in heterogeneous computing systems, high protocol complexity, poor scalability, and poor hardware support, this embodiment proposes a consistency maintenance method based on graph-driven, dynamically perceiving the operating state of heterogeneous computing systems, and dynamically adjusting the system cache coherence protocol. A cache coherence controller with computer program code for implementing the following method steps can be built into any of the above servers or cloud servers. A component for collecting operating state data and a component for collecting data block access sequences are built into each server. The operating state data includes CPU load rate, GPU cache hit rate, network latency data, etc. The cache coherence controller determines the hot data access path of the heterogeneous computing system at each moment or the concerned moment in real time according to the access order and the strength of the dependency relationship of each data block of the heterogeneous computing system. According to the hot data access path, the workload information, cache validity information, and cross-device communication information of the heterogeneous computing system at the current moment are used to generate the operating state information at the corresponding moment. Based on the relationship between the operating state of the heterogeneous computing system and the type of cache coherence protocol learned or constructed in advance, the cache coherence protocol that best matches the current operating state of the heterogeneous computing system is determined according to the operating state information at this moment. If the current heterogeneous computing system uses this cache coherence protocol, there is no need to switch. If the current heterogeneous computing system does not use this cache coherence protocol, it is switched to this cache coherence protocol to effectively and dynamically adjust the cache coherence protocol and ensure the high performance and cache data consistency of the heterogeneous computing system. It should be noted that this application scenario is only shown for the convenience of understanding the idea and principle of the present invention, and the embodiments of the present invention are not limited in this regard. On the contrary, the embodiments of the present invention can be applied to any applicable scenario. After introducing the technical solution of the present invention, the various non-limiting embodiments of the present invention will be described in detail below with reference to the drawings and specific embodiments.

[0026] First, please refer to Figure 2 , Figure 2The flow chart of a cache coherence maintenance method provided by this embodiment. Compared with homogeneous computing systems, heterogeneous computing systems are more complex. First, there are differences in memory coherence models among computing units, that is, differences in the agreements between software and memory. For example, CPUs adopt strong coherence models, while most acceleration devices such as GPUs and FPGAs use weak coherence models. Such differences make it difficult to coordinate read and write operations across devices, easily leading to data competition problems, which in turn affect the system's performance and data coherence. Second, there are significant differences in communication latency and bandwidth between devices. This difference requires protocol optimization to consider the communication characteristics between devices. For example, the communication latency between a CPU and a GPU may be relatively low, while the communication latency between a CPU and an FPGA or NPU may be relatively high. In addition, the load in a heterogeneous computing system is usually dynamically changing. Different devices may undertake different computing tasks at different times. The cache coherence protocol needs to be able to adapt to these changes in real time and dynamically adjust protocol strategies to ensure the high performance and data coherence of the system. These situations result in a very high complexity in maintaining cache coherence in heterogeneous computing systems. The present invention provides the following embodiments to effectively maintain the cache coherence of heterogeneous computing systems: S201: Determine the hot data access path of the heterogeneous computing system at the current moment according to the access order and the strength of the dependency relationship of each data block in the heterogeneous computing system at the current moment.

[0027] The heterogeneous computing system can be a multi - heterogeneous computing system, a non - multi - heterogeneous computing system, or any type of heterogeneous computing system, as long as it meets the definition of a heterogeneous computing system. The present invention makes no specific limitations in this regard. The access order refers to the order of data reading and writing between different data blocks. The strength of the dependency relationship includes whether there are read - write dependencies between different data blocks. If there are read operation dependencies or write operation dependencies, the strength of this dependency relationship. For example, the strength can be represented by the proportion of the cross - access times in the respective read and write operation times. The hot data access path refers to the access path between data blocks. The access between these data blocks is a key link in the heterogeneous computing system, or rather, the read - write situation that has the greatest impact on the performance of the current heterogeneous computing system.

[0028] S202: Generate the current running state information according to the hot data access path, the workload information, the cache validity information, and the cross - device communication information of the heterogeneous computing system at the current moment.

[0029] It can be understood that the load in a heterogeneous computing system is usually dynamically changing. Different devices may undertake different computing tasks at different times. Only by adapting to these changes in real time can the cache coherence protocol ensure the performance of the heterogeneous computing system. In this step, the hot data access path determined in the previous step, together with the workload information, cache validity information, and cross-device communication information of the heterogeneous computing system, are used as data reflecting the dynamic changes of the heterogeneous computing system at different moments. That is, the current running state information refers to the hot data access path determined through S201 at the current moment, and the dataset of workload information, cache validity information, and cross-device communication information obtained through the monitoring tool at the current moment. Among them, the workload information can be the load of the CPU of the computing node. The cache validity information refers to the effectiveness of the cache mechanism in satisfying memory requests. The cache can be the cache of the acceleration device built into the computing node, such as the cache of a GPU or an FPGA. The cross-device communication information is the network communication situation between different computing units or the network communication situation between different computing nodes.

[0030] S203: Based on the relationship between the running state of the heterogeneous computing system and the type of cache coherence protocol, determine the cache coherence protocol that best matches the current running state of the heterogeneous computing system according to the current running state information.

[0031] It is understandable that the choice of cache coherence protocol affects the overall performance of the heterogeneous computing system. To ensure high system performance, this step dynamically selects the optimal cache coherence protocol according to the current state of the system. To address the traditional protocol selection methods, such as those based on manually set thresholds or fixed protocol patterns that cannot be dynamically adjusted according to the real-time state and load changes of the system, resulting in protocol rigidity and inability to achieve optimal performance. This step can pre-learn the relationship between the operating state of the heterogeneous computing system and the type of cache coherence protocol through algorithms such as large artificial intelligence models or deep learning. When pre-learning the relationship between the two, the method for determining the operating state data in the training samples or the samples in the fine-tuning stage is the same as that of the above S201 and S202. With the help of artificial intelligence models and deep learning algorithms, an accurate relationship between the operating state and the type of cache coherence protocol can be obtained. After the operating state information of the heterogeneous computing system is determined in S202, the most suitable protocol can be automatically selected under different load scenarios. If the cache coherence protocol adopted by the current heterogeneous computing system is the same as the most matching cache coherence protocol selected, there is no need to adjust the protocol. If the cache coherence protocol adopted by the current heterogeneous computing system is different from the most matching cache coherence protocol selected, switch to the most matching cache coherence protocol selected in this step, realizing effective dynamic adjustment of the cache coherence protocol mode, real-time optimization of protocol selection, thereby minimizing communication overhead and latency, improving the system throughput, significantly enhancing the adaptability and flexibility of the system, overcoming the drawbacks of traditional protocol rigidity, and enhancing the overall performance of the heterogeneous computing system.

[0032] In the technical solution provided in this embodiment, the data flow and dependency relationship across devices can be dynamically captured according to the access information between data blocks of the heterogeneous computing system at different times, so as to accurately determine the hot data access path that reflects the key links of data access in the heterogeneous computing system. Through the hot data access path, the part that has the greatest impact on the performance of the heterogeneous computing system can be determined, providing accurate data support for the optimization of the cache coherence protocol. The dynamic changes of the heterogeneous computing system can be accurately and efficiently perceived through the current workload information, cache valid information, and cross-device communication information of the heterogeneous computing system. Under the relationship between the operating state of the heterogeneous computing system and the type of cache coherence protocol, the cache coherence protocol that is most matched with the current state of the heterogeneous computing system can be dynamically adjusted through the current state, realizing effective dynamic adjustment of the cache coherence protocol, minimizing communication overhead and latency, improving the system throughput, and ensuring the high performance and cache data consistency of the heterogeneous computing system.

[0033] The data access patterns between different computing units in a heterogeneous computing system are complex and diverse, and change dynamically with the variation of application loads. Considering the load modeling methods described in related technologies, such as those based on fixed feature vectors or static configurations, it is difficult to accurately capture such dynamic changes, resulting in a lack of accurate data support when performing protocol selection in S203. In view of this, this embodiment proposes graph-driven load modeling, which dynamically captures the data flow and dependencies across devices by constructing a data access dependency graph. The process of graph-driven load modeling may include the following: Obtain the access information between data blocks in the heterogeneous computing system, determine the access order and dependencies between data blocks according to the access information, and construct a data access dependency graph with data blocks as graph nodes and the dependencies between data blocks as the connecting edges between graph nodes; determine the corresponding edge weights according to the read / write operation time information and the number of read / write operations of data blocks with dependencies; determine the hot data access path of the heterogeneous computing system at the current moment by analyzing the edge weights of the connecting edges between different graph nodes.

[0034] In this embodiment, the access information includes at least read / write operation time information and operation type. A lightweight probe can be implanted in each computing unit in advance, and the access sequence of data blocks, including information such as the time stamps of read / write operations and operation types, is recorded in real time through this probe. An off-line analysis tool (such as Apache Spark (tool name)) is used to analyze the access information collected by the lightweight probe, and a directed data access dependency graph is constructed with data blocks as graph nodes and the dependencies between data blocks as the connecting edges between graph nodes. On this basis, for each connecting edge of the data access dependency graph, the access information of the data blocks corresponding to the graph nodes on both sides of the connecting edge is calculated to determine the strength of the dependency relationship between the two, and this dependency relationship strength is used as the edge weight of the connecting edge. Each node of this directed graph represents a data block, the edge represents the dependency relationship between data blocks, and the weight of the edge reflects the strength of the dependency. Through this data access dependency graph, the critical path and synchronization hotspots of data access can be intuitively identified. The critical path is the hot access path, and the synchronization hotspots are the data blocks on the hot access path, thus playing a role in dynamically capturing the data flow and dependencies across devices and being able to provide accurate data support for subsequent protocol optimization.

[0035] Exemplarily, an exemplary implementation of determining edge weights based on access information of data blocks is as follows: For a first data block and a second data block with read-write dependencies, the first data block and the second data block are data blocks corresponding to any two graph nodes with a connecting edge in a data access dependency graph. For the sake of convenience of description, they are respectively defined as the first data block and the second data block. Determine the strength of the dependency between the first data block and the second data block based on the maximum value between the read count and the write count of the first data block, the maximum value between the read count and the write count of the second data block, and the cross-access count between the first data block and the second data block, so as to use it as the weight of the connecting edge between the first data block and the second data block in the data access dependency graph. To further improve the overall efficiency, a dependency strength calculation formula can be pre-stored. The dependency strength calculation formula can be expressed as: ; where the first data block is a data block , and its access information can be successively expressed as: read count , write count , the second data block is a data block , and its access information can be successively expressed as: read count , write count , and the dependency relationship between the two, that is, the edge weight . For example, two data blocks and data block in the data access dependency graph have a connecting edge. Among them, has a read count , write count , data block has a read count , write count . If 's write operation depends on 's read result, and the cross-access count is 6, then the edge weight between the two is obtained by calling the above dependency strength calculation formula: .

[0036] Exemplarily, the process of determining the hot data access path is as follows: Calculate the associated connecting edges passed by data access between each two graph nodes of the data access dependency graph respectively; Use the sum of the edge weights of each associated connecting edge as the weight of the corresponding data access path, and use the data access path with the largest weight value as the current hot data access path.

[0037] In this embodiment, in the process of determining the hot data access path of the heterogeneous computing system, the maximum weight sum can reflect the key link of data access in the system. The hot data access path can select the path with the largest weight sum in the graph. By calculating the weight sum of all paths in the data access dependency graph, the path with the largest weight sum is found, which is the hot data access path. The identification of the hot data access path can adopt the longest path algorithm, and the path weight sum can be defined as: in, Represents an edge on the access path P between data block i and data block j, and W(P) is the sum of the weights of the path. For example, a graph algorithm library (such as NetworkX (algorithm library name)) can be used to regularly extract hot data access paths from the data access dependency graph through the longest path algorithm. The identification of key paths such as hot data access paths can help the system to focus on optimizing those parts that have the greatest impact on performance, thereby effectively perceiving heterogeneous computing systems and providing accurate data support for effectively optimizing cache consistency protocols.

[0038] In order to further optimize system performance, the data access dependency graph can also be optimized. For example, when the pre-set graph update conditions are met, such as at regular intervals or when instructions are received, new access information of each data block of the heterogeneous computing system is obtained; based on the new access information, the connection edges and edge weights of the data access dependency graph are updated, and the connection edges between graph nodes with edge weights less than the preset edge weight threshold are deleted from the data access dependency graph. For example, during system operation, the data access dependency graph is incrementally updated at regular intervals (such as 10 seconds), node attributes and edge weights are adjusted according to the latest data access information, and edges with weights lower than the preset edge weight threshold (such as 0.1) are pruned to avoid the data access dependency graph from occupying a large amount of memory resources and affecting system performance, so as to maintain the accuracy and timeliness of the data access dependency graph and optimize system performance.

[0039] In order to further improve the effective optimization of the cache consistency protocol, based on the above embodiment, a priority synchronization area can also be extracted, which may include the following contents: calculating the weights and corresponding access paths between different graph nodes in the statistical data access dependency graph, and determining the target access path whose weight and exceeds the preset path weight threshold; generating a hotspot data subgraph according to the target graph nodes corresponding to the target access path and their corresponding connecting edges as a high priority synchronization area.

[0040] In this embodiment, after determining that the data access dependency graph has the weights of each edge connecting the edges, the weights and the weights exceeding the preset path weight threshold can also be extracted. , marking it as a high priority synchronization region. For example, there is a path in the data access dependency graph , , , the sum of path weights is , when , then this path is marked as a path in the high-priority synchronization area. In this embodiment, by identifying the hot data subgraph of the system performance bottleneck and paying attention to and optimizing it, the data access and synchronization operations on each path of the hot data subgraph are preferentially optimized, which can effectively improve the overall performance of the heterogeneous computing system.

[0041] As can be seen from the above, in this embodiment, through graph-driven load modeling, a data access dependency graph can be constructed and maintained, and the access order and dependency strength between data blocks intuitively represented by it are used to accurately identify the synchronization hotspots and critical paths in the system, which can accurately and dynamically capture the data flow and dependency relationships across devices, reflect the system state in real time, provide an accurate data basis for subsequent protocol optimization, effectively solve the problem of inaccurate load modeling in related technologies, and improve the overall performance and adaptability of the system.

[0042] It can be understood that the real-time state perception of the heterogeneous computing system affects the entire protocol optimization. This embodiment also provides ensuring the accuracy and timeliness of the running state of the heterogeneous computing system by real-time sensing the CPU load rate, cache hit rate of the specified computing unit, and network latency performance metrics, which may include the following: obtaining the main processor load rate of the heterogeneous computing system at the current moment, cache hit rate of the target processor of a different type from the main processor, and network latency information; generating the current running state information according to the edge weights of the hot data access paths, main processor load rate, cache hit rate, and network latency information.

[0043] In this embodiment, a state space model for describing the statistical model of time series data can be constructed, and the running state of the heterogeneous computing system is reflected through this model. The state space model can be represented by a vector, which contains multiple performance metrics that can comprehensively reflect the current running situation of the system. Exemplarily, the state space model of the system can be expressed as: . Among them, the CPU load rate reflects the current workload of the CPU; the GPU cache hit rate represents the effectiveness of the GPU cache, and the network latency reflects the communication latency between devices. These three metric variables can be observed through system tools and the corresponding values can be obtained. For example, these performance metrics can be collected in real time through system monitoring tools to ensure the accuracy and timeliness of the state space model.

[0044] For example, at time t, the edge weight of the hot data access path of the data access dependency graph is 0.4, the CPU load rate is obtained as 70% through the monitoring tool, the GPU cache hit rate is 85%, and the network latency is 10 ms. Then the state space model at this moment can be .

[0045] As can be seen from the above, by comprehensively considering these factors, this embodiment can comprehensively reflect the current operating state of the system, provide accurate input information for the artificial intelligence model or deep learning algorithm, and thus achieve accurate protocol decision-making.

[0046] The above embodiments do not make any limitation on what kind of machine learning method is used to learn the relationship between the operating state of the heterogeneous computing system and the cache coherence protocol type. Among them, the reinforcement learning algorithm learns the optimal behavior through the interaction between the agent and the environment. However, the convergence speed of the reinforcement learning algorithm is slow. In a complex heterogeneous computing system, the state space and action space may be very large, which further makes the convergence speed of the reinforcement learning algorithm too slow, resulting in the inability to respond to the dynamic changes of the system in a timely manner. The present invention is based on the reinforcement learning algorithm and realizes the learning of the corresponding relationship between the system operating state and the cache coherence protocol type on the basis of overcoming the shortcoming of its slow convergence speed. As Figure 3 shown, it may include the following contents: S301: According to multiple groups of operating state sample information and the action space, using one of the cache coherence protocols in the operating state sample information and the action space as a state-action sample pair, and generating a state-protocol relationship recognition model in a way that each state-action sample pair has an expected return value.

[0047] S302: Initialize the expected return values of each state-action sample pair of the state-protocol relationship recognition model to an initial value, and construct multiple training sequences according to each state-action sample pair.

[0048] S303: Select one training sequence from multiple training sequences as the current training sequence.

[0049] Among them, the training process of the current training sequence includes the following S304~S307.

[0050] S304: Starting from the initial state, for each time step, randomly select the corresponding cache coherence protocol from the action space for the current operating state sample information with the first preset probability to generate a new state-action sample pair.

[0051] S305: Select the optimal cache coherence protocol with the largest expected return value corresponding to the current operating state sample information with the second preset probability.

[0052] S306: Execute the optimal cache coherence protocol, determine the reward value of the heterogeneous computing system for executing the optimal cache coherence protocol according to the computing performance data and network performance data of the heterogeneous computing system, and obtain the next operating state sample information of the current operating state sample information.

[0053] S307: Update the expected return value of the current state-action sample pair in the state-protocol relationship recognition model based on the current state-action sample pair formed by the current running state sample information and the optimal cache coherence protocol, the current expected return value, the reward value, and the future expected return value corresponding to the next running state sample information in the state-protocol relationship recognition model.

[0054] S308: When the maximum time step or the environment termination condition is reached, end the training of the current training sequence, jump to execute S304, and continue the corresponding training for the next training sequence until the preset number of training rounds is reached or the state-protocol relationship recognition model converges, obtaining the trained state-protocol relationship recognition model.

[0055] Among them, the reinforcement learning method learns the optimal behavior strategy through the interaction between the agent and the environment. The agent in this embodiment is a functional module that implements the computer program code for making the optimal cache coherence protocol decision in this embodiment, that is, this functional module can dynamically select the optimal cache coherence protocol according to the current state of the system, and the environment is the entire heterogeneous computing system. In order to utilize the reinforcement learning algorithm to learn the relationship between the running state of the system and the protocol selection, this embodiment also defines an action space that describes the set of actions that can be taken. The action in this embodiment refers to the cache coherence protocol to be selected. Correspondingly, the action space can include multiple different types of cache coherence protocols. These multiple cache coherence protocols can be either existing cache coherence protocols or cache coherence protocols defined and combined by those skilled in the art according to the actual scenario, which does not affect the implementation of the present invention.

[0056] Among them, a training sequence is a complete trajectory in which the state-protocol relationship recognition model executes actions, obtains rewards, and transfers states in the environment. A training sequence is a sequence starting from the initial state and ending at the termination state. For example, it can be expressed as: , is the state at time step t, T is the total number of time steps, is the action selected in the state , is the immediate reward obtained after executing the action , is the new state after the transfer. Each training sequence provides multiple state-action samples, that is, tuples to update the expected return values of the state-action samples of the state protocol relationship recognition model. The state-action samples of the state protocol relationship recognition model can exist in the form of a table, such as a Q-table, where the rows represent all possible states and the columns represent all possible actions. Each cell stores a Q-value (expected return value), i.e., Q(s, a). The state-action sample pair represents the expected return value of selecting an action in a specific state. The training of the state protocol relationship recognition model is to repeatedly update these Q-values to converge to the optimal value, i.e., to maximize the cumulative reward.

[0057] Among them, the training process of the state protocol relationship recognition model includes an inner loop and an outer loop. A single training sequence is limited by the length of the sequence and the exploration strategy of the agent, such as ε-greedy, and may only cover a part of the state-action pairs in the Q-table. The outer loop ensures that different states and actions can be explored by constructing multiple training sequences, so as to cover more or all of the state-action pairs in the Q-table. The number of times of the outer loop, that is, the number of training sequences, affects the convergence of the model. The more sequences, the more complete the covered state-action pairs, and the closer the Q-table is to the optimal. The outer loop sequentially selects each training sequence, and each training sequence starts from the beginning (initial state) until the termination state, that is, the memory loop of the training sequence. When the inner loop ends, that is, when the termination state is reached, all the transitions of this training sequence are used to update the corresponding state-action pairs. That is to say, the state-action transitions (i.e., pairs) in each training sequence are used to update the corresponding state-action pairs in the Q-table. At each time step of the inner loop, the algorithm uses a transition in the sequence to calculate the error and update the value in the Q-table. Each training sequence will update multiple state-action pairs. The number of state-action pairs updated is the same as the number of time steps in the training sequence, but each update is only for the state-action pairs actually appearing in the sequence. Among them, the current expected return value refers to the expected return value of the state-action sample pair at the current moment. The reward value is used to evaluate the immediate return of selecting a certain cache coherence protocol under a certain running state information. The future expected return value corresponding to the next running state sample information can be exemplarily selected as the maximum expected return value: from the next running state sample information with a first preset probability, randomly select the maximum value among the expected return values corresponding to each cache coherence protocol from the action space as the future expected return value.

[0058] To further improve the effectiveness of protocol optimization, based on the above embodiments, the present invention can also redefine three protocol modes, the metadata index protocol, the multicast synchronization protocol, and the hybrid response protocol, for the cache coherence protocols of the heterogeneous computing system according to different read-write ratios. Correspondingly, the action space Including an optional cache coherence protocol mode, which can be expressed as: . Among them, the metadata index protocol, the multicast synchronization protocol, and the hybrid response protocol can respectively correspond to high-write scenarios, high-read scenarios, and dynamic balance scenarios.

[0059] Among them, the metadata index protocol is implemented in a directory manner. Based on the directory protocol, it has a lightweight directory tree and adopts a hierarchical directory structure (non-global directory). Each computing unit maintains its own metadata, such as cache status and version number. That is, each computing unit stores the directory information of its own metadata through its own directory, and this directory information can exist in the form of a directory table. The directory table records the status of each cache line of the local private cache of the computing unit, whether the read and write data hits the cache, the version number, etc. The central directory information can be deployed in one of the computing units, or the computing unit with the best performance, or the computing unit specified by the user, such as the computing unit where the data block with a high write frequency is located. That is, the target data block that meets the condition that the write frequency is greater than the preset frequency threshold has central directory information. The central directory information at least records the correspondence between different directory information and the corresponding computing units, and the storage address of the data, that is, it records the information that can reflect the global cache situation. The directory information of each computing unit and the central directory information constitute the lightweight directory tree of the metadata index protocol. Through the lightweight directory tree, the metadata index protocol only queries the directory when necessary, avoiding broadcast storms. At the same time, it reduces the global lock competition through the hierarchical directory, and the write operation latency is reduced by 15% - 20%. Compared with the traditional broadcast protocol, there is no broadcast traffic and the network load is more stable. To further optimize the protocol, dynamic directory compression can also be performed: compress and store the directory entries of cold data with low access frequency to reduce memory occupancy. Compared with the traditional directory protocol's directory hierarchical compression, the metadata overhead is reduced by 30%, and the write operation latency is reduced by 15% - 20%.

[0060] Among them, the multicast synchronization protocol is applicable to high read load scenarios. By maximizing the cache hit rate, the local cache directly responds to read requests, reducing the number of metadata queries and the metadata verification latency, thereby effectively reducing the read latency. The multicast synchronization protocol enables each computing unit to perform corresponding operations based on the listening information of the multicast channel, and the multicast range is a protocol dynamically adjusted according to the cache hit rate. That is to say, the multicast synchronization protocol performs multicast probabilistically, and the probability dynamically adjusts the multicast range depending on the cache hit rate of the computing unit. Secondly, it adopts a listening-based cache verification, that is, the computing units within the multicast range listen to the multicast channel and perform corresponding operations after receiving the update notification. For example, if the state of the local cache is "non-dirty", that is, the data in the cache line of the local cache has not been modified, it is directly marked as expired and asynchronously refreshed. If the local cache is in the "dirty" state, that is, the data in the cache line of the local cache has been modified but has not been written back to the main memory, a conflict detection mechanism can be triggered, such as version number comparison, and the latest version is preferentially retained. Compared with the traditional directory protocol, the read operation of the multicast synchronization protocol does not require directory queries, has a lower latency, and the read latency is reduced by 25% - 30%. Compared with the traditional full-broadcast protocol, probabilistic multicast reduces redundant traffic, the network load drops by 10% - 15%, optimizes the bandwidth, and the bandwidth utilization rate is increased by 20%.

[0061] Among them, the hybrid response protocol is a fusion protocol of the directory protocol and the broadcast protocol. This protocol decouples the read and write strategies: the write operation adopts the directory lock mechanism of the metadata index protocol to ensure consistency. For the read operation, the strategy is dynamically selected according to the real-time load. If the current load is low, the local cache of the multicast synchronization protocol is enabled to directly respond. If the load is high, metadata verification is triggered to avoid multicast congestion, where the high and low loads can be measured by preset thresholds, and the protocol state machine of the data block can be maintained through the state migration engine. The protocol state machine records the cache states of all data blocks, and the cache states such as the modified state, exclusive state, dirty state, invalid state, and shared state ensure the validity of the data through the cache state of the data block, thereby ensuring data consistency and making the copies of the same data in different local private caches of the heterogeneous computing system consistent. This protocol dynamically balances the read-write mixed load, adapts to rapid load changes, and the state migration engine avoids cache invalidation during protocol switching by achieving a smooth transition during the protocol switching process and avoiding performance oscillation. Compared with the traditional directory protocol, it dynamically integrates the directory and broadcast mechanisms, avoiding the limitations of a single protocol. Compared with the traditional broadcast protocol, it supports on-demand switching and has stronger compatibility.

[0062] In order to further improve the model convergence speed, enhance the model training performance, and ensure that the relationship between the learned protocol and the operating state of the heterogeneous computing system is more accurate, this embodiment also provides a calculation method for the reward value of the heterogeneous computing system to execute the optimal cache coherence protocol, which may include: obtaining the throughput, network overhead, synchronization delay of the heterogeneous computing system, and their respective weight coefficients; taking the difference between the product of the throughput and the throughput weight coefficient, the product of the network overhead and the network overhead weight coefficient, and the product of the synchronization delay and the synchronization delay weight coefficient as the reward value of the heterogeneous computing system at the current moment.

[0063] In this embodiment, the system throughput is the number of transactions that the heterogeneous computing system can process per unit time, which is used to measure the system performance. The network overhead and synchronization delay reflect the network performance, and may include, for example, delay, bandwidth, throughput, and response time. In order to further improve the overall efficiency, the reward function relationship may be pre-stored. The reward function relationship may be expressed as: , where, represents the reward value of the heterogeneous computing system at time t, are the weight coefficients of the system throughput, network overhead, and synchronization delay respectively, which are used to balance the importance of different performance indicators. The default value may be set to 1 / 3, or it may be flexibly set according to the actual scenario. The present invention does not make any limitation on this.

[0064] In order to further improve the model convergence speed, enhance the model training performance, and ensure that the relationship between the learned protocol and the operating state of the heterogeneous computing system is more accurate, this embodiment also provides an exemplary expected return update method, which may include: determining the future return information according to the maximum value of the expected return values of each cache coherence protocol selected by the heterogeneous computing system under the next operating state sample information and the future return weight value, and calculating the sum of the reward value and the future return information as the return reward information; taking the difference between the return reward information and the current expected return value of the current state-action sample pair in the state-protocol relationship recognition model, and calculating the product of the difference and the update speed adjustment factor as the return reward update information; taking the sum of the current expected return value and the return reward update information as the updated value of the expected return value of the current state-action sample pair in the state-protocol relationship recognition model.

[0065] This embodiment selects the optimal strategy by learning the value of the state-action sample pair. The value represents the expected return of adopting a certain cache coherence protocol under a certain operating state information. In order to further improve the overall efficiency, the expected return update relationship may be pre-expected, and the Q value is updated by calling the expected return update relationship. The expected return update relationship may be expressed as: .

[0066] Where, is the update speed adjustment factor, used to control the update speed of the value, is the future return weight value, used to control the weight of future returns. The default settings for both are 0.5, and the values can also be flexibly adjusted according to the actual situation. is the operation status information corresponding to time t under which a cache coherence protocol is selected in , that is, the value of the current state-action sample pair in the state protocol relationship recognition model, which is also the current expected return value is the maximum value of all possible actions under the operation status sample information at the next time. value.

[0067] To make the technical solution of the present invention clearer to those skilled in the art, the present invention also provides an implementation process for determining the relationship between the operation status of a heterogeneous computing system and the type of cache coherence protocol through reinforcement learning: A11: Initialization phase: Set the Q values of all state-action sample pairs in the Q table to 0, and set the update speed adjustment factor , the future return weight value , and the weight coefficients of system throughput, network overhead, and synchronization delay respectively .

[0068] A12: State perception phase: Collect the CPU load rate, GPU cache hit rate, and network latency of the heterogeneous computing system at time t through system monitoring tools, and calculate the edge weights of the hot data access paths in the data access dependency graph to generate the operation status information .

[0069] A13: Cache coherence protocol selection phase: Use the ε-greedy greedy strategy to select a cache coherence protocol: randomly select an action with probability ε to explore new state-action sample pairs, and select the cache coherence protocol with the highest Q value in the current state with probability 1-ε to utilize the known optimal strategy. Among them, ε can be set to a larger value, such as 0.9, in the initial stage, and the value of ε is gradually reduced as the training progresses to reduce the exploration frequency and increase the utilization frequency. The value of ε can also be gradually reduced by setting a decay rate. For example, multiply the value of ε by a decay factor (such as 0.9) after each iteration, which can ensure that the value of ε gradually decreases.

[0070] A14: Protocol execution phase: According to the selected action , execute the corresponding cache coherence protocol to obtain the immediate reward after executing the action and the next state .

[0071] A15: Update the Q-table by invoking the expected return update relation.

[0072] A16: Iterative optimization: Repeat the above steps until the Q-table converges, that is, the change in Q value is less than a specified threshold, such as 0.01. If necessary, the Q-table can be fine-tuned periodically to adapt to the dynamic changes of the heterogeneous computing system. Among them, based on the pre-trained model, that is, the Q-table, small-scale training is carried out for specific task objectives (downstream tasks) and task data (downstream data) to achieve slight adjustment of the parameters of the pre-trained model, and finally a model adapted to specific tasks and data is obtained.

[0073] To avoid the relationship between the learned operating state of the heterogeneous computing system and the cache coherence protocol type from being inaccurate with the change of the environment of the heterogeneous computing system, and to avoid large fluctuations in system performance due to policy adjustment, the present invention also provides an online fine-tuning of the pre-trained model by the heterogeneous computing system according to real-time data: An experience replay cache is pre-constructed, and multiple groups of state-action history pairs during the operation of the heterogeneous computing system are stored in the experience replay cache; each state-action history pair is utilized, and on the basis of dynamically adjusting the first preset probability, the state protocol relationship recognition model is fine-tuned. Among them, the state-action history pair at least includes historical information of the operating state and its corresponding cache coherence protocol, historical information of the next operating state, and historical reward value. After actual deployment, the heterogeneous computing system will store the historical state-action pairs in the experience replay cache, and sample and update the Q-table regularly to ensure the adaptability and stability of the policy. In addition, during the process of selecting an action using the ε-greedy greedy strategy, the exploration probability ε can be dynamically adjusted. For example, the adjustment method can adopt linear decay: set the initial ε (such as 1.0) and the minimum ε (such as 0.01), and linearly decrease during the training process. The exponential function can also be used to decay the value of ε, such as through the relation , where dr represents a preset decay rate parameter, and step can be the number of training steps or the number of training sequences. Of course, it can also be dynamically adjusted according to the training performance (such as the average reward). For example, when the average reward has not improved for several consecutive episodes (training cycles), increase ε to encourage exploration.

[0074] For example, the operating state information at time t is , the currently selected protocol is the metadata index protocol, , , . According to the ε-greedy greedy strategy, select the action with the highest Q value in the current state , execute the metadata index protocol, and obtain the immediate reward and the next state : , the maximum expected return corresponding to the next state is: . Obtain , calculate , update 0.5 in the Q-table to 0.611.

[0075] As can be seen from the above, based on the reinforcement learning algorithm, this embodiment analyzes the running state of the heterogeneous computing system in real time, selects the most suitable protocol for the current state from multiple protocol modes, and solves the problem that the convergence speed of the reinforcement learning algorithm is too slow to respond to the dynamic changes of the system in a timely manner through the action selection method, the reward value determination method, and the immediate return value update determination method. By continuously optimizing the protocol selection strategy, it realizes the dynamic selection of the optimal cache coherence protocol according to the current state of the heterogeneous computing system, thereby minimizing communication overhead and latency and improving the throughput of the system. Through experience replay, the learning efficiency can be improved, the correlation of samples can be reduced, the probability value can be adjusted, the selection accuracy of the optimal cache coherence protocol can be ensured, the adaptability and flexibility of the heterogeneous computing system can be significantly improved, and the overall performance of the system can be optimized.

[0076] Considering that non-MAC (non multi-copy atomicity) devices are increasingly widely used in heterogeneous computing systems, and the cache coherence solutions of related technologies lack support for these devices, resulting in non-MAC being unable to fully utilize its performance advantages and restricting the overall computing power of the system. Based on the above embodiment, the present invention also provides an implementation method for synchronizing the cache state of non-multi-copy atomicity devices. The non-MCA compatible implementation process may include the following content: If there is at least one first target computing unit in the heterogeneous computing system that belongs to a non-multi-copy atomicity device, for a write request to the first target computing unit, store the target write data corresponding to the write request in the target private cache of the first target computing unit; when the write operation submission process is triggered, write the target write data to the target write address corresponding to the write request.

[0077] Among them, the first target computing unit is a computing unit in the heterogeneous computing system, and this computing unit is non-MAC, such as an NPU. For the convenience of description, it is defined as the first target computing unit. The write operation submission process can be any triggering strategy. That is to say, the write operation of non-MCA in this embodiment is delayed submission. Through the delayed submission method, the write operation of non-MCA can be temporarily stored in the local buffer until a certain condition is met and then submitted. When this condition is met, the write operation submission process is triggered, reducing the number of global submissions and reducing system overhead.

[0078] Exemplarily, this embodiment also provides multiple ways of deferred submission: One exemplary scenario is as follows: There are multiple write requests. When the remaining space capacity of the target private cache reaches a preset capacity threshold, the write operation submission process is triggered, and each target write data in the target private cache is batch-written to the corresponding target write address. Another parallel exemplary scenario is as follows: The target write address corresponding to the target write data is located in the target data block. When it is detected that the second target computing unit initiates a read request for the target data block, the target write data is first written to the target data block, and then the corresponding read operation is executed; where the second target computing unit is other computing units in the heterogeneous computing system that are not the first target computing unit. That is to say, the non-MCA write operations are temporarily stored in the local buffer and submitted only when one of the following conditions is met: The first condition: The buffer is full (batch submission): When the local buffer reaches a certain capacity, the cached write operations are batch-submitted. This method can reduce the number of global submissions and lower the system overhead. The second condition: The cross-device read request hits (on-demand submission): When other devices initiate a read request and hit the data in the local buffer, the relevant write operations are submitted on demand to ensure data consistency.

[0079] Furthermore, in order to fully optimize the non-MCA device synchronization operation, during the implementation of the non-MCA compatible design, in addition to supporting deferred submission and partial atomicity operations, in order to distinguish different levels of atomicity operations, partial atomicity markers can also be introduced. For example, each write operation can be added with a tag , and the global synchronization is triggered only when necessary, that is, only the operations at the FULL level trigger the global synchronization, further improving the operation efficiency of the heterogeneous computing system. This compatible design can not only effectively support non-MCA devices, but also improve the overall performance and reliability of the system, enabling the heterogeneous computing system to better adapt to diverse hardware environments.

[0080] For example, an FPGA is a non-MCA device, and it performs multiple write operations on a data block. These write operations are temporarily stored in the local buffer. When the buffer is full, these write operations are batch-submitted and marked as PARTIAL partial atomicity. If at this time other computing units initiate a read request, the relevant write operations are submitted on demand and the data consistency is ensured. Only when global synchronization is required, the write operations are marked as FULL atomicity and the global synchronization is triggered.

[0081] Furthermore, to ensure data consistency and correctness, conflict detection and rollback operations can also be performed when submitting write operations: set full atomicity tags and partial atomicity tags for write operations in advance, and the full atomicity tags trigger global synchronization operations; during the process of writing the target write data to the target write address corresponding to the write request, assign partial atomicity tags to the write request, and detect whether there is a version conflict between the global version number and the local version number of the target data block where the target write address is located; when the global version number of the target data block is less than the local version number, there is a version conflict, and load the latest version of the data from the global cache of the heterogeneous computing system; when the global version number of the target data block is greater than or equal to the local version number, write the target write data to the target write address.

[0082] In this embodiment, each data block of the heterogeneous computing system can maintain a global version number and a local version number , and the conflict condition can be: , for the i-th data block , during the submission process, a version conflict is detected, that is, when is satisfied, the local modification will be automatically rolled back, and the latest version of the data will be loaded from the global cache to ensure the stable operation of the system.

[0083] As can be seen from the above, this embodiment can be compatible with non-MCA, support the efficient synchronization of non-MCA devices, make full use of the performance of non-MCA, and improve the overall computing power of the heterogeneous computing system by supporting deferred submission and partial atomicity operations. By distinguishing different levels of atomicity operations and triggering global synchronization only when necessary, the number of global synchronizations is effectively reduced, the operation efficiency of the heterogeneous computing system is improved, and the atomicity of the data is ensured at the same time. By performing version conflict detection during the submission of non-MAC write operations, data consistency and correctness are ensured.

[0084] It should be noted that there is no strict order of execution for the steps in the present invention. As long as it conforms to the logical order, these steps can be executed simultaneously or in a certain preset order. Figure 2 - Figure 3 This is just a schematic way and does not mean that it can only be executed in this order.

[0085] Through the description of the above embodiments, those skilled in the art can clearly understand that the method according to the above embodiments can be implemented by means of software plus a necessary general hardware platform. Of course, it can also be implemented by hardware, but in many cases, the former is a better implementation method. The present invention also provides a corresponding device for the cache coherence maintenance method, further making the method more practical. Among them, the device can be described from the perspective of functional modules and the perspective of hardware respectively. The cache coherence maintenance device provided by the present invention will be introduced below. The following description will introduce the functions of each program module of this embodiment. The cache coherence maintenance device described below can be correspondingly referred to the cache coherence maintenance method described above.

[0086] From the perspective of functional modules, refer to Figure 4 , Figure 4 which is the structural diagram of the cache coherence maintenance device provided in this embodiment under a specific implementation manner. The device may include: A critical path identification module 401, configured to determine the hot data access path of the heterogeneous computing system at the current moment according to the access order and the strength of the dependency relationship of each data block of the heterogeneous computing system at the current moment.

[0087] A state awareness module 402, configured to generate current running state information according to the hot data access path, the workload information, the cache validity information, and the cross-device communication information of the heterogeneous computing system at the current moment.

[0088] A protocol dynamic selection module 403, configured to determine the cache coherence protocol that best matches the current running state of the heterogeneous computing system according to the current running state information based on the relationship between the running state of the heterogeneous computing system and the type of cache coherence protocol.

[0089] Exemplarily, in some embodiments of this embodiment, the above critical path identification module 401 may also be configured to: obtain the access information between each data block of the heterogeneous computing system, where the access information at least includes read / write operation time information and operation type; determine the access order and the dependency relationship between each data block according to the access information, construct a data access dependency graph with data blocks as graph nodes and the dependency relationship between data blocks as the connection edges between graph nodes; determine the corresponding edge weights according to the read / write operation time information and the number of read / write operations of the data blocks with dependency relationships; and determine the hot data access path of the heterogeneous computing system at the current moment by analyzing the edge weights of the connection edges between different graph nodes.

[0090] As a schematic implementation manner of the foregoing embodiment, the foregoing critical path identification module 401 may further be configured to: for a first data block and a second data block having a read-write dependency relationship, determine the dependency relationship strength between the first data block and the second data block according to the maximum value between the read count and the write count of the first data block, the maximum value between the read count and the write count of the second data block, and the cross-access count between the first data block and the second data block, so as to use it as the weight of the connection edge between the first data block and the second data block in the data access dependency graph.

[0091] As another schematic implementation manner of the foregoing embodiment, the foregoing critical path identification module 401 may further be configured to: when a graph update condition is satisfied, obtain new access information of each data block of the heterogeneous computing system; update the connection edges and edge weights of the data access dependency graph according to the new access information, and delete the connection edges between graph nodes with edge weights less than a preset edge weight threshold from the data access dependency graph.

[0092] As another schematic implementation manner of the foregoing embodiment, the foregoing critical path identification module 401 may further be configured to: count the sum of the weights corresponding to the access paths between different graph nodes in the data access dependency graph, and determine a target access path whose weight sum exceeds a preset path weight threshold; generate a hot data sub-graph according to the target graph nodes corresponding to the target access path and the connection edges corresponding thereto, so as to use it as a high-priority synchronization area.

[0093] As another schematic implementation manner of the foregoing embodiment, the foregoing critical path identification module 401 may further be configured to: respectively calculate the associated connection edges passed by each pair of graph nodes of the data access dependency graph for data access; use the sum of the edge weights of each associated connection edge as the weight of the corresponding data access path, and use the data access path with the largest weight value as the current hot data access path.

[0094] Exemplarily, in some other implementation manners of this embodiment, the foregoing status perception module 402 may further be configured to: obtain the main processor load rate of the heterogeneous computing system at the current moment, the cache hit rate of a target processor of a different type from the main processor, and network latency information; generate current running status information according to the edge weight of the hot data access path, the main processor load rate, the cache hit rate, and the network latency information.

[0095] Exemplarily, in some other embodiments of this embodiment, the above-mentioned protocol dynamic selection module 403 can also be used to: according to multiple groups of operation state sample information and the action space, use one of the cache coherence protocols of the operation state sample information and the action space as a state-action sample pair, and each state-action sample pair has an expected return value, generate a state-protocol relationship recognition model; the action space includes multiple different types of cache coherence protocols; initialize the expected return values of each state-action sample pair of the state-protocol relationship recognition model to initial values; construct multiple training sequences according to each state-action sample pair, and the training process of the current training sequence includes: starting from the initial state, for each time step, randomly select the corresponding cache coherence protocol for the current operation state sample information from the action space with a first preset probability to generate a new state-action sample pair; select the optimal cache coherence protocol with the largest expected return value corresponding to the current operation state sample information with a second preset probability; execute the optimal cache coherence protocol, determine the reward value of the heterogeneous computing system for executing the optimal cache coherence protocol according to the computing performance data and network performance data of the heterogeneous computing system, and obtain the next operation state sample information of the current operation state sample information; according to the current state-action sample pair formed by the current operation state sample information and the optimal cache coherence protocol, update the expected return value of the current state-action sample pair in the state-protocol relationship recognition model based on the current expected return value, reward value, and future expected return value corresponding to the next operation state sample information in the state-protocol relationship recognition model; when the maximum time step or the environment termination condition is reached, end the training of the current training sequence and perform corresponding training on the next training sequence until the preset number of training rounds or the state-protocol relationship recognition model converges, and obtain the trained state-protocol relationship recognition model.

[0096] As a schematic implementation manner of the above embodiment, the above-mentioned protocol dynamic selection module 403 can further be used to: obtain the throughput, network overhead, synchronization delay of the heterogeneous computing system and their respective weight coefficients; use the difference between the product of the throughput and the throughput weight coefficient, the product of the network overhead and the network overhead weight coefficient, and the product of the synchronization delay and the synchronization delay weight coefficient as the reward value of the heterogeneous computing system at the current moment.

[0097] As another schematic implementation manner of the above embodiment, the above-mentioned protocol dynamic selection module 403 can further be used to: randomly select the maximum value from the expected return values corresponding to each cache coherence protocol from the next operation state sample information with a first preset probability from the action space as the future expected return value.

[0098] As another illustrative implementation of the above embodiment, the above protocol dynamic selection module 403 may further be configured to: select the maximum value of the expected return values of each cache coherence protocol and the future return weight value according to the heterogeneous computing system under the next operating state sample information, determine the future return information, and calculate the sum of the reward value and the future return information as the return reward information; calculate the difference between the return reward information and the current expected return value of the current state-action sample pair in the state-protocol relationship recognition model, and calculate the product of the difference and the update speed adjustment factor as the return reward update information; use the sum of the current expected return value and the return reward update information as the updated value of the expected return value of the current state-action sample pair in the state-protocol relationship recognition model.

[0099] As another illustrative implementation of the above embodiment, the above protocol dynamic selection module 403 may further be configured to: pre-construct an experience replay cache, and store multiple groups of state-action history pairs during the operation of the heterogeneous computing system in the experience replay cache; wherein, the state-action history pair at least includes the operating state history information and its corresponding cache coherence protocol, the next operating state history information, and the historical reward value; use each state-action history pair and, on the basis of dynamically adjusting the first preset probability, fine-tune the state-protocol relationship recognition model.

[0100] As another illustrative implementation of the above embodiment, the above protocol dynamic selection module 403 may further be configured to: redefine the cache coherence protocol of the heterogeneous computing system into a metadata index protocol, a multicast synchronization protocol, and a hybrid response protocol according to different read-write ratios; wherein, the metadata index protocol is a protocol in which each computing unit includes directory information for storing its own metadata, and the target data block that satisfies the condition that the write frequency is greater than the preset frequency threshold has central directory information; the multicast synchronization protocol is a protocol in which each computing unit performs corresponding operations according to the listening information of the multicast channel, and the multicast range is dynamically adjusted according to the cache hit rate; the hybrid response protocol is a fusion protocol of the directory protocol and the broadcast protocol.

[0101] Exemplarily, in some other implementation manners of this embodiment, the above device may further include a non-MCA compatible module, which may be configured to: if at least one first target computing unit of the heterogeneous computing system belongs to a non-multi-copy atomic device, for the write request of the first target computing unit, store the target write data corresponding to the write request in the target private cache of the first target computing unit; when triggering the write operation submission process, write the target write data to the target write address corresponding to the write request.

[0102] As a schematic implementation of the above embodiments, the non-MCA compatible module may further be configured to: when there are multiple write requests and the remaining space capacity of the target private cache reaches a preset capacity threshold, trigger the write operation submission process, and batch write each target write data in the target private cache to the corresponding target write address.

[0103] As another schematic implementation of the above embodiments, the non-MCA compatible module may further be configured to: when the target write address corresponding to the target write data is located in the target data block, if it is detected that the second target computing unit initiates a read request for the target data block, first write the target write data to the target data block, and then execute the corresponding read operation.

[0104] As another schematic implementation of the above embodiments, the non-MCA compatible module may further be configured to: pre-set a full atomicity tag and a partial atomicity tag for the write operation, and the full atomicity tag triggers a global synchronization operation; during the process of writing the target write data to the target write address corresponding to the write request, assign a partial atomicity tag to the write request, and detect whether there is a version conflict between the global version number and the local version number of the target data block where the target write address is located; when the global version number of the target data block is less than the local version number, there is a version conflict, and load the latest version data from the global cache of the heterogeneous computing system; when the global version number of the target data block is greater than or equal to the local version number, write the target write data to the target write address.

[0105] The cache coherence maintenance device mentioned above is described from the perspective of functional modules. Further, the present invention also provides an electronic device, which is described from the perspective of hardware. Figure 5 FIG. is a schematic structural diagram of an electronic device provided in an embodiment of the present invention. The electronic device includes a memory 501 and a processor 502. A computer program is stored in the memory 501, and the processor 502 is configured to run the computer program to execute the steps in any of the above embodiments of the cache coherence maintenance method.

[0106] An embodiment of the present application also provides a non-volatile storage medium, in which a computer program is stored, and the computer program is configured to execute the steps in any of the above embodiments of the cache coherence maintenance method when running.

[0107] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to: various media such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc that can store a computer program.

[0108] An embodiment of the present application further provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the cache coherence maintenance method are implemented.

[0109] An embodiment of the present application further provides another computer program product, including a non-volatile computer-readable storage medium. The non-volatile computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the steps in any of the above embodiments of the cache coherence maintenance method are implemented.

[0110] Finally, the present invention also provides a heterogeneous computing system. Please refer to Figure 6 , which may include the following: The heterogeneous computing system at least includes a first computing node 601, a second computing node 602, and a cache coherence controller 603. The cache coherence controller 603 is connected to the first computing node 601 and the second computing node 602. The first computing node 601 and the second computing node 602 each include at least two computing units. The cache coherence controller 603 is used to implement the cache coherence maintenance method described in any of the above embodiments of the cache coherence maintenance method when executing a computer program.

[0111] Exemplarily, as Figure 7 shown, the cache coherence controller 603 may include a graph-driven load modeling component, a policy decision-making component, and an atomicity control component, construct and maintain a data access dependency graph for dynamically capturing cross-device data streams and dependencies, and intuitively identify the critical path and synchronization hotspots of data access through the data access dependency graph, that is, determine the hot data access path. The policy decision-making component, based on a reinforcement learning algorithm, analyzes the running state of the system in real time and selects the most suitable protocol mode for the current state from multiple protocol modes. The atomicity control component manages the cache state synchronization of non-MCA. Through the collaborative work of the three components, the cache coherence protocol can be dynamically optimized, significantly improving the performance and reliability of the heterogeneous computing system, and providing efficient technical support for fields such as intelligent driving, cloud computing, and edge computing. Taking various heterogeneous computing units of the heterogeneous computing system, such as CPUs, GPUs, etc., as the input of the cache coherence controller 603, it can output a heterogeneous computing system that can maintain data consistency.

[0112] As can be seen from the above, in this embodiment, through graph theory analysis and reinforcement learning techniques, the cache coherence protocol can be dynamically optimized. Among them, the graph-driven workload modeling component dynamically captures the data flow and dependencies across devices through the data access dependency graph, accurately identifies synchronization hotspots and critical paths, and provides accurate data support for protocol optimization. The policy decision-making component optimizes the protocol selection in real time based on the reinforcement learning algorithm, dynamically adjusts the protocol policy according to the current state of the system, minimizes communication overhead and latency, and improves the throughput of the system. The atomicity control component supports deferred commit and partial atomic operations, reduces the number of global commits, improves the operating efficiency of the system, and at the same time ensures the atomicity and consistency of data, thereby solving many problems faced by cache coherence in heterogeneous computing systems in related technologies, and significantly improving the performance and reliability of heterogeneous computing systems.

[0113] The above has introduced in detail a heterogeneous computing system and its cache coherence maintenance method, device, electronic device, non-volatile storage medium, and computer program product provided by the present invention. Each embodiment in this specification is described in a progressive manner, and the key point of each embodiment is the difference from other embodiments. The same or similar parts between each embodiment can be referred to each other. Whether the units and algorithm steps of each example described in the disclosed embodiments are executed in the form of electronic hardware or computer software depends on the specific application and design constraints of the technical solution. Those skilled in the art can use different methods to implement the described functions for each specific application, and such implementation should not be considered to exceed the scope of the present invention. Without departing from the principle of the present invention, several improvements and modifications can be made to the present invention, and these improvements and modifications also fall within the protection scope of the present invention.

Claims

1. A cache coherence maintenance method, characterized in that, Including: Determine the hot data access path of the heterogeneous computing system at the current moment according to the access order and the strength of the dependency relationship of each data block of the heterogeneous computing system at the current moment; Generate the current running state information according to the hot data access path, the workload information, the cache validity information, and the cross-device communication information of the heterogeneous computing system at the current moment; Based on the relationship between the running state of the heterogeneous computing system and the cache coherence protocol type, determine the cache coherence protocol that best matches the current running state of the heterogeneous computing system according to the current running state information.

2. The cache coherence maintenance method according to claim 1, wherein Determine the hot data access path of the heterogeneous computing system at the current moment according to the access order and the strength of the dependency relationship of each data block of the heterogeneous computing system at the current moment, including: Obtain the access information between each data block of the heterogeneous computing system, where the access information at least includes read / write operation time information and operation type; Determine the access order and the dependency relationship between each data block according to the access information, and construct a data access dependency graph with data blocks as graph nodes and the dependency relationship between data blocks as the connection edges between graph nodes; Determine the corresponding edge weight according to the read / write operation time information and the number of read / write operations of the data blocks with a dependency relationship; Determine the hot data access path of the heterogeneous computing system at the current moment by analyzing the edge weights of the connection edges between different graph nodes.

3. The cache coherence maintenance method according to claim 2, wherein Determine the corresponding edge weight according to the read / write operation time information and the number of read / write operations of the data blocks with a dependency relationship, including: For a first data block and a second data block with a read / write dependency relationship, determine the strength of the dependency relationship between the first data block and the second data block according to the maximum value between the number of reads and the number of writes of the first data block, the maximum value between the number of reads and the number of writes of the second data block, and the number of cross-accesses between the first data block and the second data block, and use it as the weight of the connection edge between the first data block and the second data block in the data access dependency graph.

4. The cache coherence maintenance method according to claim 2, wherein After constructing the data access dependency graph, it further includes: When the graph update condition is satisfied, obtain the new access information of each data block of the heterogeneous computing system; Update the connection edges and edge weights of the data access dependency graph according to the new access information, and delete the connection edges between graph nodes with edge weights less than the preset edge weight threshold from the data access dependency graph.

5. The cache coherence maintenance method according to claim 2, wherein After determining the hot data access path of the heterogeneous computing system at the current moment by analyzing the edge weights of the connection edges between different graph nodes, it further includes: Statistically calculate the sum of the weights corresponding to the access paths between different graph nodes in the data access dependency graph, and determine the target access path with the sum of weights exceeding the preset path weight threshold; Generate a hot data subgraph according to the target graph nodes corresponding to the target access path and their corresponding connection edges, and use it as a high-priority synchronization area.

6. The cache coherence maintenance method according to claim 2, wherein Determine the hot data access path of the heterogeneous computing system at the current moment by analyzing the edge weights of the connection edges between different graph nodes, including: Calculate the associated connection edges passed by each pair of graph nodes in the data access dependency graph for data access respectively; Take the sum of the edge weights of each associated connection edge as the weight of the corresponding data access path, and take the data access path with the largest weight value as the current hot data access path.

7. The cache coherence maintenance method according to claim 1, wherein According to the hot data access path, the workload information, cache validity information, and cross-device communication information of the heterogeneous computing system at the current moment, generate the current running state information, including: Obtain the main processor load rate of the heterogeneous computing system at the current moment, the cache hit rate of the target processor of a different type from the main processor, and the network latency information; Generate the current running state information according to the edge weight of the hot data access path, the main processor load rate, the cache hit rate, and the network latency information.

8. The cache coherence maintenance method according to claim 1, characterized in that, Based on the relationship between the running state of the heterogeneous computing system and the cache coherence protocol type, including: According to multiple groups of running state sample information and the action space, generate a state-protocol relationship recognition model in the way that one of the cache coherence protocols in the running state sample information and the action space is used as a state-action sample pair, and each state-action sample pair has an expected return value; the action space includes multiple different types of cache coherence protocols; Initialize the expected return values of each state-action sample pair in the state-protocol relationship recognition model to an initial value; Construct multiple training sequences according to each state-action sample pair. The training process of the current training sequence includes: Starting from the initial state, for each time step, randomly select the corresponding cache coherence protocol from the action space for the current running state sample information with the first preset probability to generate a new state-action sample pair; select the optimal cache coherence protocol with the largest expected return value corresponding to the current running state sample information with the second preset probability; Execute the optimal cache coherence protocol, determine the reward value of the heterogeneous computing system for executing the optimal cache coherence protocol according to the computing performance data and network performance data of the heterogeneous computing system, and obtain the next running state sample information of the current running state sample information; According to the current state-action sample pair formed by the current running state sample information and the optimal cache coherence protocol, the current expected return value in the state-protocol relationship recognition model, the reward value, and the future expected return value corresponding to the next running state sample information, update the expected return value of the current state-action sample pair in the state-protocol relationship recognition model; When the maximum time step or the environment termination condition is reached, end the training of the current training sequence, and perform corresponding training on the next training sequence until the preset number of training rounds is reached or the state-protocol relationship recognition model converges, and obtain the trained state-protocol relationship recognition model.

9. The cache coherence maintenance method according to claim 8, wherein Determine the reward value of the heterogeneous computing system for executing the optimal cache coherence protocol according to the computing performance data and network performance data of the heterogeneous computing system, including: Obtain the throughput, network overhead, synchronization latency of the heterogeneous computing system and their respective weight coefficients; Use the difference between the product of throughput and throughput weight coefficient, the product of network overhead and network overhead weight coefficient, and the product of synchronization delay and synchronization delay weight coefficient as the reward value of the heterogeneous computing system at the current moment.

10. The cache coherence maintenance method according to claim 8, wherein After obtaining the next running state sample information of the current running state sample information, it further includes: From the next running state sample information, randomly select the maximum value from the expected return values corresponding to each cache coherence protocol in the action space with the first preset probability as the future expected return value.

11. The cache coherence maintenance method according to claim 8, wherein Updating the expected return value of the current state-action sample pair in the state protocol relationship recognition model includes: According to the maximum value of each expected return value of each cache coherence protocol selected by the heterogeneous computing system under the next running state sample information and the future return weight value, determine the future return information, and calculate the sum of the reward value and the future return information as the return reward information; Calculate the difference between the return reward information and the current expected return value of the current state-action sample pair in the state protocol relationship recognition model, and calculate the product of the difference and the update speed adjustment factor as the return reward update information; Use the sum of the current expected return value and the return reward update information as the updated value of the expected return value of the current state-action sample pair in the state protocol relationship recognition model.

12. The cache coherence maintenance method according to claim 8, wherein, After obtaining the trained state protocol relationship recognition model, it further includes: Pre-construct an experience replay cache, and store multiple groups of state-action history pairs during the operation of the heterogeneous computing system in the experience replay cache; where the state-action history pair at least includes the running state history information and its corresponding cache coherence protocol, the next running state history information, and the historical reward value; Use each state-action history pair and, on the basis of dynamically adjusting the first preset probability, fine-tune the state protocol relationship recognition model.

13. The cache coherence maintenance method according to claim 8, wherein Before generating the state protocol relationship recognition model, it further includes: Redefine the cache coherence protocol of the heterogeneous computing system into a metadata index protocol, a multicast synchronization protocol, and a hybrid response protocol according to different read-write ratios, and construct an action space according to the metadata index protocol, the multicast synchronization protocol, and the hybrid response protocol; Among them, the metadata index protocol is a protocol in which each computing unit includes directory information for storing its own metadata, and the target data block that meets the condition that the write frequency is greater than the preset frequency threshold has central directory information; the multicast synchronization protocol is a protocol in which each computing unit performs corresponding operations according to the listening information of the multicast channel, and the multicast range is dynamically adjusted according to the cache hit rate; the hybrid response protocol is a fusion protocol of the directory protocol and the broadcast protocol.

14. The cache coherence maintenance method according to any one of claims 1 to 13, characterized in that, After determining the cache coherence protocol that best matches the current running state of the heterogeneous computing system according to the current running state information, it further includes: If there is at least one first target computing unit in the heterogeneous computing system that belongs to a non-multi-copy atomic device, when a write request of the first target computing unit is received, store the target write data corresponding to the write request in the target private cache of the first target computing unit; When a write operation submission process is triggered, write the target write data to the target write address corresponding to the write request.

15. The cache coherence maintenance method according to claim 14, wherein If there are multiple write requests, when a write operation submission process is triggered, writing the target write data to the target write address corresponding to the write request includes: When the remaining space capacity of the target private cache reaches a preset capacity threshold, trigger a write operation submission process, and batch-write each target write data in the target private cache to the corresponding target write address.

16. The cache coherence maintenance method according to claim 14, wherein If the target write address corresponding to the target write data is located in a target data block, when a write operation submission process is triggered, writing the target write data to the target write address corresponding to the write request includes: When it is detected that a second target computing unit initiates a read request for the target data block, first write the target write data to the target data block, and then execute the corresponding read operation.

17. The cache coherence maintenance method according to claim 14, wherein Writing the target write data to the target write address corresponding to the write request includes: Set a full atomicity label and a partial atomicity label for the write operation in advance, and the full atomicity label triggers a global synchronization operation; During the process of writing the target write data to the target write address corresponding to the write request, assign the partial atomicity label to the write request, and detect whether there is a version conflict between the global version number and the local version number of the target data block where the target write address is located; When the global version number of the target data block is less than the local version number, there is a version conflict, and load the latest version data from the global cache of the heterogeneous computing system; When the global version number of the target data block is greater than or equal to the local version number, write the target write data to the target write address.

18. A cache coherence maintenance device, characterized in that, It includes: A critical path identification module, configured to determine the hot data access path of the heterogeneous computing system at the current moment according to the access order and dependency strength of each data block of the heterogeneous computing system at the current moment; A state awareness module, configured to generate current running state information according to the hot data access path, the workload information, cache validity information, and cross-device communication information of the heterogeneous computing system at the current moment; A protocol dynamic selection module, configured to determine the cache coherence protocol that best matches the current running state of the heterogeneous computing system according to the current running state information based on the relationship between the running state of the heterogeneous computing system and the cache coherence protocol type.

19. An electronic device, characterized in that, It includes: A memory, configured to store a computer program; A processor, configured to implement the steps of the cache coherence maintenance method according to any one of claims 1 to 17 when executing the computer program.

20. A non-volatile storage medium, characterized in that, A computer program is stored on the non-volatile storage medium, and when the computer program is executed by a processor, the steps of the cache coherence maintenance method according to any one of claims 1 to 17 are implemented.

21. A computer program product, comprising a computer program / instructions, characterized in that, When the computer program / instructions are executed by a processor, the steps of the cache coherence maintenance method according to any one of claims 1 to 17 are implemented.

22. A heterogeneous computing system, characterized in that, It at least includes a first computing node, a second computing node, and a cache coherence controller. The cache coherence controller is connected to the first computing node and the second computing node. The first computing node and the second computing node each include at least two computing units; Wherein, when the cache coherence controller executes a computer program, the steps of the cache coherence maintenance method according to any one of claims 1 to 17 are implemented.

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