Anti-reverse-current circuit with overcurrent protection and overcurrent protection method

Abstract

The invention discloses an anti-reverse circuit with overcurrent protection and an overcurrent protection method. The anti-reverse circuit comprises a first PMOS tube, a second PMOS tube, an NMOS tube, a sampling resistor, a divider resistor network, a matched resistor network, a voltage comparator, a first pull-up resistor, a second pull-up resistor, a first gate resistor and a second gate resistor. One end of the sampling resistor is connected with input voltage, and the other end is connected with the drain electrode of the first PMOS tube and is connected with the voltage comparator through the matched resistor network; grid electrodes of the first PMOS tube and the second PMOS tube are connected to a control node; the grid electrode of the NMOS tube is connected with the output end of the comparator through the first gate resistor, and the drain electrode is connected with the control node through the second gate resistor. The divider resistance network provides reference voltage for the comparator; the matched resistance network provides detection voltage for the comparator. Whether the reverse connection prevention circuit is conducted or not is determined according to the detection voltage and the reference voltage, and the dual functions of reverse connection prevention and overcurrent protection of the reverse connection prevention circuit are achieved.

Description

Technical Field

[0001] This application relates to the field of electronic technologies, and particularly to an anti-reverse circuit with overcurrent protection and an overcurrent protection method. Background Art

[0002] An anti-reverse circuit is a protection circuit used to prevent reverse connection of the power supply and damage caused by overcurrent, usually implemented by a combination of PMOS and NMOS transistors. When the power supply is connected reversely, the circuit automatically cuts off the loop to avoid reverse current flow.

[0003] Most of the existing anti-reverse circuits only have a single anti-reverse function, or an overcurrent protection chip is added to implement the overcurrent protection function. Most of the overcurrent protection chips are expensive, and some overcurrent protection chips only have fixed overcurrent protection points and cannot adjust the overcurrent protection points according to the actual situation at any time. Summary of the Invention

[0004] This application provides an anti-reverse circuit with overcurrent protection and an overcurrent protection method to achieve overcurrent protection for the anti-reverse circuit.

[0005] In a first aspect, this application provides an anti-reverse circuit with overcurrent protection, including: A first PMOS transistor, a second PMOS transistor, an NMOS transistor, a sampling resistor, a voltage dividing resistor network, a matching resistor network, a voltage comparator, a first pull-up resistor, a second pull-up resistor, a first gate resistor, and a second gate resistor; One end of the sampling resistor is connected to the input voltage of the anti-reverse circuit, and the other end is connected to the drain of the first PMOS transistor; the other end of the sampling resistor is also connected to the voltage comparator through the matching resistor network; The source of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to an external load; the gates of the first PMOS transistor and the second PMOS transistor are commonly connected to a control node; The source of the NMOS transistor is grounded; the gate of the NMOS transistor is connected to the output terminal of the voltage comparator through the first gate resistor; the drain of the NMOS transistor is connected to the control node through the second gate resistor; The first pull-up resistor is connected in parallel with the first gate resistor to the output terminal of the voltage comparator; the second pull-up resistor is connected between the control node and the source of the first PMOS transistor; The voltage dividing resistor network is connected in parallel between the sampling input terminal of the sampling resistor and the ground wire; The voltage comparator includes an inverting input terminal, a non-inverting input terminal, and an output terminal; the inverting input terminal is connected to the voltage dividing resistor network for determining the reference voltage corresponding to the voltage dividing resistor network; the non-inverting input terminal is connected to the matching resistor network for determining the detected voltage corresponding to the matching resistor network.

[0006] In a second aspect, the present application provides an overcurrent protection method for an anti-reverse circuit, including: When it is detected that the anti-reverse circuit is in the positive power connection state, a reference voltage corresponding to the anti-reverse circuit is determined by using a first voltage division network corresponding to the anti-reverse circuit; Using a sampling resistor corresponding to the anti-reverse circuit, the load voltage corresponding to the anti-reverse circuit is detected; The load voltage is subjected to hysteresis processing through a preset matching resistor network, and the detected voltage after hysteresis of the matching resistor network is determined; A voltage comparator corresponding to the anti-reverse circuit is used to compare the reference voltage with the detected voltage; When the detected voltage is greater than the reference voltage, the load current corresponding to the output of the anti-reverse circuit is determined; When the detected voltage is less than the reference voltage, a low-level signal is output by the voltage comparator to cut off the load current.

[0007] The present application provides an anti-reverse circuit with overcurrent protection and an overcurrent protection method, including: a first PMOS transistor, a second PMOS transistor, an NMOS transistor, a sampling resistor, a voltage division resistor network, a matching resistor network, a voltage comparator, a first pull-up resistor, a second pull-up resistor, a first gate resistor, and a second gate resistor. One end of the sampling resistor is connected to the input voltage, the other end is connected to the drain of the first PMOS transistor, and is connected to the voltage comparator through the matching resistor network; the gates of the first PMOS transistor and the second PMOS transistor are connected to the control node; the gate of the NMOS transistor is connected to the output end of the comparator through the first gate resistor, and the drain is connected to the control node through the second gate resistor. The voltage division resistor network provides a reference voltage for the comparator; the matching resistor network provides a detected voltage for the comparator. Whether the anti-reverse circuit is turned on is determined according to the magnitude of the detected voltage and the reference voltage, realizing the dual functions of anti-reverse connection and overcurrent protection of the anti-reverse circuit.

[0008] The further effects of the above non-conventional preferred methods will be described in combination with specific embodiments below. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present application or the existing technical solutions, the following will briefly introduce the drawings required for use in the description of the embodiments or the existing technical solutions. Obviously, the drawings in the following description are only some embodiments recorded in the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0010] Figure 1 FIG. is a schematic structural diagram of an anti-reverse circuit with overcurrent protection provided by an embodiment of the present application; Figure 2 FIG. is a schematic structural diagram of a voltage division resistor network in an anti-reverse circuit with overcurrent protection provided by an embodiment of the present application; Figure 3 Schematic diagram of a matching resistor network in an anti - reverse circuit with over - current protection provided by an embodiment of the present application; Figure 4 Flowchart of an over - current protection method for an anti - reverse circuit provided by an embodiment of the present application; Figure 5 Flowchart of another over - current protection method for an anti - reverse circuit provided by an embodiment of the present application; Figure 6 Flowchart of another over - current protection method for an anti - reverse circuit provided by an embodiment of the present application. Detailed implementation manners

[0011] To make the objectives, technical solutions and advantages of the present application clearer, the technical solutions of the present application will be clearly and completely described below in conjunction with specific embodiments and the corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts shall fall within the protection scope of the present application.

[0012] The anti - reverse circuit plays an important role in the electronic system, mainly used to prevent device damage caused by reverse power supply polarity. Traditional anti - reverse circuits usually rely on the combination of PMOS and NMOS transistors to achieve the basic anti - reverse connection function, that is, when the power supply polarity is incorrect, the current path is automatically cut off through the reverse cut - off characteristic of the body diode of the MOS transistor.

[0013] However, such circuits often have a single function and can only solve the problem of reverse power supply connection. For over - current protection, an additional over - current protection chip is required. Although such dedicated chips have stable performance, they have a high cost and obvious limitations in application: the over - current protection thresholds of many chips are pre - fixed and cannot be dynamically adjusted according to actual load requirements or working environments. For example, in scenarios where different load currents need to be adapted, the protection mechanism with a fixed threshold may cause the circuit to be frequently mis - triggered or unable to respond to actual over - current situations in a timely manner, reducing the flexibility and reliability of the system.

[0014] In view of this, an embodiment of the present application proposes an anti - reverse circuit with over - current protection, referring to Figure 1 As shown, it is a specific embodiment of the anti - reverse circuit with over - current protection provided by the present application. In this embodiment, the anti - reverse circuit with over - current protection includes: The first PMOS transistor Q1, the second PMOS transistor Q2, the NMOS transistor Q3, the sampling resistor R1, the voltage - dividing resistor network, the matching resistor network, the voltage comparator U1, the first pull - up resistor R2, the second pull - up resistor R3, the first gate resistor R4 and the second gate resistor R5.

[0015] One end of the sampling resistor R1 is connected to the input voltage Vin of the reverse protection circuit, and the other end is connected to the drain of the first PMOS transistor Q1. The other end of the sampling resistor R1 is also connected to the voltage comparator U1 through a matching resistor network. The sampling resistor R1 is connected in series between the input voltage Vin and the drain of the first PMOS transistor Q1 to form a main current detection path for real-time detection of the load current. According to Ohm's law, the current flowing through the sampling resistor R1 will generate a voltage drop across it. This voltage drop is transmitted to the non-inverting input terminal of the voltage comparator U1 through the matching resistor network as the basis for detecting the voltage. By adjusting the resistance value of the sampling resistor R1, the overcurrent protection threshold can be flexibly set.

[0016] At the same time, the direct connection between the other end of R1 and the drain of the first PMOS transistor Q1 activates the body diode cooperation mechanism during the protection action. After the overcurrent is triggered, the first PMOS transistor Q1 turns off, and its drain voltage is pulled down by the load. At this time, the reverse bias characteristic of the body diode of the first PMOS transistor Q1 further reduces the load voltage, strengthens the downward trend of the detected voltage through the matching resistor network, and forms a positive feedback latch effect to ensure that the protection state is stably maintained until the fault is cleared.

[0017] The source of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to an external load; the gates of the first PMOS transistor and the second PMOS transistor are commonly connected to a control node. The first PMOS transistor Q1 and the second PMOS transistor Q2 are connected to form a main current path. The sources of the first PMOS transistor Q1 and the second PMOS transistor Q2 are directly interconnected and connected to the load voltage to form a common-source current distribution structure. This connection ensures that the two transistors share the load current evenly when conducting. The drain of the second PMOS transistor Q2 is then connected to the external load Vout. Their gates are commonly connected to the control node, and the on or off state is determined by the state of the NMOS transistor Q3.

[0018] The source of the NMOS transistor is grounded; the gate of the NMOS transistor is connected to the output terminal of the voltage comparator through a first gate resistor; the drain of the NMOS transistor is connected to the control node through a second gate resistor. The source of the NMOS transistor Q3 is grounded, the drain is connected to the control node through the second gate resistor R5, and the gate is driven by the output signal of the voltage comparator U1 through the first gate resistor R1. Q3 serves as a control switch, and its on or off state directly determines the level of the gate voltages of the first PMOS transistor Q1 and the second PMOS transistor Q2.

[0019] The first pull-up resistor R2 and the first gate resistor R4 are connected in parallel to the output terminal of the voltage comparator U1, which is used to ensure the reliable conduction of the NMOS transistor Q3 when the voltage comparator U1 outputs a high level. The second pull-up resistor R3 connects the control node to the source of the first PMOS transistor Q1, which is used to pull up the voltage of the control node by the second pull-up resistor R3 when the NMOS transistor Q3 is turned off, forcing the first PMOS transistor Q1 and the second PMOS transistor Q2 to turn off.

[0020] The voltage dividing resistor network is connected in parallel between the sampling input terminal of the sampling resistor R1 and the ground wire, providing a reference voltage for the inverting input terminal of the voltage comparator U1.

[0021] The voltage comparator U1 includes an inverting input terminal, a non-inverting input terminal, and an output terminal; the inverting input terminal is connected to the voltage dividing resistor network to determine the reference voltage corresponding to the voltage dividing resistor network; the non-inverting input terminal is connected to the matching resistor network to determine the detection voltage corresponding to the matching resistor network.

[0022] As Figure 2 shown, which is the schematic diagram of the voltage dividing resistor network in this embodiment. In the Figure 2 example, the voltage dividing resistor network includes a first voltage dividing resistor R6 and a second voltage dividing resistor R7.

[0023] The first voltage dividing resistor R6 and the second voltage dividing resistor R7 are connected in series through a voltage dividing node; the voltage dividing node is connected to the inverting input terminal of the voltage comparator U1, so that the voltage comparator U1 determines the reference voltage corresponding to the voltage dividing resistor network.

[0024] The first voltage dividing resistor R6 and the second voltage dividing resistor R7 are connected in series between the input terminal of the sampling resistor R1 and the ground. After the input voltage Vin is divided by the first voltage dividing resistor R6 and the second voltage dividing resistor R7, a reference voltage is generated. The resistance ratio of the first voltage dividing resistor R6 and the second voltage dividing resistor R7 determines the flexibility of the reference voltage. By adjusting the resistance values of the first voltage dividing resistor R6 and the second voltage dividing resistor R7, different load requirements can be adapted without replacing the hardware. For example, in industrial equipment, if the load current range changes greatly, only the ratio of the first voltage dividing resistor R6 to the second voltage dividing resistor R7 needs to be recalculated and the corresponding resistors replaced to quickly match the new protection threshold, significantly improving the adaptability of the reverse protection circuit.

[0025] As Figure 3 shown, which is the flow schematic diagram of the matching resistor network in this embodiment. In the Figure 3 example, the matching resistor network includes a first matching resistor R8 and a second matching resistor R9.

[0026] One end of the first matching resistor R8 is connected to the other end of the sampling resistor R1; the other end of the first matching resistor R8 is connected to the non-inverting input terminal of the voltage comparator U1 through a matching node; one end of the second matching resistor R9 is connected to the matching node, and the other end of the second matching resistor R9 is connected to the output terminal of the voltage comparator U1.

[0027] The first matching resistor R8 and the second matching resistor R9 together form the positive feedback network of the voltage comparator U1. Its function is to ensure that the voltage comparator U1 has a clear threshold difference during overcurrent protection triggering and recovery by introducing hysteresis characteristics, thereby avoiding frequent output level jumps caused by noise or current fluctuations.

[0028] The magnitude of the hysteresis voltage can be adjusted by the resistance ratio of the first matching resistor R8 and the second matching resistor R9. For example, reducing the first matching resistor R8 or increasing the second matching resistor R9 will widen the hysteresis window and enhance the anti-noise ability; conversely, it will narrow the window and improve the sensitivity. This characteristic is applicable to scenarios where the load current has instantaneous fluctuations (such as motor startup, power supply ripple), ensuring stable and reliable protection actions.

[0029] The voltage comparator is used to compare the reference voltage with the detected voltage; when the detected voltage is greater than the reference voltage, the voltage comparator outputs a high-level signal to turn on the NMOS transistor; when the NMOS transistor is turned on, the drain of the NMOS transistor is pulled down to near ground level, so that the gate-source voltages of the first PMOS transistor and the second PMOS transistor meet the conduction conditions, and then power is supplied to the external load; when the detected voltage is less than the reference voltage, the voltage comparator outputs a low-level signal, and the low-level signal is transmitted to the gate of the NMOS transistor, so that the gate-source voltage of the NMOS transistor is lower than the threshold voltage, causing the NMOS transistor to turn off; when the NMOS transistor is turned off, the second gate voltage corresponding to the control node is pulled up to the load voltage corresponding to the sampling resistor through the second pull-up resistor; when the second gate voltage corresponding to the control node is pulled up to the load voltage, the gate-source voltages of the first PMOS transistor and the second PMOS transistor approach zero, and the anti-reverse circuit is turned off.

[0030] When the detected voltage is higher than the reference voltage, it indicates that the load current is within the safety threshold. At this time, the voltage comparator U1 outputs a high-level signal to drive the NMOS transistor Q3 into the conduction state. After the NMOS transistor Q3 is turned on, a milliohm-level low-resistance path is formed between its drain and source, pulling down the control node connected to the gates of the dual PMOS transistors to near ground level, causing the gate-source voltages of the first PMOS transistor Q1 and the second PMOS transistor Q2 to be deeply negatively biased. The first PMOS transistor Q1 and the second PMOS transistor Q2 are turned on synchronously to establish a low-impedance power path, and the input voltage is supplied to the external load stably through the conducting transistors.

[0031] When the load current increases abnormally, causing the detected voltage to be lower than the reference voltage, the voltage comparator U1 immediately flips to a low-level output. This signal is applied to the gate of the NMOS transistor Q3, making the gate-source voltage approach zero, and the NMOS transistor Q3 instantaneously turns off. The potential of the control node is directly pulled up to the load voltage through the second pull-up resistor R3. This operation compresses the gate-source voltage difference of the dual PMOS transistors to approach zero, forcing the two transistors to turn off synchronously to cut off the power supply circuit.

[0032] As can be seen from the above technical solutions, the beneficial effects of this embodiment are as follows: The reverse connection prevention circuit includes: a first PMOS transistor, a second PMOS transistor, an NMOS transistor, a sampling resistor, a voltage-dividing resistor network, a matching resistor network, a voltage comparator, a first pull-up resistor, a second pull-up resistor, a first gate resistor, and a second gate resistor. One end of the sampling resistor is connected to the input voltage, the other end is connected to the drain of the first PMOS transistor, and is connected to the voltage comparator through the matching resistor network; the gates of the first PMOS transistor and the second PMOS transistor are connected to the control node; the gate of the NMOS transistor is connected to the output end of the comparator through the first gate resistor, and the drain is connected to the control node through the second gate resistor. The voltage-dividing resistor network provides a reference voltage for the comparator; the matching resistor network provides a detected voltage for the comparator. Whether the reverse connection prevention circuit is turned on is determined according to the magnitudes of the detected voltage and the reference voltage, realizing the dual functions of reverse connection prevention and overcurrent protection of the reverse connection prevention circuit.

[0033] As Figure 4 shown, it is a specific embodiment of an overcurrent protection method for a reverse connection prevention circuit of the present application. The method of this embodiment is applied to Figures 1-3 the reverse connection prevention circuit with overcurrent protection described above.

[0034] In this embodiment, an overcurrent protection method for a reverse connection prevention circuit includes the following steps: Step 401, when it is detected that the reverse connection prevention circuit is in the positive power supply connection state, use the first voltage-dividing network corresponding to the reverse connection prevention circuit to determine the reference voltage corresponding to the reverse connection prevention circuit.

[0035] When the reverse connection prevention circuit is in the positive power supply connection state, the input voltage generates a reference voltage through the voltage-dividing network composed of the first voltage-dividing resistor and the second voltage-dividing resistor. The first voltage-dividing resistor and the second voltage-dividing resistor are connected in series between the input end of the sampling resistor and the ground, forming a stable voltage-dividing path. According to the voltage-dividing principle, the calculation formula for the reference voltage V1 is: V1 = Vin * R6 / (R6 + R7) where, V1 is the reference voltage; Vin is the input voltage; R6 is the resistance value of the first voltage-dividing resistor; R7 is the resistance value of the second voltage-dividing resistor.

[0036] The reference voltage is directly input to the inverting input terminal of the voltage comparator as the reference threshold for judging whether the load current exceeds the standard. For example, if Vin is 12V, and R6 and R7 are 10kΩ and 5kΩ respectively, then V is 4V. The setting of this reference voltage determines the trigger point of overcurrent protection. When the load current increases, resulting in an increase in the voltage drop across the sampling resistor, the associated detection voltage will decrease accordingly. If the detection voltage is lower than the reference voltage, the voltage comparator will output a low level, triggering the overcurrent protection action.

[0037] By adjusting the resistance ratio of the first voltage-dividing resistor to the second voltage-dividing resistor, the value of the reference resistor can be dynamically changed, thus adapting to different application scenarios. For example, when it is necessary to increase the overcurrent protection threshold, the resistance value of the first voltage-dividing resistor can be reduced or the resistance value of the second voltage-dividing resistor can be increased to lower the reference voltage. Conversely, if earlier protection is required, the resistance value of the first voltage-dividing resistor needs to be increased or the resistance value of the second voltage-dividing resistor needs to be reduced to increase the reference voltage. This design abandons the limitations of the fixed-threshold chip in the traditional scheme and gives the circuit high adaptability.

[0038] Step 402: Use the sampling resistor corresponding to the reverse protection circuit to detect the load voltage corresponding to the reverse protection circuit.

[0039] In the reverse protection circuit, the sampling resistor is connected in series between the input voltage and the drain of the first PMOS transistor. Its function is to indirectly reflect the state of the load voltage by monitoring the load current flowing through the circuit in real time.

[0040] Determine the resistance value corresponding to the sampling resistor; detect the load current flowing through the sampling resistor; according to the resistance value and the load current, use Ohm's law to determine the load voltage corresponding to the sampling resistor.

[0041] According to Ohm's law, the voltage drop across the sampling resistor is: V2 = I * R1 Where, V2 is the voltage drop across the sampling resistor; I is the load current; R1 is the resistance value of the sampling resistor.

[0042] Since the load voltage can be approximately expressed as the input voltage minus the voltage drop across the sampling resistor, therefore, by detecting the value of the voltage drop across the sampling resistor, not only can it be judged whether the load current exceeds the standard, but also the change trend of the load voltage can be indirectly deduced.

[0043] Step 403: Perform hysteresis processing on the load voltage through a preset matching resistor network and determine the detection voltage after hysteresis of the matching resistor network.

[0044] The matching resistor network is not only used to divide the load voltage, but also endows the voltage comparator with hysteresis characteristics through a positive feedback mechanism, thereby improving the stability and anti-interference ability of overcurrent protection. When the load voltage is transmitted to the matching node through the first matching resistor, that is, the detected voltage, and the second matching resistor introduces a feedback signal from the output terminal of the voltage comparator. The calculation formula for the detected voltage is: V3 = V2 * R9 / (R8 + R9) + V4 * R8 / (R8 + R9) Among them, V3 is the detected voltage; V2 is the load voltage; R8 is the resistance value of the first matching resistor; R9 is the resistance value of the second matching resistor; V4 is the voltage at the output terminal of the voltage comparator.

[0045] It can be seen from this that when the voltage comparator outputs a high level, V3 will be partially pulled up; when the voltage comparator outputs a low level, V3 is only determined by the voltage division of V2.

[0046] The detected voltage not only depends on the load voltage, but is also affected by the output state of the voltage comparator. This dynamic feedback mechanism provides a necessary threshold window for the hysteresis comparator, ensuring the stability of overcurrent protection triggering and recovery.

[0047] By adjusting the ratio of the resistance value of the first matching resistor and the resistance value of the second matching resistor, the size of the hysteresis window can be controlled. For example, increasing the resistance value of the second matching resistor or decreasing the first matching resistor will enhance the positive feedback effect and expand the difference between the trigger threshold and the recovery threshold, thereby more effectively suppressing false actions caused by load current fluctuations or power supply noise.

[0048] Step 404: Use the voltage comparator corresponding to the anti-reverse circuit to compare the reference voltage with the detected voltage.

[0049] By comparing the reference voltage with the detected voltage in real time, the on or off state of the dynamic decision circuit is determined, thereby realizing an accurate overcurrent protection function.

[0050] When the detected voltage is greater than the reference voltage, the voltage comparator outputs a high level to turn on the anti-reverse circuit. When the detected voltage is less than the reference voltage, the voltage comparator outputs a low level to turn off the anti-reverse circuit, realizing overcurrent protection.

[0051] Step 405: When the detected voltage is greater than the reference voltage, determine the load current corresponding to the output of the anti-reverse circuit.

[0052] When the detected voltage is higher than the reference voltage, it indicates that the load current is within the safety threshold. At this time, the voltage comparator U1 outputs a high-level signal to drive the NMOS transistor into the conducting state. After the NMOS transistor conducts, a low-resistance path in the milliohm level is formed between its drain and source, pulling down the control node connected to the gates of the dual PMOS transistors to near-ground level, causing the gate-source voltages of the first PMOS transistor and the second PMOS transistor to be deeply negatively biased. The first PMOS transistor and the second PMOS transistor conduct synchronously to establish a low-impedance power path, and the input voltage supplies power to the external load stably through the conducting transistors.

[0053] Step 406: When the detected voltage is less than the reference voltage, use the voltage comparator to output a low-level signal to cut off the load current.

[0054] When the load current increases abnormally, causing the detected voltage to be lower than the reference voltage, the voltage comparator immediately flips to a low-level output. This signal is applied to the gate of the NMOS transistor, making its gate-source voltage approach zero, and the NMOS transistor instantaneously cuts off. The potential of the control node is directly pulled up to the load voltage through the second pull-up resistor. This operation compresses the gate-source voltage difference of the dual PMOS transistors to approach zero, forcing the two transistors to turn off synchronously to cut off the power supply circuit.

[0055] From the above technical solutions, the beneficial effects of this embodiment are as follows: When it is detected that the reverse protection circuit is in the positive power connection state, use the first voltage division network corresponding to the reverse protection circuit to determine the reference voltage corresponding to the reverse protection circuit; use the sampling resistor corresponding to the reverse protection circuit to detect the load voltage corresponding to the reverse protection circuit; perform hysteresis processing on the load voltage through the preset matching resistor network, and determine the detected voltage after hysteresis of the matching resistor network; use the voltage comparator corresponding to the reverse protection circuit to compare the reference voltage with the detected voltage; when the detected voltage is greater than the reference voltage, determine the load current corresponding to the output of the reverse protection circuit; when the detected voltage is less than the reference voltage, use the voltage comparator to output a low-level signal to cut off the load current. It realizes the intelligent control and reliable protection of the reverse protection circuit in the positive power connection state.

[0056] As Figure 5 shown, this is another specific embodiment of the overcurrent protection method for a reverse protection circuit of the present application. This embodiment is further described on the basis of the foregoing embodiment.

[0057] In this embodiment, an overcurrent protection method for a reverse protection circuit includes the following steps: Step 501: When it is detected that the reverse protection circuit is in the positive power connection state, use the first voltage division network corresponding to the reverse protection circuit to determine the reference voltage corresponding to the reverse protection circuit; Step 502: Use the sampling resistor corresponding to the reverse protection circuit to detect the load voltage corresponding to the reverse protection circuit; Step 503: Divide the load voltage through a preset matching resistor network and determine the detected voltage after the matching resistor network divides the voltage. Step 504: Use the voltage comparator corresponding to the reverse protection circuit to compare the reference voltage with the detected voltage. Step 505: When the detected voltage is greater than the reference voltage, determine the load current corresponding to the output of the reverse protection circuit. Step 506: When it is determined by the voltage comparator that the detected voltage is greater than the reference voltage, the voltage comparator outputs a high-level signal.

[0058] The first pull-up resistor is connected in parallel between the output terminal of the voltage comparator and the power supply to ensure that the comparator has a clear logic level when outputting a high level. The selection of the resistance value of the first pull-up resistor can balance signal stability and power consumption.

[0059] When the voltage comparator detects that the detected voltage at the non-inverting input terminal is higher than the input voltage at the inverting input terminal, the output terminal of the voltage comparator will switch to a high level to turn on the reverse protection circuit.

[0060] Step 507: Use the high-level signal to drive the NMOS transistor corresponding to the voltage comparator to conduct, so that the reverse protection circuit outputs the corresponding load current.

[0061] The high-level signal drives the NMOS transistor to conduct through the first gate resistor, so that the NMOS transistor forms a low-impedance path; when the NMOS transistor forms a low-impedance path, the first gate voltage corresponding to the control node is pulled down through the second gate resistor corresponding to the NMOS transistor, so that the first PMOS transistor and the second PMOS transistor meet the conduction conditions; when the first PMOS transistor and the second PMOS transistor meet the conduction conditions, the input voltage corresponding to the reverse protection circuit supplies power to the load through the circuit channels of the first PMOS transistor and the second PMOS transistor to output the load current.

[0062] The high-level signal is transmitted to the gate of the NMOS transistor through the first gate resistor to drive the NMOS transistor to conduct. The function of the first gate resistor is to limit the gate current, avoid component damage caused by transient voltage spikes or fast switching actions, and at the same time, the conduction speed and anti-interference ability can be optimized by adjusting the resistance value.

[0063] After the NMOS transistor conducts, a low-impedance path is formed between its drain and source, and at this time, the drain voltage is pulled down to close to the ground potential. The drain is connected to the gates (control nodes) of the first PMOS transistor and the second PMOS transistor through the second gate resistor. The function of the second gate resistor is to slow down the switching speed of the gate voltage and avoid high-frequency noise or voltage fluctuations generated by the charging and discharging process of the gate capacitance of the transistors at the control node.

[0064] When the control node voltage is pulled low, the gate-source voltages of the first PMOS transistor Q1 and the second PMOS transistor Q2 are deeply negatively biased. The first PMOS transistor Q1 and the second PMOS transistor Q2 are synchronously turned on to establish a low-impedance power path. The input voltage supplies power stably to the external load through the conducting transistors, thereby meeting the conduction conditions of the first PMOS transistor and the second PMOS transistor.

[0065] Step 508: When the detected voltage is less than the reference voltage, use the voltage comparator to output a low-level signal to cut off the load current.

[0066] From the above technical solutions, the beneficial effects of this embodiment are as follows: efficient and reliable load current output is achieved, while the anti-interference ability and cost-effectiveness are taken into account.

[0067] As Figure 6 shown, this is another specific embodiment of the overcurrent protection method for an anti-reverse circuit of the present application. This embodiment is further described on the basis of the foregoing embodiment.

[0068] Step 601: When it is detected that the anti-reverse circuit is in the positive power connection state, use the first voltage division network corresponding to the anti-reverse circuit to determine the reference voltage corresponding to the anti-reverse circuit.

[0069] Step 602: Use the sampling resistor corresponding to the anti-reverse circuit to detect the load voltage corresponding to the anti-reverse circuit.

[0070] Step 603: Perform voltage division processing on the load voltage through a preset matching resistor network and determine the detected voltage after voltage division by the matching resistor network.

[0071] Step 604: Use the voltage comparator corresponding to the anti-reverse circuit to compare the reference voltage with the detected voltage.

[0072] Step 605: When the detected voltage is greater than the reference voltage, determine the load current corresponding to the output of the anti-reverse circuit.

[0073] Step 606: When the detected voltage is less than the reference voltage, use the voltage comparator to output a low-level signal to cut off the load current.

[0074] Step 607: The low-level signal is transmitted to the gate of the NMOS transistor through the first gate resistor, so that the gate-source voltage of the NMOS transistor is lower than the threshold voltage.

[0075] When the voltage comparator detects that the detected voltage is lower than the reference voltage, the output terminal of the voltage comparator switches to a low level. This low-level signal is transmitted to the gate of the NMOS transistor through the first gate resistor. The function of the first gate resistor is to limit the gate current, avoid gate voltage fluctuations caused by voltage mutations or noise interference, and at the same time protect the NMOS transistor from transient current impacts. When the gate-source voltage of the NMOS transistor is lower than its threshold voltage due to the low-level input, the NMOS transistor enters the cut-off state, and the impedance between its drain and source increases sharply, forming a high-impedance state.

[0076] Step 608: When the gate-source voltage of the NMOS transistor is lower than the threshold voltage, increase the second gate voltage corresponding to the control node to cut off the load current of the first PMOS transistor and the second PMOS transistor.

[0077] Use the second pull-up resistor to pull up the second gate voltage to the load voltage corresponding to the sampling resistor; when the second gate voltage is pulled up to the load voltage, the gate-source voltages of the first PMOS transistor and the second PMOS transistor approach 0, so that the reverse protection circuit cuts off the load current.

[0078] When the control node voltage is pulled up, the gate-source voltages of the first PMOS transistor and the second PMOS transistor decrease significantly or even become zero. For example, if the load voltage is 12V and the control node voltage is pulled up to 12V, the gate and source potentials of the first PMOS transistor and the second PMOS transistor are the same, resulting in the complete cut-off of the first PMOS transistor and the second PMOS transistor.

[0079] From the above technical solutions, the beneficial effects of this embodiment are as follows: From the high-level signal drive to the conduction of the PMOS transistor, the reverse protection circuit realizes efficient and reliable load current output through precise resistor network design, MOS transistor logic control, and dynamic feedback mechanism, while taking into account anti-interference ability and cost-effectiveness.

[0080] Those skilled in the art should understand that the embodiments of the present application can be provided as a method or a computer program product. Therefore, the present application can adopt a completely hardware embodiment, a completely software embodiment, or a form combining software and hardware.

[0081] The embodiments in the present application are all described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the differences between each embodiment and other embodiments are emphasized. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can refer to the partial description of the method embodiments.

[0082] It should also be noted that the term "comprising", "including" or any other variant thereof is intended to cover non-exclusive inclusion, such that a process, method, commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or further includes elements inherent to such process, method, commodity or device. Without further limitation, an element defined by the statement "comprising an..." does not exclude the presence of additional identical elements in the process, method, commodity or device comprising the element.

[0083] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, various changes and modifications can be made to the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included within the scope of the claims of the present application.

Claims

1. An anti-reverse circuit with over-current protection, characterized in that, Including: A first PMOS transistor, a second PMOS transistor, an NMOS transistor, a sampling resistor, a voltage-dividing resistor network, a matching resistor network, a voltage comparator, a first pull-up resistor, a second pull-up resistor, a first gate resistor, and a second gate resistor; One end of the sampling resistor is connected to the input voltage of the reverse protection circuit, and the other end is connected to the drain of the first PMOS transistor; the other end of the sampling resistor is also connected to the voltage comparator through the matching resistor network; The source of the first PMOS transistor is connected to the source of the second PMOS transistor; the drain of the second PMOS transistor is connected to an external load; the gates of the first PMOS transistor and the second PMOS transistor are commonly connected to a control node; The source of the NMOS transistor is grounded; the gate of the NMOS transistor is connected to the output terminal of the voltage comparator through the first gate resistor; the drain of the NMOS transistor is connected to the control node through the second gate resistor; The first pull-up resistor and the first gate resistor are connected in parallel to the output terminal of the voltage comparator; the second pull-up resistor connects the control node and the source of the first PMOS transistor; The voltage-dividing resistor network is connected in parallel between the sampling input terminal of the sampling resistor and the ground wire; The voltage comparator includes an inverting input terminal, a non-inverting input terminal, and an output terminal; the inverting input terminal is connected to the voltage-dividing resistor network for determining the reference voltage corresponding to the voltage-dividing resistor network; The non-inverting input terminal is connected to the matching resistor network for determining the detection voltage corresponding to the matching resistor network.

2. The anti-reverse circuit according to claim 1, wherein The voltage-dividing resistor network includes: A first voltage-dividing resistor and a second voltage-dividing resistor; The first voltage-dividing resistor and the second voltage-dividing resistor are connected in series through a voltage-dividing node; The voltage-dividing node is connected to the inverting input terminal of the voltage comparator, so that the voltage comparator determines the reference voltage corresponding to the voltage-dividing resistor network.

3. The anti-reverse circuit according to claim 1, characterized in that, The matching resistor network includes: A first matching resistor and a second matching resistor; One end of the first matching resistor is connected to the other end of the sampling resistor; the other end of the first matching resistor is connected to the non-inverting input terminal of the voltage comparator through a matching node; One end of the second matching resistor is connected to the matching node, and the other end of the second matching resistor is connected to the output terminal of the voltage comparator.

4. The anti - reverse circuit according to any one of claims 1 - 3, characterized in that, It further includes: The voltage comparator is used to compare the reference voltage with the detection voltage; When the detection voltage is greater than the reference voltage, the voltage comparator outputs a high-level signal to turn on the NMOS transistor; When the NMOS transistor is turned on, the drain of the NMOS transistor is pulled down to a near-ground level, so that the gate-source voltage of the first PMOS transistor and the second PMOS transistor satisfies the conduction condition, and then power is supplied to the external load; When the detected voltage is less than the reference voltage, the voltage comparator outputs a low-level signal, and the low-level signal is transmitted to the gate of the NMOS transistor, so that the gate-source voltage of the NMOS transistor is lower than the threshold voltage, causing the NMOS transistor to cut off; when the NMOS transistor cuts off, the second gate voltage corresponding to the control node is pulled up to the load voltage corresponding to the sampling resistor through the second pull-up resistor; when the second gate voltage corresponding to the control node is pulled up to the load voltage, the gate-source voltages of the first PMOS transistor and the second PMOS transistor approach zero, and the reverse protection circuit is cut off.

5. An overcurrent protection method for an anti-reverse circuit, characterized in that, The method is used for the reverse protection circuit with overcurrent protection according to any one of claims 1-4, and includes: When it is detected that the reverse protection circuit is in the positive power connection state, the reference voltage corresponding to the reverse protection circuit is determined by using the first voltage division network corresponding to the reverse protection circuit; The load voltage corresponding to the reverse protection circuit is detected by using the sampling resistor corresponding to the reverse protection circuit; The load voltage is subjected to hysteresis processing through a preset matching resistor network, and the detected voltage after hysteresis of the matching resistor network is determined; The reference voltage and the detected voltage are compared by using the voltage comparator corresponding to the reverse protection circuit; When the detected voltage is greater than the reference voltage, the load current corresponding to the output of the reverse protection circuit is determined; When the detected voltage is less than the reference voltage, a low-level signal is output by using the voltage comparator to cut off the load current.

6. The method according to claim 5, characterized in that, The detecting the load voltage corresponding to the reverse protection circuit by using the sampling resistor corresponding to the reverse protection circuit includes: Determining the resistance value corresponding to the sampling resistor; Detecting the load current flowing through the sampling resistor; According to the resistance value and the load current, the load voltage corresponding to the sampling resistor is determined by using Ohm's law.

7. The method according to claim 5, characterized in that, The determining the load current corresponding to the output of the reverse protection circuit when the detected voltage is greater than the reference voltage includes: When it is determined by using the voltage comparator that the detected voltage is greater than the reference voltage, the voltage comparator outputs a high-level signal; The NMOS transistor corresponding to the voltage comparator is driven to conduct by using the high-level signal, so that the reverse protection circuit outputs the corresponding load current.

8. The method according to claim 7, wherein If the gates of the first PMOS transistor and the second PMOS transistor of the reverse protection circuit are commonly connected to the control node, then the driving the NMOS transistor corresponding to the voltage comparator to conduct by using the high-level signal, so that the reverse protection circuit outputs the corresponding load current includes: The high-level signal drives the NMOS transistor to conduct through the first gate resistor, so that the NMOS transistor forms a low-impedance path; When the NMOS transistor forms a low-impedance path, the first gate voltage corresponding to the control node is pulled down through the second gate resistor corresponding to the NMOS transistor, so that the first PMOS transistor and the second PMOS transistor meet the conduction conditions; When the first PMOS transistor and the second PMOS transistor meet the conduction condition, the input voltage corresponding to the reverse protection circuit supplies power to the load through the circuit channels of the first PMOS transistor and the second PMOS transistor to output the load current.

9. The method according to claim 8, wherein Utilizing the low-level signal output by the voltage comparator to cut off the load current includes: The low-level signal is transmitted to the gate of the NMOS transistor through the first gate resistor, so that the gate-source voltage of the NMOS transistor is lower than the threshold voltage; When the gate-source voltage of the NMOS transistor is lower than the threshold voltage, the second gate voltage corresponding to the control node increases, so that the first PMOS transistor and the second PMOS transistor cut off the load current.

10. The method according to claim 9, wherein The second gate voltage corresponding to the control node increases, so that the first PMOS transistor and the second PMOS transistor cut off the load current includes: Utilizing the second pull-up resistor to pull up the second gate voltage to the load voltage corresponding to the sampling resistor; When the second gate voltage is pulled up to the load voltage, the gate-source voltages of the first PMOS transistor and the second PMOS transistor approach 0, so that the reverse protection circuit cuts off the load current.

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