Code generation method and device, electronic equipment and storage medium

Abstract

The invention provides a code generation method and device, electronic equipment and a storage medium, and relates to the technical field of computers. The method comprises the steps of obtaining a logic directed graph; converting the logic directed graph into a tree structure; converting the tree structure into a recursive structure; the recursive structure comprises a branch microstructure and a linear microstructure; converting the branch microstructure and the linear microstructure into a program language structure; extracting a variable relation directed graph corresponding to the logic directed graph; the variable relation directed graph comprises variables of which the variable types are determined; performing variable type reasoning based on the variable relation directed graph to obtain all variable types in the logic directed graph; based on action range identification rules, identifying action ranges of variables corresponding to the branch microstructures and the linear microstructures; and generating a code file corresponding to the logic directed graph based on a program language structure, the logic flow directed graph, the variable type and the action range of the variable. According to the invention, the efficiency and accuracy of converting the logic directed graph into the code file can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of computer technologies, and in particular, to a code generation method, apparatus, electronic device, and storage medium. Background Art

[0002] A program flow chart graphically represents the flow and logical relationships of a program, organizes code logic in the form of nodes and connections. There are various forms of program flow charts, such as design flow charts of programs, algorithm flow charts, visual logic flow codes, etc. The program flow chart has certain advantages in overall visualization, but it is difficult to comprehensively reflect logical details, such as lacking complex programming language features like variable types and data structure definitions, and it does not have the executability of the program. Therefore, it is often necessary to convert the program flow chart into executable program code. In the prior art, the program flow chart is usually converted into program code manually or automatically into executable program code with low readability. When the flow chart is relatively complex, the former requires high labor costs, and the code obtained by the latter often has extremely poor readability and extremely low reusability. Therefore, there is an urgent need for a method that can automatically convert a program flow chart into executable program code with high accuracy, high reusability, and good readability. Summary of the Invention

[0003] The present disclosure provides a code generation method, apparatus, electronic device, and storage medium to at least solve the above technical problems existing in the prior art.

[0004] According to a first aspect of the present disclosure, a code generation method is provided. The method includes: obtaining a logical directed graph; converting the logical directed graph into a tree structure; converting the tree structure into a recursive structure; the recursive structure includes a branch micro-structure and a linear micro-structure; converting the branch micro-structure and the linear micro-structure into a program language structure; extracting a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; identifying the scopes of the variables corresponding to the branch micro-structure and the linear micro-structure based on scope identification rules; generating a code file corresponding to the logical directed graph based on the program language structure, the logical directed graph, the variable types, and the scopes of the variables.

[0005] In one possible implementation, the conversion of the logical directed graph into a tree structure includes: merging all non-branching paths in the logical directed graph into a single node to obtain a first directed graph; traversing each edge in the first directed graph, and in response to the layer span of the current edge being greater than 1, supplementing empty nodes in the current edge so that the layer span of each edge is 1 to obtain a second directed graph; the layer span is the maximum value of the difference in the number of layers between the starting node and the ending node of the current edge; performing a breadth-first traversal on the second directed graph to determine the target node in the second directed graph; the target node is the first node in the second directed graph that has multiple parent nodes; based on the target node, performing a topological structure adjustment operation on the second directed graph to obtain the tree structure.

[0006] In one possible implementation, the performing a topological structure adjustment operation on the second directed graph based on the target node to obtain the tree structure includes: in response to the target node having sibling nodes, performing a splitting operation on the target node and determining the target node in the second directed graph after the splitting operation until splitting operations are performed on all target nodes having sibling nodes in the second directed graph to obtain a third directed graph; in response to the target nodes in the third directed graph having the same type of parent nodes, merging the same type of parent nodes; the parent nodes of the same type of parent nodes are the same node; in response to the target nodes in the third directed graph not having the same type of parent nodes, performing a splitting operation on the target nodes in the third directed graph; re-determining the target nodes in the third directed graph until there are no target nodes in the third directed graph to obtain the tree structure.

[0007] In one possible implementation, the conversion of the tree structure into a recursive structure includes: traversing the tree structure to determine the number of child nodes of each node in the tree structure; in response to the node having multiple child nodes, determining the microstructures of the node and all its child nodes as branch microstructures; in response to the node not having multiple child nodes, determining the microstructures of the node and its child node as linear microstructures; combining all the branch microstructures and linear microstructures to obtain the recursive structure.

[0008] In one possible implementation, the performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph includes: traversing the variable relationship directed graph from the parent node to the child node, and determining the variable type of the child node of the first node based on the first node whose variable type has been determined; traversing the variable relationship directed graph from the child node to the parent node, and determining the variable type of the parent node of the second node based on the second node whose variable type has been determined.

[0009] In an implementable embodiment, identifying the scopes of variables corresponding to the branch microstructure and the linear microstructure based on the scope identification rules includes: constructing declared variables and self-declared variables for each node; the declared variables are variables that have been declared before the node, and the self-declared variables are variables that need to be declared in the node; determining the self-declared variables corresponding to the branch microstructure nodes and the declared variables of the subgraph leaf nodes in the branch microstructure based on the first scope identification rule corresponding to the branch microstructure; determining the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure based on the second scope identification rule corresponding to the linear microstructure; and determining the scopes of all variables based on the declared variables and self-declared variables of each node.

[0010] In an implementable embodiment, determining the self-declared variables corresponding to the branch microstructure nodes and the declared variables of the subgraph leaf nodes in the branch microstructure based on the first scope identification rule corresponding to the branch microstructure includes: determining the self-declared variables corresponding to the branch microstructure nodes as the self-declared variables of the subgraph root nodes corresponding to the branch microstructure nodes; determining the sum of the declared variables and the self-declared variables of the subgraph root nodes corresponding to the branch microstructure nodes as the declared variables of the subgraph leaf nodes in the branch microstructure; determining the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure based on the second scope identification rule corresponding to the linear microstructure includes: determining the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variables corresponding to the linear microstructure node; and determining the sum of the declared variables and the self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node as the declared variables of the subgraph leaf nodes in the linear microstructure.

[0011] According to a second aspect of the present disclosure, there is provided a code generation device, the device comprising: an extraction module for obtaining a logical directed graph; a conversion module for converting the logical directed graph into a tree structure; the conversion module is further configured to convert the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; the conversion module is further configured to convert the branch microstructure and the linear microstructure into a programming language structure; the extraction module is further configured to extract a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; an inference module for performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; an identification module for identifying the scopes of variables corresponding to the branch microstructure and the linear microstructure based on a scope identification rule; a generation module for generating a code file corresponding to the logical directed graph based on the programming language structure, the logical directed graph, the variable types, and the scopes of the variables.

[0012] According to a third aspect of the present disclosure, there is provided an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to execute the method of the present disclosure.

[0013] According to a fourth aspect of the present disclosure, there is provided a non-transitory computer-readable storage medium storing computer instructions for causing a computer to execute the method of the present disclosure.

[0014] A code generation method, device, electronic device, and storage medium of the present disclosure convert a logical directed graph into a tree structure, convert the tree structure into a recursive structure including a branch microstructure and a linear microstructure, and convert the branch microstructure and the linear microstructure into a programming language structure, then perform variable type inference based on a variable relationship directed graph corresponding to the logical directed graph to obtain all variable types in the logical directed graph, and identify the scopes of variables corresponding to the branch microstructure and the linear microstructure based on a scope identification rule, and finally generate a code file corresponding to the logical directed graph based on the programming language structure, variable types, and variable scopes. Thereby, it is possible to automatically convert a logical directed graph into a code file, improve the conversion efficiency, and moreover, based on a custom method for converting a logical directed graph into a tree structure, a method for performing variable type inference, and a method for identifying variable scopes, it is possible to improve the accuracy of converting a logical directed graph into a code file.

[0015] It should be understood that the content described in this section is not intended to identify the key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become readily understandable through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] By reading the following detailed description with reference to the accompanying drawings, the above and other objects, features, and advantages of the exemplary embodiments of the present disclosure will become readily understandable. In the drawings, several embodiments of the present disclosure are shown in an exemplary but non-limiting manner, wherein: In the drawings, the same or corresponding reference numerals represent the same or corresponding parts.

[0017] Figure 1 The flowchart of a code generation method according to an embodiment of the present disclosure is shown. Figure 1 ; Figure 2 The flowchart of a code generation method according to an embodiment of the present disclosure is shown. Figure 2 ; Figure 3 The flowchart of a code generation method according to an embodiment of the present disclosure is shown. Figure 3 ; Figure 4 The flowchart of a code generation method according to an embodiment of the present disclosure is shown. Figure 4 ; Figure 5 The flowchart of a code generation method according to an embodiment of the present disclosure is shown. Figure 5 ; Figure 6 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 1 ; Figure 7 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 2 ; Figure 8 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 3 ; Figure 9 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 4 ; Figure 10 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 5 ; Figure 11 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 6 ; Figure 12 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown. Figure 7 ; Figure 13 Shows a schematic diagram of the scenario of a code generation method according to an embodiment of the present disclosure Figure 8 ; Figure 14 Shows a schematic diagram of the scenario of a code generation method according to an embodiment of the present disclosure Figure 9 ; Figure 15 Shows a schematic structural diagram of a code generation device according to an embodiment of the present disclosure; Figure 16 Shows a schematic diagram of the composition structure of an electronic device according to an embodiment of the present disclosure. Detailed implementation manners

[0018] To make the objectives, features, and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Apparently, the described embodiments are only a part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by those skilled in the art without creative efforts shall fall within the protection scope of the present disclosure.

[0019] Figure 1 Shows a schematic flowchart of a code generation method according to an embodiment of the present disclosure Figure 1 , such as Figure 1 shown, a code generation method includes: Step S101, obtain a logical directed graph.

[0020] In this embodiment, it is first necessary to obtain a logical directed graph. The logical directed graph contains node and connection information. The specific business logic is in the nodes, and there may be conditions on the edges between the nodes, such as conditions corresponding to if / else, etc., or there may be no conditions. The logical directed graph can be extracted from a logic flow file, a natural language description, or can be designed by itself.

[0021] Step S102, convert the logical directed graph into a tree structure.

[0022] In this embodiment, it is necessary to convert the logical directed graph into a tree structure. The logical directed graph is a complex graph structure, and there may be complex relationships such as multiple branches and loops. To simplify the subsequent processing process, it is necessary to convert it into a tree structure. The tree structure is a hierarchical structure, and each node has at most one parent node, which makes the subsequent code generation process simpler and more efficient. The core of the conversion process is to process the multi-branch nodes in the graph (that is, the nodes with multiple parent nodes) to ensure that the converted tree structure can accurately reflect the logical relationship of the original logic flow. For example, for a node with multiple parent nodes, it is necessary to split or merge it to eliminate the multi-branch situation, and finally obtain an acyclic tree structure.

[0023] Step S103: Convert the tree structure into a recursive structure.

[0024] In this embodiment, after the conversion from the logical directed graph to the tree structure is completed, it is necessary to convert the tree structure into a recursive structure. A recursive structure is a structure recursively composed of branch microstructures and linear microstructures, which can better adapt to the structural characteristics of programming languages. Specifically, each node and its sub-nodes in the tree structure can be regarded as a microstructure, and according to the number of sub-nodes and logical relationships of the nodes, they are divided into branch microstructures or linear microstructures. Branch microstructures usually correspond to conditional branch structures (such as if / else) in programming languages, while linear microstructures correspond to sequentially executed code blocks.

[0025] Step S104: Convert the branch microstructures and linear microstructures into programming language structures.

[0026] In this embodiment, in the recursive structure, branch microstructures and linear microstructures respectively correspond to different structures in programming languages. Branch microstructures can be converted into conditional branch statements (such as if / else), while linear microstructures can be converted into sequentially executed code blocks. For example, if a branch microstructure contains a parent node and multiple sub-nodes, it can be converted into an if / else statement, where the logical condition of the parent node serves as the condition of the if statement, and the logics of the sub-nodes serve as the code blocks in the if and else branches respectively. Linear microstructures are converted into sequentially executed code blocks according to the logical order.

[0027] Step S105: Extract the variable relationship directed graph corresponding to the logical directed graph.

[0028] In this embodiment, it is also necessary to extract the variable relationship directed graph corresponding to the logical directed graph. All variables and their assignment relationships, function call relationships, etc. in the file corresponding to the logical directed graph can be scanned to construct a directed graph, where nodes represent variables and edges represent the relationships between variables. For example, if variable "x" is assigned the value of variable "y", then an edge is added from variable "y" to variable "x" in the variable relationship directed graph.

[0029] In an implementable manner, the variable relationship directed graph corresponding to the logic directed graph can be extracted based on the following method: scan the file corresponding to the logic directed graph and the Java files of its implementation classes, and obtain the attribute variable types of all entities based on format parsing and string regular matching; extract all the variables that appear in the logic flow; assign types to the variables or parameters that have been strictly type-declared in the file corresponding to the logic directed graph; construct a variable relationship directed graph according to the assignment relationship formed by the assignment, the input parameters of the called function, and the output parameters of the called function, the attribute relationship of multi-level variables, the sequence or element relationship of array-type variables, etc., for variable type inference.

[0030] Step S106, perform variable type inference based on the variable relationship directed graph to obtain all variable types in the logic directed graph.

[0031] In this embodiment, the process of performing variable type inference based on the variable relationship directed graph is to infer the type of each variable by analyzing the relationship between variables. Specifically, starting from the variables with known types, according to the assignment relationship and function call relationship in the variable relationship directed graph, the types of other variables are gradually inferred. For example, if variable "x" is assigned the value of variable "y", and the type of "y" is known to be an integer, then it can be inferred that the type of "x" is also an integer.

[0032] Step S107, based on the scope identification rule, identify the scopes of the variables corresponding to the branch microstructure and the linear microstructure.

[0033] In this embodiment, in a programming language, the scope of a variable refers to the effective range of the variable. By based on the scope identification rule, the scopes of the variables in the branch microstructure and the linear microstructure can be identified. Specifically, for each microstructure, according to its structural characteristics and the declaration position of the variable, the scope of the variable is determined. For example, in a branch microstructure, the scope of the variable in the branch condition may be limited to that conditional statement, while the scope of the variable inside the branch may extend to the entire branch code block.

[0034] Step S108, generate a code file corresponding to the logic directed graph based on the programming language structure, the logic directed graph, the variable types, and the scopes of the variables.

[0035] In this embodiment, after completing all the above steps, the final code file can be generated according to the programming language structure, the variable types, and the scopes of the variables. The specific process is to combine the code blocks in the programming language structure in logical order, insert variable declaration statements at appropriate positions, and organize the code blocks according to the scopes of the variables. In an example, the generated code file is a complete Java code file that can accurately implement the logical function of the logic directed graph and has good readability and maintainability.

[0036] In the present disclosure, a logical directed graph is converted into a tree structure, the tree structure is converted into a recursive structure including a branch microstructure and a linear microstructure, and the branch microstructure and the linear microstructure are converted into a programming language structure. Then, based on the variable relationship directed graph corresponding to the logic flow file, variable type inference is performed to obtain all variable types in the logical directed graph. Based on the scope identification rule, the scopes of the variables corresponding to the branch microstructure and the linear microstructure are identified. Finally, based on the programming language structure, variable types, and variable scopes, a code file corresponding to the logical directed graph is generated. Thus, the logical directed graph can be automatically converted into a code file, improving the conversion efficiency.

[0037] Figure 2 The flowchart of a code generation method according to an embodiment of the present disclosure is shown Figure 2 , such as Figure 2 shown, step S102, "converting the logical directed graph into a tree structure", includes: Step S201, merging all non-branching paths in the logical directed graph into a single node to obtain a first directed graph.

[0038] In this embodiment, in the process of converting the logical directed graph into a tree structure, it is first necessary to remove empty nodes from the logical directed graph. Figure 6 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown Figure 1 , such as Figure 6 shown, Figure 6 The logical directed graph on the left includes nodes A, B, C, D, E, F. If node F is an empty node among them, then node F needs to be removed to obtain Figure 6 the logical directed graph on the right. Then, it is necessary to simplify the logical directed graph, that is, merge all non-branching paths in the logical directed graph into a single node. A non-branching path means starting from a node, reaching another node along a unique path, and having no branches in the middle. Figure 7 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown Figure 2 , such as Figure 7 shown, Figure 7 The empty nodes have been removed from the logical directed graph on the left, which includes nodes A, B, C, D, E, F. The paths from node C to node E and from node D to node F are non-branching paths. Therefore, the path from node C to node E can be merged into node C1, and the path from node D to node F can be merged into node D1 to obtain Figure 7 the first directed graph on the right.

[0039] Step S202, traversing each edge in the first directed graph, and in response to the level span of the current edge being greater than 1, adding empty nodes to the current edge to make the level span of each edge 1, obtaining a second directed graph.

[0040] In this embodiment, after obtaining the first directed graph, in order to further regularize the graph structure, it is necessary to process each edge in the first directed graph. Specifically, traverse each edge in the first directed graph and check whether the level span of the current edge is greater than 1. The level span is the maximum value of the difference in the levels of the start node and the end node of the current edge. If the level span is greater than 1, it means that this edge spans multiple levels, and it is necessary to supplement empty nodes in the edge so that the level span of each edge is 1.

[0041] Figure 8 The scene of a code generation method according to an embodiment of the present disclosure is shown Figure 3 , as Figure 8 shown, Figure 8 In the first directed graph on the left, there are nodes A, B, and D. Among them, the level of node A is 1, the level of node B is 2, and the level of node D is 3. Obviously, the level span of the edge from node A to node D is 2. Therefore, it is necessary to supplement empty nodes in the edge from node A to node D to obtain Figure 8 the second directed graph on the right, and the level span of each edge in the second directed graph is 1.

[0042] Step S203: Perform a breadth-first traversal on the second directed graph to determine the target nodes in the second directed graph.

[0043] In this embodiment, after obtaining the second directed graph, it is necessary to determine the target nodes therein. The target node refers to the first node in the second directed graph that has multiple parent nodes. In order to find the target node, it is necessary to perform a breadth-first traversal on the second directed graph. The breadth-first traversal is an algorithm for traversing a graph layer by layer, starting from the root node and checking the number of parent nodes of each node layer by layer.

[0044] Figure 9 The scene of a code generation method according to an embodiment of the present disclosure is shown Figure 4 , as Figure 9 shown, Figure 9 The logical directed graph on the left includes nodes A, B, C, D, E, X, and Y. After the operations in steps S201 - S202, Figure 9 the second directed graph on the right is obtained, and node G is Figure 9 the first node in the second directed graph on the right that has multiple parent nodes. Therefore, node G is the target node.

[0045] Step S204: Based on the target nodes, perform a topological structure adjustment operation on the second directed graph to obtain a tree structure.

[0046] In this embodiment, after determining the target node, it is necessary to perform a topological structure adjustment operation on the second directed graph based on the target node to convert it into a tree structure. The specific operations include performing splitting or merging operations based on the target node to eliminate the case of multiple branches, and finally converting the second directed graph into a tree structure.

[0047] In the present disclosure, based on a custom method for converting a logical directed graph into a tree structure, the accuracy of converting a logical directed graph into a tree structure can be improved.

[0048] Figure 3 The flowchart of a code generation method according to an embodiment of the present disclosure is shown Figure 3 , as Figure 3 shown, step S204 "Based on the target node, perform a topological structure adjustment operation on the second directed graph to obtain a tree structure" includes: Step S301, in response to the target node having sibling nodes, perform a splitting operation on the target node, and determine the target node in the second directed graph after the splitting operation until the splitting operation is performed on all target nodes having sibling nodes in the second directed graph to obtain a third directed graph.

[0049] In this embodiment, during the process of performing a topological structure adjustment on the second directed graph, if the target node has sibling nodes, it means that its parent node has multiple branches, and thus a splitting operation needs to be performed on the target node. Specifically, the logic of the target node is split into multiple independent parts, each part corresponding to a parent node, that is, the target node can be copied, and the parent node of the target node is pointed to the newly copied target node. Figure 10 The scenario diagram of a code generation method according to an embodiment of the present disclosure is shown Figure 5 , as Figure 10 shown, Figure 10 For the second directed graph on the left, where the target node is node G, and node G has a sibling node E, so a splitting operation needs to be performed on node G to obtain node G1 and node G2, thereby obtaining Figure 10 the third directed graph in the middle.

[0050] Step S302, in response to the target nodes in the third directed graph having the same type of parent nodes, merge the same type of parent nodes.

[0051] In this embodiment, after obtaining the third directed graph, if the parent nodes of the target node belong to the same class, that is, the parent nodes of these parent nodes are the same node, then these parent nodes can be merged. That is, if the sum of the branch conditions of the parent nodes in the same class constitutes a complete event (that is, it includes all the nodes under the grandfather node of this class), then all the parent nodes in the same class are formed into a tree node, and this tree node uses the null node as the root node and all the parent nodes in the same class as the child nodes of the root node, thereby forming a branch microstructure; if a complete event cannot be constituted (that is, there are nodes among the child nodes of the grandfather node that are the parent nodes of the target node), then these conditions are aggregated, and the parent nodes in this class are merged to form a tree node.

[0052] As Figure 10 shown, Figure 10 in the third directed graph in the middle, the target node is node G2, the two parent nodes of node G1 are node C and node D, and the parent nodes of node C and node D are both node A. Therefore, node G2 has parent nodes in the same class, so node C and node D can be merged to obtain node P, and node P is the tree node, thus obtaining Figure 10 the tree structure on the right.

[0053] Step S303, in response to the non-existence of parent nodes in the same class for the target node in the third directed graph, perform a splitting operation on the target node in the third directed graph.

[0054] Step S304, re-determine the target node in the third directed graph until there is no target node in the third directed graph, and obtain the tree structure.

[0055] In this embodiment, if the parent nodes of the target node do not belong to the same class, that is, their parent nodes are different, then continue to perform a splitting operation on the target node. Through repeated splitting and merging operations, the third directed graph is finally converted into a tree structure.

[0056] Figure 4 shows the flowchart of a code generation method according to an embodiment of the present disclosure Figure 4 As Figure 4 shown, step S103 "Convert the tree structure into a recursive structure" includes: Step S401, traverse the tree structure to determine the number of child nodes of each node in the tree structure.

[0057] In this embodiment, during the process of converting the tree structure into a recursive structure, it is first necessary to traverse the tree structure to determine the number of child nodes of each node. Specifically, starting from the root node, traverse the tree structure layer by layer and count the number of child nodes of each node.

[0058] Step S402: In response to a node having multiple child nodes, determine the microstructures of the node and all its child nodes as branch microstructures.

[0059] In this embodiment, after determining the number of child nodes of each node, if a node has multiple child nodes, then the structure formed by this node and its child nodes can be regarded as a branch microstructure. The branch microstructure generally corresponds to a conditional branch structure (such as if / else) in programming languages. Figure 11 The figure shows a scenario schematic of a code generation method according to an embodiment of the present disclosure Figure 6 , such as Figure 11 shown Figure 11 In the tree structure on the left, node B has two child nodes. Then, node B and its child nodes E and G1 can be regarded as a branch microstructure, resulting in Figure 11 node B1 in the middle tree structure.

[0060] Step S403: In response to a node not having multiple child nodes, determine the microstructures of the node and its child node as a linear microstructure.

[0061] In this embodiment, if a node has only one child node, then the structure formed by this node and its child node can be regarded as a linear microstructure. The linear microstructure generally corresponds to a code block that is executed sequentially in programming languages. As Figure 11 shown Figure 11 In the tree structure on the left, node P has one child node. Then, node P and its child node G2 are determined as a linear microstructure, resulting in Figure 11 node P1 in the middle tree structure.

[0062] Step S404: Combine all branch microstructures and linear microstructures to obtain a recursive structure.

[0063] In this embodiment, after determining the branch microstructures and linear microstructures, combine these microstructures according to the structural relationship of the tree to form a recursive structure. The recursive structure is recursively composed of branch microstructures and linear microstructures and can well represent the logical structure of the program. For example, a tree structure may contain multiple branch microstructures and linear microstructures. Through recursive combination, a complete recursive structure can be obtained. The generation of the recursive structure is based on the hierarchical relationship of the tree structure and the logical relationship of the microstructures, providing a structural form closer to the target language for subsequent code generation. As Figure 11 shown Figure 11 The tree structure on the left is converted into Figure 11 the tree structure in the middle and finally converted into Figure 11 the recursive structure on the right.

[0064] Figure 12The scenario of a code generation method according to an embodiment of the present disclosure is shown Figure 7 , such as Figure 12 shown, for the branch microstructure on the left side in the recursive structure, which includes nodes A, B, and C, this branch microstructure can be converted into the programming language structure on the right side as shown in Figure 12 . Figure 12 Figure 13 The scenario of a code generation method according to an embodiment of the present disclosure is shown Figure 8 , such as Figure 13 shown, for the linear microstructure on the left side in the recursive structure, which includes nodes D, E, and F, this linear microstructure can be converted into the programming language structure on the right side as shown in Figure 13 . Figure 13

[0065] In another embodiment, step S106, "performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph", includes: Traversing the variable relationship directed graph from the parent node to the child node, and determining the variable type of the child node of the first node according to the first node with the determined variable type; Traversing the variable relationship directed graph from the child node to the parent node, and determining the variable type of the parent node of the second node according to the second node with the determined variable type.

[0066] In this embodiment, during the process of performing variable type inference, it is first necessary to traverse the variable relationship directed graph from the parent node to the child node. Specifically, starting from the variable node with a known type, the variable type of its child node is inferred according to the assignment relationship or function call relationship. For example, if variable "x" is assigned the value of variable "y", and the type of "y" is known to be an integer, then it can be inferred that the type of "x" is also an integer. This traversal method from the parent node to the child node is based on the assignment relationship and logical dependency between variables, and can effectively infer the variable type of the child node.

[0067] In this embodiment, during the process of performing variable type inference, in addition to traversing from the parent node to the child node, it is also necessary to traverse the variable relationship directed graph from the child node to the parent node. Specifically, starting from the variable node with a known type, the variable type of its parent node is inferred according to the assignment relationship or function call relationship. For example, if variable "z" is assigned from variable "w", and the type of "z" is known to be a string, then it can be inferred that the type of "w" is also a string. This traversal method from the child node to the parent node is based on the reverse assignment relationship and logical dependency between variables, and can effectively supplement and verify the inference result of the variable type.

[0068] Figure 5 ​​The flowchart of a code generation method according to an embodiment of the present disclosure is shown Figure 5 , as Figure 5 shown, step S107, "Based on the scope recognition rule, recognize the scopes of variables corresponding to the branch microstructure and the linear microstructure", includes: Step S501, construct the declared variables and self-declared variables for each node.

[0069] In this embodiment, during the process of recognizing the variable scope, it is first necessary to construct the declared variables and self-declared variables for each node. Declared variables refer to variables that have been declared before this node, while self-declared variables refer to variables that need to be declared in this node. For example, in a node, if the variable "a" has been declared in a previous node, then it is a declared variable; if the variable "b" needs to be declared in the current node, then it is a self-declared variable. By distinguishing between declared variables and self-declared variables, the variable scope can be determined more accurately.

[0070] Step S502, based on the first scope recognition rule corresponding to the branch microstructure, determine the self-declared variables corresponding to the branch microstructure nodes and the declared variables of the subgraph leaf nodes in the branch microstructure.

[0071] In this embodiment, when recognizing the variable scope in the branch microstructure, it is necessary to recognize based on the first scope recognition rule. Specifically, for each node in the branch microstructure, according to its position and logical relationship in the branch microstructure, determine its corresponding self-declared variables and declared variables. For example, in a branch microstructure, the variable scope in the branch condition may be limited to that conditional statement, while the variable scope inside the branch may extend to the entire branch code block. Through this scope recognition rule based on the characteristics of the branch microstructure, the scope of each variable can be accurately determined.

[0072] Step S503, based on the second scope recognition rule corresponding to the linear microstructure, determine the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure.

[0073] In this embodiment, when recognizing the variable scope in the linear microstructure, it is necessary to recognize based on the second scope recognition rule. Specifically, for each node in the linear microstructure, according to its position and logical relationship in the linear microstructure, determine its corresponding self-declared variables and declared variables. For example, in a linear microstructure, the variable scope may extend from its declaration position to the end of the entire linear microstructure.

[0074] Step S504, based on the declared variables and self-declared variables of each node, determine the scopes of all variables.

[0075] In the present disclosure, a method based on custom recognition of variable scopes can improve the accuracy of variable scope recognition.

[0076] In one implementable manner, step S502, "Based on the first scope recognition rule corresponding to the branch microstructure, determine the self-declared variables corresponding to the branch microstructure nodes and the declared variables of the subgraph leaf nodes in the branch microstructure", includes: Determine the self-declared variables corresponding to the subgraph root nodes of the branch microstructure nodes as the self-declared variables corresponding to the branch microstructure nodes; Determine the sum of the declared variables of the subgraph root nodes corresponding to the branch microstructure nodes and the self-declared variables as the declared variables of the subgraph leaf nodes in the branch microstructure.

[0077] In this embodiment, when recognizing the scope of variables in the branch microstructure, for the self-declared variables of the subgraph root nodes corresponding to the branch microstructure nodes, directly determine them as the self-declared variables of the branch microstructure nodes. That is, the self-declared variables of the branch microstructure nodes = the self-declared variables of the subgraph root nodes.

[0078] In this embodiment, when recognizing the scope of variables in the branch microstructure, for the declared variables of the subgraph leaf nodes in the branch microstructure, determine them as the sum of the declared variables of the subgraph root nodes and the self-declared variables. That is, the declared variables of the subgraph leaf nodes = the declared variables of the root nodes + the self-declared variables of the root nodes.

[0079] In one implementable manner, step S503, "Based on the second scope recognition rule corresponding to the linear microstructure, determine the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure", includes: Determine the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variable corresponding to the linear microstructure node; Determine the sum of the declared variables and the self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node as the declared variables of the subgraph leaf nodes in the linear microstructure.

[0080] In this embodiment, in the linear microstructure, the self-declared variable of a node is the sum of the self-declared variables of all nodes in its subgraph. That is, the self-declared variable of the simple path structure node is equal to the sum of the self-declared variables of all nodes in the subgraph.

[0081] In this embodiment, in the linear microstructure, the declared variable of the subgraph leaf node is the sum of the declared variable of its parent node and the self-declared variable. That is, the declared variable of the sub-node in the subgraph = the declared variable of the parent node + the self-declared variable of the parent node.

[0082] Figure 14The scenario of a code generation method according to an embodiment of the present disclosure is shown Figure 9 , as Figure 14 shown, for the branch microstructure G2, its subgraph is a structure composed of nodes C, G1, and D, and X represents a self-declared variable, and Y represents a declared variable. Then, the calculation formula for the self-declared variable of the branch microstructure G2 is , where is the self-declared variable of the branch microstructure G2, is the self-declared variable of the root node C of the subgraph; the calculation formula for the declared variable of the leaf node D of the subgraph is , where is the declared variable of the leaf node D of the subgraph, is the self-declared variable of the root node C of the subgraph, is the declared variable of the root node C of the subgraph.

[0083] For the linear microstructure G1, its subgraph is a structure composed of nodes A and B, and X represents a self-declared variable, and Y represents a declared variable. Then, the calculation formula for the self-declared variable of the linear microstructure G1 is , where is the self-declared variable of the linear microstructure G1, is the self-application variable of the subgraph node A, is the self-application variable of the subgraph node B; the calculation formula for the declared variable of the sub-node B in the subgraph is , where is the declared variable of the sub-node B in the subgraph, is the self-declared variable of the parent node of the sub-node B, is the declared variable of the parent node of the sub-node B.

[0084] Figure 15 The structural schematic diagram of a code generation device according to an embodiment of the present disclosure is shown, as Figure 15 shown, a code generation device includes: An extraction module 10 is used to obtain a logical directed graph; a conversion module 11 is used to convert the logical directed graph into a tree structure; the conversion module 11 is also used to convert the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; the conversion module 11 is also used to convert the branch microstructure and the linear microstructure into a program language structure; the extraction module 10 is also used to extract a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; an inference module 12 is used to perform variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; an identification module 13 is used to identify the scopes of variables corresponding to the branch microstructure and the linear microstructure based on a scope identification rule; a generation module 14 is used to generate a code file corresponding to the logical directed graph based on the program language structure, the logical directed graph, the variable types, and the scopes of variables.

[0085] In an implementable embodiment, the conversion module 11 is further used to: merge all non-branching paths in the logical directed graph into a single node to obtain a first directed graph; traverse each edge in the first directed graph, and in response to the layer span of the current edge being greater than 1, supplement empty nodes in the current edge so that the layer span of each edge is 1 to obtain a second directed graph; the layer span is the maximum value of the difference in the number of layers between the starting node and the ending node of the current edge; perform a breadth-first traversal on the second directed graph to determine the target nodes in the second directed graph; the target nodes are the first nodes in the second directed graph that have multiple parent nodes; based on the target nodes, perform a topological structure adjustment operation on the second directed graph to obtain a tree structure.

[0086] In an implementable embodiment, the conversion module 11 is further used to: in response to the target nodes having sibling nodes, perform a splitting operation on the target nodes, and determine the target nodes in the second directed graph after the splitting operation until the splitting operation is performed on all target nodes having sibling nodes in the second directed graph to obtain a third directed graph; in response to the target nodes in the third directed graph having the same type of parent nodes, merge the same type of parent nodes; the parent nodes of the same type of parent nodes are the same node; in response to the target nodes in the third directed graph not having the same type of parent nodes, perform a splitting operation on the target nodes in the third directed graph; re-determine the target nodes in the third directed graph until there are no target nodes in the third directed graph to obtain a tree structure.

[0087] In an implementable embodiment, the conversion module 11 is further used to: traverse the tree structure to determine the number of child nodes of each node in the tree structure; in response to a node having multiple child nodes, determine the microstructure of the node and all its child nodes as a branch microstructure; in response to a node not having multiple child nodes, determine the microstructure of the node and its child node as a linear microstructure; combine all the branch microstructures and linear microstructures to obtain a recursive structure.

[0088] In one implementable manner, the inference module 12 is further configured to: traverse the variable relationship directed graph from the parent node to the child node, and determine the variable type of the child node of the first node according to the first node whose variable type has been determined; traverse the variable relationship directed graph from the child node to the parent node, and determine the variable type of the parent node of the second node according to the second node whose variable type has been determined.

[0089] In one implementable manner, the recognition module 13 is further configured to: construct declared variables and self-declared variables for each node; the declared variables are the variables that have been declared before the node, and the self-declared variables are the variables that need to be declared in the node; based on the first scope recognition rule corresponding to the branch microstructure, determine the self-declared variables corresponding to the branch microstructure node and the declared variables of the subgraph leaf nodes in the branch microstructure; based on the second scope recognition rule corresponding to the linear microstructure, determine the self-declared variables corresponding to the linear microstructure node and the declared variables of the subgraph leaf nodes in the linear microstructure; based on the declared variables and self-declared variables of each node, determine the scopes of all variables.

[0090] In one implementable manner, the recognition module 13 is further configured to: determine the self-declared variables corresponding to the subgraph root node of the branch microstructure node as the self-declared variables corresponding to the branch microstructure node; determine the sum of the declared variables and the self-declared variables of the subgraph root node corresponding to the branch microstructure node as the declared variables of the subgraph leaf nodes in the branch microstructure.

[0091] In one implementable manner, the recognition module 13 is further configured to: determine the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variables corresponding to the linear microstructure node; determine the sum of the declared variables and the self-declared variables of the parent node of the leaf node in the subgraph corresponding to the linear microstructure node as the declared variables of the subgraph leaf nodes in the linear microstructure.

[0092] According to the embodiments of the present disclosure, the present disclosure also provides an electronic device and a readable storage medium.

[0093] Figure 16 FIG. shows a schematic block diagram of an exemplary electronic device 800 that can be used to implement the embodiments of the present disclosure. The electronic device is intended to represent various forms of digital computers, such as, laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. The electronic device can also represent various forms of mobile devices, such as, personal digital processors, cellular phones, smart phones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are only examples and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0094] As Figure 16 shown, device 800 includes a computing unit 801, which can perform various appropriate actions and processes according to computer programs stored in a read-only memory (ROM) 802 or computer programs loaded from a storage unit 808 into a random access memory (RAM) 803. In the RAM 803, various programs and data required for the operation of device 800 can also be stored. The computing unit 801, the ROM 802, and the RAM 803 are connected to each other via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0095] Multiple components in device 800 are connected to the I / O interface 805, including: an input unit 806, such as a keyboard, a mouse, etc.; an output unit 807, such as various types of displays, speakers, etc.; a storage unit 808, such as a magnetic disk, an optical disc, etc.; and a communication unit 809, such as a network card, a modem, a wireless communication transceiver, etc. The communication unit 809 allows device 800 to exchange information / data with other devices via a computer network such as the Internet and / or various telecommunication networks.

[0096] The computing unit 801 can be various general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various dedicated artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any appropriate processor, controller, microcontroller, etc. The computing unit 801 executes the various methods and processes described above, such as a code generation method. For example, in some embodiments, a code generation method can be implemented as a computer software program, which is tangibly contained in a machine-readable medium, such as the storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed onto device 800 via the ROM 802 and / or the communication unit 809. When the computer program is loaded into the RAM 803 and executed by the computing unit 801, one or more steps of a code generation method described above can be executed. Alternatively, in other embodiments, the computing unit 801 can be configured to execute a code generation method in any other appropriate manner (e.g., by means of firmware).

[0097] The various embodiments of the systems and techniques described above in this document can be implemented in digital electronic circuitry, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems-on-chip (SOCs), complex programmable logic devices (CPLDs), computer hardware, firmware, software, and / or combinations thereof. These various embodiments can include: being implemented in one or more computer programs that are executable and / or interpretable on a programmable system including at least one programmable processor, which can be a special-purpose or general-purpose programmable processor that receives data and instructions from a storage system, at least one input device, and at least one output device, and transmits the data and instructions to the storage system, the at least one input device, and the at least one output device.

[0098] The program code for implementing the methods of the present disclosure can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, such that when the program codes are executed by the processor or controller, the functions / operations specified in the flowchart and / or block diagram are implemented. The program code can be executed entirely on the machine, partially on the machine, executed partially on the machine as an independent software package and partially on a remote machine, or executed entirely on a remote machine or server.

[0099] In the context of the present disclosure, a machine-readable medium can be a tangible medium that can contain or store a program for use by or in connection with an instruction execution system, apparatus, or device. A machine-readable medium can be a machine-readable signal medium or a machine-readable storage medium. A machine-readable medium can include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specific examples of machine-readable storage media would include electrical connections based on one or more wires, portable computer disks, hard disks, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, compact disc read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0100] To provide interaction with a user, the systems and techniques described herein can be implemented on a computer having: a display device for displaying information to the user (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor); and a keyboard and a pointing device (e.g., a mouse or a trackball) through which the user can provide input to the computer. Other kinds of devices can also be used to provide interaction with the user; for example, the feedback provided to the user can be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user can be received in any form (including acoustic input, voice input, or tactile input).

[0101] The systems and techniques described herein can be implemented in a computing system including backend components (e.g., as a data server), or a computing system including middleware components (e.g., an application server), or a computing system including frontend components (e.g., a user computer having a graphical user interface or a web browser through which the user can interact with an implementation of the systems and techniques described herein), or a computing system including any combination of such backend components, middleware components, or frontend components. The components of the system can be interconnected to each other by digital data communication in any form or medium (e.g., a communication network). Examples of communication networks include: local area network (LAN), wide area network (WAN), and the Internet.

[0102] A computer system can include a client and a server. The client and the server are generally far from each other and typically interact through a communication network. The client-server relationship is created by computer programs running on the respective computers and having a client-server relationship with each other. The server can be a cloud server, or a server of a distributed system, or a server incorporating a blockchain.

[0103] It should be understood that the various forms of processes shown above can be used, with steps reordered, added, or deleted. For example, the steps recited in this disclosure can be executed in parallel, sequentially, or in a different order, as long as the desired results of the technical solution of this disclosure can be achieved, and no limitation is imposed herein.

[0104] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" can explicitly or implicitly include at least one of the features. In the description of this disclosure, "a plurality" means two or more unless otherwise specifically defined.

[0105] As described above, it is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims described above.

Claims

1. A code generation method, characterized in that, The method includes: Obtaining a logical directed graph; Converting the logical directed graph into a tree structure; Converting the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; Converting the branch microstructure and the linear microstructure into a programming language structure; Extracting a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; Performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; Identifying the scopes of variables corresponding to the branch microstructure and the linear microstructure based on scope identification rules; Generating a code file corresponding to the logical directed graph based on the programming language structure, the logical directed graph, the variable types, and the scopes of the variables.

2. The method according to claim 1, characterized in that, The converting the logical directed graph into a tree structure includes: Merging all non-branching paths in the logical directed graph into a single node to obtain a first directed graph; Traversing each edge in the first directed graph, and in response to the level span of the current edge being greater than 1, supplementing empty nodes in the current edge so that the level span of each edge is 1 to obtain a second directed graph; the level span is the maximum value of the difference in the number of layers between the starting node and the ending node of the current edge; Performing a breadth-first traversal on the second directed graph to determine a target node in the second directed graph; the target node is the first node in the second directed graph that has multiple parent nodes; Performing a topological structure adjustment operation on the second directed graph based on the target node to obtain the tree structure.

3. The method according to claim 2, characterized in that, The performing a topological structure adjustment operation on the second directed graph based on the target node to obtain the tree structure includes: In response to the target node having sibling nodes, performing a splitting operation on the target node and determining the target node in the second directed graph after the splitting operation until splitting operations are performed on all target nodes having sibling nodes in the second directed graph to obtain a third directed graph; In response to the target nodes in the third directed graph having the same type of parent nodes, merging the same type of parent nodes; the parent nodes of the same type of parent nodes are the same node; In response to the target nodes in the third directed graph not having the same type of parent nodes, performing a splitting operation on the target nodes in the third directed graph; Redetermining the target nodes in the third directed graph until there are no target nodes in the third directed graph to obtain the tree structure.

4. The method according to claim 1, wherein The converting the tree structure into a recursive structure includes: Traversing the tree structure to determine the number of child nodes of each node in the tree structure; In response to the node having multiple child nodes, determining the microstructure of the node and all its child nodes as a branch microstructure; In response to the node not having multiple child nodes, determining the microstructure of the node and its child node as a linear microstructure; Combining all the branch microstructures and linear microstructures to obtain the recursive structure.

5. The method according to claim 1, wherein Performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph, including: Traversing the variable relationship directed graph from the parent node to the child node, and determining the variable type of the child node of the first node according to the first node with the determined variable type; Traversing the variable relationship directed graph from the child node to the parent node, and determining the variable type of the parent node of the second node according to the second node with the determined variable type.

6. The method according to claim 1, characterized in that, Based on the scope recognition rule, recognizing the scopes of the variables corresponding to the branch microstructure and the linear microstructure, including: Constructing declared variables and self-declared variables for each node; the declared variables are the variables declared before the node, and the self-declared variables are the variables that need to be declared in the node; Based on the first scope recognition rule corresponding to the branch microstructure, determining the self-declared variables corresponding to the branch microstructure nodes and the declared variables of the subgraph leaf nodes in the branch microstructure; Based on the second scope recognition rule corresponding to the linear microstructure, determining the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure; Based on the declared variables and self-declared variables of each node, determining the scopes of all variables.

7. The method according to claim 6, wherein Based on the first scope recognition rule corresponding to the branch microstructure, determining the self-declared variables corresponding to the branch microstructure nodes and the declared variables of the subgraph leaf nodes in the branch microstructure, including: Determining the self-declared variables corresponding to the branch microstructure nodes as the self-declared variables of the subgraph root nodes corresponding to the branch microstructure nodes; Determining the sum of the declared variables and self-declared variables of the subgraph root nodes corresponding to the branch microstructure nodes as the declared variables of the subgraph leaf nodes in the branch microstructure; Based on the second scope recognition rule corresponding to the linear microstructure, determining the self-declared variables corresponding to the linear microstructure nodes and the declared variables of the subgraph leaf nodes in the linear microstructure, including: Determining the sum of the self-declared variables of all nodes in the subgraph corresponding to the linear microstructure node as the self-declared variables corresponding to the linear microstructure node; Determining the sum of the declared variables and self-declared variables of the parent nodes of the leaf nodes in the subgraph corresponding to the linear microstructure node as the declared variables of the subgraph leaf nodes in the linear microstructure.

8. A code generation device, characterized in that, The device includes: An extraction module for obtaining a logical directed graph; A conversion module for converting the logical directed graph into a tree structure; The conversion module is further configured to convert the tree structure into a recursive structure; the recursive structure includes a branch microstructure and a linear microstructure; The conversion module is further configured to convert the branch microstructure and the linear microstructure into a programming language structure; The extraction module is further configured to extract a variable relationship directed graph corresponding to the logical directed graph; the variable relationship directed graph includes variables with determined variable types; An inference module for performing variable type inference based on the variable relationship directed graph to obtain all variable types in the logical directed graph; An identification module, configured to identify the scopes of variables corresponding to the branch microstructures and the linear microstructures based on scope identification rules; A generation module, configured to generate a code file corresponding to the logic directed graph based on the program language structure, the logic directed graph, the variable types, and the scopes of the variables.

9. An electronic device, characterized in that, Comprising: At least one processor; And A memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can execute the method according to any one of claims 1-7.

10. A non-transitory computer-readable storage medium storing computer instructions, characterized in that, The computer instructions are used to cause a computer to execute the method according to any one of claims 1-7.

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