FPGA array adaptive dynamic scheduling method, device and computer-readable storage medium

Abstract

The present invention provides an FPGA array adaptive dynamic scheduling method. The dynamic scheduling device receives a task, allocates an FPGA board according to initial settings, and loads a corresponding code stream file to the FPGA board according to the initial settings. The dynamic scheduling device selects an FPGA board with an idle working state in the FPGA array based on the load status of the FPGA array, and then selects an FPGA board with a resource occupancy rate that matches the task requirements based on the resource occupancy rate of the selected FPGA board. The dynamic scheduling device adjusts the configuration file of the selected FPGA board and generates control information for controlling the selected FPGA board. The dynamic scheduling device downloads a code stream file that implements a specific algorithm function to the FPGA board based on the control information and the location where the code stream file is stored. The present invention also provides an FPGA array adaptive dynamic scheduling device and a computer-readable storage medium.

Description

Technical Field

[0001] The present invention belongs to the field of big data technology, and in particular relates to a method and device for adaptive dynamic scheduling of an FPGA array, and a computer-readable storage medium. Background Art

[0002] FPGAs (field programmable gate arrays) are a highly flexible hardware technology whose logic functions can be customized through programming. With the rapid development of technologies such as the internet, big data, and artificial intelligence, the use of FPGAs in data centers is primarily focused on improving the efficiency of specific types of computing, accelerating data processing tasks, and enhancing network functionality. The types of tasks that data centers need to handle are becoming increasingly diverse, including machine learning, deep learning, video processing, encryption and decryption, and database queries. These tasks require varying amounts of computing resources, and traditional CPUs may not be able to efficiently meet all of these requirements. Due to their high programmability and flexibility, FPGAs can be optimized for specific tasks, providing higher performance and efficiency.

[0003] As data centers grow in volume and workloads, energy consumption has become a significant component of their operating costs. Maintaining high-performance data centers while reducing energy consumption is a crucial consideration as computing demands increase. FPGA arrays offer a higher performance-to-power ratio than traditional CPUs and GPUs when performing specific computing tasks, helping data centers reduce energy consumption and improve energy efficiency.

[0004] In existing technology, data centers allocate and coordinate FPGA array resources based on the latency between the user's host and the FPGA array. When a user requests access to the FPGA array, the FPGA board with the lowest latency to the host in the FPGA resource pool is allocated to the user, thus achieving FPGA array resource allocation. This resource allocation method places an additional burden on users, as users must not only perform their own tasks but also request FPGA tasks. Furthermore, this resource allocation method is limited in its considerations, solely focusing on latency, without taking into account the number of users and tasks, or the status of the boards in the FPGA array. In reality, some FPGA boards in the FPGA array may consistently have high resource utilization, while others may remain idle for extended periods. This not only results in high energy consumption for the FPGA array, but also in relatively low utilization efficiency.

[0005] Therefore, it is necessary to optimize the existing FPGA resource allocation method so that the call of the FPGA array matches the user's needs, which can not only reduce energy consumption but also improve the utilization efficiency of the FPGA array. Summary of the Invention

[0006] The present invention provides a method and device for adaptive dynamic scheduling of an FPGA array, which can efficiently schedule the FPGA array while reducing the energy consumption of the FPGA array.

[0007] The present invention also provides a computer-readable storage medium for implementing an FPGA array adaptive dynamic scheduling method.

[0008] Other purposes and advantages of the present invention can be further understood from the technical features disclosed in the present invention.

[0009] To achieve one, part, or all of the above-mentioned objectives or other objectives, a technical solution of the present invention provides an FPGA array adaptive dynamic scheduling method, wherein a task sent by a data center to the FPGA array is received by a dynamic scheduling device, which allocates an FPGA board according to initial settings and loads a corresponding bitstream file to the FPGA board according to the initial settings; the dynamic scheduling device selects an FPGA board in the FPGA array with an idle working state based on the load status of the FPGA array, and then selects an FPGA board with a resource occupancy rate that matches the task requirements based on the resource occupancy rate of the selected FPGA board; adjusts the selected FPGA board configuration file and generates control information for controlling the selected FPGA board; searches for the location of the bitstream file corresponding to the task sent by the data center in a bitstream file library; and the dynamic scheduling device downloads the bitstream file that implements a specific algorithm function to the FPGA board based on the control information and the location of the bitstream file.

[0010] After the tasks sent by the data center to the FPGA array are received by the dynamic scheduling device, the tasks with a high degree of matching with the currently available FPGA resources are prioritized, and the prioritized tasks are sent to the corresponding matching FPGA board to execute the tasks. Tasks with a low degree of matching enter the queue sequence and wait for the corresponding resources to be released; if the task waiting time exceeds the set time, command forced instructions are prioritized for scheduling. When there are multiple command forced instructions, they are scheduled in the order in which they are received.

[0011] After receiving the task sent by the data center, the dynamic scheduling device compares the network segment where the task is located and selects an FPGA board with an idle working status in the same network segment; if the resource occupancy rate of the network segment where the task is located reaches a threshold, the dynamic scheduling device selects an FPGA board with an idle working status in the network segment with the lowest resource occupancy rate among other network segments, and assigns the scheduling right of the selected FPGA board to the network segment where the task is located.

[0012] A load monitoring list is created in the dynamic scheduling device, and the load status of the FPGA board is recorded in the load monitoring list. The load monitoring list records at least the number, status, implemented functions, resource size and resource occupancy rate of each FPGA board; after the dynamic scheduling device receives the task sent by the data center, it searches for the FPGA board in the load monitoring list whose working status is idle.

[0013] If there is already an FPGA board card executing the input task in the load monitoring list, confirm the resource occupancy rate of the FPGA board card executing the task, and select an FPGA board card with a number of resources that matches the task requirements within the same network segment of the task based on the size of the resource occupancy rate.

[0014] If the resource occupancy rate of the FPGA board card that is executing the task is high, then other idle FPGA boards with a higher number of resources are selected within the network segment; if the resource occupancy rate of the FPGA board card that is executing the task is low, then other idle FPGA boards with a lower number of resources are selected within the network segment.

[0015] The code stream files corresponding to the tasks sent by the data center are managed through a code stream status list, which at least includes the number, location, implemented tasks, and number of FPGA boards that execute the corresponding tasks of each code stream; the location where the code stream files corresponding to the tasks sent by the data center are stored is searched in the code stream status list; when the configuration of any FPGA board is completed, the code stream status list is updated.

[0016] The code stream status list is updated by indexing according to the number corresponding to any code stream, and updating the number of the FPGA boards that execute the task corresponding to the code stream.

[0017] If the dynamic scheduling device does not receive any task within the set time, it determines that the load of the FPGA array is not saturated, searches the board status in the load monitoring list, records the FPGA board number with an idle working status, adjusts the corresponding FPGA board configuration file, starts the sleep program, and after the FPGA board enters sleep, the FPGA board does not accept task assignments; after the FPGA board configuration is completed or enters sleep, it is fed back to the load monitoring list, and the working status of the FPGA board in the load monitoring list is updated.

[0018] When a fault is detected in one of the FPGA boards, the system reloads the code stream and performs a self-test to determine whether the fault is resolved. If the fault is resolved, the FPGA board operates normally; if the fault is not resolved, the code stream is replaced with another task code stream and a functional self-test is performed; if the fault of the FPGA board is not resolved after the code stream replacement test is performed a set number of times, the FPGA board is reported to be faulty.

[0019] The code stream file library is divided into a main code stream area and a local code stream area. The main code stream file is configured in the static area of ​​the FPGA logic, and the static area includes the basic functions of the FPGA operation; the local code stream file is configured in the reconfigurable area of ​​the FPGA logic; when the dynamic scheduling device switches the FPGA board according to the resource occupancy rate of the FPGA, the local code stream is loaded from the code stream file library to the switched FPGA board to update some functions of the FPGA to adapt to the new task processing requirements.

[0020] Another technical solution of the present invention provides an FPGA array adaptive dynamic scheduling device, which includes: a task allocation module that allocates FPGA boards according to initial settings, and a dynamic loading module that loads corresponding code stream files to the allocated FPGA boards according to the initial settings; a load monitoring module that receives tasks sent by the data center and compares the network segment where the tasks are located, selects FPGA boards with idle working status in the same network segment, selects an FPGA board with a resource occupancy rate that matches the task requirements among the FPGA boards based on the resource occupancy rate of the selected FPGA boards, and feeds back the number of the FPGA board; a state control module that adjusts the FPGA board based on the FPGA board number and the configuration requirements of the FPGA board fed back by the load monitoring module. GA board configuration file, and generates the FPGA control information; or when the FPGA array load is not saturated, the corresponding idle FPGA board is dormant; the device update module stores a code stream status list, and the device update module finds the location of the code stream corresponding to the task in the code stream file library through the code stream status list; the dynamic loading module starts the loading process to download the code stream file of the specified algorithm function to the corresponding FPGA board according to the received FPGA board control information and the code stream position corresponding to the task, configures the FPGA board, or starts the dormancy of the corresponding FPGA board; after the FPGA configuration is completed, the task allocation module updates the FPGA board status in the FPGA array and feeds back to the load monitoring module.

[0021] The load monitoring module creates a load monitoring list to monitor the load of the FPGA array, and the load monitoring list records at least the number, status, implemented functions, resource size and resource occupancy rate of each FPGA board; after the load monitoring module selects the FPGA board with an idle working status in the same network segment, it finds that there is already an FPGA board executing the task in the load monitoring list; confirms the resource occupancy rate of the FPGA board; if the resource occupancy rate of the FPGA board executing the task is high, selects other idle FPGA boards with a higher resource count in the network segment; if the resource occupancy rate of the FPGA board executing the task is low, selects other idle FPGA boards with a lower resource count in the network segment.

[0022] Another technical solution of the present invention provides a computer-readable storage medium, in which program code is stored. The program code is called by a processor to execute the FPGA array adaptive dynamic scheduling method for a data center as described above.

[0023] Compared with the prior art, the present invention has the following advantages: the method and apparatus for adaptive dynamic scheduling of FPGA arrays can adaptively schedule boards in an FPGA array resource pool. The method and apparatus can monitor the operating status of FPGA boards within the resource pool and, based on the requirements of the FPGA board's operating status and resource utilization for tasks issued by a resource center, select an FPGA board with a resource utilization rate and number of resources that meet the requirements to perform a specific task. Furthermore, the method and apparatus can also put FPGA boards in the FPGA array that have been idle for a long time into hibernation, reducing the energy consumption of the FPGA array. This allows the method and apparatus for adaptive dynamic scheduling of FPGA arrays to achieve efficient resource scheduling while also reducing the power consumption of the FPGA array.

[0024] In order to make the above and other objects, features and advantages of the present invention more clearly understood, preferred embodiments are given below with reference to the accompanying drawings for detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] In order to more clearly illustrate the technical solutions in the specific embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0026] Figure 1 This is a flow chart of the FPGA array adaptive dynamic scheduling method of the present invention.

[0027] Figure 2This is a diagram of the data center and FPGA array architecture of the FPGA array adaptive dynamic scheduling device of the present invention.

[0028] Figure 3 This is a flow chart of the adaptive updating of FPGA board cards by the FPGA array adaptive dynamic scheduling device of the present invention.

[0029] Figure 4 Schematic diagram of the load monitoring list of the present invention.

[0030] Figure 5 Schematic diagram of the code stream status list of the present invention. DETAILED DESCRIPTION

[0031] The foregoing and other technical aspects, features, and functions of the present invention are clearly presented in the following detailed description of a preferred embodiment with reference to the accompanying drawings. Directional terms such as up, down, left, right, front, and back, used in the following embodiments, are intended solely to refer to the directions in the accompanying drawings. Therefore, the directional terms used are for illustrative purposes only and are not intended to limit the present invention.

[0032] Example 1

[0033] Example 1 A method for adaptive dynamic scheduling of an FPGA array, wherein a task sent by a data center to an FPGA array is received by a dynamic scheduling device, the dynamic scheduling device allocates an FPGA board according to an initial setting, and loads a corresponding code stream file to the FPGA board according to the initial setting; the dynamic scheduling device selects an FPGA board with an idle working state in the FPGA array based on the load status of the FPGA array, and then selects an FPGA board with a resource occupancy rate that matches the task requirement based on the resource occupancy rate of the selected FPGA board; adjusts the configuration file of the selected FPGA board and generates control information for controlling the selected FPGA board; searches for the location of the code stream file corresponding to the task sent by the data center in a code stream file library; the dynamic scheduling device downloads the code stream file that implements a specific algorithm function to the FPGA board based on the control information and the location where the code stream file is stored.

[0034] The following is a detailed description with reference to the accompanying drawings:

[0035] See Figure 2 The cloud data center server array sends tasks to the FPGA array through the data flow channel. Between the cloud data center server array and the FPGA array, a dynamic scheduling device receives the tasks and adaptively selects the FPGA board that meets the requirements according to the requirements of the task on the FPGA board. Figure 1 The FPGA array adaptive dynamic scheduling method of embodiment 1 includes the following steps:

[0036] Step S1: The task sent by the data center to the FPGA array is received and parsed by the dynamic scheduling device. Based on the load status of the FPGA array, the FPGA board card with an idle working status in the same network segment as the sending task is searched from the load monitoring list. Based on the resource occupancy rate and number of resources of the idle board card, the FPGA board card that matches the task requirements is selected and the number of the optional FPGA board card is fed back.

[0037] After receiving tasks from the data center, the dynamic scheduling device first allocates FPGA boards based on the initial settings and loads the corresponding bitstream files onto the FPGA boards. The initial allocation of FPGA boards can be proportional to the predicted number of tasks, proportional to task type, or evenly distributed. After configuring the FPGA according to the initial settings, the dynamic scheduling device dynamically adjusts the FPGA array configuration during subsequent task processing based on the tasks and load.

[0038] A bitstream file is a binary file used to configure an FPGA. It contains configuration information for all programmable resources within the FPGA, including logic unit settings, wiring patterns, and I / O pin configurations. Bitstream files are generated by FPGA design software, which synthesizes and places and routes the user's design (usually in a hardware description language like Verilog or VHDL) to generate the corresponding bitstream file. The bitstream file configures all transistors within the FPGA chip in the form of binary data.

[0039] Step 1 specifically includes the following steps:

[0040] Step S1-1:

[0041] In order to facilitate the management of the load of the FPGA array, a load monitoring list is created. The dynamic scheduling device monitors the load of the FPGA array according to the created load monitoring list and records the load of the FPGA board in the load monitoring list. Figure 4 The load monitoring list shown contains at least the number, status, implemented functions, resource size, and resource usage of each FPGA board. The board number includes a high-order value and a low-order value. The high-order value indicates the network segment where the board is located, and the low-order value indicates the order of the boards within the same network segment. Figure 4Taking the board No. 001002 as an example, the first half "001" represents the network segment, and the second half "002" represents the serial number of the board in the 001 network segment); the board status is divided into three types: working, idle and dormant; the board implementation work mainly includes: large-capacity memory access, high-performance image processing, a large number of floating-point operations, high-speed encryption and decryption engines, a large number of I / O and interfaces; the board resource size is divided into high, medium and low levels; the board resource utilization rate is divided into high, medium and low levels. At the same time, the load monitoring list can also record the power consumption of the board. In Example 1, resource utilization rate ≤30% is low, 30% < resource utilization rate ≤70% is medium, and resource utilization rate >70% is high.

[0042] Step S1-2: After receiving the task sent by the data center, the dynamic scheduling device searches the load monitoring list for an FPGA board with an idle status in the same network segment as the task, and feeds back the FPGA board number.

[0043] If the resource occupancy rate of the network segment where the task is located reaches a threshold value (which can be set according to the specific situation of the FPGA array, for example, set to 80%), the dynamic scheduling device selects an FPGA board with an idle working status in the network segment with the lowest resource occupancy rate among other network segments, and assigns the scheduling right of the selected FPGA board to the network segment where the task is located (that is, the selected FPGA board is removed from the status maintenance table of the original network segment, and updated to the status maintenance table of the network segment where the task is located for use in task scheduling in the network segment where the task is located. This process does not change the ownership of the FPGA board network segment, but only changes the scheduling authority of the FPGA board).

[0044] Step S1-3: If a board already exists in the load monitoring list and is currently executing the currently entered task, the resource utilization of the board currently executing the task must be confirmed. If the resource utilization is high, a board with higher resource utilization is selected from the available boards. If the resource utilization is low, a board with lower resource utilization is selected from the available FPGA boards, and the FPGA board number is fed back. The resources of different FPGA boards determine the performance ceiling of the board. High resource utilization can easily affect board performance. Selecting a board with high FPGA resources can reduce the resource utilization, thereby minimizing the impact on performance. When the resource utilization is low, the board resources have little impact on board performance. Selecting a board with low resources can avoid wasting board resources.

[0045] When tasks sent from the data center to the FPGA array are received by the dynamic scheduling device, they are prioritized for tasks that have a high degree of compatibility with currently available FPGA resources. These prioritized tasks are then sent to the corresponding FPGA board for execution, while less compatible tasks are queued to await resource release. If a task's waiting time exceeds a set time, command-forcing instructions are prioritized. If multiple command-forcing instructions exist, they are dispatched in the order in which they were received. By adjusting task scheduling priorities, the FPGA array's resources can be fully utilized.

[0046] Step S2: According to the fed-back FPGA board card numbers, the configuration files of these FPGA board cards are adjusted, and control information for controlling these FPGA board cards is generated.

[0047] Step S3: Search the data center for the bitstream file storage location corresponding to the task sent, and download the bitstream file to the corresponding FPGA board according to the bitstream file storage location and FPGA board control information, and configure these selected FPGA boards. Specifically, the steps include:

[0048] Step S3-1: Create a stream status list for managing stream files. The stream files are uniformly stored in the stream file library. The created stream status list includes at least the number, position, task to be implemented, and the number of FPGA boards that perform the corresponding task for each stream. The stream status list is shown in Figure 5 Schematic diagram.

[0049] Step S3-2: Search the stream status list for the location where the stream file corresponding to the task sent by the data center is stored;

[0050] Step S3-3: Based on the board control information and the storage location of the code stream file corresponding to the task, the code stream loader is started on the FPGA board with the specified number, and the code stream file of the specified algorithm function is downloaded to the corresponding FPGA board. After the FPGA board is configured, the specific task can be completed based on the downloaded code stream file;

[0051] The code stream file library is divided into a main code stream area and a partial code stream area. The main code stream file is configured in the static area of ​​the FPGA logic resources, which includes the basic functions of the FPGA operation. The partial code stream file is configured in the reconfigurable area of ​​the FPGA logic resources. When the dynamic scheduling device switches the FPGA board based on the FPGA resource utilization rate, it loads the partial code stream from the code stream file library into the switched FPGA board to update some of the FPGA's functions to adapt to the new task processing requirements. By configuring the partial code stream file, the time required to reconfigure the FPGA board resources when processing different tasks can be reduced.

[0052] Step S3-4: Feedback the configured FPGA board information to the code stream status list, index it according to the code stream number, find the number of the FPGA board that executes the corresponding task corresponding to the specific code stream, and update it.

[0053] If a fault is detected in an FPGA board during the FPGA board configuration process, the system reloads the code stream and performs a self-test to determine whether the fault is resolved. If the fault is resolved, the FPGA board operates normally; if the fault is not resolved, the dynamic scheduling device loads other task code streams into the faulty FPGA and performs a functional self-test; if the fault of the FPGA board is not resolved after the code stream replacement test reaches the set number of times, the FPGA board fault is reported, and the code stream status list is dynamically updated during this process.

[0054] Step S4: If the dynamic scheduling device does not receive any task within the set time, it determines that the load of the FPGA array is not saturated, searches the board status in the load monitoring list, records the FPGA board number with an idle working status, adjusts the corresponding FPGA board configuration file, and starts the sleep program of the FPGA board with an idle working status. After the FPGA board enters sleep mode, the FPGA board does not accept task assignments.

[0055] Step S5: For the FPGA boards that have been configured and the FPGA boards that have started the sleep program, the status of these FPGA boards is fed back to the load monitoring list, and the working status of the FPGA boards in the load monitoring list is updated.

[0056] Example 2

[0057] Example 2 provides an FPGA array adaptive dynamic scheduling device, the dynamic scheduling device is used to receive tasks sent by a cloud data center server array, the dynamic scheduling device task allocation module, the task allocation module allocates FPGA boards according to initial settings; the dynamic loading module loads the corresponding code stream file to the allocated FPGA board according to the initial settings; the load monitoring module receives the task sent by the data center and compares the network segment where the task is located, selects the FPGA board with an idle working status in the same network segment, selects the FPGA board with a resource occupancy rate that matches the task requirement among the FPGA boards according to the resource occupancy rate of the selected FPGA board, and feeds back the number of the FPGA board; the state control module receives the FPGA board feedback from the load monitoring module A board card number and the configuration requirements of the FPGA board card are used to adjust the FPGA board card configuration file and generate the FPGA control information; or when the FPGA array load is not saturated, the corresponding idle FPGA board card is put into hibernation; the device update module stores a code stream status list, and the device update module finds the location of the code stream corresponding to the task in the code stream file library through the code stream status list; the dynamic loading module starts the loading process according to the received FPGA board card control information and the code stream location corresponding to the task, configures the FPGA board card, or starts the hibernation of the corresponding FPGA board card; after the FPGA configuration is completed, the task allocation module updates the FPGA board card status in the FPGA array and feeds back to the load monitoring module.

[0058] The load monitoring module creates a load monitoring list to monitor the load of the FPGA array, wherein the load monitoring list records at least the number, status, implemented functions, resource size, and resource occupancy rate of each FPGA board; after the load monitoring module selects the FPGA board with an idle working status in the same network segment, it finds that there is already an FPGA board executing the task in the load monitoring list; the resource occupancy rate of the FPGA board is confirmed; if the resource occupancy rate of the FPGA board executing the task is high, other idle FPGA boards with a higher resource count are selected in the network segment; if the resource occupancy rate of the FPGA board executing the task is low, other idle FPGA boards with a lower resource count are selected in the network segment.

[0059] The second embodiment provides an FPGA array adaptive dynamic scheduling device, which is used to execute the steps of the FPGA array adaptive dynamic scheduling method in the first embodiment.

[0060] Example 3

[0061] Example 3 provides a computer-readable storage medium, in which program code is stored. The program code is called by a processor to execute the FPGA array adaptive dynamic scheduling method for a data center in Example 1.

[0062] The above describes in detail the FPGA array adaptive dynamic scheduling method, apparatus, and computer-readable storage medium provided by the present invention. Specific examples are used herein to illustrate the structure and operating principles of the present invention. The description of the above embodiments is intended only to facilitate understanding of the method and core concepts of the present invention. It should be noted that those skilled in the art may make various improvements and modifications to the present invention without departing from the principles of the present invention, and such improvements and modifications fall within the scope of protection of the claims.

Claims

1. A method for adaptive dynamic scheduling of FPGA arrays, characterized in that: The tasks sent by the data center to the FPGA array are received by the dynamic scheduling device, which allocates FPGA boards according to the initial settings and loads the corresponding bitstream files to the FPGA boards according to the initial settings; The dynamic scheduling device selects an FPGA board in the FPGA array whose working state is idle according to the load state of the FPGA array, and then selects an FPGA board whose resource occupancy rate matches the task requirement according to the resource occupancy rate of the selected FPGA board; Adjusting the selected FPGA board configuration file and generating control information for controlling the selected FPGA board; Searching for a location in a stream file library where a stream file corresponding to the task sent by the data center is stored; The dynamic scheduling device downloads the code stream file that implements the specific algorithm function to the FPGA board according to the control information and the location where the code stream file is stored; After the tasks sent by the data center to the FPGA array are received by the dynamic scheduling device, the tasks with a high degree of matching with the currently available FPGA resources are prioritized and sent to the corresponding matching FPGA board for execution. Tasks with a low degree of matching enter the queue sequence and wait for the corresponding resources to be released. If the task waiting time exceeds the set time, the command forced instruction is prioritized. When there are multiple command forced instructions, they are scheduled in the order in which they are received. After receiving the task sent by the data center, the dynamic scheduling device compares the network segment where the task is located and selects an FPGA board with an idle working status in the same network segment; if the resource occupancy rate of the network segment where the task is located reaches a threshold, the dynamic scheduling device selects an FPGA board with an idle working status in the network segment with the lowest resource occupancy rate among other network segments, and assigns the scheduling right of the selected FPGA board to the network segment where the task is located.

2. The FPGA array adaptive dynamic scheduling method according to claim 1, characterized in that: A load monitoring list is created in the dynamic scheduling device, and the load status of the FPGA board is recorded in the load monitoring list. The load monitoring list records at least the number, status, implemented function, resource size and resource occupancy rate of each FPGA board; After receiving the task sent by the data center, the dynamic scheduling device searches for an FPGA board card in the load monitoring list whose working status is idle.

3. The FPGA array adaptive dynamic scheduling method according to claim 2, characterized in that: If there is already an FPGA board card executing the input task in the load monitoring list, confirm the resource occupancy rate of the FPGA board card executing the task, and select an FPGA board card with a number of resources that matches the task requirements within the same network segment of the task based on the size of the resource occupancy rate.

4. The FPGA array adaptive dynamic scheduling method according to claim 3, characterized in that: If the resource occupancy rate of the FPGA board currently executing the task is high, select another idle FPGA board with a higher resource count within the network segment; If the resource occupancy rate of the FPGA board that is executing the task is low, another idle FPGA board with a lower resource count is selected within the network segment.

5. The FPGA array adaptive dynamic scheduling method according to claim 1, characterized in that: The code stream files corresponding to the tasks sent by the data center are managed through a code stream status list, and the code stream status list includes at least the number, position, implemented task, and number of the FPGA boards executing the corresponding task of each code stream; Searching the stream status list for a location where the stream file corresponding to the task sent by the data center is stored; After any of the FPGA boards are configured, the code stream status list is updated.

6. The FPGA array adaptive dynamic scheduling method according to claim 5, characterized in that: The code stream status list is updated by indexing according to the number corresponding to any code stream, and updating the number of the FPGA boards that execute the task corresponding to the code stream.

7. The FPGA array adaptive dynamic scheduling method according to claim 2, characterized in that: If the dynamic scheduling device does not receive any task within the set time, it determines that the load of the FPGA array is not saturated, searches the board status in the load monitoring list, records the number of the FPGA board card with an idle working status, adjusts the corresponding FPGA board card configuration file, and starts the sleep program. After the FPGA board card enters sleep mode, the FPGA board card does not accept task allocation; After the FPGA board is configured or enters sleep mode, it is fed back to the load monitoring list to update the working status of the FPGA board in the load monitoring list.

8. The FPGA array adaptive dynamic scheduling method according to claim 1, characterized in that: When a fault is detected on one of the FPGA boards, the system reloads the code stream and performs a self-test to determine whether the fault has been resolved. If the fault has been resolved, the FPGA board operates normally. If the fault persists, change to another task code stream and perform a functional self-test; After the code stream replacement test is performed for a set number of times, if the FPGA board card does not resolve the fault, the FPGA board card fault is reported.

9. The FPGA array adaptive dynamic scheduling method according to claim 1, characterized in that: The code stream file library is divided into a main code stream area and a local code stream area. The configuration file of the main code stream area is configured to the static area of ​​the FPGA logic. The static area of ​​the FPGA logic includes the basic functions of the FPGA operation. The configuration file of the local bitstream area is configured to the reconfigurable area of ​​the FPGA logic; When the dynamic scheduling device switches the FPGA board according to the resource occupancy rate of the FPGA, the configuration file of the local code stream area is loaded from the code stream file library to the switched FPGA board to update some functions of the FPGA and adapt to new task processing requirements.

10. An FPGA array adaptive dynamic scheduling device, characterized in that: include: A task allocation module allocates FPGA boards according to initial settings, and a dynamic loading module loads corresponding code stream files to the allocated FPGA boards according to initial settings; The load monitoring module receives tasks sent by the data center and compares the network segment where the tasks are located, selects FPGA boards with an idle working state in the same network segment, selects an FPGA board with a resource occupancy rate that matches the task requirements based on the resource occupancy rate of the selected FPGA boards, and feeds back the FPGA board number; A state control module adjusts the FPGA board configuration file and generates the FPGA control information based on the FPGA board number and the configuration requirements of the FPGA board fed back by the load monitoring module; or puts the corresponding idle FPGA board into hibernation when the FPGA array load is not saturated; The device update module stores a code stream status list, and the device update module finds the location where the code stream corresponding to the task is stored in the code stream file library through the code stream status list; A dynamic loading module, based on the received FPGA board control information and the code stream position corresponding to the task, starts a loading process to download the code stream file of the specified algorithm function to the corresponding FPGA board, configures the FPGA board, or starts the corresponding FPGA board to sleep; After the FPGA configuration is completed, the task allocation module updates the FPGA board status in the FPGA array and feeds back to the load monitoring module.

11. The FPGA array adaptive dynamic scheduling device according to claim 10, characterized in that: The load monitoring module creates a load monitoring list to monitor the load of the FPGA array, wherein the load monitoring list records at least the number, status, implemented functions, resource size, and resource occupancy of each FPGA board; After the load monitoring module selects the FPGA board card in the same network segment and is in an idle working state, it is found that the load monitoring list already has an FPGA board card that performs the task; Confirm the resource occupancy rate of the FPGA board; If the resource occupancy rate of the FPGA board currently executing the task is high, then selecting another idle FPGA board with a higher resource count within the network segment; If the resource occupancy rate of the FPGA board that is executing the task is low, another idle FPGA board with a lower resource count is selected within the network segment.

12. A computer-readable storage medium, characterized in that The computer-readable storage medium stores program code, and the program code is called by a processor to execute the method for adaptive dynamic scheduling of an FPGA array according to any one of claims 1 to 9.

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