Data accelerator, driving device and chip
By optimizing the data interaction between external devices and the processor through the configuration and control modules of the data accelerator, the problems of data link latency and resource consumption are solved, and a low-power always-on state and chip function expansion are achieved.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- BEIJING X RING TECHNOLOGY CO LTD
- Filing Date
- 2024-02-29
- Publication Date
- 2026-07-03
AI Technical Summary
In the existing technology, the connection method of external sensor devices to the high-speed bus inside the chip via the APB bus results in excessively long data links and large delays, which may interrupt the processor, increase chip resource consumption, limit chip function expansion, and increase power consumption by frequently waking up the processor.
Design a data accelerator including a configuration module, a backbone module, and a control module. Generate configuration information based on the functional attributes of external devices. Connect the processor's high-speed bus and external devices through the backbone module. The control module schedules data interaction, maintains a constant online state, reduces the path of the APB bus bridging the high-speed bus, and shortens the data link path.
It enables low-power external devices to always be online, reduces chip resource consumption, shortens data latency, expands chip functionality, reduces processor wake-up times, and improves processor efficiency.
Smart Images
Figure CN120371752B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of chip design and application technology, and in particular to a data accelerator, driving device and chip. Background Technology
[0002] Many handheld devices and IoT (Internet of Things) devices connect to external sensor devices via a low-speed bus (Advanced Peripheral Bus, APB, used to connect low-speed peripherals. APB is used to set up low-power interfaces for peripherals with low bandwidth and those that do not require high-performance buses. APB is a non-pipelined architecture; all signals are only related to the rising edge of the clock, and each transmission takes at least two cycles without wait cycles or response signals). Specifically, the external sensor device is bridged to a high-speed bus inside the chip via the APB bus (high-speed buses include AHB and AXI. AHB stands for Advanced High Performance Bus, used for connections between high-performance modules such as CPUs, DMA, and DSPs. AHB operates on a single clock edge; it is non-tri-state; it supports burst transmission; it supports segmented transmission; it supports multiple master controllers; it can be configured with a 32-bit to 128-bit bus width; and it supports byte, half-word, and word transmissions. AXI stands for Advanced eXtensible Bus). Interface (APB) is an on-chip bus designed for high performance, high bandwidth, and low latency. Its address / control and data phases are separated, supporting unaligned data transmission. In burst transmissions, only the starting address is needed. It also features separate read / write data channels, supports outstanding and out-of-order access, and facilitates timing closure. However, this connection method, where the data link is too long and has significant latency, can interrupt the processor at random points, leading to multiple processor wake-ups and hindering low-power always-on operation. On the other hand, connecting external sensor devices to the high-speed bus and on-chip memory via the APB bus can increase the data interaction architecture, leading to higher chip resource consumption and limiting the chip's functional expansion.
[0003] It should be noted that the above introduction to the technical background is only for the purpose of providing a clear and complete explanation of the technical solutions of this application and facilitating understanding by those skilled in the art. It should not be assumed that these technical solutions are known to those skilled in the art simply because they have been described in the background section of this application. Summary of the Invention
[0004] This application provides a data accelerator, a driving device, and a chip.
[0005] The first aspect of this application provides a data accelerator, comprising:
[0006] The configuration module is used to generate configuration information for deploying the transmission and interrupt handling of external device data based on the functional attributes of the external device and the received processor commands;
[0007] The backbone module is connected between the processor's high-speed bus and external devices, and is used as a medium for data interaction between the processor and external devices based on control signals.
[0008] The control module has its input terminal connected to the output terminal of the configuration module and its output terminal connected to the main module. It generates control signals for scheduling data interaction actions based on configuration information and maintains the constant online state of data interaction between the processor and external devices.
[0009] A second aspect of this application provides a driving device, comprising: the driving device being configured to set executable code, the executable code controlling an operating system to perform data transmission operations with the data accelerator described in the first aspect of this application.
[0010] A third aspect of this application provides a chip comprising: a processor, an external device interface, and the data accelerator described in the first aspect of this application, wherein: the external device interface is connected to a corresponding external device for data transmission; and the data accelerator is connected between the processor's high-speed bus and the external device interface for maintaining a constantly online state for data interaction between the processor and the external device.
[0011] The technical solutions provided by the embodiments of this application bring at least the following beneficial effects:
[0012] Based on the functional attributes of external devices, corresponding configuration information is generated for deployment. A data interaction architecture is set up to normalize low-power external devices and reduce the path of APB bus bridging high-speed bus, shortening the data link path, reducing latency, reducing chip resource consumption, which is conducive to the expansion of chip functions. It eliminates the need to wake up the processor multiple times and realizes the always-on state of low-power external devices.
[0013] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and do not limit this application. Attached Figure Description
[0014] The above and / or additional aspects and advantages of this application will become apparent and readily understood from the following description of the embodiments taken in conjunction with the accompanying drawings, wherein:
[0015] Figure 1A schematic diagram of the structure of the intelligent sensor hub provided in the first example of this application;
[0016] Figure 2 A schematic diagram of the structure of the intelligent sensor hub provided in the second example of this application;
[0017] Figure 3 This is a schematic diagram of the structure of a data accelerator provided in an embodiment of this application;
[0018] Figure 4 This is a schematic diagram of the structure of a chip provided in an embodiment of this application. Detailed Implementation
[0019] Exemplary embodiments will now be described in detail, examples of which are illustrated in the accompanying drawings. When the following description relates to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application. Rather, they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application as detailed in the appended claims.
[0020] The terminology used in the embodiments of this application is for the purpose of describing particular embodiments only and is not intended to limit the embodiments of this application. The singular forms “a” and “the” as used in the embodiments of this application and the appended claims are also intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the term “and / or” as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.
[0021] It should be understood that although the terms first, second, third, etc., may be used to describe various information in the embodiments of this application, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words "if" and "suppose" as used herein can be interpreted as "when," "when," or "in response to a determination."
[0022] Embodiments of this application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein the same or similar reference numerals denote the same or similar elements throughout. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain this application, and should not be construed as limiting this application.
[0023] It should be noted that the data accelerator provided in any embodiment of this application can be executed alone, or can be executed together with possible implementation methods in other embodiments, or can be executed together with any technical solution in related technologies.
[0024] The data accelerator, driving device, and chip of this application are described below with reference to the accompanying drawings.
[0025] Figure 1 A schematic diagram of an intelligent sensor hub is shown. Figure 1As shown, the intelligent sensor hub can be a handheld mobile device or an IoT device. It is based on a low-power MCU (Microcontroller Unit, which integrates a central processing unit with a reduced frequency, memory, counters, peripheral interfaces, and display driver circuits onto a single chip, forming a chip-level computer for different applications such as mobile phones, automotive electronics, stepper motors, and robotic arms) and a lightweight RTOS (Real-time Operating System). A real-time operating system (RTOS) manages system resources in a prioritized manner and provides a consistent foundation for application development. Its most significant characteristic compared to a conventional operating system is its real-time performance. If a task needs to be executed, the ROS will execute it immediately or within a short timeframe, without significant delay. This characteristic ensures the timely execution of all tasks. The ROS is a hardware and software integrated solution built upon this system. Its main function is to connect and process data from various external devices. External devices are matched, read, and fused through the external device kernel, and then bridged to high-speed buses (including AHB, AXI, etc.) and the CPU via the on-chip APB bus. On-chip memory (including static RAM, dynamic RAM, and TCM, TCM stands for Tightly Coupled) is also present. Memories, translated as tightly coupled memory, differ from static RAM and dynamic RAM. TCM is a fixed-size RAM tightly coupled to the processor core, providing performance comparable to cache. Its advantage over cache is that program code can precisely control the location of which functions or code are stored. TCM is never evicted from main memory, thus possessing a user-preset function. The CPU deploys a low-speed bus and drives external devices. If the data volume is relatively small, the data is directly read from the TCM by the CPU; if the data volume is relatively large, the data can be read from the TCM via DMA (Direct Memory Access). DMA transfer copies data from one address space to another, providing high-speed data transfer between peripherals and memory, or between memory locations. When the CPU initiates this transfer, the transfer itself is implemented and completed by the DMA controller. DMA transfer does not require direct CPU control of the transfer, nor does it involve saving and restoring the context like interrupt handling. It opens a direct data transfer channel between RAM and I / O devices through hardware, greatly improving CPU efficiency.When an external device has a task, it needs to wake up the CPU to power it on; when the external device is idle, the CPU enters a sleep or power-off state. Therefore, frequent wake-ups lead to increased power consumption. If more external devices are added, it may result in an increased data interaction architecture, leading to increased chip resource consumption and limiting the expansion of chip functionality. On the one hand... Figure 1 The architecture shown is a purely hardware-based solution, which cannot be configured. The types and number of connected external devices are fixed. Any external device may interrupt the CPU at any time, affecting the data interaction of other external devices.
[0026] Figure 2 A schematic diagram of another type of intelligent sensor hub is shown. For example... Figure 2 As shown, in Figure 1 The demonstrated smart sensor hub adds a collection module to collect data from external devices, stores the collected data in the TCM, and manages related interrupt operations. However, this architecture increases the complexity of the chip, leading to increased chip resource consumption.
[0027] Therefore, this application provides a data accelerator, a driving device, and a chip.
[0028] Figure 3 This is a schematic diagram of the structure of a data accelerator provided in an embodiment of this application. Figure 3 As shown, the data accelerator includes:
[0029] like Figure 3 As shown, the configuration module is used to generate configuration information for deploying the transmission and interrupt handling of external device data based on the functional attributes of the external device and the received processor commands.
[0030] Optionally, as an example, the configuration module includes: a configuration unit, a command parsing unit, and a first generation unit, wherein:
[0031] The configuration unit is used to set the corresponding descriptor according to the functional attributes of the external device. It should be noted that the descriptor is an object attribute of "binding behavior". In the descriptor protocol, it can be accessed through several methods, including get(), set() and delete(). Any one of these methods is defined in an object, and this object is a descriptor.
[0032] The command parsing unit is used to set the corresponding execution strategy according to the priority of the processor commands. Further, the processor commands enter a queue; the command parsing unit parses the queue to obtain the priority of the processor commands in the queue; and sets the corresponding execution strategy according to the priority of the processor commands.
[0033] The first generation unit generates configuration information for the transmission and / or interruption handling of data deployed from external devices based on descriptors and execution policies.
[0034] Furthermore, the configuration module can also be configured using a hardware description language (based on the hardware description language, the interfaces, functional logic, connection relationships, timing, frequency, data throughput, etc. of the configuration unit, command parsing unit, and first generation unit are set, and then the configuration unit, command parsing unit, and first generation unit are transformed into a combination of actual circuits, converted into a gate-level circuit netlist by an automatic synthesis tool, and then converted into a specific circuit routing structure to be implemented using an application-specific integrated circuit or field-programmable gate array automatic placement and routing tool). Alternatively, it can be configured using an IP core (IP core stands for Intellectual Property, which is a general term for integrated circuit cores with intellectual property rights. It is a macro-module (logic or functional unit) of integrated circuit design that has been repeatedly verified, has specific functions, can be reused, and contains specific core elements (instruction set, functional description, code, etc.) that is gradually separated in the chip design process. It can be understood as a partially reusable "chip design module"). As long as the configuration information for the transmission and interrupt handling of external device data can be generated and deployed according to the functional attributes of the external device and the received processor commands, any configuration module setting form is applicable and is not limited to this embodiment.
[0035] like Figure 3 As shown, the data accelerator also includes a backbone module, which is connected between the processor's high-speed bus and external devices, and is used as a medium for data interaction between the processor and external devices based on control signals.
[0036] Optionally, as an example, the backbone module includes a high-speed bus master device and at least one external device core, wherein:
[0037] The external device kernel is used to interact with external devices. If the number of external device kernels exceeds one, the main module also includes a multiplexer. A multiplexer is a multi-input, single-output combinational logic circuit. An n (n>1) input multiplexer is an n-channel digital switch. It can select one output from n inputs to a common output terminal according to different channel selection control signals. It should be noted that the external device kernel includes at least one of the following: SPI device, I2C device, UART device, I2S device, GPIO device, and SDIO device.
[0038] The high-speed bus master device is connected between the processor's high-speed bus and the external device core, serving as a medium for data interaction between the processor and the external device core. Further, the data interaction between the processor and the external device includes: when the processor sends data to the external device, the control module adjusts the backbone module based on configuration information to retrieve data from the processor's tightly coupled memory and transmit the data to the corresponding external device; when the processor receives data from the external device, the control module writes the data into the processor's tightly coupled memory based on configuration information, allowing the processor to perform the next operation.
[0039] Furthermore, the backbone module can also be configured using a hardware description language or an IP core. As long as it can use control signals as a medium for data interaction between the processor and external devices, any configuration of the backbone module is applicable and is not limited to this embodiment.
[0040] like Figure 3 As shown, the data accelerator also includes a control module. The input of the control module is connected to the output of the configuration module, and the output of the control module is connected to the backbone module. The control module generates control signals for scheduling data interaction actions based on configuration information and maintains the constant online state of data interaction between the processor and external devices.
[0041] Optionally, as an example, the control module includes: a detection unit and a second generation unit, wherein:
[0042] The detection unit detects the empty / full status of the FIFO in the external device based on configuration information, or executes a corresponding response based on an interrupt request from the external device. FIFO stands for First In, First Out, meaning data that enters first and exits last is processed last. The FIFO acts as a buffer for the system, caching continuous data streams to prevent data loss during data entry and storage operations; it centralizes data for entry and storage, avoiding frequent bus operations and reducing the CPU load; and it allows the system to perform DMA operations, improving data transfer speed.
[0043] The second generation unit generates the control signal for scheduling data interaction actions based on configuration information, and maintains the constant online state of data interaction between the processor and external devices through the control signal.
[0044] Furthermore, when data is sent to an external device via the data accelerator, the CPU places the data into the TCM (Tracking Management Module). The configuration module parses the commands from the command queue according to priority and maps the parsing results to the control module. The control module then adjusts the backbone module to retrieve data from the TCM and transmit the data to the corresponding external device. It should be noted that if the data volume is relatively large, the data transmission process is completed via DMA (Distributed Data Interchange) and is not adjusted by the control module.
[0045] When the data accelerator receives data sent by an external device, the control module adjusts the FIFO based on its empty / full state, the priority set by the configuration module, and the interrupt requested by the external device. Based on the adjustment process, it selects whether to send an interrupt signal to the processor for the next operation.
[0046] Since interrupts on the low-speed bus are concentrated on the data accelerator, the processor's bus setup can be reduced, saving interrupt resources. When the data accelerator is working, no processor intervention is required, which can expand the processor's functionality and improve the processor's operating efficiency. When the processor interacts with external devices, resource consumption is minimized, and the processor can maintain a constantly online state for data interaction with external devices.
[0047] Furthermore, the control module can also be configured using a hardware description language or an IP core. As long as the control signal can schedule the data interaction actions based on the configuration information and maintain the constant online state of data interaction between the processor and external devices, any configuration of the backbone module is applicable and is not limited to this embodiment.
[0048] Specifically, according to embodiments of this application, the process described in the above-referenced flowchart can be implemented as a driving device. The driving device is used to set executable code, which controls the operating system to perform data transmission operations with the data accelerator described in this embodiment. As an example, the format of the file generated by the executable code includes at least one of the following: CAT file format, INF file format, SYS file format, and DLL file format. The specific process of the data transmission operation will not be elaborated here.
[0049] Based on the functional attributes of external devices, corresponding configuration information is generated for deployment. A data interaction architecture is set up to normalize low-power external devices and reduce the path of APB bus bridging high-speed bus, shortening the data link path, reducing latency, reducing chip resource consumption, which is conducive to the expansion of chip functions. It eliminates the need to wake up the processor multiple times and realizes the always-on state of low-power external devices.
[0050] Figure 4 This is a schematic diagram of a chip structure provided in an embodiment of this application. Figure 4As shown, the chip includes: a processor, an external device interface, and the data accelerator described in this embodiment, wherein:
[0051] The external device interface is connected to the corresponding external device for data transmission;
[0052] The data accelerator is connected between the processor's high-speed bus and the external device interface to maintain the constant online state of data interaction between the processor and the external device.
[0053] It should be noted that the chip can be configured using an application-specific integrated circuit (ASIC, which is a proprietary application chip designed and manufactured for specific user requirements and specific electronic systems, and whose computing power and efficiency can be customized according to the algorithm requirements) or an IP core. The specific configuration process will not be described in detail here.
[0054] This chip can generate corresponding configuration information based on the functional attributes of external devices, set up a data interaction architecture to normalize low-power external devices, reduce the path of APB bus bridging high-speed bus, shorten the data link path, reduce latency, reduce chip resource consumption, facilitate the expansion of chip functions, and achieve the always-on state of low-power external devices without having to wake up the processor multiple times.
[0055] Other embodiments of the invention will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of the invention that follow the general principles of the invention and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this application are indicated by the following claims.
[0056] It should be understood that this application is not limited to the precise structure described above and shown in the accompanying drawings, and various modifications and changes can be made without departing from its scope. The scope of this application is limited only by the appended claims.
Claims
1. A data accelerator, characterized in that, include: The configuration module is used to generate configuration information for deploying the transmission and interrupt handling of external device data based on the functional attributes of the external device and the received processor commands; The backbone module is connected between the processor's high-speed bus and external devices, and is used as a medium for data interaction between the processor and external devices based on control signals. The control module has its input terminal connected to the output terminal of the configuration module and its output terminal connected to the main module. It generates control signals for scheduling data interaction actions based on configuration information and maintains the constant online state of data interaction between the processor and external devices.
2. The data accelerator according to claim 1, characterized in that, The configuration module includes a configuration unit, a command parsing unit, and a first generation unit, wherein: the configuration unit is used to set corresponding descriptors according to the functional attributes of the external device; the command parsing unit is used to set corresponding execution strategies according to the priority of processor commands; and the first generation unit generates configuration information for deploying the transmission and / or interrupt handling of external device data based on the descriptors and execution strategies.
3. The data accelerator according to claim 2, characterized in that, Processor commands enter the queue; the command parsing unit parses the queue to obtain the priority of the processor commands in the queue; based on the priority of the processor commands, the command parsing unit sets the corresponding execution strategy.
4. The data accelerator according to claim 1, characterized in that, The control module includes a detection unit and a second generation unit, wherein: the detection unit detects the empty / full state of the FIFO in the external device based on configuration information, or executes a corresponding response based on the interrupt request of the external device; the second generation unit generates the control signal for scheduling the data interaction actions based on the configuration information, and maintains the constant online state of data interaction between the processor and the external device through the control signal.
5. The data accelerator according to claim 1, characterized in that, The backbone module includes a high-speed bus master device and at least one external device core, wherein: the external device core is used to interact with external devices; the high-speed bus master device is connected between the processor's high-speed bus and the external device core, and serves as a medium for data interaction between the processor and the external device core.
6. The data accelerator according to claim 1 or 5, characterized in that, The processor and external devices interact in the following ways: when the processor sends data to the external device, the control module adjusts the backbone module to obtain data from the processor's tightly coupled memory based on configuration information and transmits the data to the corresponding external device; when the processor receives data from the external device, the control module writes the data into the processor's tightly coupled memory based on configuration information, and the processor performs the next operation.
7. The data accelerator according to claim 5, characterized in that, The external device kernel includes at least one of the following: SPI device, I2C device, UART device, I2S device, GPIO device, and SDIO device.
8. A driving device, characterized in that, The driving device is used to set executable code, which controls the operating system to perform data transmission operations with the data accelerator as described in any one of claims 1-7.
9. The apparatus according to claim 8, characterized in that, The executable code generates a file in any of the following formats: CAT file format, INF file format, SYS file format, or DLL file format.
10. A chip, characterized in that, The chip includes: a processor, an external device interface, and a data accelerator as described in any one of claims 1-7, wherein: the external device interface is connected to a corresponding external device for data transmission; the data accelerator is connected between the processor's high-speed bus and the external device interface to maintain the processor and external device in a constantly online state for data interaction.