Shifting register, driving circuit, driving method, display substrate and display device

Abstract

The invention provides a shift register, a driving circuit, a driving method, a display substrate and a display device, and relates to the technical field of display. The shift register comprises an input circuit which is configured to control the potential of a first node under the control of a first input signal from a first input end and a second input signal from a second input end; the control circuit is configured to control the potential of the second node to be different from the potential of the first node under the control of the potential of the first node, a second input signal and a reset signal from a reset end; and the output circuit is configured to output a scanning signal under the control of the potentials of the first node and the second node.

Description

Technical Field

[0001] The present disclosure relates to the field of display technologies, and in particular, to a shift register, a driving circuit, a driving method, a display substrate, and a display device. Background Art

[0002] A gate driver circuit (Gate on Array, GOA) integrated on an array substrate scans a pixel array of a display panel row by row to provide a gate driving signal. A common GOA circuit uses an inverter module, such as a Darlington inverter. Such an inverter module will cause a direct current path to appear between the high and low levels connected by the GOA circuit, thereby affecting the stability of the GOA circuit. Summary of the Invention

[0003] The present disclosure provides a shift register, a driving circuit, a driving method, a display substrate, and a display device.

[0004] According to a first aspect, the present disclosure provides a shift register, including: an input circuit configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit configured to control the potential of a second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal; and an output circuit configured to output a scan signal under the control of the potentials of the first node and the second node.

[0005] For example, the control circuit is configured to control the potential of the second node under the control of the potential of the first node, the second input signal, and the reset signal from the reset terminal as follows: charge the second node with a first voltage of a first power supply under the control of a first level of the first node, the reset signal, and the second input signal; and pull down the potential of the second node under the control of a second level of the first node.

[0006] For example, the control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor. Among them, the control electrode of the first transistor is electrically connected to the second input terminal, the first electrode of the first transistor is electrically connected to the first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; the control electrode of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to the first power supply, and the second electrode of the second transistor is electrically connected to the control electrode of the third transistor; the first electrode of the third transistor is electrically connected to the first power supply, and the second electrode of the third transistor is electrically connected to the second node; the control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to the second power supply; and the control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to the third power supply.

[0007] For example, the control circuit further includes a first capacitor. Among them, the first end of the first capacitor is electrically connected to the first power supply, and the second end of the first capacitor is electrically connected to the control electrode of the third transistor.

[0008] For example, the control circuit further includes a first capacitor. Among them, the first end of the first capacitor is electrically connected to the control electrode of the third transistor, and the second end of the first capacitor is electrically connected to the third power supply.

[0009] For example, the output circuit includes a shift signal output terminal configured to output a shift signal.

[0010] For example, the output circuit includes a plurality of output terminals configured to output a plurality of scan signals for driving a plurality of rows of sub-pixel units.

[0011] According to a second aspect, the present disclosure provides a driving circuit including a plurality of shift registers provided in the embodiments of the present disclosure connected in cascade.

[0012] For example, the first input terminal of the nth stage shift register is electrically connected to the shift signal output terminal of the (n - 2)th stage shift register, and the second input terminal of the nth stage shift register is electrically connected to the shift signal output terminal of the (n + 2)th stage shift register, where n is a positive integer.

[0013] According to a third aspect, the present disclosure provides a display device including a display panel and a driving circuit provided in the embodiments of the present disclosure. Among them, the display panel includes a plurality of sub-pixel units arranged in an array, and the driving circuit is used to drive the sub-pixel units.

[0014] According to a fourth aspect, the present disclosure provides a driving method, which is applied to the shift register provided in the embodiments of the present disclosure, and includes: controlling the potential of a first node through an input circuit under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; controlling the potential of a second node to be different from the potential of the first node through a control circuit under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal; and outputting a scan signal through an output circuit under the control of the potentials of the first node and the second node.

[0015] According to a fifth aspect, the present disclosure provides a display substrate, including: a shift register; and a compensation circuit configured to compensate an input signal or an output signal of the shift register to obtain a plurality of scan signals to control a relative difference between falling times of the plurality of scan signals.

[0016] For example, the compensation circuit is configured to compensate the input signal of the shift register to obtain a plurality of scan signals as follows: compensating a plurality of clock signals from a plurality of clock terminals to control a relative difference between falling times of the plurality of clock signals, obtaining a plurality of compensated clock signals, so that the shift register outputs a plurality of scan signals based on the plurality of compensated clock signals.

[0017] For example, the compensation circuit includes a plurality of compensation sub-circuits, and the number of the plurality of compensation sub-circuits is the same as the number of the plurality of clock terminals.

[0018] For example, each of the plurality of compensation sub-circuits includes a compensation resistor and a compensation capacitor; wherein, a first end of the compensation resistor is electrically connected to the clock terminal, a second end of the compensation resistor is electrically connected to the shift register; and a first end of the compensation capacitor is electrically connected to the clock terminal, a second end of the compensation capacitor is electrically connected to a fourth power supply.

[0019] For example, the compensation circuit includes: a plurality of clock signal lines configured to compensate a plurality of clock signals to obtain a plurality of compensated clock signals; wherein, the length of one of the plurality of clock signal lines is less than the lengths of the remaining clock signal lines among the plurality of clock signal lines, or the width of one of the plurality of clock signal lines is greater than the widths of the remaining clock signal lines among the plurality of clock signal lines.

[0020] For example, the shift register includes a plurality of driving capacitors, and the number of the plurality of driving capacitors is the same as the number of the plurality of clock terminals; wherein, the capacitance of one of the plurality of driving capacitors is less than the capacitances of the remaining driving capacitors among the plurality of driving capacitors.

[0021] For example, the compensation circuit includes a plurality of output signal lines configured to compensate the output signals of the shift register to obtain a plurality of scan signals. Among them, the length of one output signal line among the plurality of output signal lines is less than the lengths of the remaining output signal lines among the plurality of output signal lines, or the width of one output signal line among the plurality of output signal lines is greater than the widths of the remaining output signal lines among the plurality of output signal lines.

[0022] For example, the shift register includes: an input circuit configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; a control circuit configured to control the potential of a second node under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal; and an output circuit configured to output a scan signal under the control of the potentials of the first node and the second node.

[0023] According to a sixth aspect, the present disclosure also provides a display device including a display substrate provided in an embodiment of the present disclosure.

[0024] According to a seventh aspect, the present disclosure also provides a driving method applied to a display substrate provided in an embodiment of the present disclosure, including: compensating an input signal or an output signal of a shift register through a compensation circuit to obtain a plurality of scan signals, so as to control the relative difference between the falling times of the plurality of scan signals. Description of the Drawings

[0025] Figure 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure;

[0026] Figure 2A is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0027] Figure 2B is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0028] Figure 2C is a schematic structural diagram of a shift register according to another embodiment of the present disclosure;

[0029] Figure 3 is a schematic signal timing diagram of a shift register according to an embodiment of the present disclosure;

[0030] Figure 4A is a schematic diagram of voltage and current in an exemplary shift register;

[0031] Figure 4B is a schematic diagram of voltage and current in a shift register according to an embodiment of the present disclosure;

[0032] Figure 5It is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure;

[0033] Figure 6 It is a schematic structural diagram of a display device according to an embodiment of the present disclosure;

[0034] Figure 7 It is a flowchart of a driving method according to an embodiment of the present disclosure;

[0035] Figure 8 It is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0036] Figure 9 It is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure;

[0037] Figure 10A It is a brightness schematic diagram of an exemplary display panel driven by a pre-compensation shift register;

[0038] Figure 10B It is a brightness schematic diagram of a display panel driven by a post-compensation shift register according to an embodiment of the present disclosure;

[0039] Figure 11A It is a capacitance matching schematic diagram of capacitor C2 according to an embodiment of the present disclosure;

[0040] Figure 11B It is a capacitance matching schematic diagram of capacitors C3 to C6 according to an embodiment of the present disclosure;

[0041] Figure 12A It is a simulation schematic diagram of an output signal before capacitance matching according to an embodiment of the present disclosure;

[0042] Figure 12B It is a simulation schematic diagram of an output signal after capacitance matching according to an embodiment of the present disclosure;

[0043] Figure 13 It is a compensation schematic diagram of a signal line according to an embodiment of the present disclosure;

[0044] Figure 14A It is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure;

[0045] Figure 14B It is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure;

[0046] Figures 15A to 15D For Figure 14A The hierarchical layout of the display substrate shown;

[0047] Figures 16A to 16D For Figure 14B The hierarchical layout of the display substrate shown;

[0048] Figure 17 is a schematic structural diagram of a display device according to another embodiment of the present disclosure; and

[0049] Figure 18 is a flowchart of a driving method according to another embodiment of the present disclosure. Detailed Embodiments

[0050] To make the objectives, technical solutions, and advantages of the embodiments of the present disclosure clearer, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure. Obviously, the described embodiments are only a part rather than all of the embodiments of the present disclosure. All other embodiments obtained by those of ordinary skill in the art based on the described embodiments of the present disclosure without creative efforts shall fall within the scope of protection of the present disclosure. It should be noted that throughout the drawings, the same elements are denoted by the same or similar reference numerals. In the following description, some specific embodiments are for illustrative purposes only and should not be construed as any limitation to the present disclosure, but merely examples of the embodiments of the present disclosure. Conventional structures or configurations will be omitted when they may cause confusion in the understanding of the present disclosure. It should be noted that the shapes and sizes of the components in the figures do not reflect the actual sizes and proportions, but merely illustrate the content of the embodiments of the present disclosure.

[0051] Unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present disclosure should have the ordinary meanings understood by those skilled in the art. The "first", "second", and similar terms used in the embodiments of the present disclosure do not denote any order, quantity, or importance, but are only used to distinguish different components.

[0052] In addition, in the description of the embodiments of the present disclosure, the term "connected" or "connected to" may mean that two components are directly connected, or may mean that two components are connected via one or more other components. In addition, the two components may be connected or coupled in a wired or wireless manner.

[0053] The source and drain of the switching transistor used in the embodiments of the present disclosure are symmetric, so the source and drain can be interchanged. In the embodiments of the present disclosure, according to its function, the control electrode can be referred to as the control electrode, one of the source and drain can be referred to as the first electrode, and the other of the source and drain can be referred to as the second electrode.

[0054] It should be noted that in the description of the embodiments of the present disclosure, the symbol OUTPUT can represent both a scan signal and the output terminal of the scan signal. Similarly, the symbol INPUT can represent both an input signal and the input terminal of the input signal, the symbol VDD can represent both a power supply and the voltage provided by the power supply, and the symbol VGL can represent both a power supply and the voltage provided by the power supply. For example, the power supply VGL can provide a low voltage, such as ground. The power supply VDD can provide a high level. The same applies to the following embodiments, and similar parts will not be described again.

[0055] Figure 1 is a schematic structural diagram of a shift register according to an embodiment of the present disclosure.

[0056] As Figure 1 shown, the shift register 100 includes an input circuit 110, a control circuit 120, and an output circuit 130.

[0057] In the embodiment of the present disclosure, the input circuit 110 is electrically connected to a first input terminal INPUT1 and a second input terminal INPUT2, the control circuit 120 is electrically connected to the second input terminal INPUT2 and a reset terminal RST, and the output circuit 130 is electrically connected to an output terminal OUTPUT.

[0058] The input circuit 110 and the control circuit 120 are electrically connected to a first node Q, the input circuit 110 and the output circuit 130 are electrically connected to the first node Q, and the control circuit 220 and the output circuit 130 are electrically connected to a second node QB.

[0059] In the embodiment of the present disclosure, the input circuit 110 is configured to control the potential of the first node Q under the control of a first input signal INPUT1 from the first input terminal INPUT1 and a second input signal INPUT2 from the second input terminal INPUT2. The control circuit 120 is configured to control the potential of the second node QB to be different from the potential of the first node Q under the control of the potential of the first node Q, the second input signal INPUT2, and a reset signal RST from the reset terminal RST. The output circuit 130 is configured to output a scan signal OUTPUT under the control of the potentials of the first node Q and the second node QB.

[0060] For example, when the first node Q is at a low level, the control circuit 120 controls the second node QB to be at a high level. When the first node Q is at a high level, the control circuit 120 controls the second node QB to be at a low level.

[0061] In the embodiment of the present disclosure, the control circuit 120 may be an inverter of the shift register 100. The control circuit 120 is also electrically connected to power supplies providing high level and low level, respectively, and the potential of the first node Q, the second input signal INPUT2 and the reset signal RST control the on and off of the control circuit 120.

[0062] In the embodiment of the present disclosure, under the control of the first level of the first node Q, the reset signal RST and the second input signal INPUT2, the control circuit 220 charges the second node QB with the first voltage of the first power supply. Under the control of the second level of the first node Q, the control circuit 120 pulls down the level of the second node QB.

[0063] In the embodiment of the present disclosure, the first level is a low level, the second level is a high level, and the first voltage provided by the first power supply is a high level. The control circuit 120 is also electrically connected to the second power supply, and the second voltage provided by the second power supply is a low level.

[0064] When the level of any one of the reset signal RST and the second input signal INPUT2 is high, the first power supply is connected to the second node QB, and the control circuit 220 charges the second node QB through the first voltage of the first power supply, so that the second node QB is high. At this time, under the control of the low level of the first node Q, the second node QB is disconnected from the second power supply. In this case, the second node QB is high, and the second node QB is connected to the first power supply and disconnected from the second power supply.

[0065] When the levels of the reset signal RST and the second input signal INPUT2 are both low, the first power supply is disconnected from the second node QB. Under the high level control of the first node Q, the second power supply is connected to the second node QB, and the control circuit 220 pulls down the level of the second node QB so that the second node QB is low. In this case, the second node QB is low, and the second node QB is connected to the second power supply and disconnected from the first power supply.

[0066] In the embodiment of the present disclosure, under the control of the level of the first node Q, the second input signal INPUT2 and the reset signal RST, a DC path can be avoided between the two power supplies providing high level and low level, thereby avoiding leakage in the shift register 100 and improving the stability of the shift register 100.

[0067] Figure 2A , Figure 2B and Figure 2C is a schematic structural diagram of a shift register according to another embodiment of the present disclosure.

[0068] like Figure 2AAs shown, the shift register 200a includes an input circuit 210a, a control circuit 220a, and an output circuit 230a.

[0069] In an embodiment of the present disclosure, the input circuit 210a includes transistors M1 to M13, transistor M19, transistor M20, transistor M34, and capacitor C1, where transistors M11 and M34 are double-gate transistors. The control circuit 220a includes transistors M14 to M18, and transistors M14 to M18 form an inverter. The output circuit 230a includes transistors M21 to M33 and capacitors C2 to C6. Transistors M1 to M34 are all N-type transistors.

[0070] In an embodiment of the present disclosure, the control electrodes of transistors M1 and M2 are electrically connected to the select control signal terminal OE. The first electrode of transistor M1 is electrically connected to the first input terminal CR(N - 2). The second electrode of transistor M1 is electrically connected to the first electrode of transistor M2. The second electrode of transistor M2 is electrically connected to node H.

[0071] The first electrode of transistor M3 is electrically connected to the first electrode of transistor M2. The second electrode of transistor M3 is electrically connected to the power supply VDD1. The control electrode of transistor M3 is electrically connected to node H. The first end of capacitor C1 is electrically connected to node H, and the second end is electrically connected to the power supply VDD1.

[0072] The first electrode of transistor M4 is electrically connected to the clock terminal CLKA. The control electrode of transistor M4 is electrically connected to node H. The second electrode of transistor M4 is electrically connected to the first electrode of transistor M5. The second electrode of transistor M5 is electrically connected to the first electrode of transistor M6. The second electrode of transistor M6 is electrically connected to the first node q. The control electrodes of transistor M5 and transistor M6 are electrically connected to the clock terminal CLKA.

[0073] The control electrodes of transistors M7 and M8 are electrically connected to the first input terminal CR(N - 2). The first electrode of transistor M7 is electrically connected to the power supply VDD1. The second electrode of transistor M7 is electrically connected to the first electrode of transistor M8. The second electrode of transistor M8 is electrically connected to the first node Q. The control electrodes of M34_1 and M34_2 are electrically connected to the power supply VDD3. The first electrode of transistor M34_1 is electrically connected to the power supply VDD3. The second electrode of transistor M34_1 is electrically connected to the first electrode of transistor M34_2. The second electrode of transistor M34_2 is electrically connected to the first electrode of transistor M8.

[0074] The control electrodes of transistor M9 and transistor M10 are electrically connected to the reset terminal RST. The first electrode of transistor M9 is electrically connected to the first node Q, and the second electrode of transistor M9 is electrically connected to the first electrode of transistor M10 and the first electrode of transistor M6. The second electrode of transistor M10 is electrically connected to the power supply VGL1. The control electrodes of transistor M34_1 and transistor M34_2 are electrically connected to the power supply VDD3. The first electrode of transistor M34_1 is electrically connected to the power supply VDD3, the second electrode of transistor M34_1 is electrically connected to the first electrode of transistor M34_2, and the second electrode of transistor M34_2 is electrically connected to the first electrode of transistor M8.

[0075] The control electrodes of transistor M11_1 and transistor M11_2 are electrically connected to the first node Q. The first electrode of transistor M11_1 is electrically connected to the power supply VDD1, the second electrode of transistor M11_1 is electrically connected to the first electrode of transistor M11_2, and the second electrode of transistor M11_2 is electrically connected to the first electrode of transistor M10.

[0076] The control electrodes of transistor M12 and transistor M13 are electrically connected to the second input terminal CR(N + 2). The first electrode of transistor M12 is electrically connected to the first node Q, the second electrode of transistor M12 is electrically connected to the first electrode of transistor M13, and the second electrode of transistor M13 is electrically connected to the first electrode of transistor M10.

[0077] The control electrodes of transistor M19 and transistor M20 are electrically connected to the second node QB. The first electrode of transistor M19 is electrically connected to the first node Q, the second electrode of transistor M19 is electrically connected to the first electrode of transistor M20, and the second electrode of transistor M20 is electrically connected to the power supply VGL1 of transistor M10.

[0078] In the embodiment of the present disclosure, the control electrode of transistor M14 is electrically connected to the second input terminal CR(N + 2), the first electrode of transistor M14 is electrically connected to the power supply VDD2, and the second electrode of transistor M14 is electrically connected to the control electrode of transistor M16.

[0079] The control electrode of transistor M15 is electrically connected to the reset terminal RST, the first electrode of transistor M15 is electrically connected to the power supply VDD2, and the second electrode of transistor M15 is electrically connected to the control electrode of transistor M16. The first electrode of transistor M16 is electrically connected to the power supply VDD2, and the second electrode of transistor M16 is electrically connected to the second node QB.

[0080] The control electrode of transistor M17 is electrically connected to the first node Q. The first electrode of transistor M17 is electrically connected to the control electrode of transistor M16. The second electrode of transistor M17 is electrically connected to the power supply VGL3. The control electrode of transistor M18 is electrically connected to the first node Q. The first electrode of transistor M18 is electrically connected to the second node QB. The second electrode of transistor M18 is electrically connected to the power supply VGL1.

[0081] In an embodiment of the present disclosure, the output circuit 230a includes a plurality of output terminals configured to output a plurality of scan signals for driving multiple rows of sub-pixel units. For example, the plurality of output terminals include output terminal OUT(N), output terminal OUT(N + 1), output terminal OUT(N + 2), and output terminal OUT(N + 3). The output terminal OUT(N), output terminal OUT(N + 1), output terminal OUT(N + 2), and output terminal OUT(N + 3) can be used to drive four rows of sub-pixels.

[0082] It should be noted that the present disclosure does not limit the number of output terminals.

[0083] The control electrodes of transistors M21, M23, M25, M27, and M29 are electrically connected to the first node Q. The first electrode of transistor M21 is electrically connected to the clock terminal CLKD1. The second electrode of transistor M21 is electrically connected to the shift signal output terminal CR(N), which is configured to output the shift signal CR(N).

[0084] The first electrode of transistor M23 is electrically connected to the clock terminal CLK1. The second electrode of transistor M23 is electrically connected to the output terminal OUT(N). The first electrode of transistor M25 is electrically connected to the clock terminal CLK2. The second electrode of transistor M25 is electrically connected to the output terminal OUT(N + 1). The first electrode of transistor M27 is electrically connected to the clock terminal CLK3. The second electrode of transistor M27 is electrically connected to the output terminal OUT(N + 2). The first electrode of transistor M29 is electrically connected to the clock terminal CLK4. The second electrode of transistor M29 is electrically connected to the output terminal OUT(N + 3).

[0085] The first ends of capacitors C2, C3, C4, C5, and C6 are electrically connected to the first node Q. The second end of capacitor C2 is electrically connected to the shift signal output terminal CR(N). The second end of capacitor C3 is electrically connected to the output terminal OUT(N). The second end of capacitor C4 is electrically connected to the output terminal OUT(N + 1). The second end of capacitor C5 is electrically connected to the output terminal OUT(N + 2). The second end of capacitor C6 is electrically connected to the output terminal OUT(N + 3).

[0086] The control electrodes of transistor M22, transistor M24, transistor M26, transistor M28, and transistor M30 are electrically connected to the second node QB. The second electrodes of transistor M22, transistor M24, transistor M26, transistor M28, and transistor M30 are electrically connected to the power supply VGI2.

[0087] The first pole of transistor M22 is the shift signal output terminal CR(N), and the shift signal output terminal CR(N) is configured to output the shift signal CR(N). The first pole of transistor M24 is electrically connected to the output terminal OUT(N). The first pole of transistor M26 is electrically connected to the output terminal OUT(N + 1). The first pole of transistor M27 is electrically connected to the output terminal OUT(N + 2). The first pole of transistor M30 is electrically connected to the output terminal OUT(N + 3).

[0088] The control electrode of transistor M31 is electrically connected to the clock terminal CLKA. The first pole of transistor M31 is electrically connected to the first pole of transistor M32, the second pole of transistor M32 is electrically connected to the power supply VGL1, and the control electrode of transistor M32 is electrically connected to the node H. The control electrode of transistor M33 is electrically connected to the clock terminal CLKA. The control electrode of transistor M33 is electrically connected to the first input terminal CR(N - 2), the first pole of transistor M33 is electrically connected to the second node QB, and the second pole of transistor M33 is electrically connected to the power supply VGL1.

[0089] As Figure 2B shown, the shift register 200b includes an input circuit 210b, a control circuit 220b, and an output circuit 230b.

[0090] In the embodiment of the present disclosure, the input circuit 210b and the output circuit 230b are respectively similar in structure to the input circuit 210a and the output circuit 230a described above, and will not be described in detail for the sake of brevity.

[0091] In the embodiment of the present disclosure, the control circuit 220b further includes a capacitor C7 on the basis of the control circuit 220a described above. The first end of the capacitor C7 is electrically connected to the power supply VDD2, and the second end of the capacitor C7 is electrically connected to the control electrode of transistor M16.

[0092] As Figure 2C shown, the shift register 200c includes an input circuit 210c, a control circuit 220c, and an output circuit 230c.

[0093] In the embodiment of the present disclosure, the input circuit 210c and the output circuit 230c are respectively similar in structure to the input circuit 210a and the output circuit 230a described above, and will not be described in detail for the sake of brevity.

[0094] In the embodiment of the present disclosure, the control circuit 220c further includes a capacitor C7 on the basis of the control circuit 220a described above.

[0095] In the embodiment of the present disclosure, the first end of the capacitor C7 is electrically connected to the control electrode of the transistor M16, and the second end of the capacitor C7 is electrically connected to the power supply VGL1.

[0096] Figure 3 It is a signal timing diagram of a shift register according to an embodiment of the present disclosure.

[0097] Figure 3 It shows a signal timing diagram corresponding to a frame of display picture. The signal period corresponding to a frame of display picture includes a display period and a blanking period. During the display period of a frame of display picture, the shift register provides a scan driving signal for the scan transistor, and during the blanking period of a frame of display picture, the shift register provides a sense driving signal for the sense transistor.

[0098] As Figure 3 shown, the clock terminals CLK1 to CLK12 are respectively the clock terminals connected to 3 cascaded shift registers, and the clock terminals CLK1 to CLK12 provide clock signals CLK1 to CLK12 for the 3 cascaded shift registers. For example, the shift register can be Figure 2A 、 Figure 2B and Figure 2C the shift register shown, and each shift register includes four output terminals, which are respectively electrically connected to four clock terminals. The clock terminals CLKD1 to CLKD3 are respectively electrically connected to the transistors M21 of the 3 shift registers. The timings of the clock signals CLKD1 to CLKD3 provided by the clock terminals CLKD1 to CLKD3 are the same as the timings of the shift signals CR(N), CR(N + 1) output by the Nth-stage shift register, and CR(N + 2) output by the (N + 2)th-stage shift register, respectively.

[0099] In Figure 2A the shift register 200a shown, the second input signal provided by the second input terminal CR(N + 2) electrically connected to the control electrode of the transistor M14 can be a reset signal of the pixel row corresponding to the output terminal OUT(n). The reset terminal RST electrically connected to the control electrode of the transistor MI 5 can be an overall reset signal for a plurality of cascaded shift registers 200a.

[0100] When the reset signal RST is at a high level, the shift signal CR(N+2) (the second input signal) is at a low level. Under the control of the high level of the reset signal RST, the transistor M15 is turned on. The transistor M14 is cut off by the second input signal CR(N+2). The voltage VDD2 is applied to the control electrode of the transistor M16 through the transistor M15, and the transistor M16 is turned on. The voltage VDD2 charges the second node QB through the transistor M16.

[0101] When the reset signal RST is at a high level, the select control signal OE and the first input signal CR(N-2) are at low levels. The transistors M1, M2, M7, and M8 are cut off. At this time, the potential of the first node Q is at a low level. The transistors M17 and M18 are cut off by the low level of the first node Q.

[0102] When both the reset signal RST and the second input signal CR(N+2) are at low levels, the transistors M14, M15, and M16 are cut off. Since the potential of the first node Q remains at a low level at this time, the transistors M17 and M18 are cut off, and the potential of the second node QB remains at a high level.

[0103] When the reset signal RST is at a low level and the first input signal CR(N-2) is at a high level, the transistors M7 and M8 are turned on. The voltage VDD1 charges the first node Q through the transistors M7 and M8, the potential of the first node Q is at a high level, and the transistors M17 and M18 are turned on. Since both the reset signal RST and the second input signal CR(N+2) are at low levels, the transistors M14, M15, and M16 are cut off. At this time, the potential of the second node QB gradually decreases until the potential of the second node QB is pulled down to a low level.

[0104] When the potential of the first node Q becomes low again, the second input signal CR(N+2) is at a high level, the transistors M14 and M16 are turned on, the transistors M17 and M18 are cut off, and the potential of the second node QB is at a high level.

[0105] In Figure 2B In the shift register 200b shown, when the reset signal RST is at a high level, the second input signal CR(N+2) is at a low level. Under the control of the high level of the reset signal RST, the transistor M15 is turned on. The transistor M14 is cut off by the second input signal CR(N+2). The voltage VDD2 is applied to the control electrode of the transistor M16 through the transistor M15, and the transistor M16 is turned on. The voltage VDD2 charges the capacitor C7 and the second node QB through the transistor M16.

[0106] When the reset signal RST is at a high level, the select control signal OE and the first input signal CR(N - 2) are at low levels. The transistors M1, M2, M7, and M8 are turned off. At this time, the potential of the first node Q is at a low level. The transistors M17 and M18 are turned off by the low level of the first node Q.

[0107] When both the reset signal RST and the second input signal CR(N + 2) are at low levels, the transistors M14, M15, and M16 are turned off. Since the potential of the first node Q remains at a low level at this time, the transistors M17 and M18 are turned off. The capacitor C7 keeps the potential of the second node QB at a high level.

[0108] When the reset signal RST is at a low level and the first input signal CR(N - 2) is at a high level, the transistors M7 and M8 are turned on. The voltage VDD1 charges the first node Q through the transistors M7 and M8, and the potential of the first node Q is at a high level, and the transistors M17 and M18 are turned on. Since both the reset signal RST and the second input signal CR(N + 2) are at low levels, the transistors M14, M15, and M16 are turned off. At this time, the voltage of the capacitor C7 is released through the transistors M17 and M18, and the potential of the second node QB gradually decreases until the potential of the second node QB is pulled down to a low level.

[0109] When the potential of the first node Q becomes low again, the second input signal CR(N + 2) is at a high level, the transistors M14 and M16 are turned on, the transistors M17 and M18 are turned off, and the potential of the second node QB is at a high level.

[0110] Figure 2C The shown shift register 200c is similar to Figure 2B the working principle of the shown shift register 200b, and will not be elaborated for the sake of simplicity.

[0111] In one example, the control electrodes of the transistors M14 and M15 are electrically connected to the power supply VDD2. The first electrode of the transistor M14 is electrically connected to the power supply VDD2. The second electrode of the transistor M14 is electrically connected to the first electrode of the transistor M15. The second electrode of the transistor M15 is electrically connected to the control electrode of the transistor M16. The first electrode of the transistor M16 is electrically connected to the power supply VDD2. The second electrode of the transistor M16 is electrically connected to the second node QB. The control electrodes of the transistors M17 and M18 are electrically connected to the first node Q. The first electrode of the transistor M17 is electrically connected to the control electrode of the transistor M16. The second electrode of the transistor M17 is electrically connected to the power supply VGL3. The first electrode of the transistor M18 is electrically connected to the second node QB. The second electrode of the transistor M18 is electrically connected to the power supply VGL1.

[0112] In the exemplary shift register, the power supply VDD2 provides a high-level voltage. Under the control of the voltage VDD2 from the power supply VDD2, the transistors M14 and M15 are turned on, and the voltage VDD2 is applied to the control electrode of the transistor M16 through the transistors M14 and M15, causing the transistor M16 to turn on. When the input signal CR(N - 2) provided at the input terminal CR(N - 2) is at a high level, the high level is applied to the first node Q. Under the control of the high level at the first node Q, the transistors M17 and M18 are turned on. The voltage VDD2 is applied to the second node QB through the transistor M16, and at this time, the second node QB is connected to the power supply VGL1. Since the power supply VGL1 provides a low-level voltage and the potential of the second node QB is at a high level, a path is formed between the high level and the low level, resulting in a relatively large current. This can cause the transistors in the Darlington inverter circuit to burn out, thereby affecting the stability of the shift register 100.

[0113] Since the transistors M14 and M15 in the exemplary shift register are always in the on state, when the transistor M17 is turned on, a path is formed between the high level and the low level. Based on the problems existing in the exemplary shift register, the shift register provided by the present disclosure controls the on and off of the transistors M14 and M15 based on the second input signal INPUT2 and the reset signal RST, thereby avoiding a direct current path between the two power supplies providing high and low levels, and thus avoiding the occurrence of leakage in the shift register provided by the present disclosure and improving the stability of the shift register.

[0114] Figure 4A is a schematic diagram of voltage and current in an exemplary shift register. Figure 4B is a schematic diagram of voltage and current in the shift register according to an embodiment of the present disclosure.

[0115] Figure 4A in Figure (a) and Figure 4B in Figure (a) shows the voltage change of the second node QB, Figure 4A in Figure (b) and Figure 4B in Figure (b) shows the voltage change of the first node Q. Figure 4A in Figure (c) and Figure 4B in Figure (c) shows the current change at the source of the transistor M17, that is, the current change from the power supply VDD2 to the power supply VGL3. Figure 4A in Figure (d) and Figure 4B in Figure (d) shows the current change at the source of the transistor M18, that is, the current change from the power supply VDD2 to the power supply VGL1.

[0116] Such as Figure 4AAs shown, when the potential of the first node Q is high, the maximum transient current of the current flowing from the power supply VDD2 to the power supply VGL3 is 80 uA, and the maximum transient current of the current flowing from the power supply VDD2 to the power supply VGL1 is 37 uA.

[0117] As Figure 4B shown, when the potential of the first node Q is high, the maximum transient current of the current flowing from the power supply VDD2 to the power supply VGL3 is 50 uA, and the maximum transient current of the current flowing from the power supply VDD2 to the power supply VGL1 is 16 uA. Compared with Figure 4A that Figure 4B shown, the maximum instantaneous current in the shift register is reduced.

[0118] In the shift registers 200a, 200b, and 200c, when the potential of the first node Q is high, there will be no large current for a long time in the shift registers 200a, 200b, and 200c, reducing the risk of the transistors in the shift registers 200a, 200b, and 200c being burned out.

[0119] Figure 5 is a schematic structural diagram of a driving circuit according to an embodiment of the present disclosure.

[0120] As Figure 5 shown, the driving circuit 500 includes N cascaded shift registers, where N is a positive integer greater than 1. The N shift registers include a shift register ST1, a shift register ST2, a shift register ST3,..., and a shift register STN.

[0121] In the embodiment of the present disclosure, the shift register can be any one of the foregoing shift register 100, shift registers 200a, 200b, and 200c. For example, all N shift registers are shift register 200a. For example, all N shift registers are shift register 200b. Details are not described herein again.

[0122] In the embodiment of the present disclosure, in the N cascaded shift registers, the first input terminal INPUT1 of the nth-stage shift register is electrically connected to the shift signal output terminal CR(N - 2) of the (n - 2)th-stage shift register, and the second input terminal INPUT of the nth-stage shift register is electrically connected to the shift signal output terminal CR(N + 2) of the (n + 2)th-stage shift register, where n is a positive integer less than N.

[0123] For example, the first input signal terminal INPUT1 of the third-stage shift register ST3 is electrically connected to the shift signal output terminal CR1 of the first-stage shift register ST1, and the second input signal terminal INPUT2 of the third-stage shift register ST2 is electrically connected to the shift signal output terminal CR5 of the fifth-stage shift register.

[0124] In an embodiment of the present disclosure, the first input signal terminal INPUT1 of the first-stage shift register ST1 is electrically connected to the scan trigger signal terminal STV, and the second input signal terminal INPUT2 of the Nth-stage shift register STN is electrically connected to the anti-static terminal ESD.

[0125] In an embodiment of the present disclosure, the reset terminals RST of the cascaded N shift registers are electrically connected to the reset terminal rst, and the selection control signal terminals OE are electrically connected to the selection control signal terminals oe. The clock terminal CLKD1 is electrically connected to the clock terminal clkd, and the clock terminal CLKA is electrically connected to the clock terminal clka. The clock terminal CLK1 is electrically connected to the clock signal terminal clk1, the clock terminal CLK2 is electrically connected to the clock signal terminal clk2, the clock terminal CLK3 is electrically connected to the clock signal terminal clk3, and the clock terminal CLK4 is electrically connected to the clock signal terminal clk4.

[0126] Figure 6 It is a schematic structural diagram of a display device according to an embodiment of the present disclosure.

[0127] As shown in FIG. 12, the display device 600 may include a display panel 610 and a driving circuit 620.

[0128] In an embodiment of the present disclosure, the driving circuit 610 may be the driving circuit 500 described above, which will not be elaborated herein.

[0129] In an embodiment of the present disclosure, the display panel 610 includes a plurality of sub-pixel units Pixel arranged in an array, and the driving circuit 610 is used to drive the sub-pixel units Pixel.

[0130] It should be noted that the number of sub-pixel units included in the display panel 610 is only for illustrative purposes, and the present disclosure does not limit the number of sub-pixel units.

[0131] Figure 7 It is a flowchart of a driving method according to an embodiment of the present disclosure.

[0132] As Figure 7 shown, the driving method may include operation S710 to operation S730.

[0133] In an embodiment of the present disclosure, the driving method may be applied to the shift register 100, the shift register 200a, the shift register 200b, and the shift register 200c described above.

[0134] In operation S710, under the control of the first input signal from the first input terminal and the second input signal from the second input terminal, the potential of the first node is controlled through the input circuit.

[0135] In operation S720, under the control of the potential of the first node, the second input signal, and the reset signal from the reset terminal, the potential of the second node is controlled by the control circuit.

[0136] In operation S730, under the control of the potentials of the first node and the second node, a scan signal is output through the output circuit.

[0137] In the embodiments of the present disclosure, operations S710 to S730 are similar to the operations performed by the shift registers 200a, 200b, and 200c described above, and will not be elaborated here.

[0138] Figure 8 It is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure.

[0139] As Figure 8 , the display substrate 800 includes a compensation circuit 810 and a shift register 820.

[0140] In the embodiments of the present disclosure, the compensation circuit 810 is configured to compensate the input signal or the output signal of the shift register 810 to obtain a plurality of scan signals, so as to control the relative difference between the falling times of the plurality of scan signals.

[0141] Figure 8 The number of input signals received and output signals output by the shift register 810 shown is only illustrative.

[0142] In the embodiments of the present disclosure, the shift register 820 may include: an input circuit configured to control the potential of the first node under the control of the first input signal from the first input terminal and the second input signal from the second input terminal; a control circuit configured to control the potential of the second node under the control of the potential of the first node, the second input signal, and the reset signal from the reset terminal; and an output circuit configured to output a scan signal under the control of the potentials of the first node and the second node.

[0143] In the embodiments of the present disclosure, the shift register 820 may be the shift register 100, shift register 200a, shift register 200b, and shift register 200c described above. For the sake of brevity, it will not be elaborated here.

[0144] In the embodiments of the present disclosure, by using the compensation circuit 810 to compensate the input signal or the output signal of the shift register 810, the relative difference between the falling times of the plurality of input signals can be controlled, or the relative difference between the falling times of the plurality of output signals can be controlled, thereby reducing the relative difference between the falling times of the plurality of scan signals for driving the pixel circuit.

[0145] In an embodiment of the present disclosure, a compensation circuit 810 compensates an input signal of a shift register 820, and a plurality of scan signals are configured to: compensate a plurality of clock signals from a plurality of clock terminals to control a relative difference between falling times of the plurality of clock signals, so as to obtain a plurality of compensated clock signals, such that the shift register 820 outputs a plurality of scan signals based on the plurality of compensated clock signals.

[0146] For example, in the shift register 200a, transistors M21, M23, M25, M27, and M29 share a first node Q. Capacitors C2, C3, C4, C5, and C6 have a bootstrap function and can enhance the level of the first node Q. However, since the clock signals CLK1, CLK2, CLK3, and CLK4 are sequentially transmitted, the bootstrap degree of the first node Q is different, so the falling times TF of the scan signals OUT(N), OUT(N + 1), OUT(N + 2), and OUT(N + 3) are also different.

[0147] Since the falling times TF of the scan signals OUT(N), OUT(N + 1), OUT(N + 2), and OUT(N + 3) are different, when the sub-pixels in 4 rows of a pixel circuit are respectively written with the same data voltage under the drive of the scan signals OUT(N), OUT(N + 1), OUT(N + 2), and OUT(N + 3), due to the different currents of the scan signals, the brightness of the sub-pixels in different rows will be different. In this case, bright lines and dark lines will appear on the display screen.

[0148] To avoid this phenomenon, the compensation circuit 810 can compensate the clock signals CLK1, CLK2, CLK3, and CLK4 of the clock terminals CLK1, CLK2, CLK3, and CLK4 electrically connected to the shift register 200a to increase the falling times TF of the clock signals CLK1, CLK2, CLK3, and CLK4. Under the drive of the compensated clock signals, the falling times of the 4 scan signals can be increased, thereby reducing the relative difference between the falling times of the 4 scan signals. The relative difference is the ratio of the difference between the falling times of the 4 scan signals to the falling time of any one of the scan signals.

[0149] For example, before compensating the clock signals by using the compensation circuit 810, the falling time of the clock signal CLK1 is 400 ns and the falling time of the clock signal CLK2 is 440 ns. At this time, the difference between the falling time of the clock signal CLK1 and the falling time of the clock signal CLK2 is 40 ns, and the relative difference is 40 / 400 = 10%.

[0150] After compensating the clock signal by the compensation circuit 810, the fall time of the clock signal CLK1 increases to 450 ns and the fall time of the clock signal CLK2 increases to 480 ns. At this time, the difference between the fall time of the clock signal CLK1 and the fall time of the clock signal CLK2 is 30 ns, and the relative difference is 30 / 450 = 6.7%.

[0151] In an embodiment of the present disclosure, the compensation circuit 810 may be integrated on the driving chip together with the shift register 820. The compensation circuit 810 may also be externally connected to the driving chip, and the shift register 820 is integrated on the driving chip.

[0152] In an embodiment of the present disclosure, by compensating the clock signal by the compensation circuit 810, increasing the difference between the fall times of multiple clock signals, the relative difference between the fall times of multiple scan signals can be reduced, thereby reducing the difference between multiple scan signals and improving the luminance difference between different sub-pixel rows in the pixel circuit.

[0153] Figure 9 It is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.

[0154] As Figure 9 , the display substrate 900 includes a compensation circuit 910 and a shift register 920.

[0155] In an embodiment of the present disclosure, when the shift register 920 includes multiple output terminals, the compensation circuit 910 includes multiple compensation sub-circuits, and the number of multiple compensation sub-circuits is the same as the number of multiple clock terminals.

[0156] For example, the shift register 200a described above includes 4 output terminals. Therefore, the compensation circuit 910 is electrically connected to 4 clock terminals, and the compensation circuit 910 includes 4 compensation sub-circuits.

[0157] In an embodiment of the present disclosure, each compensation sub-circuit among multiple compensation sub-circuits includes a compensation resistor and a compensation capacitor. For example, the compensation sub-circuit 911 includes a compensation resistor R1 and a compensation capacitor C1, and the compensation sub-circuit 912 includes a compensation resistor R2 and a compensation capacitor C2.

[0158] In an embodiment of the present disclosure, the first end of the compensation resistor R1 is electrically connected to the clock terminal CLK1, and the second end of the compensation resistor R1 is electrically connected to the shift register 920. The first end of the compensation capacitor C1 is electrically connected to the clock terminal CLK1, and the second end of the compensation capacitor C1 is electrically connected to the power supply VDD.

[0159] The first end of the compensation resistor R2 is electrically connected to the clock terminal CLK2, and the second end of the compensation resistor R2 is electrically connected to the shift register 920. The first end of the compensation capacitor C2 is electrically connected to the clock terminal CLK2, and the second end of the compensation capacitor C2 is electrically connected to the power supply VDD.

[0160] The power supplies to which the compensation capacitor C1 and the compensation capacitor C2 are electrically connected may be the same or different.

[0161] In the embodiments of the present disclosure, external compensation is performed on the clock signal through the compensation circuit 910, so that the falling time of all clock signals increases, thereby increasing the falling time of the output scanning signal. The resistance of the compensation resistor and the capacitance of the compensation capacitor in the compensation sub-circuit can be determined by formula (1):

[0162]

[0163] τ represents the difference between the falling times of the scanning signals, in seconds. R is the resistance of the compensation resistor, in ohms. C is the capacitance of the compensation capacitor, in farads. V0 is the initial voltage value of the compensation capacitor, and V1 is the voltage after the compensation capacitor is charged or the voltage after it is discharged. V t is the voltage on the compensation capacitor at time t.

[0164] Through formula (1), when the difference in the falling time of the scanning signal is τ, the values of the resistance of the corresponding compensation resistor and the capacitance of the compensation capacitor can be determined. The resistances of the compensation resistors included in the multiple compensation sub-circuits may be equal or unequal. The capacitances of the compensation capacitors included in the multiple compensation sub-circuits may be equal or unequal.

[0165] In the embodiments of the present disclosure, the compensation resistor and the compensation capacitor can be provided on the printed circuit board, so as to perform external compensation on the clock signal.

[0166] Figure 10A is a schematic diagram of the brightness of an exemplary display panel driven by a shift register before compensation. Figure 10B is a schematic diagram of the brightness of a display panel driven by a shift register after compensation according to the embodiments of the present disclosure. Figure 10A and Figure 10B show the brightness of the sub-pixels in the first row to the twelfth row of the pixel circuit. The solid line shows the brightness of the sub-pixels obtained by actual measurement, and the dotted line shows the brightness of the sub-pixels obtained by simulation. For example, Figure 10A shows the brightness of the display panel driven by the shift register 920 alone. Figure 10B shows the brightness of the display panel driven by the compensation circuit 910 and the shift register 920.

[0167] Figure 10AFigure (a) in Figure 10B Figure (a) in Figure 10A shows the brightness of sub - pixels with 32 gray levels, Figure 10B Figure (b) in Figure 10A and Figure 10B Figure (b) in Figure 10A shows the brightness of sub - pixels with 63 gray levels. Figure 10B Figure (c) in

[0168] and Figure 10A Figure (c) in

[0169] shows the brightness of sub - pixels with 128 gray levels. Figure 10B Figure (d) in Figure 10A Figure 10B shows the brightness of sub - pixels with 255 gray levels.

[0170] Figure 11A Figure 11B

[0171] Figure 11A Figure 11B

[0172] is a schematic diagram of the capacitance matching of capacitor C2 according to an embodiment of the present disclosure.

[0173] In the embodiments of the present disclosure, the number of driving capacitors is the same as the number of clock terminals. By setting the capacitance values of capacitors C2 to C6, the influence of capacitive coupling on the clock signal can be reduced, thereby reducing the difference between the falling times of the scanning signals.

[0174] In the embodiments of the present disclosure, the capacitance of one driving capacitor among multiple driving capacitors is smaller than the capacitance of the remaining driving capacitors among the multiple driving capacitors. For example, referring to Figure 10A , the difference between the falling time of the scanning signal for driving the sub-pixels in the 4th row and the falling times of other scanning signals is relatively large. Therefore, the capacitance of the driving capacitor electrically connected to the output terminal for outputting the scanning signal for driving the sub-pixels in the 4th row is smaller than that of other driving capacitors.

[0175] Figure 11A shows the variation of the falling times of 4 scanning signals when capacitors C3 to C6 are fixed at 0 and only the capacitance of capacitor C2 is changed. When capacitor C2 < 4 pF, the difference between the falling times of the 4 scanning signals decreases as the capacitance of capacitor C2 increases. When capacitance C2 > 4 pF, the difference between the falling times of the 4 scanning signals increases as capacitance C2 increases. When capacitance C2 = 4 pF, the difference between the falling times of the 4 scanning signals is the smallest.

[0176] Figure 11B Figure (a) in the figure shows the variation of the falling times of 4 scanning signals when the capacitance of capacitor C2 is fixed at 4 pF, the capacitance values of capacitors C4, C5, and C6 are fixed at 0, and only the capacitance of C3 is changed. Figure 11B Figure (b) in the figure shows the variation of the falling times of 4 scanning signals when the capacitance of capacitor C2 is fixed at 4 pF, the capacitance values of capacitors C3, C5, and C6 are fixed at 0, and only the capacitance of capacitor C4 is changed. Figure 11B Figure (c) in the figure shows the variation of the falling times of 4 scanning signals when the capacitance of capacitor C2 is fixed at 4 pF, the capacitance values of capacitors C3, C4, and C6 are fixed at 0, and only the capacitance of capacitor C5 is changed. Figure 11B Figure (d) in the figure shows the variation of the falling times of 4 scanning signals when the capacitance of capacitor C2 is fixed at 4 pF, the capacitance values of capacitors C3, C4, and C5 are fixed at 0, and only the capacitance of capacitor C6 is changed.

[0177] In Figure 11BIn Figure (a), when the capacitance C3 < 0.5 pF, the difference between the fall times of the four scan signals decreases as the capacitance of capacitor C3 increases. When the capacitance C3 > 0.5 pF, the difference between the fall times of the four scan signals increases as the capacitance of capacitor C3 increases. When the capacitance C3 = 0.5 pF, the difference in the fall times of the four scan signals is the smallest.

[0178] In Figure 11B Figure (b), when the capacitance C4 < 0.5 pF, the difference between the fall times of the four scan signals decreases as the capacitance of capacitor C3 increases. When the capacitance C4 > 0.5 pF, the difference between the fall times of the four scan signals increases as the capacitance of capacitor C4 increases. When the capacitance C4 = 0.5 pF, the difference in the fall times of the four scan signals is the smallest.

[0179] In Figure 11B Figure (c), when the capacitance C5 < 1 pF, the difference between the fall times of the four scan signals decreases as the capacitance of capacitor C3 increases. When the capacitance C5 > 1 pF, the difference between the fall times of the four scan signals increases as the capacitance of capacitor C5 increases. When the capacitance C5 = 1 pF, the difference in the fall times of the four scan signals is the smallest.

[0180] In Figure 11B Figure (d), when the capacitance C6 > 0 pF, the difference between the fall times of the four scan signals increases as the capacitance of capacitor C6 increases. When the capacitance C6 = 0 pF, the difference in the fall times of the four scan signals is the smallest.

[0181] In the embodiment of the present disclosure, according to the difference in the brightness of the first row to the fourth row of sub-pixels, it can be determined that the difference between the fall times of the scan signals for driving the first row to the fourth row of sub-pixels is small, and the difference between the fall time of the scan signal for driving the fourth row of sub-pixels and the fall times of the scan signals of the sub-pixels in the first three rows is large. Therefore, the capacitances of capacitor C3, capacitor C4, and capacitor C5 can be increased, so that the coupling capabilities of capacitor C3, capacitor C4, and capacitor C5 increase, and correspondingly the fall time TF of the scan signal becomes larger. At the same time, the capacitance of capacitor C6 is reduced, the coupling ability of capacitor C6 is reduced, and correspondingly the fall time TF of the scan signal becomes smaller.

[0182] Therefore, after matching, the capacitance C2 = 4 pF, the capacitance C3 = 0.5 pF, the capacitance C4 = 0.5 pF, the capacitance C5 = 1 pF, and the capacitance C6 = 0 pF. The capacitance sizes after matching are C2 > C5 > C3 = C4 > C6.

[0183] Figure 12AIt is a simulation schematic diagram of the output signal before capacitance matching according to an embodiment of the present disclosure. Figure 12B It is a simulation schematic diagram of the output signal after capacitance matching according to an embodiment of the present disclosure.

[0184] Figure 12A and Figure 12B show the voltage changes of the first node Q, scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) in the shift register. Figure 12A and Figure 12B The red waveform in shows the voltage change of the first node Q, Figure 12A and Figure 12B The dark blue waveform in is the voltage change of the scan signal OUT(1), Figure 12A and Figure 12B The green waveform in is the voltage change of the scan signal OUT(2), Figure 12A and Figure 12B The light blue waveform in is the voltage change of the scan signal OUT(3), Figure 12A and Figure 12B The purple waveform in is the voltage change of the scan signal OUT(4).

[0185] According to the voltage magnitude of the first node Q when the scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) are at high level, determine the bootstrapping degree of the first node Q when each scan signal is output.

[0186] As Figure 12A shown, the bootstrapping degrees of the first node Q corresponding to the scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) are different. The bootstrapping degree of the first node Q corresponding to the scan signal OUT(4) is less than that of the first node Q corresponding to the scan signal OUT(1), scan signal OUT(2), and scan signal OUT(3).

[0187] The falling times of the scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) are also different. The falling times of the scan signal OUT(1), scan signal OUT(2), scan signal OUT(3), and scan signal OUT(4) are 428.53ns, 432.99ns, 439.13ns, and 480.67ns respectively, and the maximum difference ΔTF between the falling times of the 4 scan signals is 480.67 - 428.53 = 52.14ns.

[0188] As Figure 12BAs shown, the difference between the voltages of the first node Q corresponding to the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) decreases, and the difference in the bootstrapping degree of the first node Q corresponding to the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) is small. The falling times of the scan signals OUT(1), OUT(2), OUT(3), and OUT(4) are 427.4 ns, 430.62 ns, 431.29 ns, and 457.19 ns respectively, and the maximum difference ΔTF between the falling times of the four scan signals is 457.19 - 427.4 = 29.79 ns. The difference in the falling time after capacitance matching decreases from 52.14 ns to 22.35 ns, and the difference decreases by 43%.

[0189] In one embodiment, the compensation circuit includes a plurality of output signal lines. The plurality of output signal lines are respectively electrically connected to a plurality of output terminals, and the plurality of output signal lines are configured to compensate the output signals of the shift register to obtain a plurality of scan signals and output the plurality of scan signals.

[0190] In the embodiments of the present disclosure, refer to Figure 10A , the difference between the falling time of the scan signal for driving the sub-pixels in the 4th row and the falling times of other scan signals is large. Therefore, the length of the output signal line for outputting the scan signal for driving the sub-pixels in the 4th row is less than the lengths of the remaining output signal lines among the plurality of output signal lines, and the width of the output signal line for outputting the scan signal for driving the sub-pixels in the 4th row is greater than the widths of the remaining output signal lines among the plurality of output signal lines.

[0191] In the embodiments of the present disclosure, the length and width of the output signal line can be adjusted on the periphery line glass (PLG) area of the glass substrate to achieve RC compensation for the PLG routing before entering the GOA area. Since the output signal lines are usually arranged in sequence from outside to inside, the lengths of the output signal lines are all different. The resistance of the output signal line can be determined by formula (2):

[0192]

[0193] R represents the resistance of the output signal line, L represents the length of the output signal line, S represents the width of the output signal line, and R S is the sheet resistance. The sheet resistances of the output signal lines are the same. When the widths and lengths of the output signal lines are different, the resistances of each output signal line are different.

[0194] The resistance of the output signal line has a greater impact on the AC signal. The resistance of the output signal line will affect the fall time of the scan signal and the signal voltage. When the shift register is electrically connected to multiple output signal lines, since the shift register is relatively sensitive to the fall time of the scan signal, unequal-width wiring design can be performed on multiple output signal lines within the display screen.

[0195] For example, for the output signal lines arranged on the outer side, since the length L of the output signal line is relatively long, the width S of the output signal line is increased, thereby reducing the resistance of the output signal line. For the output signal lines arranged on the inner side, since the length L of the output signal line is relatively short, the width S of the output signal line is reduced, thereby increasing the resistance of the output signal line.

[0196] Through software simulation, the resistance of the output signal line is extracted, and the lengths and widths of all output signal lines are fine-tuned.

[0197] In the embodiment of the present disclosure, the compensation circuit includes multiple clock signal lines. The multiple clock signal lines are respectively electrically connected to multiple clock terminals, and are used to input multiple clock signals into the shift register. The multiple clock signal lines are configured to compensate multiple clock signals to obtain multiple compensated clock signals.

[0198] In the embodiment of the present disclosure, refer to Figure 10A , the difference between the fall time of the scan signal for driving the sub-pixels in the 4th row and the fall times of other scan signals is relatively large. Therefore, the length of the clock signal line electrically connected to the previously described clock terminal CLK4 is less than the lengths of the remaining clock signal lines among the multiple clock signal lines, and the width of the clock signal line electrically connected to the previously described clock terminal CLK4 is greater than the widths of the remaining clock signal lines among the multiple clock signal lines.

[0199] The resistances of the multiple clock signal lines are extracted through software simulation, and the lengths and widths of all multiple clock signal lines are fine-tuned to adjust the resistances of the multiple clock signal lines.

[0200] Figure 13 is a compensation schematic diagram of the signal line according to the embodiment of the present disclosure.

[0201] As Figure 13 shown, Fig. (a) is the original state of the signal line. When it is necessary to increase the resistance of the signal line, the length of the signal line can be increased through the wiring method shown in Fig. (b), thereby increasing the resistance of the signal line. When it is necessary to increase the resistance of the signal line and increase the capacitor at the same time, a metal layer can be added on the upper layer or the lower layer of the signal line, thereby performing capacitance compensation, as shown in Fig. (c).

[0202] In the PLG, RC compensation can be performed on the clock signal on the upper layer of the DC signal (such as power supplies VGL / VDD, etc.). Since the DC signal does not generate transitions and is not easily affected by capacitance to generate noise.

[0203] Figure 14A It is a schematic structural diagram of a display substrate according to an embodiment of the present disclosure. Figure 14B It is a schematic structural diagram of a display substrate according to another embodiment of the present disclosure.

[0204] Figure 14A and Figure 14B shows the layout of transistors M23, M25, M27, M29, output signal lines L1, L2, L3, and L4 in the display substrate.

[0205] Output signal line L1 is electrically connected to transistor M23, output signal line L2 is electrically connected to transistor M25, output signal line L3 is electrically connected to transistor M27, and output signal line L4 is electrically connected to transistor M29.

[0206] As Figure 14A shown, the positions of transistors M23, M25, M27, and M29 are different. Transistors M23 and M29 are close to the output end, and transistors M25 and M27 are far from the output end. To ensure that the resistances of output signal lines L1, L2, L3, and L4 are close, the lengths of output signal lines L2 and L3 can be compensated to make the lengths of output signal lines L1, L2, L3, and L4 equal.

[0207] Output signal lines L2 and L3 can be bent in the blank area of the PLG to increase the lengths of output signal lines L2 and L3 to avoid the influence of high-frequency signals. When the space of the PLG is limited, the wiring can also be carried out on the upper layer of the DC signal line (the signal line connecting the power supply).

[0208] In the shift register, since the falling time of the scan signal OUT(4) is relatively large, the resistance and capacitance to be compensated can be calculated according to formula (1) and the falling time difference, so as to finely adjust output signal line L4 for RC compensation. The compensation method can refer to Figure 13 the wiring method shown.

[0209] The capacitances and resistances for compensating output signal lines L1, L2, L3, and L4 can be different, and the wiring lengths of output signal lines L1, L2, L3, and L4 on the layout can also be different.

[0210] Due to the presence of RC loads on output signal lines L1, L2, L3, and L4, when providing a scan signal for a relatively large display screen, there will also be differences in the scan signals provided for the sub-pixels at the near and far ends.

[0211] For example, the driving circuit composed of shift registers can be distributed on the left and right sides of the pixel array. The sub-pixels located on both sides of each row of sub-pixels in the pixel array are closer to the corresponding shift registers, so the sub-pixels located on both sides are regarded as near-end sub-pixels. The sub-pixels located in the middle of each row of sub-pixels are far from the corresponding shift registers, so the sub-pixels located in the middle are regarded as far-end sub-pixels.

[0212] By Figure 14B changing the resistance of output signal lines L1, L2, L3, and L4 through the wiring method shown, compensation for the near-end and far-end sub-pixels is performed.

[0213] As shown in FIG. 14, by increasing the lengths of output signal lines L1, L2, L3, and L4, the resistance of output signal lines L1, L2, L3, and L4 is increased. After the resistances of output signal lines L1, L2, L3, and L4 are all increased, the relative differences between output signal lines L1, L2, L3, and L4 can be reduced, thereby reducing the differences in the scan signals received by the near-end and far-end sub-pixels.

[0214] For example, capacitance compensation can also be performed through the overlapping area. When there is an overlapping area between the output signal line and the metal layer, an overlapping capacitance can be generated. When a hole is dug in the lower layer of the output signal line, the overlapping capacitance can be reduced.

[0215] Figures 15A to 15D For Figure 14A the hierarchical layout of the display substrate shown.

[0216] Figure 15A shows Figure 14A the shield layer of the display substrate shown, Figure 15B shows Figure 14A the active layer of the display substrate shown, Figure 15C shows Figure 14A the gate insulator (GI) layer of the display substrate shown, Figure 15D shows Figure 14A the gate layer of the display substrate shown.

[0217] Figures 16A to 16D ForFigure 14B The hierarchical layout of the display substrate shown.

[0218] Figure 16A Shows Figure 14B The shield layer of the display substrate shown. Figure 16B Shows Figure 14B The active layer of the display substrate shown. Figure 16C Shows Figure 14B The gate insulator (GI) layer of the display substrate shown. Figure 16D Shows Figure 14B The gate layer of the display substrate shown.

[0219] Figure 17 It is a schematic diagram of the structure of a display device according to another embodiment of the present disclosure.

[0220] As Figure 17 shown, the display device 1700 includes a display substrate 1710.

[0221] In the embodiments of the present disclosure, the display substrate 1710 may be the display substrate 800 or the display substrate 900 described above. For the sake of simplicity, it will not be elaborated here.

[0222] Figure 18 It is a flowchart of a driving method according to another embodiment of the present disclosure.

[0223] As Figure 18 shown, the driving method may include operation S1810.

[0224] In the embodiments of the present disclosure, the driving method may be applied to the display substrates 800 and 900 described above.

[0225] In operation S1810, the input signal or the output signal of the shift register is compensated by a compensation circuit to obtain a plurality of scan signals, so as to control the relative difference between the falling times of the plurality of scan signals.

[0226] In the embodiments of the present disclosure, operation S18710 is similar to the operations performed by the display substrates 800 and 900 described above, and will not be elaborated here.

[0227] The flowcharts and block diagrams in the accompanying drawings illustrate the possible architectures, functions, and operations of systems, methods, and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagram may represent a module, a segment of a program, or a part of code, and the above-mentioned module, segment of a program, or part of code contains one or more executable instructions for implementing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order from that marked in the accompanying drawings. For example, two consecutive blocks shown may actually be executed substantially in parallel, and they may sometimes be executed in the reverse order, depending on the functions involved. It should also be noted that each block in the block diagram or flowchart, as well as combinations of blocks in the block diagram or flowchart, can be implemented by a dedicated hardware-based system that performs the specified functions or operations, or can be implemented by a combination of dedicated hardware and computer instructions.

[0228] Those skilled in the art can understand that the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways, even if such combinations or combinations are not explicitly recited in the present disclosure. In particular, without departing from the spirit and teachings of the present disclosure, the features recited in the various embodiments and / or claims of the present disclosure can be combined and / or combined in various ways. All such combinations and / or combinations fall within the scope of the present disclosure.

[0229] The above describes the embodiments of the present disclosure. However, these embodiments are merely for illustrative purposes and not for limiting the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and all such substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A shift register, comprising: An input circuit configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; A control circuit configured to control the potential of a second node to be different from the potential of the first node under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal; And An output circuit configured to output a scan signal under the control of the potentials of the first node and the second node.

2. The shift register according to claim 1, wherein The control circuit is configured to control the potential of the second node under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal as follows: Charge the second node with a first voltage of a first power supply under the control of a first level of the first node, the reset signal, and the second input signal; And Pull down the potential of the second node under the control of a second level of the first node.

3. The shift register according to claim 1 or 2, wherein The control circuit includes a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; Wherein, the control electrode of the first transistor is electrically connected to the second input terminal, the first electrode of the first transistor is electrically connected to a first power supply, and the second electrode of the first transistor is electrically connected to the control electrode of the third transistor; The control electrode of the second transistor is electrically connected to the reset terminal, the first electrode of the second transistor is electrically connected to a first power supply, and the second electrode of the second transistor is electrically connected to the control electrode of the third transistor; The first electrode of the third transistor is electrically connected to a first power supply, and the second electrode of the third transistor is electrically connected to the second node; The control electrode of the fourth transistor is electrically connected to the first node, the first electrode of the fourth transistor is electrically connected to the control electrode of the third transistor, and the second electrode of the fourth transistor is electrically connected to a second power supply; and The control electrode of the fifth transistor is electrically connected to the first node, the first electrode of the fifth transistor is electrically connected to the second node, and the second electrode of the fifth transistor is electrically connected to a third power supply.

4. The shift register according to claim 3, wherein, The control circuit further includes a first capacitor; Wherein, a first end of the first capacitor is electrically connected to the first power supply, and a second end of the first capacitor is electrically connected to the control electrode of the third transistor.

5. The shift register according to claim 3, wherein, The control circuit further includes a first capacitor; Wherein, a first end of the first capacitor is electrically connected to the control electrode of the third transistor, and a second end of the first capacitor is electrically connected to the third power supply.

6. The shift register according to claim 1, wherein, The output circuit includes: A shift signal output terminal configured to output a shift signal.

7. The shift register according to any one of claims 1-6, wherein, The output circuit includes a plurality of output terminals configured to output a plurality of scan signals for driving a plurality of rows of sub-pixel units.

8. A driving circuit, comprising a plurality of shift registers as claimed in any one of claims 1-7 connected in cascade.

9. The driving circuit according to claim 8, wherein, The first input terminal of the nth - stage shift register is electrically connected to the shift - signal output terminal of the (n - 2)th - stage shift register, and the second input terminal of the nth - stage shift register is electrically connected to the shift - signal output terminal of the (n + 2)th - stage shift register, where n is a positive integer.

10. A display device, comprising: A display panel; And The driving circuit as claimed in claim 8 or 9; Wherein, the display panel includes a plurality of sub - pixel units arranged in an array, and the driving circuit is used to drive the sub - pixel units.

11. A driving method, applied to the shift register as claimed in any one of claims 1 - 7, comprising: Under the control of a first input signal from a first input terminal and a second input signal from a second input terminal, controlling the potential of a first node through an input circuit; Under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal, controlling the potential of a second node to be different from the potential of the first node through a control circuit; And Under the control of the potentials of the first node and the second node, outputting a scan signal through an output circuit.

12. A display substrate, comprising: A shift register; And A compensation circuit configured to compensate an input signal or an output signal of the shift register to obtain a plurality of scan signals, so as to control the relative difference between the falling times of the plurality of scan signals.

13. The display substrate according to claim 12, wherein The compensation circuit compensating the input signal of the shift register to obtain a plurality of scan signals is configured to: compensate a plurality of clock signals from a plurality of clock terminals to control the relative difference between the falling times of the plurality of clock signals, obtain a plurality of compensated clock signals, such that the shift register outputs the plurality of scan signals based on the plurality of compensated clock signals.

14. The display substrate according to claim 13, wherein, The compensation circuit includes a plurality of compensation sub - circuits, and the number of the plurality of compensation sub - circuits is the same as the number of the plurality of clock terminals.

15. The display substrate according to claim 14, wherein Each of the plurality of compensation sub - circuits includes a compensation resistor and a compensation capacitor; Wherein, the first end of the compensation resistor is electrically connected to the clock terminal, and the second end of the compensation resistor is electrically connected to the shift register; and The first end of the compensation capacitor is electrically connected to the clock terminal, and the second end of the compensation capacitor is electrically connected to a fourth power supply.

16. The display substrate according to claim 13, wherein, The compensation circuit includes: A plurality of clock signal lines configured to compensate the plurality of clock signals to obtain a plurality of compensated clock signals; Wherein, the length of one clock signal line among the plurality of clock signal lines is less than the lengths of the remaining clock signal lines among the plurality of clock signal lines, or the width of one clock signal line among the plurality of clock signal lines is greater than the widths of the remaining clock signal lines among the plurality of clock signal lines.

17. The display substrate according to claim 12, wherein, The shift register includes a plurality of driving capacitors, and the number of the plurality of driving capacitors is the same as the number of the plurality of clock terminals; Wherein, the capacitance of one driving capacitor among the plurality of driving capacitors is less than the capacitances of the remaining driving capacitors among the plurality of driving capacitors.

18. The display substrate according to claim 12 or 13, wherein, The compensation circuit includes: A plurality of output signal lines are configured to compensate the output signals of the shift register to obtain the plurality of scan signals; Wherein, the length of one output signal line among the plurality of output signal lines is less than the length of the remaining output signal lines among the plurality of output signal lines, or the width of one output signal line among the plurality of output signal lines is greater than the width of the remaining output signal lines among the plurality of output signal lines.

19. The display substrate according to claim 12, wherein The shift register includes: An input circuit configured to control the potential of a first node under the control of a first input signal from a first input terminal and a second input signal from a second input terminal; A control circuit configured to control the potential of a second node under the control of the potential of the first node, the second input signal, and a reset signal from a reset terminal; and An output circuit configured to output a scan signal under the control of the potentials of the first node and the second node.

20. A display device, comprising: The display substrate according to any one of claims 12-19.

21. A driving method applied to the display substrate according to any one of claims 12-19, comprising: Compensating the input signal or output signal of the shift register through a compensation circuit to obtain a plurality of scan signals, so as to control the relative difference between the falling times of the plurality of scan signals.

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