Shifting register, display panel and display device

Abstract

The invention provides a shift register, a display panel and a display device, relates to the technical field of display, and aims to improve the stability of a signal output by the shift register. The shift register comprises a shift unit for outputting a signal with an effective level being a high level; the shift unit comprises a first output module which writes a signal of a first high-potential line into an output end when a first node is at a high level; the second output module writes the signal of the low-potential line into the output end when the second node is at the high level; the first control module writes a signal into the first node; the second control module is used for writing a signal into the second node; the first control module comprises a first unit and a first transistor; the first unit responds to a signal provided by a first clock end and writes the signal of the input end into a third node; the first transistor is electrically connected between the third node and the first node, the grid electrode of the first transistor is electrically connected with the second high-potential line, and the voltage value of a signal provided by the second high-potential line is smaller than the voltage value of a high level in the signal provided by the input end.

Description

Technical Field

[0001] The present invention relates to the field of display technologies, and in particular, to a shift register, a display panel, and a display device. Background Art

[0002] In a display panel, a shift register is used to provide a driving signal to a pixel circuit, so that the pixel circuit transmits a driving current to a light-emitting element under the action of the driving signal, driving the light-emitting element to emit light. However, there is a problem of node leakage in the current circuit structure of the shift register, which further leads to abnormal output and affects the display. Summary of the Invention

[0003] Embodiments of the present invention provide a shift register, a display panel, and a display device, which are used to improve the stability of the signal output by the shift register.

[0004] In a first aspect, an embodiment of the present invention provides a shift register, including a plurality of cascaded shift units, and the shift unit is used to output a driving signal with an effective level of high level; The shift unit includes: A first output module, configured to write the signal of a first high-potential line to an output terminal when a first node is at a high level; A second output module, configured to write the signal of a low-potential line to the output terminal when a second node is at a high level; A first control module, configured to write a signal to the first node; A second control module, configured to write a signal to the second node; Wherein, the first control module includes a first unit and a first transistor; the first unit writes the signal of an input terminal to a third node in response to the signal provided by a first clock terminal; the first transistor is electrically connected between the third node and the first node, and the gate of the first transistor is electrically connected to a second high-potential line, wherein the second high-potential line provides a second high-potential signal, and the voltage value of the second high-potential signal is less than the voltage value of the high level in the signal provided by the input terminal.

[0005] In a second aspect, based on the same inventive concept, an embodiment of the present invention further provides a display panel, including: A pixel circuit; At least one of the above shift registers, and the shift register is electrically connected to the pixel circuit.

[0006] In a third aspect, based on the same inventive concept, an embodiment of the present invention further provides a display device, including the above display panel.

[0007] The technical solutions provided by the embodiments of the present invention have the following beneficial effects: In an embodiment of the present invention, the gate of the first transistor receives a second high potential signal. By making the voltage value of the second high potential signal less than the voltage value of the high level in the signal provided at the input terminal, after the first output module outputs a high level, the first transistor can be in a fully off state, preventing the occurrence of off-state leakage current problems, and thus effectively preventing the first node from leaking electricity, improving the stability of the signal output by the shift unit.

[0008] In another aspect, after the first output module outputs a high level, the gate-source voltage of the first transistor is negative, further increasing the difference between the gate-source voltage and the threshold voltage of the first transistor. Even if the threshold voltage of the first transistor fluctuates due to reasons such as process accuracy or environmental factors, resulting in a slightly smaller actual value, it can still ensure that the first transistor is in a fully off state. By adopting the technical solution provided in the embodiment of the present invention, the process fluctuation range allowed for the threshold voltage of the transistors in the shift unit can also be increased, greatly improving the feasibility of mass production of the circuit. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the following drawings are some embodiments of the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0010] Figure 1 It is a schematic structural diagram of a shift register in the related art; Figure 2 It is a timing diagram in the related art; Figure 3 It is a schematic structural diagram of the shift register provided by the embodiment of the present invention; Figure 4 It is a schematic circuit structural diagram of a shift unit provided by the embodiment of the present invention; Figure 5 For Figure 4 A corresponding timing diagram; Figure 6 It is another schematic circuit structural diagram of the shift unit provided by the embodiment of the present invention; Figure 7 It is still another schematic circuit structural diagram of the shift unit provided by the embodiment of the present invention; Figure 8 For Figure 7 A corresponding timing diagram; Figure 9 It is yet another schematic circuit structural diagram of the shift unit provided by the embodiment of the present invention; Figure 10Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 11 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 12 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 13 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 14 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 15 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 16 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 17 Another schematic diagram of the circuit structure of the shift unit provided by the embodiment of the present invention; Figure 18 A schematic diagram of the structure of the display panel provided by the embodiment of the present invention; Figure 19 A schematic diagram of the circuit structure of the pixel circuit provided by the embodiment of the present invention; Figure 20 Another schematic diagram of the structure of the display panel provided by the embodiment of the present invention; Figure 21 A schematic diagram of the structure of the display device provided by the embodiment of the present invention. Detailed implementation manners

[0011] For a better understanding of the technical solutions of the present invention, the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0012] It should be clear that the described embodiments are only a part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without any creative work fall within the scope of protection of the present invention.

[0013] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the" and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise.

[0014] It should be understood that the term "and / or" used herein is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B can represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in this text generally represents an "or" relationship between the associated objects before and after.

[0015] The present invention relates to a shift register, which includes a plurality of cascaded shift units. The shift unit is used to output a driving signal with an effective level of high level. A certain N-type transistor in the pixel circuit is turned on under the action of the high level of the driving signal, so that the pixel circuit performs corresponding operations.

[0016] Before elaborating on the technical solutions provided by the embodiments of the present invention, the present invention first explains the problems existing in the shift register in the related art.

[0017] As Figure 1 and Figure 2 shown, Figure 1 FIG. is a schematic structural diagram of a shift register in the related art. Figure 2 FIG. is a timing diagram in the related art. The shift register includes a plurality of cascaded shift units 01'. The shift unit 01' includes a transistor T1', a transistor T2', and a transistor T3'.

[0018] Among them, the transistor T1' is electrically connected between the input terminal In' and the node N1'. The transistor T2' is electrically connected between the node N1' and the node N2', and its gate is electrically connected to the high potential line VGH'. The transistor T3' is electrically connected between the high potential line VGH' and the output terminal Out', and its gate is electrically connected to the node N2'.

[0019] During the process of controlling the output terminal Out' to output a high level, the transistor T1' is controlled to be turned on, and the high level provided by the input terminal In' is written into the node N1'. The high level of the node N1' is written into the node N2' through the turned-on transistor T2', and then the transistor T3' is turned on under the action of the high level of the node N2', and the high level of the high potential line VGH' is written into the output terminal Out'.

[0020] In general, in two adjacent shift units 01', the signal input at the input terminal In' of the latter shift unit 01' is the same as the signal output at the output terminal Out' of the former shift unit 01'. For example, the input terminal In' of the latter shift unit 01' is directly electrically connected to the output terminal Out' of the former shift unit 01'. Further, it can be understood that the voltage value of the high level provided at the input terminal In' of the latter shift unit 01' is equal to the voltage value of the high level output at the output terminal Out' of the former shift unit 01', and this voltage value is equal to the voltage v0' provided by the high potential line VGH'.

[0021] Furthermore, in combination with the process of the output terminal Out' outputting a high level, when the output terminal Out' outputs a high level, the potential of the node N1' is the high-level voltage v0' provided by the input terminal In', and the potential of the node N2' is greater than or equal to the high-level voltage v0' provided by the input terminal In'. For example, when a capacitor c' is connected between the node N2' and the output terminal Out', when the signal output by the output terminal Out' changes from low to high, the capacitor c' will couple and pull up the potential of the node N2' to v1', where v1' is greater than v0'. Since the potential received by the gate of the transistor T2' is v0', the gate-source voltage of the transistor T2' is 0.

[0022] In this way, when the threshold voltage of the transistor T2' is small, the transistor T2' is prone to off-state leakage current, and a leakage path will be formed from the node N2', the node N1' to the input terminal In', resulting in leakage of the node N2', and further resulting in abnormal output of the output terminal Out'. In other words, this circuit structure allows a very small process fluctuation range for the transistor threshold voltage, leading to an increase in process difficulty and a decrease in mass production feasibility.

[0023] In view of this, an embodiment of the present invention provides a shift register. Based on the circuit design of the shift unit in the shift register, the above-mentioned leakage problem can be effectively improved.

[0024] As Figure 3 shown Figure 3 FIG. is a schematic structural diagram of a shift register provided by an embodiment of the present invention. The shift register includes a plurality of cascaded shift units 1, and the shift unit 1 is used to output a drive signal with an effective level of high level.

[0025] The shift unit 1 has an input terminal In, a first clock terminal ck1, and an output terminal Out. Among them, the input terminal In of the first-stage shift unit 1 is electrically connected to the start signal line STV. In two adjacent stages of shift units 1, the signal input to the input terminal In of the subsequent-stage shift unit 1 is the same as the signal output from the output terminal Out of the previous-stage shift unit 1. Exemplarily, the input terminal In of the subsequent-stage shift unit 1 can be directly electrically connected to the output terminal Out of the previous-stage shift unit 1. And, in two adjacent stages of shift units 1, the first clock terminal ck1 of one of the shift units 1 is electrically connected to the first clock signal line CK, and the first clock terminal ck1 of the other shift unit 1 is electrically connected to the second clock signal line XCK.

[0026] As Figure 4 and Figure 5 shown, Figure 4 FIG. is a schematic circuit diagram of the shift unit 1 provided by an embodiment of the present invention, Figure 5 is Figure 4 a corresponding timing diagram. The shift unit 1 includes a first output module 2, a second output module 3, a first control module 4, and a second control module 5.

[0027] The first output module 2 is configured to write the signal of the first high potential line VGH1 to the output terminal Out when the first node N1 is at a high level; the second output module 3 is configured to write the signal of the low potential line VGL to the output terminal Out when the second node N2 is at a high level.

[0028] The first control module 4 is configured to write a signal to the first node N1; the second control module 5 is configured to write a signal to the second node N2.

[0029] Among them, the first control module 4 includes a first unit 6 and a first transistor T1. The first unit 6 writes the signal of the input terminal In to the third node N3 in response to the signal provided by the first clock terminal ck1. The first transistor T1 is electrically connected between the third node N3 and the first node N1. The first transistor T1 can be an N-type transistor, and the gate of the first transistor T1 is electrically connected to the second high potential line VGH2. Among them, the second high potential line VGH2 provides a second high potential signal, and the voltage value of the second high potential signal is less than the voltage value of the high level in the signal provided by the input terminal In.

[0030] The first high potential line VGH1 provides a first high potential signal. Combining the foregoing analysis, it can be seen that the voltage value of the high level in the signal provided by the input terminal In is equal to the voltage value of the first high potential signal. Furthermore, the voltage value of the second high potential signal is also less than the voltage value of the first high potential signal. The voltage value of the low level in the signal provided by the input terminal In is equal to the voltage value of the signal of the low potential line VGL.

[0031] In the embodiment of the present invention, the voltage value of the second highest potential signal is v1, and the voltage value of the high level in the signal provided by the input terminal In is v2.

[0032] During the process of the output terminal Out outputting a high level, the first unit 6 writes the high level provided by the input terminal In into the third node N3 in response to the signal provided by the first clock terminal ck1. The high level of the third node N3 is further written into the first node N1 through the turned-on first transistor T1, so that the first output module 2 outputs a high level to the output terminal Out in response to the high level of the first node N1.

[0033] During this process, after the third node N3 is written with a high level, its voltage becomes v2, and after the first node N1 is written with a high level, its voltage becomes greater than or equal to v2. For example, see Figure 2 , when there is a third capacitor c3 connected between the first node N1 and the output terminal Out, and the signal output by the output terminal Out changes from low to high, the third capacitor c3 will couple and pull up the potential of the first node N1 to v3, and v3 is greater than v2. It can be seen that after the first output module 2 starts to output a high level, the potentials of both poles of the first transistor T1 are v2 and v3 respectively, and both v2 and v3 are greater than its gate potential v1, so that the gate-source voltage of the first transistor T1 is negative, much smaller than its threshold voltage, and the first transistor T1 is in a fully turned-off state, which can effectively prevent the first node N1 from leaking electricity on the path where the first transistor T1 is located, and the potential of the first node N1 is more stable. Correspondingly, the first output module 2 can stably output a high level.

[0034] In summary, in the embodiment of the present invention, the gate of the first transistor T1 receives the second highest potential signal. By making the voltage value of the second highest potential signal less than the voltage value of the high level in the signal provided by the input terminal In, after the first output module 2 outputs a high level, the first transistor T1 can be in a fully turned-off state, preventing the occurrence of off-state leakage current problems, and further effectively preventing the first node N1 from leaking electricity, and improving the stability of the signal output by the shift unit 1.

[0035] From another perspective, after the first output module 2 outputs a high level, the gate-source voltage of the first transistor T1 is negative, further increasing the difference between the gate-source voltage and the threshold voltage of the first transistor T1. Even if the threshold voltage of the first transistor T1 fluctuates due to process accuracy or environmental factors, etc., resulting in its actual value being slightly smaller, it can still ensure that the first transistor T1 is in a fully turned-off state. By adopting the technical solution provided by the embodiment of the present invention, the process fluctuation range allowed by the threshold voltage of the transistors in the shift unit 1 can also be increased, greatly improving the feasibility of mass production of the circuit.

[0036] Next, in combination with Figure 4 and Figure 5, the working process of the shift unit 1 will be described.

[0037] In the first time period t1, the input terminal In provides a high level, the first clock terminal ck1 provides a high level, the first unit 6 responds to the high level of the first clock terminal ck1 and turns on, writes the high level of the input terminal In to the third node N3, and the high level of the third node N3 is written to the first node N1 via the conducting first transistor T1. The first output module 2 responds to the high level of the first node N1 and outputs a high level to the output terminal Out. At the same time, the second control module 5 writes a low level to the second node N2. During this time period, after the output terminal Out outputs a high level, the first transistor T1 is in a completely off state.

[0038] In the second time period t2, the input terminal In continuously provides a high level, the third node N3 and the first node N1 maintain a high level, and the output terminal Out continuously outputs a high level. During this time period, the first transistor T1 is still in an off state.

[0039] In the third time period t3, the input terminal In provides a low level, the first clock terminal ck1 provides a low level, the first unit 6 turns off, the third node N3 and the first node N1 maintain a high level, and the output terminal Out continuously outputs a high level. During this time period, the first transistor T1 is still in an off state.

[0040] In the fourth time period t4, the input terminal In provides a low level, the first clock terminal ck1 provides a high level, the first unit 6 turns on, writes the low level provided by the input terminal In to the third node N3. At this time, the gate-source voltage of the first transistor T1 becomes greater than its threshold voltage, the first transistor T1 conducts, writes the low level of the third node N3 to the first node N1, and the first output module 2 turns off. During this time period, the second control module 5 writes a high level to the second node N2, and the second output module 3 responds to the high level of the second node N2 and outputs a low level to the output terminal Out.

[0041] In a feasible implementation, 1V ≤ v2 - v1 ≤ 3V.

[0042] Under the condition that v2 is constant, the voltage difference between v2 and v1 satisfies less than or equal to 3V, which can avoid the situation that v2 is too low, and further prevent the first transistor T1 from not conducting normally. At the same time, the voltage difference between v2 and v1 also satisfies greater than or equal to 1V, which can ensure that the gate-source voltage of the first transistor T1 is sufficiently negative after the first output module 2 starts to output a high level, and further ensure that the gate-source voltage of the first transistor T1 is much less than its threshold voltage, so that the first transistor T1 is turned off more thoroughly.

[0043] In a feasible implementation, as Figure 6 shown, Figure 6Another schematic diagram of the circuit structure of the shift unit 1 provided by the embodiment of the present invention. The shift unit 1 further includes a first capacitor c1. The first end of the first capacitor c1 is electrically connected to the third node N3, and the second end of the first capacitor c1 receives a fixed potential signal.

[0044] The first unit 6 is respectively electrically connected to the first clock terminal ck1 and the third node N3. Connecting the first capacitor c1 at the third node N3 can stabilize the voltage of the third node N3 by using the first capacitor c1, improve the anti-coupling ability of the third node N3, and reduce the influence on the potential of the third node N3 when the voltage of the first clock signal jumps.

[0045] Further, referring to Figure 6 , the second end of the first capacitor c1 can be electrically connected to the low potential line VGL, the first high potential line VGH1 or the second high potential line VGH2. These signal lines are constant voltage lines that the shift unit 1 originally needs to connect. Fixed potential signals are transmitted on the constant voltage lines. Connecting the first capacitor c1 to these signal lines can simplify the structure without adding other constant voltage lines specifically for the first capacitor c1.

[0046] In a feasible implementation manner, referring to Figure 4 again, the first unit 6 includes a second transistor T2, and the second transistor T2 can be an N-type transistor. The second transistor T2 is electrically connected between the input terminal In and the third node N3, and the gate of the second transistor T2 is electrically connected to the first clock terminal ck1.

[0047] When the first clock terminal ck1 provides a high level, the second transistor T2 is turned on, and the signal at the input terminal In is written into the third node N3.

[0048] In a feasible implementation manner, as shown in Figure 7 and Figure 8 , Figure 7 Another schematic diagram of the circuit structure of the shift unit 1 provided by the embodiment of the present invention. Figure 8 For Figure 7 A corresponding timing diagram. The second transistor T2 is electrically connected to the third node N3 through a third transistor T3. The third transistor T3 can be an N-type transistor. The gate of the third transistor T3 is electrically connected to the gate of the second transistor T2. There is a first intermediate node N01 between the second transistor T2 and the third transistor T3.

[0049] The first control module 4 further includes a second unit 7, and the second unit 7 writes a high level to the first intermediate node N01 in response to the first signal.

[0050] The third transistor T3 and the second unit 7 are used to prevent the third node N3 from leaking electricity. For example, comparing Figure 5 and Figure 8, in the third time period t3, the gate of the third transistor T3 receives the low level provided by the first clock terminal ck1. At this time, the second unit 7 can write a high level to the first intermediate node N01 in response to the first signal, thereby making the voltages at both poles of the third transistor T3 much greater than its gate voltage. The gate-source voltage of the third transistor T3 is much smaller than its threshold voltage, and the third transistor T3 is in a fully off state, which can effectively prevent the third node N3 from leaking to the input terminal In on this path and improve the potential stability of the third node N3.

[0051] Further, referring to Figure 7 , Figure 9 and Figure 10 , Figure 9 is another schematic circuit diagram of the shift unit 1 provided by the embodiment of the present invention. Figure 10 is another schematic circuit diagram of the shift unit 1 provided by the embodiment of the present invention. The second unit 7 includes a fourth transistor T4, and the fourth transistor T4 is electrically connected between the first high potential line VGH1 and the third node N3.

[0052] In one structure, referring to Figure 7 and Figure 9 , the fourth transistor T4 is an N-type transistor. Wherein, the gate of the fourth transistor T4 is electrically connected to the third node N3, and at this time the aforementioned first signal is the signal of the third node N3; or, the gate of the fourth transistor T4 is electrically connected to the first node N1, and at this time the aforementioned first signal is the signal of the first node N1; or, the gate of the fourth transistor T4 is electrically connected to the output terminal Out, and at this time the aforementioned first signal is the signal of the output terminal Out.

[0053] Combined with Figure 8 it can be seen that at the same moment, the level states of the signals of the third node N3, the first node N1, and the output terminal Out are the same. When the fourth transistor T4 is an N-type transistor, connecting its gate to any one of the third node N3, the first node N1, and the output terminal Out can control the fourth transistor T4 to conduct in the third time period t3, thereby making the fourth transistor T4 write a high level to the first intermediate node N01.

[0054] In the embodiment of the present invention, referring to Figure 9 , the gate of the fourth transistor T4 can be electrically connected to the third node N3. On the one hand, the fourth transistor T4 is of the same type as transistors such as the first transistor T1, and the transistors in the shift unit 1 can all use N-type transistors, making the process of the circuit simpler. On the other hand, the conduction state of the fourth transistor T4 is directly controlled by the third node N3, and the fourth transistor T4 has a higher correlation with the third node N3, which can enhance the anti-leakage ability of the third node N3 to a greater extent.

[0055] Alternatively, in another structure, refer to Figure 10 where the fourth transistor T4 is a P-type transistor, and the gate of the fourth transistor T4 is electrically connected to the second node N2.

[0056] Combined with Figure 8 it can be seen that at the same moment, the level states of the signals of the second node N2 and the third node N3 are opposite. When the fourth transistor T4 is a P-type transistor and its gate is electrically connected to the second node N2, the fourth transistor T4 can be controlled to conduct in the third time period t3, and then the fourth transistor T4 writes a high level to the first intermediate node N01.

[0057] In addition, in some time periods of the fourth time period t4, the first clock terminal ck1 provides a high level, the input terminal In provides a low level, and the third node N3 is at a low level. With the above two designs of the fourth transistor T4, it will be turned off under the action of its gate voltage, preventing it from writing a high level to the first node N1 through the conducting third transistor T3 and causing an incorrect potential of the first node N1.

[0058] In addition, in at least some time periods of the second time period t2, the input terminal In is at a high level, the first clock terminal ck1 is at a high level, and the high level of the input terminal In is written to the third node N3 through the conducting second transistor T2 and third transistor T3. During this time period, the fourth transistor T4 is also conducting and writes a high level to the third node N3. Among the first high potential line VGH1 and the second high potential line VGH2, in the embodiments of the present invention, it is selected that the fourth transistor T4 is electrically connected to the first high potential line VGH1, so that the voltage of the high level written by the fourth transistor T4 to the third node N3 can be the same as the voltage of the high level of the input terminal In in this part of the time period, and the voltage received by the third node N3 on the two paths is consistent, and the node stability is better.

[0059] In a feasible implementation manner, refer to Figure 4 and Figure 5 where the second control module 5 includes a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, and a second capacitor c2, and the fifth transistor T5, the sixth transistor T6, and the seventh transistor T7 can all be N-type transistors.

[0060] Among them, the fifth transistor T5 is electrically connected between the low potential line VGL and the second node N2, and the gate of the fifth transistor T5 is electrically connected to the third node N3. The sixth transistor T6 is electrically connected between the low potential line VGL and the fourth node N4, and the gate of the sixth transistor T6 is electrically connected to the input terminal In. The seventh transistor T7 is electrically connected between the first clock terminal ck1 and the second node N2, and the gate of the seventh transistor T7 is electrically connected to the fourth node N4. The second capacitor c2 is electrically connected between the first clock terminal ck1 and the fourth node N4.

[0061] During the first time period t1, the third node N3 is at a high level to control the fifth transistor T5 to conduct, and the fifth transistor T5 writes the low level of the low potential line VGL to the first node N1. At the same time, the input terminal In provides a high level to control the sixth transistor T6 to conduct, and the sixth transistor T6 writes the low level of the low potential line VGL to the fourth node N4, so that the seventh transistor T7 is cut off under the action of the low level at the fourth node N4. During the second time period t2 and the third time period t3, the third node N3 maintains a high level, and the fifth transistor T5 continuously writes a low level to the first node N1.

[0062] During the fourth time period t4, the third node N3 is at a low level, and the fifth transistor T5 is cut off. The input terminal In provides a low level, and the sixth transistor T6 is cut off, stopping writing the low level to the fourth node N4. During this time period, when the first clock terminal ck1 is at a high level, under the action of the second capacitor c2, the potential of the fourth node N4 is raised to a high level, controlling the seventh transistor T7 to conduct, and writing the high level of the first clock terminal ck1 to the first node N1, so that the second output module 3 responds to the high level at the first node N1 and outputs a low level to the output terminal Out. When the signal of the first clock terminal ck1 jumps to a low level, the second capacitor c2 couples and pulls down the potential of the fourth node N4 to a low level, the seventh transistor T7 is cut off, the first node N1 maintains a high level, and the output terminal Out continuously outputs a low level.

[0063] In a feasible implementation manner, as Figure 11 shown, Figure 11 is another circuit structure schematic diagram of the shift unit 1 provided by the embodiment of the present invention. The seventh transistor T7 is electrically connected to the second node N2 through the eighth transistor T8. The eighth transistor T8 can be an N-type transistor. The gate of the eighth transistor T8 is connected to the gate of the seventh transistor T7. There is a second intermediate node N02 between the seventh transistor T7 and the eighth transistor T8.

[0064] The second control module 5 further includes a third unit 8, and the third unit 8 writes a high level to the second intermediate node N02 in response to the second signal.

[0065] The eighth transistor T8 and the third unit 8 are used to prevent the second node N2 from leaking electricity. During the time period when the second node N2 is at a high level, the third unit 8 can write a high level to the second intermediate node N02 in response to the second signal, so that the gate-source voltage of the eighth transistor T8 is less than the threshold voltage and the eighth transistor T8 is completely turned off, thereby preventing the second node N2 from leaking electricity to the first clock terminal ck1 on this path, and enabling the second output module 3 to stably output a low level.

[0066] Further, referring to Figure 11 and Figure 12 ,Figure 12 Another schematic diagram of the circuit structure of the shift unit 1 provided by the embodiment of the present invention. The third unit 8 includes a ninth transistor T9, and the ninth transistor T9 is electrically connected between the first high potential line VGH1 and the second intermediate node N02.

[0067] In one structure, referring to Figure 11 , the ninth transistor T9 is an N-type transistor, and the gate of the ninth transistor T9 is electrically connected to the second node N2. At this time, the aforementioned second signal is the signal of the second node N2.

[0068] In this structure, the ninth transistor T9 has the same type as transistors such as the first transistor T1. The transistors in the shift unit 1 can all be N-type transistors, and the process of the circuit is simpler. On the other hand, the conduction state of the ninth transistor T9 is directly controlled by the second node N2, and the correlation between the ninth transistor T9 and the second node N2 is higher, which can enhance the anti-leakage ability of the second node N2 to a greater extent.

[0069] Alternatively, in another structure, referring to Figure 12 , the ninth transistor T9 is a P-type transistor. Among them, the gate of the ninth transistor T9 is electrically connected to the third node N3. At this time, the aforementioned second signal is the signal of the third node N3; or the gate of the ninth transistor T9 is electrically connected to the first node N1. At this time, the aforementioned second signal is the signal of the first node N1; or the gate of the ninth transistor T9 is electrically connected to the output terminal Out. At this time, the aforementioned second signal is the signal of the output terminal Out.

[0070] Combined with Figure 8 It can be seen that at the same moment, the level states of the signals of the third node N3, the first node N1, and the output terminal Out and the signal of the second node N2 are all opposite. When the ninth transistor T9 is a P-type transistor, connecting the gate of the ninth transistor T9 to any one of the third node N3, the first node N1, and the output terminal Out can control the ninth transistor T9 to conduct during the period when the second node N2 is at a high level, and write a high level to the second intermediate node N02 by using the ninth transistor T9.

[0071] In a feasible implementation manner, as Figure 13 shown, Figure 13 Another schematic diagram of the circuit structure of the shift unit 1 provided by the embodiment of the present invention. The fifth transistor T5 is electrically connected to the second node N2 through a tenth transistor T10. The tenth transistor T10 can be an N-type transistor, and the gate of the tenth transistor T10 is electrically connected to the gate of the fifth transistor T5. There is a third intermediate node N03 between the fifth transistor T5 and the tenth transistor T10.

[0072] The second control module 5 further includes a fourth unit 9, and the fourth unit 9 writes a high level to the third intermediate node N03 in response to the third signal.

[0073] The tenth transistor T10 and the fourth unit 9 are used to prevent the second node N2 from leaking electricity. During the period when the second node N2 is at a high level, the fourth unit 9 can be turned on in response to the third signal, write a high level to the third intermediate node N03, make the gate-source voltage of the tenth transistor T10 less than its threshold voltage, and turn off the tenth transistor T10 completely, thereby preventing the second node N2 from leaking electricity to the low potential line VGL on this path, and ensuring that the second output module 3 can stably output a low level.

[0074] Further, referring to Figure 13 and Figure 14 , Figure 14 is another schematic circuit diagram of the shift unit 1 provided by the embodiment of the present invention. The fourth unit 9 includes an eleventh transistor T11. One pole of the eleventh transistor T11 is electrically connected to the first high potential line VGH1 or the second high potential line VGH2, and the other pole of the eleventh transistor T11 is electrically connected to the third intermediate node N03.

[0075] In one structure, referring to Figure 13 , the eleventh transistor T11 is an N-type transistor, and the gate of the eleventh transistor T11 is electrically connected to the second node N2. At this time, the aforementioned third signal is the signal of the second node N2.

[0076] In this structure, the type of the eleventh transistor T11 is the same as that of transistors such as the first transistor T1. The transistors in the shift unit 1 can all be N-type transistors, and the process of the circuit is simpler. On the other hand, the on state of the eleventh transistor T11 is directly controlled by the second node N2, and the correlation between the eleventh transistor T11 and the second node N2 is higher, which can enhance the anti-leakage ability of the second node N2 to a greater extent.

[0077] Or, in another structure, referring to Figure 14 , the eleventh transistor T11 is a P-type transistor. Among them, the gate of the eleventh transistor T11 is electrically connected to the third node N3. At this time, the aforementioned third signal is the signal of the third node N3, or the gate of the eleventh transistor T11 is electrically connected to the first node N1. At this time, the aforementioned third signal is the signal of the first node N1, or the gate of the eleventh transistor T11 is electrically connected. At this time, the aforementioned third signal is the signal of the output terminal Out.

[0078] Combined with Figure 8It can be seen that at the same moment, the level states of the signals of the third node N3, the first node N1, and the output terminal Out with respect to the second node N2 are opposite. When the eleventh transistor T11 is a P-type transistor, if the gate of the eleventh transistor T11 is electrically connected to any one of the third node N3, the first node N1, and the output terminal Out, the eleventh transistor T11 can be controlled to conduct during the period when the second node N2 is at a high level, and the eleventh transistor T11 is used to write a high level to the third intermediate node N03.

[0079] In addition, in the embodiment of the present invention, the eleventh transistor T11 can be electrically connected to the first high-potential line VGH1 or the second high-potential line VGH2.

[0080] According to the foregoing analysis, it can be known that the voltage value of the second high-potential signal provided by the second high-potential line VGH2 is less than the voltage value of the first high-potential signal provided by the first high-potential line VGH1. However, even when the eleventh transistor T11 is connected to the second high-potential line VGH2, a good anti-leakage effect can still be achieved: the gate of the tenth transistor T10 is electrically connected to the third node N3. Refer to Figure 8 , at the same moment, the level states of the signals of the third node N3 and the second node N2 are opposite, that is, when the second node N2 is at a high level, the third node N3 is at a low level, which means that the gate of the tenth transistor T10 is at a low level. At this time, even if the eleventh transistor T11 is electrically connected to the second high-potential line VGH2 and writes a second high-potential signal to the third intermediate node N03, it can still ensure that the tenth transistor T10 is completely turned off, avoiding leakage of the second node N2 on this path.

[0081] In a feasible embodiment, as Figure 15 and Figure 16 shown, Figure 15 is another circuit structure diagram of the shift unit 1 provided by the embodiment of the present invention. Figure 16 is another circuit structure diagram of the shift unit 1 provided by the embodiment of the present invention. The seventh transistor T7 is electrically connected to the second node N2 through the eighth transistor T8. The eighth transistor T8 can be an N-type transistor, and the gate of the eighth transistor T8 is connected to the gate of the seventh transistor T7. There is a second intermediate node N02 between the seventh transistor T7 and the eighth transistor T8.

[0082] The fifth transistor T5 is electrically connected to the second node N2 through the tenth transistor T10. The tenth transistor T10 can be an N-type transistor, and the gate of the tenth transistor T10 is electrically connected to the gate of the fifth transistor T5. There is a third intermediate node N03 between the fifth transistor T5 and the tenth transistor T10.

[0083] The second control module 5 further includes a fifth unit 10, and the fifth unit 10 writes a high level to the second intermediate node N02 and the third intermediate node N03 in response to the fourth signal.

[0084] During the period when the second node N2 is at a high level, the fifth unit 10 can write a high level to the second intermediate node N02 and the third intermediate node N03 in response to the fourth signal, thereby completely turning off the eighth transistor T8 and the tenth transistor T10, avoiding the leakage of the second node N2 to the first clock terminal ck1 on the path where the eighth transistor T8 is located, and avoiding the leakage of the second node N2 to the low potential line VGL on the path where the tenth transistor T10 is located. The second node N2 is more stable, and the output terminal Out stably outputs a low level.

[0085] Further, referring to Figure 15 and Figure 16 , the fifth unit 10 includes a twelfth transistor T12. One pole of the twelfth transistor T12 is electrically connected to the first high potential line VGH1, and the other pole of the twelfth transistor T12 is electrically connected to the second intermediate node N02 and the third intermediate node N03.

[0086] In one structure, referring to Figure 15 , the twelfth transistor T12 is an N-type transistor, and the gate of the twelfth transistor T12 is electrically connected to the second node N2. At this time, the aforementioned fourth signal is the signal of the second node N2.

[0087] In this structure, the twelfth transistor T12 is of the same type as transistors such as the first transistor T1. The transistors in the shift unit 1 can all be N-type transistors, and the process of the circuit is simpler. On the other hand, the conduction state of the twelfth transistor T12 is directly controlled by the second node N2, and the twelfth transistor T12 has a higher correlation with the second node N2, which can enhance the anti-leakage ability of the second node N2 to a greater extent.

[0088] Alternatively, in another structure, referring to Figure 16 , the twelfth transistor T12 is a P-type transistor. Among them, the gate of the twelfth transistor T12 is electrically connected to the third node N3. At this time, the aforementioned second signal is the signal of the third node N3; or, the gate of the twelfth transistor T12 is electrically connected to the first node N1. At this time, the aforementioned second signal is the signal of the first node N1; or, the gate of the twelfth transistor T12 is electrically connected to the output terminal Out. At this time, the aforementioned second signal is the signal of the output terminal Out.

[0089] Combined with Figure 8It can be seen that at the same moment, the signal level states of the third node N3, the first node N1, and the output terminal Out are all opposite to that of the second node N2. When the twelfth transistor T12 is a P-type transistor, connecting the gate of the twelfth transistor T12 to any one of the third node N3, the first node N1, and the output terminal Out can control the twelfth transistor T12 to conduct during the period when the second node N2 is at a high level, and use the ninth transistor T9 to write a high level to the second intermediate node N02 and the third intermediate node N03.

[0090] In addition, the above structure only uses the twelfth transistor T12 to write a high level to the second intermediate node N02 and the third intermediate node N03 at the same time, and the circuit structure is simpler.

[0091] In a feasible implementation manner, as Figure 17 shown, Figure 17 FIG. 10 is another schematic circuit diagram of the shift unit 1 provided by the embodiment of the present invention. The sixth transistor T6 is electrically connected to the fourth node N4 through the thirteenth transistor T13. The thirteenth transistor T13 can be an N-type transistor. The gate of the thirteenth transistor T13 is electrically connected to the gate of the sixth transistor T6. There is a fourth intermediate node N04 between the sixth transistor T6 and the thirteenth transistor T13.

[0092] The second control module 5 further includes a sixth unit 11. The sixth unit 11 writes a high level to the fourth intermediate node N04 in response to the fifth signal.

[0093] The thirteenth transistor T13 and the sixth unit 11 are used to prevent the second node N2 from leaking electricity. During the period when the fourth node N4 is at a high level, the sixth unit 11 can write a high level to the fourth intermediate node N04 in response to the fifth signal, so that the gate-source voltage of the sixth unit 11 is less than its threshold voltage, and the sixth unit 11 is completely turned off, which can effectively prevent the fourth node N4 from leaking electricity to the low-potential line VGL on this path and improve the signal stability of the fourth node N4.

[0094] Further, referring back to Figure 17 , the sixth unit 11 includes a fourteenth transistor T14. One pole of the fourteenth transistor T14 is electrically connected to the first high-potential line VGH1 or the second high-potential line VGH2, and the other pole of the fourteenth transistor T14 is electrically connected to the fourth intermediate node N04.

[0095] The fourteenth transistor T14 is an N-type transistor. The gate of the fourteenth transistor T14 is electrically connected to the fourth node N4. At this time, the aforementioned fifth signal is the signal of the fourth node N4.

[0096] In this structure, the fourteenth transistor T14 is of the same type as transistors such as the first transistor T1. The transistors in the shift unit 1 can all be N-type transistors, and the process of the circuit is simpler. On the other hand, the on-state of the fourteenth transistor T14 is directly controlled by the fourth node N4, and the correlation between the fourteenth transistor T14 and the fourth node N4 is higher, which can enhance the anti-leakage ability of the fourth node N4 to a greater extent.

[0097] In addition, the fourteenth transistor T14 can be electrically connected to the first high-potential line VGH1 or the second high-potential line VGH2.

[0098] According to the foregoing analysis, it can be known that the voltage value of the second high-potential signal provided by the second high-potential line VGH2 is less than the voltage value of the first high-potential signal provided by the first high-potential line VGH1. However, even if the fourteenth transistor T14 is connected to the second high-potential line VGH2, a good anti-leakage effect can still be achieved: the gate of the thirteenth transistor T13 is electrically connected to the input terminal In. Refer to Figure 8 , when the fourth node N4 is at a high level, the input terminal In is at a low level, that is, the gate of the thirteenth transistor T13 is at a low level. At this time, even if the fourteenth transistor T14 is electrically connected to the second high-potential line VGH2 and a second high-potential signal is written to the fourth intermediate node N04, it can still be ensured that the thirteenth transistor T13 is completely turned off, avoiding leakage of the fourth node N4 on this path.

[0099] In a feasible implementation manner, refer to Figure 4 and Figure 5 , the first output module 2 includes a fifteenth transistor T15 and a third capacitor c3.

[0100] Among them, the fifteenth transistor T15 can be an N-type transistor. The fifteenth transistor T15 is electrically connected between the first high-potential line VGH1 and the output terminal Out, and the gate of the fifteenth transistor T15 is electrically connected to the first node N1. The fifteenth transistor T15 is turned on when the first node N1 is at a high level, and the high level of the first high-potential line VGH1 is written to the output terminal Out.

[0101] The third capacitor c3 is electrically connected between the first node N1 and the output terminal Out. When the signal at the output terminal Out jumps from a low level to a high level, due to the coupling effect of the third capacitor c3, the potential of the first node N1 is pulled to a higher level, ensuring that the fifteenth transistor T15 is turned on more completely.

[0102] The second output module 3 includes a sixteenth transistor T16 and a fourth capacitor c4.

[0103] Among them, the sixteenth transistor T16 can be an N-type transistor. The sixteenth transistor T16 is electrically connected between the low potential line VGL and the output terminal Out, and the gate of the sixteenth transistor T16 is electrically connected to the second node N2. The sixteenth transistor T16 conducts when the second node N2 is at a high level, and writes the low level of the low potential line VGL to the output terminal Out.

[0104] The fourth capacitor c4 is electrically connected between the second node N2 and the low potential line VGL, and is used to stabilize the potential of the second node N2.

[0105] In a feasible implementation manner, the shift unit 1 includes a plurality of transistors, and all of the plurality of transistors are N-type transistors, such as Indium Gallium Zinc Oxide (IGZO) transistors.

[0106] Exemplarily, refer to Figure 13 , the plurality of transistors include the first transistor T1 - the eleventh transistor T11, the thirteenth transistor T13 - the sixteenth transistor T16, and all of these transistors are N-type transistors. Or, refer to Figure 17 , the plurality of transistors include the first transistor T1 - the eighth transistor T8, the tenth transistor T10, the twelfth transistor T12 - the sixteenth transistor T16, and all of these transistors are N-type transistors.

[0107] In this circuit design, the types of the transistors in the shift unit 1 are the same, and the film process is simpler. Moreover, the device driving ability of the N-type transistor is stronger, and the circuit performance is better.

[0108] In a feasible implementation manner, the shift unit 1 includes a plurality of transistors. Among them, some transistors are N-type transistors, such as IGZO transistors; some transistors are P-type transistors, such as Low Temperature Poly – Silicon (LTPS) transistors.

[0109] Exemplarily, refer to Figure 10 , Figure 12 , Figure 14 and Figure 16 , in the shift unit 1, the fourth transistor T4, the ninth transistor T9, the eleventh transistor T11 and / or the twelfth transistor T12 are P-type transistors, and the other transistors are N-type transistors.

[0110] This circuit design includes two types of transistors, and the connection method of the transistor gates will be more flexible. For example, refer to Figure 16 , when the twelfth transistor T12 is a P-type transistor, the gate of the twelfth transistor T12 can be selected to be connected to one of the multiple nodes, and the circuit design is more flexible.

[0111] Based on the same inventive concept, an embodiment of the present invention further provides a display panel, as Figure 18 shown. Figure 18 FIG. is a schematic structural diagram of the display panel provided by the embodiment of the present invention. The display panel includes a pixel circuit 100 and at least one of the aforementioned shift registers 200, and the shift register 200 is electrically connected to the pixel circuit 100.

[0112] Combined with the foregoing analysis, in the display panel provided by the embodiment of the present invention, since the signals output by the shift register 200 are more stable, the working reliability of the pixel circuit 100 is higher, and the display panel can have a better display effect.

[0113] In the embodiment of the present invention, in order to improve afterimage and reduce costs, the transistors in the pixel circuit 100 can all adopt N-type transistor designs.

[0114] Generally, the pixel circuit 100 includes a driving transistor, a first reset transistor for resetting the gate of the driving transistor, a second reset transistor for resetting the anode of the light-emitting element, a data writing transistor for charging the gate of the driving transistor, and a light-emitting control transistor for controlling light emission. These transistors can all be N-type transistors, that is, the effective levels of the driving signals required by these transistors are all high levels.

[0115] Among these transistors, in the driving signals corresponding to the first reset transistor, the second reset transistor, and the light-emitting control transistor, the driving logic between the output of the high level and the clock control signal is similar. Therefore, in the embodiment of the present invention, at least one of the first reset transistor, the second reset transistor, and the light-emitting control transistor can be electrically connected to the shift register 200 provided by the embodiment of the present invention.

[0116] There can be various circuit structures of the pixel circuit 100 in the embodiment of the present invention. The present invention exemplarily gives a circuit structure, as Figure 19 shown. Figure 19 FIG. is a schematic circuit structure diagram of the pixel circuit provided by the embodiment of the present invention. The pixel circuit includes a driving transistor M0, a first reset transistor M1, a light-emitting control transistor M2, a second reset transistor M3, a data writing transistor M4, a capacitor C01, and a capacitor C02.

[0117] The gate of the first reset transistor M1 is electrically connected to the first scan line S1, the first pole is electrically connected to the first reset line ref1, and the second pole is electrically connected to the gate of the driving transistor M0. The first reset transistor M1 responds to the high level in the signal provided by the first scan line S1 and writes the signal of the first reset line ref1 into the gate of the driving transistor M0.

[0118] The gate of the light-emitting control transistor M2 is electrically connected to the light-emitting control line Emit, the first pole is electrically connected to the power supply line PVDD, and the second pole is electrically connected to the first pole of the driving transistor M0. The light-emitting control transistor M2 responds to the high level in the signal provided by the light-emitting control line Emit and writes the signal of the power supply line PVDD to the first pole of the driving transistor M0.

[0119] The gate of the second reset transistor M3 is electrically connected to the second scan line S2, the first pole is electrically connected to the second reset line ref2, and the second pole is electrically connected to the anode of the light-emitting element 300. The second reset transistor M3 responds to the high level in the signal provided by the second scan line S2 and writes the signal of the second reset line ref2 to the anode of the light-emitting element 300.

[0120] The gate of the data writing transistor M4 is electrically connected to the third scan line S3, the first pole is electrically connected to the data line Data, and the second pole is electrically connected to the gate of the driving transistor M0. The data writing transistor M4 responds to the high level in the signal provided by the third scan line S3 and writes the signal of the data line Data to the gate of the driving transistor M0.

[0121] The capacitor C01 is electrically connected between the gate of the driving transistor M0 and the second pole of the driving transistor M0.

[0122] The capacitor C02 is electrically connected between the second pole of the driving transistor M0 and the cathode of the light-emitting element 300.

[0123] Wherein, the above-mentioned driving transistor M0 may include only one gate, or may also include two gates, namely a top gate and a bottom gate. When the driving transistor M0 includes a top gate and a bottom gate, the gate of the driving transistor M0 mentioned above is understood to be the top gate of the driving transistor M0. Further, the bottom gate of the driving transistor M0 may also be electrically connected to the second pole of the driving transistor M0.

[0124] As Figure 20 shown, Figure 20 is another schematic structural diagram of the display panel provided by the embodiment of the present invention. The first scan line S1 is electrically connected to the first shift register 201, the second scan line S2 is electrically connected to the second shift register 202, and the light-emitting control line Emit is electrically connected to the third shift register 203.

[0125] In the embodiment of the present invention, the shift register 200 may include at least one of the first shift register 201, the second shift register 202, and the third shift register 203, so as to make the first scan signal, the light-emitting control signal, and / or the second scan signal received by the pixel circuit 100 more stable, and enable the pixel circuit 100 to perform operations such as reset and light-emitting control more reliably.

[0126] Among them, Figure 20 The fact that the illustrated first shift register 201, second shift register 202, and third shift register 203 are located on one side of the pixel circuit 100 is only for illustrative purposes. These shift registers 200 can also be located on opposite sides of the pixel circuit 100. In addition, the third scan line S3 can be connected to other types of shift registers so that the pixel circuit 100 can receive the third scan signal.

[0127] Based on the same inventive concept, an embodiment of the present invention also provides a display device, such as Figure 21 shown, Figure 21 is a schematic structural diagram of the display device provided by the embodiment of the present invention. This display device includes the above-mentioned display panel 1000. Of course, Figure 21 The display device shown is only for illustrative purposes. This display device can be any electronic device with a display function, such as a mobile phone, a tablet computer, a laptop computer, an e-book reader, or a television.

[0128] The above are only the preferred embodiments of the present invention and are not intended to limit the present invention. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present invention shall be included within the scope of protection of the present invention.

[0129] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A shift register, characterized in that, It includes a plurality of cascaded shift units, and the shift units are used to output a driving signal with an effective level of high level; The shift unit includes: A first output module, which is used to write the signal of the first high potential line to the output terminal when the first node is at a high level; A second output module, which is used to write the signal of the low potential line to the output terminal when the second node is at a high level; A first control module, which is used to write a signal to the first node; A second control module, which is used to write a signal to the second node; Wherein, the first control module includes a first unit and a first transistor; the first unit writes the signal of the input terminal to the third node in response to the signal provided by the first clock terminal; the first transistor is electrically connected between the third node and the first node, and the gate of the first transistor is electrically connected to the second high potential line, wherein, the second high potential line provides a second high potential signal, and the voltage value of the second high potential signal is less than the voltage value of the high level in the signal provided by the input terminal.

2. The shift register according to claim 1, wherein, The voltage value of the second high potential signal is v1, and the voltage value of the high level in the signal provided by the input terminal is v2, and 1V≤v2 - v1≤3V.

3. The shift register according to claim 1, wherein, The shift unit further includes a first capacitor, a first end of the first capacitor is electrically connected to the third node, and a second end of the first capacitor receives a fixed potential signal.

4. The shift register according to claim 3, wherein, The second end of the first capacitor is electrically connected to the low potential line, the first high potential line or the second high potential line.

5. The shift register according to claim 1, wherein, The first unit includes a second transistor, the second transistor is electrically connected between the input terminal and the third node, and the gate of the second transistor is electrically connected to the first clock terminal.

6. The shift register according to claim 5, wherein, The second transistor is electrically connected to the third node through a third transistor, the gate of the third transistor is electrically connected to the gate of the second transistor, and there is a first intermediate node between the second transistor and the third transistor; The first control module further includes a second unit, and the second unit writes a high level to the first intermediate node in response to a first signal.

7. The shift register according to claim 6, wherein, The second unit includes a fourth transistor, the fourth transistor is electrically connected between the first high potential line and the third node; Wherein, the fourth transistor is an N-type transistor, and the gate of the fourth transistor is electrically connected to one of the third node, the first node and the output terminal; Or, the fourth transistor is a P-type transistor, and the gate of the fourth transistor is electrically connected to the second node.

8. The shift register according to claim 1, wherein The second control module includes: A fifth transistor, the fifth transistor is electrically connected between the low potential line and the second node, and the gate of the fifth transistor is electrically connected to the third node; A sixth transistor, electrically connected between the low potential line and the fourth node, and a gate of the sixth transistor is electrically connected to the input terminal; A seventh transistor, electrically connected between the first clock terminal and the second node, and a gate of the seventh transistor is electrically connected to the fourth node; A second capacitor, electrically connected between the first clock terminal and the fourth node.

9. The shift register according to claim 8, wherein the seventh transistor is electrically connected to the second node through an eighth transistor, a gate of the eighth transistor is connected to the gate of the seventh transistor, and a second intermediate node is provided between the seventh transistor and the eighth transistor; the second control module further includes a third unit, and the third unit writes a high level to the second intermediate node in response to a second signal.

10. The shift register according to claim 9, wherein the third unit includes a ninth transistor, electrically connected between the first high potential line and the second intermediate node; wherein, the ninth transistor is an N-type transistor, and a gate of the ninth transistor is electrically connected to the second node; alternatively, the ninth transistor is a P-type transistor, and a gate of the ninth transistor is electrically connected to one of the third node, the first node, and the output terminal.

11. The shift register according to claim 8, wherein the fifth transistor is electrically connected to the second node through a tenth transistor, a gate of the tenth transistor is electrically connected to the gate of the fifth transistor, and a third intermediate node is provided between the fifth transistor and the tenth transistor; the second control module further includes a fourth unit, and the fourth unit writes a high level to the third intermediate node in response to a third signal.

12. The shift register according to claim 11, wherein the fourth unit includes an eleventh transistor, one pole of the eleventh transistor is electrically connected to the first high potential line or the second high potential line, and the other pole of the eleventh transistor is electrically connected to the third intermediate node; wherein, the eleventh transistor is an N-type transistor, and a gate of the eleventh transistor is electrically connected to the second node; alternatively, the eleventh transistor is a P-type transistor, and a gate of the eleventh transistor is electrically connected to one of the third node, the first node, and the output terminal.

13. The shift register according to claim 8, wherein the seventh transistor is electrically connected to the second node through an eighth transistor, a gate of the eighth transistor is connected to the gate of the seventh transistor, and a second intermediate node is provided between the seventh transistor and the eighth transistor; the fifth transistor is electrically connected to the second node through a tenth transistor, a gate of the tenth transistor is electrically connected to the gate of the fifth transistor, and a third intermediate node is provided between the fifth transistor and the tenth transistor; The second control module further includes a fifth unit, and the fifth unit writes a high level to the second intermediate node and the third intermediate node in response to a fourth signal.

14. The shift register according to claim 13, wherein the fifth unit includes a twelfth transistor, one pole of the twelfth transistor is electrically connected to the first high potential line, and the other pole of the twelfth transistor is electrically connected to the second intermediate node and the third intermediate node; wherein, the twelfth transistor is an N-type transistor, and the gate of the twelfth transistor is electrically connected to the second node; alternatively, the twelfth transistor is a P-type transistor, and the gate of the twelfth transistor is electrically connected to one of the third node, the first node, and the output terminal.

15. The shift register according to claim 8, wherein the sixth transistor is electrically connected to the fourth node through a thirteenth transistor, the gate of the thirteenth transistor is electrically connected to the gate of the sixth transistor, and there is a fourth intermediate node between the sixth transistor and the thirteenth transistor; the second control module further includes a sixth unit, and the sixth unit writes a high level to the fourth intermediate node in response to a fifth signal.

16. The shift register according to claim 15, wherein the sixth unit includes a fourteenth transistor, one pole of the fourteenth transistor is electrically connected to the first high potential line or the second high potential line, and the other pole of the fourteenth transistor is electrically connected to the fourth intermediate node; the fourteenth transistor is an N-type transistor, and the gate of the fourteenth transistor is electrically connected to the fourth node.

17. The shift register according to claim 1, wherein the first output module includes a fifteenth transistor and a third capacitor; wherein, the fifteenth transistor is electrically connected between the first high potential line and the output terminal, and the gate of the fifteenth transistor is electrically connected to the first node; the third capacitor is electrically connected between the first node and the output terminal; the second output module includes a sixteenth transistor and a fourth capacitor; wherein, the sixteenth transistor is electrically connected between the low potential line and the output terminal, and the gate of the sixteenth transistor is electrically connected to the second node; the fourth capacitor is electrically connected between the second node and the low potential line.

18. The shift register according to claim 1, wherein the shift unit includes a plurality of transistors, and all of the plurality of transistors are N-type transistors.

19. The shift register according to claim 1, wherein the shift unit includes a plurality of transistors, some of the transistors are N-type transistors, and some of the transistors are P-type transistors.

20. A display panel, characterized in that, Comprising: a pixel circuit; at least one shift register according to any one of claims 1 to 19, the shift register being electrically connected to the pixel circuit.

21. The display panel according to claim 20, wherein The pixel circuit includes: a driving transistor; a first reset transistor, in response to a high level in the signal provided by the first scan line, writing the signal of the first reset line to the gate of the driving transistor; The light-emitting control transistor writes the signal of the power supply line to the first pole of the driving transistor in response to a high level in the signal provided by the light-emitting control line; The second reset transistor writes the signal of the second reset line to the light-emitting element in response to a high level in the signal provided by the second scan line; The data writing transistor writes the signal of the data line to the gate of the driving transistor in response to a high level in the signal provided by the third scan line; Wherein, the first scan line is electrically connected to the first shift register, the second scan line is electrically connected to the second shift register, and the light-emitting control line is electrically connected to the third shift register; The shift register includes at least one of the first shift register, the second shift register, and the third shift register.

22. A display device, characterized in that, A display panel according to claim 20 or 21.

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