Gate driver and display device including the same

Abstract

The invention provides a gate driver and a display device including the same. The gate driver includes: a level shifter configured to output a first mode gate clock in a normal scan rate mode and a second mode gate clock in a high scan rate mode; and a gate shift register configured to output a normal scan rate scan signal synchronized with the first mode gate clock in a normal scan rate mode, and to output a high scan rate scan signal synchronized with the second mode gate clock in a high scan rate mode, adjacent gate clocks of the first-mode gate clock have a phase difference equal to one horizontal period, adjacent gate clock pairs of the second-mode gate clock have a phase difference equal to one horizontal period, and two gate clocks constituting the same gate clock pair are synchronized with each other, and the first-mode gate clock is implemented as a 16-phase clock, and the second-mode gate clock is implemented as a 16-phase clock. And the second mode gate clock is implemented as a 16-phase clock.

Description

[0001] Cross - reference to related applications

[0002] This application claims the benefit of Korean Patent Application No. 10 - 2024 - 0011090, filed on January 24, 2024, which is incorporated herein by reference in its entirety as if fully set forth herein. Technical Field

[0003] The present disclosure relates to a gate driver and a display device including the gate driver. Background Art

[0004] A display device includes a gate driver for driving gate lines of a display panel.

[0005] Recently, gate drivers are designed to selectively implement a normal scan rate mode and a high scan rate mode. The gate driver can provide a scan signal shifted by one row unit to the gate lines to implement the normal scan rate, and can provide a scan signal shifted by two - row units to the gate lines to implement the high scan rate.

[0006] However, compared with a gate driver that only implements the normal scan rate mode, a gate driver that implements both the normal scan rate mode and the high scan rate mode has a problem of increased mounting area. Summary of the Invention

[0007] To overcome the above problems in the related art, the present disclosure can provide a gate driver and a display device including the gate driver, which can implement the normal scan rate mode and the high scan rate mode without increasing the mounting area.

[0008] To achieve these and other advantages and in accordance with the purpose of the present disclosure, as embodied and broadly described herein, a gate driver includes a level shifter and a gate shift register. The level shifter is configured to output a first - mode gate clock in the normal scan rate mode and a second - mode gate clock in the high scan rate mode. The gate shift register is configured to output a normal scan rate scan signal synchronized with the first - mode gate clock in the normal scan rate mode and a high scan rate scan signal synchronized with the second - mode gate clock in the high scan rate mode. Wherein, adjacent gate clocks of the first - mode gate clock have a phase difference equal to 1 horizontal period, adjacent gate clock pairs of the second - mode gate clock have a phase difference equal to 1 horizontal period, and two gate clocks constituting the same gate clock pair are synchronized with each other, and the first - mode gate clock is implemented as a 16 - phase clock, and the second - mode gate clock is implemented as a 16 - phase clock. Brief Description of the Drawings

[0009] The accompanying drawings are included to provide a further understanding of the present disclosure and are incorporated into and constitute a part of this application. The accompanying drawings illustrate embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure. In the accompanying drawings:

[0010] Figure 1 is a diagram showing a display device according to the present embodiment;

[0011] Figure 2 schematically shows Figure 1 the pixels shown in;

[0012] Figure 3 is a diagram showing the connection configuration between a timing controller and a gate driver in a display device according to the present embodiment;

[0013] Figure 4 is a diagram showing an example of selectively executing a normal scan rate mode and a high scan rate mode based on a mode control signal;

[0014] Figure 5 schematically shows the configuration of one stage included in a gate shift register;

[0015] Figure 6 is a diagram showing an example of a screen achieving a first resolution in a normal scan rate mode and a screen achieving a second resolution in a high scan rate mode;

[0016] Figures 7 to 10 is a diagram for describing the operation of a panel driver for achieving a screen with a first resolution in a normal scan rate mode;

[0017] Figures 11 to 14 is a diagram for describing the operation of a panel driver for achieving a screen with a second resolution in a high scan rate mode;

[0018] Figure 15 is a diagram showing a comparison example in which each of a first mode gate clock and a second mode gate clock is implemented as a 12-phase clock;

[0019] Figure 16 is a diagram showing an embodiment in which each of a first mode gate clock and a second mode gate clock is implemented as a 16-phase clock;

[0020] Figure 17 is a diagram showing a carry connection configuration and a differential pulse width configuration of a gate clock for optimizing a driving margin for each scan rate mode;

[0021] Figure 18 is a diagram showing in detail the configuration of a one-stage circuit according to the present embodiment;

[0022] Figure 19 and Figure 20 is a diagram showing a configuration modification of a stage circuit for enhancing the discharge characteristics of a Q node and an effect based thereon;

[0023] Figure 21 is a diagram showing Q node ripples that occur based on the input period of a gate clock in a normal scan rate mode and a high scan rate mode;

[0024] Figure 22 and Figure 23 is a diagram showing a configuration modification of a stage circuit for reducing Q node ripples and an effect based thereon;

[0025] Figure 24 and Figure 25 is a diagram showing an example in which the voltage levels of Q nodes are different at the scan output time in a normal scan rate mode and a high scan rate mode; and

[0026] Figure 26 is a diagram showing an example in which line resistances are designed differently for each clock line to compensate for output characteristic deviations that occur due to the different voltage levels of Q nodes at the scan output time. DETAILED DESCRIPTION

[0027] Hereinafter, the present disclosure will be described more fully with reference to the drawings showing exemplary embodiments of the present disclosure. However, the present disclosure can be embodied in many different forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concept of the present disclosure to those skilled in the art.

[0028] The display device according to the present disclosure can be applied to a television (TV), a video player, a personal computer (PC), a home theater, vehicle electronic devices, and a smart phone, but is not limited thereto. The display device according to the present disclosure can be implemented as a light-emitting display device, a quantum dot display (QDD) device, or a liquid crystal display (LCD) device. Hereinafter, for ease of description, a light-emitting display device based on an inorganic light-emitting diode or an organic light-emitting diode will be described, for example.

[0029] In addition, examples in which the light-emitting display device described below includes an n-type or p-type transistor will be described, but the light-emitting display device can be implemented as a type in which an n-type transistor and a p-type transistor are jointly provided. The transistor can be a three-electrode element including a gate, a source, and a drain. The source and drain of the transistor can be switched based on an applied voltage. Based on this, in the following description, examples in which one of the source and drain is a first electrode and the other of the source and drain is a second electrode will be described.

[0030] Figure 1 This is a diagram showing a display device according to the present embodiment. Figure 2 This schematically shows Figure 1 the pixels shown in

[0031] As Figure 1 and Figure 2 shown in

[0032] The display device according to the present embodiment may include a host system 110, a timing controller 120, a gate driver 130, a data driver 140, a display panel 150, and a power circuit 180. Depending on the implementation type of the display device, one or more of the timing controller 120, the gate driver 130, and the data driver 140 may be integrated into a single integrated circuit (IC).

[0033] The timing controller 120 may output a gate timing control signal GDC for controlling the operation timing of the gate driver 130 and a data timing control signal DDC for controlling the operation timing of the data driver 140 based on the synchronous timing signal. The timing controller 120 may provide image data DATA and the data timing control signal DDC to the data driver 140. The timing controller 120 may be formed in an IC type and may be mounted on a printed circuit board (PCB), but is not limited thereto.

[0034] The gate driver 130 may output a scan signal based on the gate timing control signal GDC provided from the timing controller 120. The gate driver 130 may provide the scan signal to the pixels PIX of the display panel 150 through a plurality of gate lines GL1 to GLm. The gate driver 130 may be formed in an IC type or may be directly formed as a gate-in-panel (GIP) type on the display panel 150, but is not limited thereto.

[0035] The data driver 140 may sample and latch the image data DATA based on the data timing control signal DDC provided from the timing controller 120, and may map the latched data to a gamma compensation voltage to generate an analog data voltage. The data driver 140 may provide the data voltage to the pixels PIX of the display panel 150 through a plurality of data lines DL1 to DLn. The data driver 140 may be formed in an IC type and may be bonded to or mounted on the PCB, but is not limited thereto.

[0036] The power circuit 180 can generate a high-level first panel power EVDD and a low-level second panel power EVSS based on a direct current (DC) input voltage provided from the outside. The power circuit 180 can also generate a gate high voltage VGH and a gate low voltage VGL required to drive the gate driver 130 and a source voltage required to drive the data driver 140.

[0037] The display panel 150 can include a screen for displaying an input image. The screen can be configured with a pixel array. The pixel array can include a plurality of data lines DL1 to DLn, a plurality of gate lines GL1 to GLm intersecting the data lines DL1 to DLn, and a plurality of pixels PIX.

[0038] The pixels PIX can be arranged on the screen AA in a matrix type defined by the data lines DL1 to DLn and the gate lines GL1 to GLm. The pixels PIX can be arranged on the screen in various types, such as a stripe type, a diamond type, and a matrix type.

[0039] The pixel array can include a plurality of pixel columns and a plurality of pixel rows intersecting the pixel columns. Each of the pixel columns can include pixels PIX arranged in the Y-axis direction. The pixel rows can include pixels PIX arranged in the X-axis direction. One vertical period can be one frame time required to write the image data DATA of one frame in all the pixels PIX of the screen. One horizontal period can be a time obtained by dividing one frame period by the number of pixel rows L1 to Ln. One horizontal period can be a time required to write the image data DATA of one pixel row sharing a gate line in the pixels PIX of one pixel row.

[0040] The pixels PIX can include red (R) pixels, green (G) pixels, blue (B) pixels, and white (W) pixels for color implementation. Each of the pixels PIX can include a pixel circuit, which includes a light-emitting device, a driving element, a switching element, and a capacitor. Each of the driving element and the switching element can be implemented as a thin-film transistor (TFT). The TFT can be implemented as a P-type, an N-type, or a hybrid type in which P-type and N-type are jointly provided. In addition, the semiconductor layer of each TFT can include amorphous silicon, polycrystalline silicon, or an oxide.

[0041] Figure 3 is a diagram showing a connection configuration between a timing controller and a gate driver in a display device according to the present embodiment. Figure 4 is a diagram showing an example of selectively performing a normal scan rate mode and a high scan rate mode based on a mode control signal. Figure 5 is a diagram schematically showing a configuration of one stage included in a gate shift register.

[0042] Refer to Figure 3, the gate driver 130 may include a level shifter 135 and a gate shift register 131.

[0043] The level shifter 135 may generate a gate clock GCLK based on a gate timing control signal GDC (i.e., a start signal VST, an on clock (On CLK), and an off clock (Off CLK)) input from the timing controller 120, and a gate high voltage VGH and a gate low voltage VGL each input from the power circuit 180.

[0044] As Figure 4 shown, the level shifter 135 may generate a first mode gate clock GCLK_MOD1 and a second mode gate clock GCLK_MOD2 for implementing a scan rate mode based on a mode control signal CMOD input from the timing controller 120, and output them to the gate shift register 131.

[0045] The level shifter 135 may output the first mode gate clock GCLK_MOD1 to the gate shift register 131 in response to a mode control signal CMOD of a first logic voltage H. The first mode gate clock GCLK_MOD1 may be used to implement a normal scan rate mode MODE1. In the first mode gate clock GCLK_MOD1, adjacent gate clocks may have a phase difference equal to 1 horizontal period.

[0046] The level shifter 135 may output the second mode gate clock GCLK_MOD2 to the gate shift register 131 in response to a mode control signal CMOD of a second logic voltage L. The second mode gate clock GCLK_MOD2 may be used to implement a high scan rate mode MODE2. In the second mode gate clock GCLK_MOD2, adjacent gate clock pairs may have a phase difference equal to 1 horizontal period. The two gate clocks constituting the same gate clock pair may have the same phase.

[0047] The level shifter 135 may provide the first mode gate clock GCLK_MOD1 to the gate shift register 131 through a plurality of clock lines in the normal scan rate mode MODE1, and may provide the second mode gate clock GCLK_MOD2 to the gate shift register 131 through a clock line in the high scan rate mode MODE2.

[0048] The level shifter 135 may also output the start signal VST to the gate shift register 131 through a start line in each of the normal scan rate mode MODE1 and the high scan rate mode MODE2.

[0049] The gate shift register 131 can generate a normal scan rate scan signal SCAN synchronized with the first mode gate clock GCLK_MOD1 in the normal scan rate mode MODE1, and output it to the gate lines.

[0050] The gate shift register 131 can generate a high scan rate scan signal SCAN synchronized with the second mode gate clock GCLK_MOD2 in the high scan rate mode MODE2, and output it to the gate lines.

[0051] The gate shift register 131 can include a plurality of gate stages STG1 to STG(m / 4) connected dependently to each other. In order to reduce the circuit area occupied by the gate shift register 131, the gate shift register 131 can be designed such that the number of m / 4 gate stages drives the number of m gate lines.

[0052] For this purpose, as Figure 5 shown, a first-stage STG1 according to the present embodiment can include four output nodes OP1 to OP4, and can output four scan signals SCAN1 to SCAN4 through the output nodes OP1 to OP4.

[0053] A first-stage STG1 according to the present embodiment can include: a first scan output circuit PU1 and PD1 connected to the first output node OP1, a second scan output circuit PU2 and PD2 connected to the second output node OP2, a third scan output circuit PU3 and PD3 connected to the third output node OP3, a fourth scan output circuit PU4 and PD4 connected to the fourth output node OP4, and a carry output circuit PU and PD connected to the carry output node OP. A first-stage STG1 according to the present embodiment can include a node control circuit NC for controlling the operations of the first to fourth scan output circuits and the carry output circuit. A start signal VST, a reset signal RST, a high-level drive voltage GVDD, and a low-level drive voltage GVSS can be provided to the node control circuit NC. A start carry signal can be used instead of the start signal VST, and a reset carry signal can be used instead of the reset signal RST. The start carry signal can be a carry output of one of the previous stages, and the reset carry signal can be a carry output of one of the subsequent stages.

[0054] The first to fourth scan output circuits and the carry output circuit can share the Q node and the QB node of the node control circuit NC. When the voltage of the Q node is maintained at an effective level, the voltage of the QB node can be maintained at an ineffective level. On the other hand, when the voltage of the Q node is maintained at an ineffective level, the voltage of the QB node can be maintained at an effective level.

[0055] The gate electrodes of the first to fourth pull-up transistors PU1 to PU4 included in the first to fourth scan output circuits may be commonly connected to the Q node. When the voltage of the Q node has a valid level, the first to fourth gate clocks SCLK1 to SCLK4 may be applied to the first to fourth output nodes OP1 to OP4 through the first to fourth pull-up transistors PU1 to PU4. Accordingly, the first to fourth scan signals SCAN1 to SCAN4 output from the first to fourth output nodes OP1 to OP4 may be synchronized with the first to fourth gate clocks SCLK1 to SCLK4.

[0056] The first to fourth gate clocks SCLK1 to SCLK4 may be the first mode gate clock GCLK_MOD1 in the normal scan rate mode MODE1 and may be the second mode gate clock GCLK_MOD2 in the high scan rate mode MODE2.

[0057] The gate electrodes of the first to fourth pull-down transistors PD1 to PD4 included in the first to fourth scan output circuits may be commonly connected to the QB node. When the voltage of the QB node has a valid level, the low-level driving voltage GVSS may be applied to the first to fourth output nodes OP1 to OP4 through the first to fourth pull-down transistors PD1 to PD4.

[0058] In addition, when the voltage of the Q node has a valid level, the carry clock CRCLK1 may be applied to the carry output node OP through the pull-up transistor PU. Additionally, when the voltage of the QB node has a valid level, the low-level driving voltage GVSS may be applied to the carry output node OP through the pull-down transistor PD. The carry output C1 output from the carry output node OP may be synchronized with the carry clock CRCLK1. The carry output C1 may be input to another stage and may be used as a start carry signal or a reset carry signal in another stage.

[0059] Figure 6 is a diagram showing an example of a screen that implements a first resolution in the normal scan rate mode and a second resolution in the high scan rate mode.

[0060] Refer to Figure 6 , a screen with a first resolution HD1 may be implemented in the normal scan rate mode MODE1, while a screen with a second resolution HD2 may be implemented in the high scan rate mode MODE2. In the high scan rate mode MODE2, two gate lines configuring the same gate line pair may be scanned simultaneously, and thus, the vertical resolution of the screen may be reduced by half compared to the normal scan rate mode.

[0061] In the normal scanning rate mode MODE1, a screen with the first resolution HD1 can be achieved by scanning signals at the normal scanning rate. The normal scanning rate scanning signals can be synchronized with the first mode gate clock GCLK_MOD1. "DLG:OFF" can be achieved through the first mode gate clock GCLK_MOD1. "DLG:OFF" can indicate that the resolution reduction function is deactivated. In the normal scanning rate mode MODE1, the input image data can be displayed on the screen without omission. The frame frequency of the normal scanning rate mode MODE1 can be 240 Hz.

[0062] In the high scanning rate mode MODE2, a screen with the second resolution HD2 can be achieved by scanning signals at the high scanning rate. The high scanning rate scanning signals can be synchronized with the second mode gate clock GCLK_MOD2. "DLG:ON" can be achieved through the second mode gate clock GCLK_MOD2. "DLG:ON" can indicate that the resolution reduction function is activated. In the high scanning rate mode MODE2, the input image data can be displayed on the screen in a state where a part of the input image data is omitted. The frame frequency of the high scanning rate mode MODE2 can be 480 Hz.

[0063] Figures 7 to 10 It is a diagram for describing the operation of a panel driver for achieving a screen with the first resolution in the normal scanning rate mode.

[0064] Refer to Figures 7 to 10 , in the normal scanning rate mode MODE1, the gate driver can respectively provide the first scan signal SCAN1 to the m-th scan signal SCANm with a phase difference equal to 1 horizontal period 1HT to the first gate line to the m-th gate line to achieve a screen with the first resolution UH1 (H*V).

[0065] In this case, the data driver can synchronize the input image data with the first scan signal SCAN1 to the m-th scan signal SCANm to output the input image data to the data lines without reduction.

[0066] That is to say, the data driver can output the first data voltage D1 during the first horizontal period H1 overlapping with the first scan signal SCAN1, output the second data voltage D2 during the second horizontal period H2 overlapping with the second scan signal SCAN2, output the third data voltage D3 during the third horizontal period H3 overlapping with the third scan signal SCAN3, and output the fourth data voltage D4 during the fourth horizontal period H4 overlapping with the fourth scan signal SCAN4. In this way, the data driver can output the m-th data voltage Dm during the m-th horizontal period Hm overlapping with the m-th scan signal SCANm.

[0067] Therefore, during one vertical period (one frame period) 1VT, the first data voltage D1 to the m-th data voltage Dm can be sequentially provided to all pixel rows of the display panel 150, and thus the screen of the first resolution HD1 can be completed.

[0068] In the normal scan rate mode MODE1, the first scan signal SCAN1 to the fourth scan signal SCAN4 can be synchronized with the first mode gate clock GCLK_MOD1. That is, in one stage, the first mode gate clock GCLK_MOD1 can be output as the first scan signal SCAN1 to the fourth scan signal SCAN4.

[0069] As Figure 10 shown, the first mode gate clock GCLK_MOD1 can be implemented by the first gate clock SCLK1 to the fourth gate clock SCLK4 having a phase difference equal to 1 horizontal period 1HT between adjacent gate clocks. Each of the first gate clock SCLK1 to the fourth gate clock SCLK4 can have a pulse width equal to 4 horizontal periods 4HT.

[0070] The rising edge of the first mode gate clock GCLK_MOD1 can be distributed in time with a phase difference equal to 1 horizontal period 1HT. Similarly, the falling edge of the first mode gate clock GCLK_MOD1 can also be distributed in time with a phase difference equal to 1 horizontal period 1HT.

[0071] Figures 11 to 14 is a diagram for describing the operation of a panel driver for implementing a screen of a second resolution in a high scan rate mode.

[0072] Referring to Figure 11 , in order to implement a screen of a second resolution HD2 (H*V / 2) in the high scan rate mode MODE2, the gate driver can reduce one vertical period 1VT to half compared to normal based on the second mode gate clock GCLK_MOD2, and the data driver can reduce the input image data to reduce the vertical resolution to half compared to normal.

[0073] To reduce one vertical period in the high scan rate mode MODE2, gate line pairs each including two gate lines can be configured, the gate line pairs can be sequentially scanned with a phase difference equal to 1 horizontal period 1HT, and the two gate lines in the same gate line pair can be scanned simultaneously. For this purpose, the first scan signal SCAN1 and the second scan signal SCAN2 respectively provided to the first gate line and the second gate line can be synchronized with each other, and the third scan signal SCAN3 and the fourth scan signal SCAN4 respectively provided to the third gate line and the fourth gate line can be synchronized with each other.

[0074] Referring to Figure 12 , in order to implement a screen with a second resolution HD2 (H*V / 2) in the high scan rate mode MODE2, the gate driver may provide a pair of scan signals having a phase difference equal to 1 horizontal period 1HT to the first gate line to the m-th gate line, respectively.

[0075] In this case, the data driver may downsize the input image data and output the input image data to the data lines in synchronization with the pair of scan signals.

[0076] That is, the data driver may output a first data voltage D1 corresponding to the first scan signal SCAN1 and the second scan signal SCAN2, and may output a second data voltage D3 corresponding to the third scan signal SCAN3 and the fourth scan signal SCAN4. In this way, the data driver may output an m / 2-th data voltage Dm-1 corresponding to the (m-1)-th scan signal SCANm-1 and the m-th scan signal SCANm.

[0077] Therefore, during one vertical period 1VT, the first data voltage to the m / 2-th data voltage (D1, D3, …, and Dm-1) may be sequentially provided to all pixel rows of the display panel 150, and thus a screen with the second resolution HD2 may be completed.

[0078] In the high scan rate mode MODE2, as Figure 13 shown, the first scan signal SCAN1 to the fourth scan signal SCAN4 may be synchronized with the second mode gate clock GCLK_MOD2. As Figure 14 shown, the second mode gate clock GCLK_MOD2 may include a first gate clock SCLK1 and a second gate clock SCLK2 having the same phase, and a third gate clock SCLK3 and a fourth gate clock SCLK4 having the same phase. In this case, the phase of the third gate clock SCLK3 and the fourth gate clock SCLK4 may be 1 horizontal period 1HT later than the phase of the first gate clock SCLK1 and the second gate clock SCLK2. In addition, each of the first gate clock SCLK1 to the fourth gate clock SCLK4 may have a pulse width equal to three horizontal periods 3HT.

[0079] Figure 15 is a diagram showing a comparative example in which each of the first mode gate clock and the second mode gate clock is implemented as a 12-phase clock. Figure 16 is a diagram showing an embodiment in which each of the first mode gate clock and the second mode gate clock is implemented as a 16-phase clock.

[0080] Referring to Figure 15, in a comparative example where each of the first-mode gate clock GCLK_MOD1 and the second-mode gate clock GCLK_MOD2 is implemented as a 12-phase clock, the timing margin TM in the first-mode gate clock GCLK_MOD1 can be 8 horizontal time periods 8HT, while the timing margin TM in the second-mode gate clock GCLK_MOD2 can be 4 horizontal time periods 4HT.

[0081] When a primary configuration is implemented as Figure 5 shown, the timing margin TM between gate clocks can be determined in units of four gate clocks with adjacent phases to each other. That is, the timing margin TM between gate clocks can be determined as the interval between the falling edge FE of the gate clock SCLK4 with the latest phase among the four gate clocks and the rising edge RE of the gate clock SCLK1 with the earliest phase among the four gate clocks.

[0082] When the timing margin TM between gate clocks is insufficient, the quality of the scan output may deteriorate. In the normal scan rate mode MODE1, since the timing margin TM between gate clocks is 8 horizontal time periods 8HT, there may not be a big problem. However, in the high scan rate mode MODE2, since the timing margin TM between gate clocks is 4 horizontal time periods 4HT and is relatively short, the time required for output discharge may be insufficient, and due to this, the scan output may be distorted.

[0083] To solve such a problem, in the present embodiment, as Figure 16 shown, each of the first-mode gate clock GCLK_MOD1 and the second-mode gate clock GCLK_MOD2 can be implemented as a 16-phase clock. Therefore, the timing margin TM in the first-mode gate clock GCLK_MOD1 can be increased to 12 horizontal time periods 12HT, while the timing margin TM in the second-mode gate clock GCLK_MOD2 can be increased to 6 horizontal time periods 6HT.

[0084] Figure 17 is a diagram showing a carry connection configuration for optimizing the drive margin in each scan rate mode and a differential pulse width configuration of the gate clock.

[0085] According to Figure 17In this embodiment, the pulse width of each of the first-mode gate clocks GCLK_MOD1 for implementing the normal scan rate mode MODE1 may be 4 horizontal time periods 4HT. On the other hand, the pulse width of each of the second-mode gate clocks GCLK_MOD2 for implementing the high scan rate mode MODE2 may be 3 horizontal time periods 3HT. That is to say, the pulse width of each of the second-mode gate clocks GCLK_MOD2 can be designed to be narrower than that of the first mode. Therefore, the timing margin for Q-node charging in the high scan rate mode MODE2 can be increased, thereby preventing a decrease in the quality of the scan output caused by insufficient timing margin.

[0086] Referring to Figure 17 , the Q-node charging margin and the output discharge margin may not be a problem in the normal scan rate mode MODE1, but may be a problem in the high scan rate mode MODE2 with a short timing margin.

[0087] As shown in Comparative Example 1, when the carry output C(k - 2) of the (k - 2)-th stage is set as the start carry signal, the carry output C(k + 2) of the (k + 2)-th stage is set as the reset carry signal, and the pulse width of each of the second-mode gate clocks GCLK_MOD2 is set to 4 horizontal time periods 4HT, all of the Q-node charging margin and the output discharge margin may be insufficient.

[0088] As shown in Comparative Example 2, when the carry output C(k - 2) of the (k - 2)-th stage is set as the start carry signal, the carry output C(k + 3) of the (k + 3)-th stage is set as the reset carry signal, and the pulse width of each of the second-mode gate clocks GCLK_MOD2 is set to 4 horizontal time periods 4HT, the insufficiency of the output discharge margin can be solved, but the insufficiency of the Q-node charging margin may not be solved.

[0089] Therefore, in this embodiment, in order to fully ensure the Q-node charging margin and the output discharge margin, the carry output C(k - 2) of the (k - 2)-th stage can be set as the start carry signal, the carry output C(k + 3) of the (k + 3)-th stage can be set as the reset carry signal, and the pulse width of each of the second-mode gate clocks GCLK_MOD2 can be set to 3 horizontal time periods 3HT.

[0090] In this embodiment, since the pulse width of each of the second-mode gate clocks GCLK_MOD2 is set to 3 horizontal time periods 3HT, each of the Q-node charging margin and the output discharge margin in the high scan rate mode MODE2 can ensure 1 horizontal time period 1HT.

[0091] In the present embodiment, since the carry output C(k + 3) of the (k + 3)-th stage is set as a reset carry signal, the output discharge margin in the high scan rate mode MODE2 can further ensure three horizontal periods 3HT.

[0092] Figure 18 FIG. is a diagram showing in detail the configuration of a stage circuit according to the present embodiment.

[0093] Referring to Figure 18 , the k-th stage circuit STG(k) may include a Q node, a QH node, and a QB node. The k-th stage circuit STG(k) may include a Q / QH node controller BK1, a QB node controller BK2, a carry output unit BK3, and a scan output unit BK4.

[0094] The Q / QH node controller BK1 may charge the Q node to the level of a first high-level voltage GVDD1 in response to the input of a previous carry signal C(k - 2), and may discharge the Q node to the level of a third low-level voltage GVSS3 in response to the input of a next carry signal C(k + 3). To this end, the Q / QH node controller BK1 may include a first transistor T21 to an eighth transistor T28.

[0095] The first transistor T21 and the second transistor T22 may be connected between the Q node and a first high-level voltage line for transmitting the first high-level voltage GVDD1. The first transistor T21 and the second transistor T22 may be connected in series with each other. The first transistor T21 and the second transistor T22 may charge the Q node to the level of the first high-level voltage GVDD1 in response to the input of the previous carry signal C(k - 2). The first transistor T21 may be turned on based on the input of the previous carry signal C(k - 2), and may transmit the first high-level voltage GVDD1 to a connection node NC2. The second transistor T22 may be turned on based on the input of the previous carry signal C(k - 2), and may electrically connect the connection node NC2 to the Q node. Therefore, when the first transistor T21 and the second transistor T22 are simultaneously turned on, the first high-level voltage GVDD1 may be provided to the Q node.

[0096] The fifth transistor T25 and the sixth transistor T26 can be connected to a third high-level voltage line for transmitting a third high-level voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 can transmit the third high-level voltage GVDD3 to a connection node NC2 in response to the third high-level voltage GVDD3. The fifth transistor T25 and the sixth transistor T26 can be turned on simultaneously by the third high-level voltage GVDD3, and can continuously transmit the third high-level voltage GVDD3 to the connection node NC2, and thus can increase the voltage difference between the gate voltage of the first transistor T21 and the connection node NC2. Therefore, when the first transistor T21 is turned off due to the input of a previous carry signal C(k - 2) of a carry level to the gate of the first transistor T21, due to the voltage difference between the gate voltage of the first transistor T21 and the connection node NC2, the first transistor T21 can be completely maintained in the off state. Therefore, current leakage of the first transistor T21 and a voltage drop of the Q node caused thereby can be prevented, and thus the voltage of the Q node can be stably maintained. For this purpose, the third high-level voltage GVDD3 can be set to a voltage level lower than the first high-level voltage GVDD1.

[0097] The third transistor T23 and the fourth transistor T24 can be connected between the Q node and a third low-level voltage line for transmitting a third low-level voltage GVSS3. The third transistor T23 and the fourth transistor T24 can be connected in series with each other. The third transistor T23 and the fourth transistor T24 can discharge the Q node and the QH node to the third low-level voltage GVSS3 in response to the input of a next carry signal C(k + 3). The fourth transistor T24 can be turned on based on the input of the next carry signal C(k + 3), and can discharge the QH node to the second low-level voltage GVSS2 level. The third transistor T23 can be turned on based on the input of the next carry signal C(k + 3), and can electrically connect the Q node to the QH node. Therefore, when the third transistor T23 and the fourth transistor T24 are turned on simultaneously, each of the Q node to the QH node can be discharged to the third low-level voltage GVSS3 level.

[0098] The seventh transistor T27 and the eighth transistor T28 may be connected between the Q node and the first high-level voltage line for transmitting the first high-level voltage GVDD1 and between the QH node and the first high-level voltage line for transmitting the first high-level voltage GVDD1. The seventh transistor T27 and the eighth transistor T28 may be connected in series with each other. The seventh transistor T27 and the eighth transistor T28 may transmit the first high-level voltage GVDD1 to the QH node in response to the voltage of the Q node. When the voltage of the Q node has a conductive level, the seventh transistor T27 may conduct and may transmit the first high-level voltage GVDD1 to the shared node of the seventh transistor T27 and the eighth transistor T28. When the voltage of the Q node has a conductive level, the eighth transistor T28 may conduct and may electrically connect the shared node to the QH node. Therefore, when the voltage of the Q node has a conductive level, the seventh transistor T27 and the eighth transistor T28 may conduct simultaneously, and may transmit the first high-level voltage GVDD1 to the QH node. When the first high-level voltage GVDD1 is supplied to the QH node, the voltage difference between the gate of the third transistor T23 and the QH node may increase. Therefore, when the third transistor T23 is turned off due to the next carry signal C(k + 3) of the off level being input to the gate of the third transistor T23, the third transistor T23 may be completely maintained in the off state due to the voltage difference between the gate voltage of the third transistor T23 and the QH node. Therefore, current leakage of the third transistor T23 and the resulting voltage drop of the Q node can be prevented, and thus the voltage of the Q node can be stably maintained.

[0099] The Q / QH node controller BK1 can discharge the Q node and the QH node to the third low-level voltage GVSS3 in response to the voltage of the QB node. To this end, the Q / QH node controller BK1 can further include a first additional transistor T31 and a second additional transistor T32. The first additional transistor T31 and the second additional transistor T32 can be connected between the Q node and the third low-level voltage line for transmitting the third low-level voltage GVSS3. The first additional transistor T31 and the second additional transistor T32 can be connected in series with each other. The first additional transistor T31 and the second additional transistor T32 can discharge the Q node and the QH node to the third low-level voltage GVSS3 level in response to the voltage of the QH node. When the voltage of the QB node has a conducting level, the second additional transistor T32 can conduct, and can transmit the third low-level voltage GVSS3 to the shared node of the first additional transistor T31 and the second additional transistor T32. When the voltage of the QB node has a conducting level, the first additional transistor T31 can conduct, and can electrically connect the Q node to the QH node. Therefore, when the first additional transistor T31 and the second additional transistor T32 conduct simultaneously in response to the voltage of the QB node, each of the Q node and the QH node can be discharged to the third low-level voltage GVSS3 level.

[0100] The QB node controller BK2 can shift the voltage level of the Q node to the voltage level of the QB node. To this end, the QB node controller BK2 can include a first transistor T41 to a fifth transistor T45.

[0101] The second transistor T42 and the third transistor T43 may be connected between a third connection node NC3 and a second high-level voltage line for transmitting a second high-level voltage GVDD2. The second transistor T42 and the third transistor T43 may be connected in series with each other. The second transistor T42 and the third transistor T43 may transmit the second high-level voltage GVDD2 to the connection node NC3 in response to the second high-level voltage GVDD2. The second transistor T42 may be turned on by the second high-level voltage GVDD2 and may transmit the second high-level voltage GVDD2 to a shared node of the second transistor T42 and the third transistor T43. The third transistor T43 may be turned on by the second high-level voltage GVDD2 and may electrically connect the connection node NC3 to the shared node of the second transistor T42 and the third transistor T43. Therefore, when the second transistor T42 and the third transistor T43 are simultaneously turned on by the second high-level voltage GVDD2, the connection node NC3 may be charged to the second high-level voltage GVDD2 level. The fourth transistor T44 may be connected between the connection node NC3 and a second low-level voltage line for transmitting a second low-level voltage GVSS2. The fourth transistor T44 may transmit the second low-level voltage GVSS2 to the connection node NC3 in response to the voltage of the Q node. When the voltage of the Q node has a conductive level, the fourth transistor T44 may discharge or reset the connection node NC3 to the second low-level voltage GVSS2.

[0102] The first transistor T41 may be connected between a QB node and a second high-level voltage line for transmitting a second high-level voltage GVDD2. The first transistor T41 may transmit the second high-level voltage GVDD2 to the QB node in response to the voltage of the connection node NC3. When the voltage of the connection node NC3 has a conductive level, the first transistor T41 may charge the QB node to the second high-level voltage GVDD2 level. The fifth transistor T45 may be connected between the QB node and a third low-level voltage line for transmitting a third low-level voltage GVSS3. The fifth transistor T45 may transmit the third low-level voltage GVSS3 to the QB node in response to the voltage of the Q node. When the voltage of the Q node has a conductive level, the fifth transistor T45 may charge the QB node to the third low-level voltage GVSS3 level.

[0103] The QB node controller BK2 may discharge the QB node to the third low-level voltage GVSS3 level in response to the input of the next carry signal C(k - 2). To this end, the QB node controller BK2 may further include a first additional transistor T51.

[0104] The first additional transistor T51 may be connected between the QB node and a third low-level voltage line for transmitting a third low-level voltage GVSS3. The first additional transistor T51 may transmit the third low-level voltage GVSS3 to the QB node in response to the input of a next carry signal C(k-2).

[0105] The carry output unit BK3 may output a carry clock CRCLK(k) of a gate conduction voltage as a carry signal C(k) of the conduction voltage when charging the Q node with a conduction voltage level, and may output the third low-level voltage GVSS3 as a carry signal C(k) of the conduction voltage when charging the QB node with a conduction voltage level.

[0106] The carry output unit BK3 may include a first transistor T81, a second transistor T82, and a boost capacitor CC. The first transistor T81 may be connected between an output node NO and a clock signal line of the carry clock CRCLK(k). The boost capacitor CC may be connected between the gate and the source of the first transistor T81. When the carry clock CRCLK(k) of the gate conduction voltage is output to the output node NO, the boost capacitor CC may bootstrap the voltage of the Q node to a boosted voltage level higher than the level of the first high-level voltage GVDD1 synchronously with the carry clock CRCLK(k) of the gate conduction voltage. When the voltage of the Q node is bootstrapped, the carry signal C(k) of the conduction voltage may be quickly charged into the output node NO without distortion. Therefore, the carry signal C(k) of the conduction voltage may be output from the output node NO. The second transistor T82 may transmit the third low-level voltage GVSS3 to the output node NO in response to the voltage of the QB node. Therefore, the carry signal C(k) of the turn-off voltage may be output from the output node NO.

[0107] The scan output unit BK4 may output a first gate clock SCLK(n-3) to a fourth gate clock SCLK(n) of a gate conduction voltage as a first scan signal SCAN(n-3) to a fourth scan signal SCAN(n) of the conduction voltage when charging the Q node with a conduction voltage level, and may output a first low-level voltage GVSS1 as a first scan signal SCAN(n-3) to a fourth scan signal SCAN(n) of the turn-off voltage when charging the QB node with a conduction voltage level. To this end, the scan output unit BK4 may include a first transistor T71 to an eighth transistor T78 and a first boost capacitor CS1 to a fourth boost capacitor CS4.

[0108] The first transistor T71 can be connected between the clock signal line of the first gate clock SCLK(n - 3) and the first output node NO1. The first boost capacitor CS1 can be connected between the gate and the source of the first transistor T71. When the first gate clock SCLK(n - 3) with a gate conduction voltage is output to the first output node NO1, the first boost capacitor CS1 can boost the voltage of the Q node to a boost voltage level higher than the first high-level voltage GVDD1 level synchronously with the first gate clock SCLK(n - 3) having the gate conduction voltage. When the voltage of the Q node is boosted, the first scan signal SCAN(n - 3) with a conduction voltage can be quickly charged into the first output node NO1 without distortion. Therefore, the first scan signal SCAN(n - 3) with a conduction voltage can be output from the first output node NO1. The second transistor T72 can transmit the first low-level voltage GVSS1 to the first output node NO1 in response to the voltage of the QB node. Therefore, the first scan signal SCAN(n - 3) with a turn-off voltage can be output from the first output node NO1.

[0109] The third transistor T73 can be connected between the clock signal line of the second gate clock SCLK(n - 2) and the second output node NO2. The second boost capacitor CS2 can be connected between the gate and the source of the third transistor T73. When the second gate clock SCLK(n - 2) with a gate conduction voltage is output to the second output node NO2, the second boost capacitor CS2 can boost the voltage of the Q node to a boost voltage level higher than the first high-level voltage GVDD1 level synchronously with the second gate clock SCLK(n - 2) having the gate conduction voltage. When the voltage of the Q node is boosted, the second scan signal SCAN(n - 2) with a conduction voltage can be quickly charged into the second output node NO2 without distortion. Therefore, the second scan signal SCAN(n - 2) with a conduction voltage can be output from the second output node NO2. The fourth transistor T74 can transmit the first low-level voltage GVSS1 to the second output node NO2 in response to the voltage of the QB node. Therefore, the second scan signal SCAN(n - 2) with a turn-off voltage can be output from the second output node NO2.

[0110] The fifth transistor T75 can be connected between the clock signal line of the third gate clock SCLK(n - 1) and the third output node NO3. The third boost capacitor CS3 can be connected between the gate and the source of the fifth transistor T75. When the third gate clock SCLK(n - 1) with a gate conduction voltage is output to the third output node NO3, the third boost capacitor CS3 can bootstrap the voltage of the Q node to a boost voltage level higher than the first high-level voltage GVDD1 level synchronously with the third gate clock SCLK(n - 1) with the gate conduction voltage. When the voltage of the Q node is bootstrapped, the third scan signal SCAN(n - 1) with a conduction voltage can be quickly and distortionlessly charged into the third output node NO3. Therefore, the third scan signal SCAN(n - 1) with a conduction voltage can be output from the third output node NO3. The sixth transistor T76 can transmit the first low-level voltage GVSS1 to the third output node NO3 in response to the voltage of the QB node. Therefore, the third scan signal SCAN(n - 1) with a turn-off voltage can be output from the third output node NO3.

[0111] The seventh transistor T77 can be connected between the clock signal line of the fourth gate clock SCLK(n) and the fourth output node NO4. The fourth boost capacitor CS4 can be connected between the gate and the source of the seventh transistor T77. When the fourth gate clock SCLK(n) with a gate conduction voltage is output to the fourth output node NO4, the fourth boost capacitor CS4 can bootstrap the voltage of the Q node to a boost voltage level higher than the first high-level voltage GVDD1 level synchronously with the fourth gate clock SCLK(n) with the gate conduction voltage. When the voltage of the Q node is bootstrapped, the fourth scan signal SCAN(n) with a conduction voltage can be quickly and distortionlessly charged into the fourth output node NO4. Therefore, the fourth scan signal SCAN(n) with a conduction voltage can be output from the fourth output node NO4. The eighth transistor T78 can transmit the first low-level voltage GVSS1 to the fourth output node NO4 in response to the voltage of the QB node. Therefore, the fourth scan signal SCAN(n) with a turn-off voltage can be output from the fourth output node NO4.

[0112] In the present embodiment, in order to stabilize the voltages of the Q node, the QB node, and the QH node by minimizing the turn-off current flowing in the transistor in the off state, the high-level voltage and the low-level voltage can be set to three (or two) different voltage levels.

[0113] For example, the first high-level voltage GVDD1 can be set to 20V, the second high-level voltage GVDD2 can be set to 16V, the third high-level voltage GVDD3 can be set to 14V, the first low-level voltage GVSS1 can be set to -6V, the second low-level voltage GVSS2 can be set to -10V, and the third low-level voltage GVSS3 can be set to -12V. As another example, the first low-level voltage GVSS1 and the second low-level voltage GNSS2 can be set to the same voltage (e.g., -6V). Such values can be only embodiments, and the levels of the high-level voltage and the low-level voltage can be set differently according to the embodiments.

[0114] Figure 19 and Figure 20 FIG. is a diagram showing a configuration modification of a stage circuit for enhancing the discharge characteristics of a Q node and an effect based thereon.

[0115] Referring to Figure 19 , the third transistor T23 and the fourth transistor T24 can be connected in series with each other to configure the first discharge transistor Tdis1. The first discharge transistor Tdis1 can discharge the Q node in response to the carry output C(k + 3) of the (k + 3)-th stage.

[0116] Referring to Figure 20 , it may be necessary for the capacitance of the first discharge transistor Tdis1 to be two times or more larger than the capacitance of the pull-down transistor T82 of the carry output circuit to enhance the discharge characteristics of the Q node. The capacitance of the first discharge transistor Tdis1 can be designed to have the maximum size within the allowable design area.

[0117] When the discharge characteristics of the Q node are enhanced, the timing margin can be easily ensured within a specified time.

[0118] Figure 21 FIG. is a diagram showing Q node ripples that occur based on the input period of the gate clock in the normal scan rate mode and the high scan rate mode.

[0119] Referring to Figure 16 and Figure 21 , each of the first mode gate clocks GCLK_MOD1 in the normal scan rate mode MODE1 can be repeated at a period PED of 19 horizontal periods 19HT, while each of the second mode gate clocks GCLK_MOD2 in the high scan rate mode MODE2 can be repeated at a period PED of 10 horizontal periods 10HT.

[0120] Therefore, in the normal scan rate mode MODE1, each stage of Q nodes may be affected by ripples according to the repetition period 19HT of the first mode gate clock SCLK, while in the high scan rate mode MODE2, each stage of Q nodes may be affected by ripples according to the repetition period 10HT of the second mode gate clock SCLK.

[0121] In the normal scan rate mode MODE1, the amplitude of the ripples that appear in the Q nodes can be PR1, while in the high scan rate mode MODE2, the amplitude of the ripples that appear in the Q nodes can be PR2, and PR2 is greater than PR1. This may be because, different from the normal scan rate mode MODE1, in the high scan rate mode MODE2, the gate clock pairs with the same phase can affect the Q nodes.

[0122] Figure 22 and Figure 23 are diagrams showing the configuration modification of the stage circuit for reducing the ripples in the Q nodes and the effects based thereon.

[0123] Referring to Figure 22 , the first additional transistor T31 and the second additional transistor T32 can be connected in series with each other to configure the second discharge transistor Tdis2. The second discharge transistor Tdis2 can be turned on in response to the voltage of the QB node and can thus keep the Q node in a discharged state.

[0124] Referring to Figure 23 , the capacity of the second discharge transistor Tdis2 that may be required is two times or more times larger than the capacity of the pull - down transistor T82 of the carry - output circuit to enhance the discharge characteristics of the Q node. The capacity of the second discharge transistor Tdis2 can be designed to have the maximum size within the allowable design area.

[0125] When the discharge characteristics of the Q node are enhanced, the amplitude of the ripples that appear in the Q node in each of the normal scan rate mode MODE1 and the high scan rate mode MODE2 can be reduced.

[0126] Figure 24 and Figure 25 are diagrams showing examples where the voltage levels of the Q node are different at the scan output times in the normal scan rate mode and the high scan rate mode.

[0127] Referring to Figure 24 , in the normal scan rate mode MODE1, the voltage level of the Q node may be different at the falling edges of the first gate clock SCLK1 to the fourth gate clock SCLK4. Therefore, a deviation may occur between the output characteristics of the first scan signal SCAN1 to the fourth scan signal SCAN4.

[0128] Referring toFigure 25 In the high scan rate mode MODE2, the voltage level of the Q node may be different at the falling edges of the first gate clock SCLK1 to the fourth gate clock SCLK4. Therefore, a deviation may occur between the output characteristics of the first scan signal SCAN1 to the fourth scan signal SCAN4.

[0129] Figure 26 FIG. is a diagram showing an example in which the line resistance is designed differently for each clock line to compensate for the deviation of the output characteristics that occurs due to the different voltage levels of the Q node at the scan output time.

[0130] Refer to Figure 16 and Figure 26 According to the present embodiment, the level shifter can supply the first mode gate clock GCLK_MOD1 to the gate shift register through sixteen clock lines CL in the normal scan rate mode MODE1, and can supply the second mode gate clock GCLK_MOD2 to the gate shift register through sixteen clock lines CL in the high scan rate mode MODE2.

[0131] Here, the sixteen clock lines CL can be grouped in units of four clock lines corresponding to four gate clocks. For example, the first clock line CL1 to the fourth clock line CL4 among the sixteen clock lines CL can be configured in the same group and can transmit the first gate clock SCLK1 to the fourth gate clock SCLK4. In this case, the first clock line CL1 to the fourth clock line CL4 can be designed to have different line resistances. That is, when the line resistances of the first clock line CL1 to the fourth clock line CL4 are R1, R2, R3, and R4, the relationship can be R1 > R2 > R3 > R4.

[0132] In addition, preferably, it can be designed such that the resistance of the first clock line among the four clock lines CL1 to CL4 included in the same group is greater than the resistance of the second clock line. Here, the gate clock having a relatively earlier phase among the four gate clocks can be supplied to the first clock line, and the gate clock having a relatively later phase among the four gate clocks can be supplied to the second clock line.

[0133] This embodiment can implement both the normal scan rate mode and the high scan rate mode while maintaining the mounting area equal to that of the normal scan rate mode.

[0134] This embodiment can optimize the input constants of the gate clock, optimize the connection between the start carry signal and the reset carry signal, and optimize the pulse width of the gate clock for each scan rate mode, and thus can sufficiently ensure the timing margin (or drive margin) in the normal scan rate mode and the high scan rate mode.

[0135] The effects according to the present disclosure are not limited to the above examples, and various other effects may be included in the specification.

[0136] Although the present disclosure has been specifically shown and described with reference to exemplary embodiments thereof, those of ordinary skill in the art will understand that various changes in form and detail may be made therein without departing from the spirit and scope of the present disclosure as defined by the appended claims.

Claims

1. A gate driver, comprising: A level shifter configured to output a first-mode gate clock in a normal scan rate mode and a second-mode gate clock in a high scan rate mode; And A gate shift register configured to output a normal scan rate scan signal synchronized with the first-mode gate clock in the normal scan rate mode and a high scan rate scan signal synchronized with the second-mode gate clock in the high scan rate mode, Wherein adjacent gate clocks of the first-mode gate clock have a phase difference equal to 1 horizontal period, Wherein adjacent gate clock pairs of the second-mode gate clock have a phase difference equal to 1 horizontal period, and two gate clocks constituting the same gate clock pair are synchronized with each other, and Wherein the first-mode gate clock is implemented as a 16-phase clock, and the second-mode gate clock is implemented as a 16-phase clock.

2. The gate driver according to claim 1, wherein, Each of the first-mode gate clocks has a pulse width equal to 4 horizontal periods, and Wherein each of the second-mode gate clocks has a pulse width equal to 3 horizontal periods.

3. The gate driver according to claim 1, wherein The gate shift register includes a plurality of stages connected dependently to each other, and Each of the plurality of stages includes: A node control circuit configured to control a Q node and a QB node; and Four scan output circuits and one carry output circuit configured to share the Q node and the QB node.

4. The gate driver according to claim 3, wherein, The node control circuit of the k-th stage among the plurality of stages includes: A charging transistor configured to charge the Q node in response to a carry output of the (k - 2)-th stage; and A first discharging transistor configured to discharge the Q node in response to a carry output of the (k + 3)-th stage, Where k is a natural number.

5. The gate driver according to claim 4, wherein The carry output circuit includes a pull-down transistor, and the pull-down transistor includes a gate electrode connected to the QB node, and The capacity of the first discharging transistor is two times or more than two times the capacity of the pull-down transistor of the carry output circuit.

6. The gate driver according to claim 3, wherein, The node control circuit includes a second discharging transistor configured to discharge the Q node in response to the voltage of the QB node, The carry output circuit includes a pull-down transistor, and the pull-down transistor includes a gate electrode connected to the QB node, and The capacity of the second discharging transistor is two times or more than two times the capacity of the pull-down transistor of the carry output circuit.

7. The gate driver according to claim 1, wherein, The level shifter provides the first-mode gate clock to the gate shift register through sixteen clock lines in the normal scan rate mode and provides the second-mode gate clock to the gate shift register through the sixteen clock lines in the high scan rate mode, Wherein the sixteen clock lines are grouped in units of four clock lines corresponding to four gate clocks, and Wherein the resistance of the first clock line among the four clock lines included in the same group is greater than the resistance of the second clock line.

8. The gate driver according to claim 7, wherein, Provide the gate clock among the four gate clocks having a relatively earlier phase to the first clock line, and Provide the gate clock among the four gate clocks having a relatively later phase to the second clock line.

9. The gate driver according to claim 3, wherein, At least a part of the node control circuit, the four scan output circuits, and the one carry output circuit in each stage are respectively driven by a high-level driving voltage having different voltage levels and a low-level driving voltage having different voltage levels.

10. A display device, comprising the gate driver according to any one of claims 1 to 9.

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