Polarization code coding method and device, communication equipment, chip and storage medium

Abstract

The invention provides a polar code coding method and device, communication equipment, a chip and a storage medium, and relates to the technical field of data processing, and the method comprises the steps: obtaining an initial code; based on a preset coding rule, a first coder and at most a first number of first exclusive-OR gates, the initial code is processed to obtain a target code, the first coder adopts a combinational logic circuit, and the number of the input ends and the number of the output ends of the first coder are both larger than a first threshold value. Therefore, due to the fact that at most the first number of the first exclusive-OR gates are needed, initial coding can be processed, the performance of coding high-speed calculation can be guaranteed through few exclusive-OR gate resources, the utilization rate of hardware resources is increased, and the calculation speed and hardware resource consumption are balanced.

Description

Technical Field

[0001] The present disclosure relates to the technical field of data processing, and in particular, to a coding method, apparatus, communication device, chip, and storage medium for polar codes. Background Art

[0002] A polar code is a coding method that can approach the Shannon limit in a binary erasure channel (BEC) and a binary discrete memoryless channel (B-DMC). With further research and optimization, the application of polar codes in the communication field has gradually expanded.

[0003] The coding process of polar codes is relatively complex and has certain requirements for hardware computing resources. Therefore, how to achieve high-speed polar coding under limited hardware resources is an urgent problem to be solved at present. Summary of the Invention

[0004] The present disclosure provides a coding method, apparatus, communication device, chip, and storage medium for polar codes, aiming to at least solve one of the technical problems in the related art to some extent.

[0005] A first aspect embodiment of the present disclosure provides a coding method for polar codes, including:

[0006] Obtaining an initial code;

[0007] Processing the initial code based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target code,

[0008] wherein the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

[0009] A second aspect embodiment of the present disclosure provides a coding apparatus for polar codes, including:

[0010] An obtaining module, configured to obtain an initial code;

[0011] A processing module, configured to process the initial code based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target code,

[0012] wherein the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

[0013] According to a third aspect of the embodiments of the present disclosure, a communication device is provided, including: one or more processors; wherein, the processor is configured to call instructions to cause the communication device to execute the encoding method of the polar code according to the first aspect.

[0014] According to a fourth aspect of the embodiments of the present disclosure, a storage medium is provided, which stores instructions. When the instructions run on a communication device, the communication device is caused to execute the encoding method of the polar code as described in the first aspect.

[0015] An embodiment of a fifth aspect of the present disclosure provides a chip, including a processor and an interface. The processor is configured to read instructions to execute the encoding method of the polar code disclosed in the embodiments of the present disclosure.

[0016] In the embodiments of the present disclosure, an initial encoding is first obtained, and then based on a preset encoding rule, a first encoder, and at most a first number of first exclusive-OR gates, the initial encoding is processed to obtain a target encoding. The first encoder adopts a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold. Thus, since the first encoder adopts a combinational logic circuit, it can respond promptly to changes in the input. This characteristic of instant response ensures low latency, making the first encoder very effective in processing high-speed signals. Since the number of input terminals and output terminals is greater than the first threshold, the first encoder can process multiple data bits simultaneously, thereby improving data throughput and being applicable to scenarios requiring high-speed data transmission or processing. Since at most a first number of first exclusive-OR gates are required to implement the processing of the initial encoding, fewer exclusive-OR gate resources can be used to ensure the performance of high-speed encoding calculation, improving the utilization rate of hardware resources and balancing the calculation speed and hardware resource consumption.

[0017] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, and cannot limit the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The accompanying drawings herein are incorporated into the specification and constitute a part of this specification, showing embodiments consistent with the present disclosure, and are used together with the specification to explain the principles of the present disclosure, wherein:

[0019] Figure 1 is a schematic flowchart of the encoding method of the polar code according to the first embodiment of the present disclosure;

[0020] Figure 2 is a schematic diagram of the encoding recursive logic according to the embodiments of the present disclosure;

[0021] Figure 3 is a schematic diagram of an encoder according to the embodiments of the present disclosure;

[0022] Figure 4 It is a timing diagram of 128-point polar coding provided according to an embodiment of the present disclosure;

[0023] Figure 5 It is a schematic flowchart of an encoding method of a polar code provided according to a second embodiment of the present disclosure;

[0024] Figure 6 It is a schematic flowchart of an encoding method of a polar code provided according to a third embodiment of the present disclosure;

[0025] Figure 7 It is a timing diagram of 1024-point polar coding provided according to an embodiment of the present disclosure;

[0026] Figure 8 It is a schematic flowchart of an encoding method of a polar code provided according to a fourth embodiment of the present disclosure;

[0027] Figure 9 It is an application scenario diagram of Polar coding in 5G-NR;

[0028] Figure 10 It is a schematic flowchart of an encoding method of a polar code provided according to a fifth embodiment of the present disclosure;

[0029] Figure 11 It is a schematic flowchart of an encoding method of a polar code provided according to a sixth embodiment of the present disclosure;

[0030] Figure 12 It is a schematic flowchart of an encoding method of a polar code provided according to a seventh embodiment of the present disclosure;

[0031] Figure 13 It is a schematic flowchart of an encoding method of a polar code provided according to an eighth embodiment of the present disclosure;

[0032] Figure 14 It is a timing flowchart of multi-task polar_pre;

[0033] Figure 15 It is a schematic diagram of the read-write relationship of a register bank;

[0034] Figure 16 It is a flowchart of an overall Polar coding scheme;

[0035] Figure 17 It is a schematic diagram of an encoding device of a polar code according to an embodiment of the present disclosure;

[0036] Figure 18 It is a block diagram of a communication device for implementing an encoding method of a polar code according to an embodiment of the present disclosure;

[0037] Figure 19 It is a block diagram of a communication chip for implementing the encoding method of the polar code according to an embodiment of the present disclosure. Specific implementation manners

[0038] Here, some embodiments of the present disclosure will be described in detail, and their examples are shown in the drawings. When the following description refers to the drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. Various changes, modifications, and equivalents of the methods, apparatuses, and / or systems described herein will become apparent after understanding the present disclosure. For example, the order of the operations described herein is merely an example and is not limited to those set forth herein. Instead, it can be changed as will be apparent after understanding the present disclosure, except for operations that must be performed in a specific order. Additionally, for the sake of clarity and conciseness, the description of features known in the art may be omitted.

[0039] The implementation manners described in some embodiments of the present disclosure below do not represent all implementation manners consistent with the present disclosure. On the contrary, they are merely examples of apparatuses and methods consistent with some aspects of the present disclosure as detailed in the appended claims.

[0040] It should be noted that the execution subject of the encoding method of the polar code in this embodiment may be an encoding device of the polar code, and this device may be implemented in software and / or hardware. The execution subject of the encoding method of the polar code in the embodiments of the present disclosure is any type of communication device, such as a mobile phone, a smart bracelet, a tablet, a notebook, a desktop computer, a vehicle-mounted terminal, a smart home appliance, a wearable device, etc., or may also be an Internet of Things device, or may also be a processing chip inside the terminal, which is not limited herein.

[0041] In the embodiments of the present disclosure, the "encoding device of the polar code" will be used as the execution subject to execute the encoding method of the polar code for description, hereinafter simply referred to as the "device", which is not limited herein.

[0042] Figure 1 It is a schematic flowchart of the encoding method of the polar code according to the first embodiment of the present disclosure.

[0043] As Figure 1 shown, the method includes:

[0044] S101: Obtain an initial encoding.

[0045] Among them, the initial encoding may be encoded data obtained after preprocessing the input information.

[0046] Among them, the input information may be any type of information, such as a request message, a control message, a scheduling message, etc., which is not limited herein.

[0047] As a possible implementation, the input information may be uplink control information (UCI), which is not limited herein.

[0048] Furthermore, the input information may be the payload part in UCI data, that is, the valid data part (UCI payload) included in the uplink control information, which is not limited herein.

[0049] The embodiments of the present disclosure can be applied to various scenarios. For example, it can be applied to the generation of uplink baseband data for the physical uplink control channel (PUCCH) and the physical uplink shared channel (PUSCH) with UCI in the fifth generation new radio (5G-NR), which is not limited herein.

[0050] Among them, PUCCH can be used to transmit UCI information, and PUSCH can carry UCI under some configurations.

[0051] Optionally, the implementation manners of obtaining the initial coding may at least include the following two, which are not limited herein.

[0052] As a first possible implementation manner, an initial coding with the same coding length as the target coding can be obtained.

[0053] For example, for a target coding with a maximum number of points of 1024, in the stage of preprocessing the input information, the input information needs to be converted into an initial coding of 1024. At this time, the lengths of the initial coding and the target coding are both 1024, which is not limited herein.

[0054] As a second possible implementation manner, the initial codings output in each clock cycle (there are multiple initial codings at this time) can be obtained.

[0055] For example, in the stage of preprocessing the input information, 16-bit codings can be read in each clock cycle. When the length of the target coding is 1024, 64 initial codings output in 64 clock cycles need to be obtained (64×16 = 1024), that is, 64 segments of initial codings are obtained in segments, and the length of each segment of initial coding is 16 bits, which is not limited herein.

[0056] Alternatively, if 32 bits of encoding can be read in each clock cycle and the length of the target encoding is 1024, then the initial encoding output in 32 clock cycles can be obtained (32 × 32 = 1024), that is, 32 segments of initial encoding are obtained in time segments, and the length of each segment of initial encoding is 32 bits, which is not limited herein.

[0057] It should be noted that the above examples are only illustrative and do not limit the present disclosure.

[0058] S102: Process the initial encoding based on a preset encoding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target encoding.

[0059] Among them, the first encoder adopts a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

[0060] Among them, the preset encoding rule can be a pre-configured rule for converting the original information into a target encoding, and this rule can be embodied in the form of an encoding timing diagram. For target encodings of different lengths, the corresponding encoding timing diagrams are usually different.

[0061] It should be noted that the encoding structure of the first encoder can be related to the encoding length of the initial encoding, or it can be irrelevant to the encoding length of the initial encoding, which is not limited herein.

[0062] Among them, the target encoding can be a Polar encoding obtained by processing the initial encoding according to a preset encoding rule.

[0063] It should be noted that the encoder has output terminals and input terminals, and the number of output terminals and input terminals can be the same or different. As an example, the first encoder can be an encoder with the same number of output terminals and input terminals.

[0064] Among them, the first threshold can be the number threshold of the output terminals and the number threshold of the input terminals.

[0065] As an example, in the embodiments of the present disclosure, the number of the first thresholds can be 31. Since the number of output terminals and input terminals is greater than the first threshold, the number of output terminals and input terminals can both be 32, which is not limited herein.

[0066] As a possible implementation manner, before processing the initial encoding, a first encoder can be constructed according to an encoding matrix corresponding to the encoding length of the initial encoding.

[0067] Among them, the encoding calculation of the Polar code can be implemented by introducing an encoding matrix G:

[0068] x = uG

[0069] Among them, u represents the data stream to be encoded as input, G represents the encoding matrix, and x represents the encoded output result.

[0070] For a Polar code with a mother code length of N = 2 n , its encoding matrix G can be calculated by the Arikan kernel as follows: denotes the tensor product. For example:

[0071]

[0072] As Figure 2 shown, Figure 2 the (1) in Figure 2 is the encoding structure of G2, Figure 2 the (2) in

[0073] is the encoding structure of G4, Figure 2 and the (3) in 0＝ is a deformation of the encoding structure of G4 in (2). Among them, u0, u1, u2, u3 are the input bit streams. Among them, u0, u1, u2, u3 can be extended to data streams of any number of bits, and x0, x1, x2, x3 are the output bit streams. 1＝ u1 + u3, x 2＝ u2 + u3, x 3＝ u3, as shown in the following formula:

[0074]

[0075] In the embodiments of the present disclosure, when the encoding length of the initial encoding is 32, an encoder G Figure 3 as shown in 32 can be constructed according to the encoding matrix.

[0076] As Figure 3 shown, this encoder G 32 has a total of 32 inputs, which are u0, u1, u2, u3... u 31 , and each input can be 1-bit data. The outputs are x0, x1, x2, x3... x 31 . The hardware implementation of this encoder can be a combinational logic recursive implementation, which requires 80 exclusive-OR gates, and the maximum logic level is 5 levels of exclusive-OR gates.

[0077] Among them, the first encoder adopts a combinational logic circuit. A combinational logic circuit is a circuit whose output depends only on the current input state and does not depend on the historical state of the circuit. The combinational logic circuit does not contain any storage elements (such as flip-flops, registers, etc.) and does not have a memory function. Therefore, the first encoder can respond immediately to changes in the input. This characteristic of immediate response ensures low latency, making the first encoder very effective in processing high-speed signals.

[0078] As a possible implementation, when the length of the initial encoding is 32 bits, the encoder G 32 can be used as the first encoder.

[0079] As an example, in the embodiments of the present disclosure, the first exclusive-OR gate can be a 32-bit exclusive-OR gate, which is not limited herein. Among them, the first quantity can be the minimum quantity of the first exclusive-OR gates used to generate the target encoding.

[0080] As an example, the first quantity can be 3, that is, by using 3 32-bit exclusive-OR gates, the initial encoding can be encoded in combination with the first encoder to obtain the target encoding. It should be noted that 3 32-bit first exclusive-OR gates can meet the hardware resources required for the maximum scenario, that is, meet the polar encoding requirements of 1024 points.

[0081] In some cases, 2 first exclusive-OR gates can also be used to encode the initial encoding to obtain the target encoding, which is not limited herein.

[0082] The following takes Figure 4 the polar encoding of 128 points in

[0083] as an example, that is, the code length of the target encoding is 128. Figure 4 As shown in Figure 4 the right half of Figure 4 is the encoding timing diagram of the 128-point polar encoding, that is, the corresponding encoding rule. Figure 4 The left half of Figure 3 is the recursive implementation logic corresponding to this encoding rule. Among them, 32 the first encoder used can be the encoder G

[0084] Hereinafter, the input counter will be denoted as cnt_in, the extended counter will be denoted as cnt_ext, and the output counter will be denoted as cnt_out.

[0085] Among them, A0, A1, A2, and A2 represent that the counts of the input counter are 0, 1, 2, and 3 respectively, that is, cnt_in = 0, cnt_in = 1, cnt_in = 2, and cnt_in = 3. B0 represents that the count of the extended counter is 0, that is, cnt_ext = 0. C0 and C1 represent that the counts of the output counter are 0 and 1 respectively, that is, cnt_out = 0 and cnt_out = 1.

[0086] Among them, cache 0～31 is a 32-bit register that can be composed of 32 basic storage units. Among them, the basic storage unit can be a D flip-flop (DFF, D Flip-Flop) or other types of storage elements.

[0087] Among them, a D flip-flop is a basic storage element in digital circuits and can store one-bit binary data (0 or 1). For example, if each basic storage unit is a D flip-flop, cache 0～31 can refer to a 32-bit register composed of 32 D flip-flops, which is not limited here.

[0088] It should be noted that cache 32～63 、cache 64～95 、cache 96～127 can refer to the description of cache 0～31 above and will not be elaborated here.

[0089] Among them, G0, G1, G2, and G3 are the encoding results corresponding to 4 different clock cycles respectively. Taking G0 as an example, in the first clock cycle, the initial encoding can be input into the first encoder G 32 to obtain the encoding result G0.

[0090] Next, the polar encoding of 128 points will be described in combination with the Figure 4 encoding rule:

[0091] 1. When cnt_in = 0, G0 is generated according to the initial encoding 1 obtained in the first clock cycle and the first encoder G 32 and then stored in cache 0～31 ;

[0092] 2. When cnt_in = 1, G1 is generated according to the initial encoding 2 obtained in the second clock cycle and the first encoder G 32 and then stored in cache 32～63 , and cache 0～31 (that is, the currently stored G0) and G1 are used as the inputs of xor0 for calculation, and then cache is updated according to the calculation result of xor00～31 ;

[0093] 3. When cnt_in = 2, generate G2 based on the initial code 3 obtained in the 3rd clock cycle and the first encoder G, and then store it in the cache 32 ; 64～95 ;

[0094] 4. When cnt_in = 3, generate G3 based on the initial code 4 obtained in the 4th clock cycle and the first encoder G, and then store it in the cache 32 ; calculate G2 (i.e., the currently stored G2) and G3 as the inputs of xor0, and then update the cache according to the calculation result of xor0 96～127 , and use the cache 64～95 ; 64～95 ;

[0095] 5. When cnt_ext = 0, calculate the cache 0～31 and the cache 64～95 as the inputs of xor0, and then update the cache according to the calculation result of xor0 0～31 ;

[0096] 6. When cnt_out = 0, calculate the cache 32～63 and the cache 96～127 as the inputs of xor1, and then update the cache according to the calculation result of xor1 32～63 ;

[0097] 7. When cnt_out = 1, end the encoding. At this time, the total 128 - point code stored in the cache 0～31 , cache 32～63 , cache 64～95 and cache 96～127 is the target code.

[0098] It should be noted that xor0 and xor1 are the first XOR gates used (32 - bit XOR gate resources), and the number is 2.

[0099] It can be understood that when designing the encoding rule in advance, by reasonably arranging the inputs of the XOR gate resources in each clock cycle, the first XOR gate can be used flexibly, so as to avoid excessive resource consumption while ensuring the design efficiency.

[0100] In the embodiments of the present disclosure, an initial code is first obtained, and then the initial code is processed based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target code. Wherein, the first encoder adopts a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold. Thus, since the first encoder adopts a combinational logic circuit, it can respond promptly to changes in the input. This characteristic of immediate response ensures low latency, making the first encoder very effective in processing high-speed signals. Since the number of input terminals and output terminals is greater than the first threshold, the first encoder can process multiple data bits simultaneously, thereby improving data throughput and being applicable to scenarios requiring high-speed data transmission or processing. Since at most a first number of first exclusive-OR gates are required to implement the processing of the initial code, fewer exclusive-OR gate resources can be used to ensure the performance of high-speed coding calculation, improving the utilization rate of hardware resources and balancing the calculation speed and hardware resource consumption.

[0101] Figure 5 It is a schematic flowchart of a coding method for a polar code according to the second embodiment of the present disclosure.

[0102] As Figure 5 shown, the method includes:

[0103] S201: Obtain an initial code.

[0104] It should be noted that the specific implementation manner of step S201 may refer to the above embodiments and will not be elaborated herein.

[0105] S202: Input at least one initial code into the first encoder according to a first clock order to obtain a first coding result corresponding to the initial code.

[0106] Wherein, the first clock order may be the order of each clock cycle recorded by an input counter.

[0107] Wherein, the first coding result may be the result obtained by inputting the initial code received in any clock cycle into the first encoder, and the any clock cycle belongs to a certain clock cycle in the first clock order.

[0108] Wherein, the input counter refers to a device or circuit that can receive an external input signal and count according to specific conditions or rules. For example, the count value can be increased each time a trigger signal is received.

[0109] Hereinafter, the input counter will be denoted as cnt_in. For example:

[0110] When cnt_in = 0, the initial code 1 can be input into the first encoder to generate a first coding result G0;

[0111] When cnt_in = 1, the initial code 2 can be input into the first encoder to generate the first coding result G1;

[0112] When cnt_in = 2, the initial code 3 can be input into the first encoder to generate the first coding result G2;

[0113] When cnt_in = 3, the initial code 4 can be input into the first encoder to generate the first coding result G3.

[0114] Among them, the initial code 1, the initial code 2, the initial code 3, and the initial code 4 respectively represent the initial codes received in different clock cycles, and the corresponding coding lengths are the same, such as 32bit for all, which is not limited here.

[0115] S203: Determine the target code based on at least one of the first coding results and at most the first number of first XOR gates.

[0116] It should be noted that when generating the target code based on each first coding result, the XOR operation can be performed on each first coding result according to the preset recursive logic to obtain the target code.

[0117] Combined with the examples in the above embodiments, for Figure 4 the 128-point polar coding shown. The input counter is cnt_in, and the obtained first coding results are G0, G1, G2, and G3.

[0118] As Figure 4 shown by the recursive logic in the left half, G3 is used as the fourth segment output x 96～127 ; the result N1 obtained by performing the XOR operation on G2 and G3 is used as the third segment output x 64～95 ; the result obtained by performing the XOR operation on G1 and G3 is used as the second segment output x 32～63 ; the result obtained by performing the XOR operation on G0 and G1 is used as N2, and the result obtained by performing the XOR operation on N2 and N1 is used as the first segment output x 0～31 . In the intermediate process, xor0 and xor1 are required, that is, 2 first XOR gates (32bit XOR gate resources).

[0119] Furthermore, the first segment output x 0～31 , the second segment output x 32～63 , the third segment output x 64～95 , and the fourth segment output x 96～127 can be used to determine the target code x 0～127 .

[0120] It should be noted that the specific process of the above examples can be referred to the above examples, and will not be elaborated here.

[0121] In the embodiments of the present disclosure, first, an initial code is obtained, and then, according to the first clock order, at least one initial code is input into the first encoder to obtain a first coding result corresponding to the initial code. After that, based on at least one of the first coding results and at most a first number of first exclusive-OR gates, a target code is determined. Thus, since each initial code is input into the first encoder to obtain a first coding result corresponding to each initial code, the first encoder is multiplexed in each clock cycle corresponding to the first clock order, saving computing resources. Since at most a first number of first exclusive-OR gates are required to process the initial code, fewer exclusive-OR gate resources can be used to ensure the performance of high-speed coding calculation, improving the utilization rate of hardware resources and balancing the computing speed and hardware resource consumption.

[0122] Figure 6 It is a schematic flowchart of a coding method for polar codes according to the third embodiment of the present disclosure.

[0123] As Figure 6 shown, the method includes:

[0124] S301: Obtain an initial code.

[0125] S302: According to the first clock order, input at least one initial code into the first encoder to obtain a first coding result corresponding to the initial code.

[0126] It should be noted that the specific implementation manners of steps S301 - S302 can be referred to the above embodiments, and will not be elaborated here.

[0127] S303: If the index value of any clock cycle in the first clock order satisfies the first condition, determine the clock cycle as the target clock cycle.

[0128] Among them, the first condition can be that the index value is odd or the index value is even, which can be configured according to the actual situation and will not be limited here.

[0129] Among them, the target clock cycle can be a clock cycle that can satisfy the first condition among the clock cycles corresponding to the first clock order.

[0130] In the third embodiment of the present disclosure, the 1024-point polar coding as Figure 7 shown will be described. Figure 7It is a 1024-point polar coding timing diagram. Among them, M1, M2, M3...M45 represent the total number of clock cycles required to obtain the target code with a length of 1024, that is, 45 cycles.

[0131] Among them, A0, A1, A2, A3...A31 represent the first clock order, and the index values of the corresponding 32 clock cycles are "0", "1", "2", "3"... "31" respectively. Among them, the first clock order is 32 cycles counted by the input counter cnt_in, and the corresponding clock cycles are M1, M2, M3...M32 respectively.

[0132] As a possible implementation, if the index value of any clock cycle in the first clock order is odd, it is determined that the any clock cycle satisfies the first condition.

[0133] For example, since the index value corresponding to the clock cycle M2 in the first clock order is the odd number "1", M2 can be used as the target clock cycle.

[0134] Similarly, since the index values corresponding to M4, M6, M8...M32 in the first clock order are "3", "5", "7"... "31" respectively, M4, M6, M8...M32 can all be used as the target clock cycle, which is not limited here.

[0135] S304: Determine the adjacent previous clock cycle of at least one target clock cycle.

[0136] For example, for the target clock cycle M2, its corresponding adjacent previous clock cycle is M1. For the target clock cycles M4, M6, M8...M32, their corresponding adjacent previous cycles are M3, M5, M7...M31 respectively, which is not limited here.

[0137] S305: Perform an exclusive OR operation on the first coding result corresponding to the adjacent previous clock cycle and the first coding result of the target clock cycle to obtain the second coding result corresponding to the target clock cycle.

[0138] Among them, the second coding result can be the operation result obtained by performing an exclusive OR operation on the first coding result E1 and the first coding result E2. Among them, E1 is the first coding result corresponding to the adjacent previous cycle of the target clock cycle, and E2 is the first coding result corresponding to the target clock cycle.

[0139] Such as Figure 7As shown, the first encoding results corresponding to the target clock cycles M2, M4, M6, M8... M32 are G1, G3, G5, G7, G31 respectively. The first encoding results corresponding to the adjacent previous cycles M1, M3, M5, M7... M31 of the target clock cycles are G0, G2, G4, G6, G30 respectively.

[0140] Optionally, G0 and G1 can be XOR - operated to obtain the second encoding result (denoted as P1) corresponding to the target clock cycle M2; G2 and G3 can be XOR - operated to obtain the second encoding result (denoted as P2) corresponding to the target clock cycle M4; G4 and G5 can be XOR - operated to obtain the second encoding result (denoted as P3) corresponding to the target clock cycle M6; G6 and G7 can be XOR - operated to obtain the second encoding result (denoted as P4) corresponding to the target clock cycle M8...... G30 and G31 can be XOR - operated to obtain the second encoding result (denoted as P16) corresponding to the target clock cycle M32, which is not limited herein.

[0141] S306: Determine the target encoding based on at least one first encoding result, at most the first number of first XOR gates, and the second encoding result corresponding to the target clock cycle.

[0142] The following will combine Figure 7 the encoding timing shown to illustrate how to determine the target encoding based on the first encoding result and the second encoding result corresponding to each target clock cycle.

[0143] As an optional implementation, a 1024 - bit storage space can be prepared first, which can be divided into 32 cache spaces, and each cache space is used to store 32 - bit encoded data. For example, the 32 cache spaces can be respectively labeled as X0, X1, X2, X3, X4, X5... X31. Among them, X0, X1, X2, X3, X4, X5... X31 store the 1024 - bit target encoded data in sequence.

[0144] First, the first encoding results corresponding to each clock cycle M1, M2, M3, M4... M32 can be denoted as G0, G1, G2, G3... G31. The second encoding results corresponding to each target clock cycle M2, M4, M6, M8... M32 can be denoted as P1, P2, P3, P4... P16.

[0145] Optionally, the first encoding result G31 can be stored in the cache space X31.

[0146] Optionally, the second encoding result P16 can be stored in the cache space X30.

[0147] Optionally, the exclusive OR operation can be performed on G29 and G31 to obtain the operation result W1, and then the operation result W1 is stored in the cache space X29.

[0148] Optionally, the exclusive OR operation can be performed on P15 and P16 to obtain the operation result W2, and then the operation result W2 is stored in the cache space X28.

[0149] Optionally, the exclusive OR operation can be performed on G27 and G31 to obtain the operation result W3, and then the operation result W3 is stored in the cache space X27.

[0150] Optionally, the exclusive OR operation can be performed on P14 and P16 to obtain the operation result W4, and then the operation result W4 is stored in the cache space X26.

[0151] Optionally, the exclusive OR operation can be performed on G25 and G27 to obtain the operation result W5, then the exclusive OR operation is performed on W5 and W1 to obtain the operation result W6, and then the operation result W6 is stored in the cache space X25.

[0152] Optionally, the exclusive OR operation can be performed on P13 and P14 to obtain the operation result W7, then the exclusive OR operation is performed on W7 and W2 to obtain the operation result W8, and then the operation result W8 is stored in the cache space X24.

[0153] Optionally, the exclusive OR operation can be performed on G23 and G31 to obtain the operation result W9, and then the operation result W9 is stored in the cache space X23.

[0154] Optionally, the exclusive OR operation can be performed on P12 and P16 to obtain the operation result W10, and then the operation result W10 is stored in the cache space X22.

[0155] Optionally, the exclusive OR operation can be performed on G21 and G23 to obtain the operation result W11, then the exclusive OR operation is performed on W11 and W1 to obtain the operation result W12, and then the operation result W12 is stored in the cache space X21.

[0156] Optionally, the exclusive OR operation can be performed on P11 and P12 to obtain the operation result W13, then the exclusive OR operation is performed on W13 and W2 to obtain the operation result W14, and then the operation result W14 is stored in the cache space X20.

[0157] Optionally, the exclusive OR operation can be performed on G19 and G23 to obtain the operation result W15, then the exclusive OR operation is performed on W15 and W3 to obtain the operation result W16, and then the operation result W16 is stored in the cache space X19.

[0158] Optionally, P10 and P12 can be XOR - operated to obtain an operation result W17, then W17 and W4 are XOR - operated to obtain an operation result W18, and then the operation result W18 is stored in the cache space X18.

[0159] Optionally, G17 and G19 can be XOR - operated to obtain an operation result W19, then W19 and W11 are XOR - operated to obtain an operation result W20, then W20 and W6 can be XOR - operated to obtain an operation result W21, and then the operation result W21 is stored in the cache space X17.

[0160] Optionally, P9 and P10 can be XOR - operated to obtain an operation result W22, then W22 and W13 are XOR - operated to obtain an operation result W23, then W23 and W8 can be XOR - operated to obtain an operation result W24, and then the operation result W24 is stored in the cache space X16.

[0161] Optionally, G15 and G31 can be XOR - operated to obtain an operation result W25, and then the operation result W25 is stored in the cache space X15.

[0162] Optionally, P8 and P16 can be XOR - operated to obtain an operation result W26, and then the operation result W26 is stored in the cache space X14.

[0163] Optionally, G13 and G15 can be XOR - operated to obtain an operation result W27, then W27 and W1 are XOR - operated to obtain an operation result W28, and then the operation result W28 is stored in the cache space X13.

[0164] Optionally, P7 and P8 can be XOR - operated to obtain an operation result W29, then W29 and W2 are XOR - operated to obtain an operation result W30, and then the operation result W30 is stored in the cache space X12.

[0165] Optionally, G11 and G15 can be XOR - operated to obtain an operation result W31, then W31 and W3 are XOR - operated to obtain an operation result W32, and then the operation result W32 is stored in the cache space X11.

[0166] Optionally, P6 and P8 can be XOR - operated to obtain an operation result W33, then W33 and W4 are XOR - operated to obtain an operation result W34, and then the operation result W34 is stored in the cache space X10.

[0167] Optionally, the exclusive OR operation can be performed on G9 and G11 to obtain the operation result W35, then the exclusive OR operation is performed on W35 and W27 to obtain the operation result W36, then the exclusive OR operation is performed on W36 and W6 to obtain the operation result W37, and then the operation result W37 is stored in the cache space X9.

[0168] Optionally, the exclusive OR operation can be performed on P5 and P6 to obtain the operation result W38, then the exclusive OR operation is performed on W38 and W29 to obtain the operation result W39, then the exclusive OR operation is performed on W39 and W8 to obtain the operation result W40, and then the operation result W40 is stored in the cache space X8.

[0169] Optionally, the exclusive OR operation can be performed on G7 and G15 to obtain the operation result W41, then the exclusive OR operation is performed on W41 and W9 to obtain the operation result W42, and then the operation result W42 is stored in the cache space X7.

[0170] Optionally, the exclusive OR operation can be performed on P4 and P8 to obtain the operation result W43, then the exclusive OR operation is performed on W43 and W10 to obtain the operation result W44, and then the operation result W44 is stored in the cache space X6.

[0171] Optionally, the exclusive OR operation can be performed on G5 and G7 to obtain the operation result W45, then the exclusive OR operation is performed on W45 and W27 to obtain the operation result W46, then the exclusive OR operation is performed on W46 and W12 to obtain the operation result W47, and then the operation result W47 is stored in the cache space X5.

[0172] Optionally, the exclusive OR operation can be performed on P3 and P4 to obtain the operation result W48, then the exclusive OR operation is performed on W48 and W29 to obtain the operation result W49, then the exclusive OR operation is performed on W49 and W14 to obtain the operation result W50, and then the operation result W50 is stored in the cache space X4.

[0173] Optionally, the exclusive OR operation can be performed on G3 and G7 to obtain the operation result W51, then the exclusive OR operation is performed on W51 and W31 to obtain the operation result W52, then the exclusive OR operation is performed on W52 and W16 to obtain the operation result W53, and then the operation result W53 is stored in the cache space X3.

[0174] Optionally, the exclusive OR operation can be performed on P2 and P3 to obtain the operation result W54, then the exclusive OR operation is performed on W54 and W33 to obtain the operation result W55, then the exclusive OR operation is performed on W55 and W18 to obtain the operation result W56, and then the operation result W56 is stored in the cache space X2.

[0175] Optionally, the exclusive OR operation can be performed on G1 and G3 to obtain the operation result W57. Then, the exclusive OR operation is performed on W57 and W45 to obtain the operation result W58. Then, the exclusive OR operation is performed on W58 and W36 to obtain the operation result W59.

[0176] Then, the exclusive OR operation is performed on W59 and W21 to obtain the operation result W60. After that, the operation result W60 is stored in the cache space X1.

[0177] Optionally, the exclusive OR operation can be performed on P1 and P2 to obtain the operation result W61. Then, the exclusive OR operation is performed on W61 and W48 to obtain the operation result W62. Then, the exclusive OR operation is performed on W62 and W39 to obtain the operation result W63. Then, the exclusive OR operation is performed on W63 and W24 to obtain the operation result W64. After that, the operation result W64 is stored in the cache space X0.

[0178] In summary, through the above steps, the target encoding stored in 32 cache spaces such as X0, X1, X2, X3, X4, X5..X31 can be obtained, that is, the 1024-point polar encoding.

[0179] It can be understood that in the 1024-point polar encoding timing diagram, cnt_in, cnt_ext, and cnt_out respectively represent the input counter, the extended counter, and the output counter. These three types of counters can achieve time-division multiplexing, and the maximum value can be up to 31, and the bit width can be 5 bits, which will not be limited here.

[0180] Among them, xor32 represents 32-bit exclusive OR gate resources, and xor0, xor1, and xor2 represent three first exclusive OR gates (three 32-bit exclusive OR gates). As Figure 7 shown, the number of the first exclusive OR gates used in each clock cycle (that is, Figure 7 each column in) does not exceed 3.

[0181] Among them, A0, A1...A31 represent that the counts of cnt_in are 0, 1...31 respectively, B0, B1, B2, and B3 represent that the counts of cnt_ext are 0, 1, 2, and 3 respectively, and C0, C1, C2, C3, C4, C5, C6 represent that the counts of cnt_out are 0, 1, 2, 3, 4, 5, and 6 respectively.

[0182] It should be noted that by reasonably arranging the inputs of xor32 in each clock cycle of M1, M2, M3...M45, the maximum number of the first exclusive OR gates used in each clock cycle does not exceed 3. Among them, Figure 7The 45 clock cycles shown mean that, with limited hardware resources, the maximum calculation delay is 45 clock cycles, the area consumption is 176 exclusive-OR gates, and the performance and area performance are very excellent.

[0183] In the embodiment of the present disclosure, first, an initial code is obtained, and then, according to the first clock order, at least one initial code is input into the first encoder to obtain a first coding result corresponding to each initial code. After that, if the index value of any clock cycle in the first clock order satisfies the first condition, it is determined that any clock cycle is the target clock cycle. Then, the first coding result corresponding to the adjacent previous clock cycle of at least one target clock cycle is determined. After that, the first coding result corresponding to the adjacent previous clock cycle and the first coding result of the target clock cycle are subjected to an exclusive-OR operation to obtain a second coding result corresponding to the target clock cycle. Finally, based on at least one first coding result, at most the first number of first exclusive-OR gates, and the second coding result corresponding to the target clock cycle, the target code is determined. Thus, since each initial code is input into the first encoder to obtain a first coding result corresponding to each initial code, the multiplexing of the first encoder is realized in each clock cycle corresponding to the first clock order, saving computing resources. And it has a certain degree of flexibility and scalability. By modifying the specific implementation of the first condition, the coding method, and the exclusive-OR operation, it can adapt to different application scenarios and requirements. For example, the index value of the clock cycle, the number of bits of the coding result, or the way of the exclusive-OR operation can be adjusted as needed. Through precise time synchronization and data processing, the stable operation and high efficiency of the system can be ensured. Since at most the first number of first exclusive-OR gates are required to realize the processing of the initial code, fewer exclusive-OR gate resources can be used to ensure the performance of high-speed coding calculation, improving the utilization rate of hardware resources and balancing the computing speed and hardware resource consumption.

[0184] Figure 8 It is a schematic flowchart of the encoding method of the polar code provided by the third embodiment of the present disclosure.

[0185] As Figure 8 shown, the method includes:

[0186] S401: Determine the first data sequence after cyclic redundancy check.

[0187] Among them, cyclic redundancy check (CRC) is a method used to detect possible errors after data transmission or storage.

[0188] Among them, the first data sequence can be the data obtained by performing CRC check on the input information. It should be noted that the CRC check can be directly performed on the input information, or after dividing the input information into code blocks, the CRC check is performed on the code blocks, and this is not limited here.

[0189] Optionally, when the code length of the input information is less than or equal to the second threshold, the input information can be directly subjected to cyclic redundancy check without division, so as to obtain the first data sequence.

[0190] Among them, the input information can be any type of information, such as request information, control information, scheduling information, etc., and this is not limited here.

[0191] As a possible implementation, the input information can be uplink control information (Uplink Control Information, UCI), and this is not limited here.

[0192] Furthermore, the input information can be the payload part in UCI data, that is, the valid data part (UCI payload) included in the uplink control information, and this is not limited here.

[0193] It should be noted that UCI is important information sent by the user equipment (UE) to the base station, which can include ACK / NACK (acknowledgment / non-acknowledgment), SR (scheduling request), CSI (channel state information), etc. The processing of this information involves operations such as rate matching, coding, cyclic redundancy check, etc. to ensure the reliable transmission of information.

[0194] Optionally, when the code length of the input information is greater than the second threshold, according to the code length of the input information and the code length after rate matching, the input information can be divided into at least one code block, and then the cyclic redundancy check is performed on the code block to obtain the first data sequence corresponding to the code block.

[0195] Among them, at least one code block means that the number of code blocks can be 1, 2, or more, and this is not limited here.

[0196] Among them, the second threshold can be the threshold of the code length of the input information, such as it can be 12, and this is not limited here.

[0197] As a possible implementation, the cyclic redundancy check can be performed on each code block to detect possible errors during the transmission process.

[0198] Among them, the data length corresponding to the first data sequence can be calculated by the following formula:

[0199] K = A + c

[0200] Wherein, A is the original number of bits of a code block (CB), c is the number of CRC check bits (such as 6 or 11), and K is the data length of the first data sequence, that is, the data length of the code block after adding CRC.

[0201] Optionally, the first data sequence can be stored in the first register bank.

[0202] As an example, the first register bank can be denoted as crc_reg_cb. If the input information is divided into two code blocks, the first data sequences after CRC check of the two code blocks can be stored in crc_reg_cb0 and crc_reg_cb1 respectively, which is not limited herein.

[0203] S402: Determine the initial encoding according to the type tag of the channel in the second data sequence and the first data sequence.

[0204] Wherein, the type tag is used to represent the channel type to which the channel belongs, such as a data channel, an invalid channel, and a PC channel, which is not limited herein.

[0205] Wherein, the data channel refers to the physical path or logical connection used to transmit data in a communication system, which is responsible for transmitting the data bit stream and ensuring the reliable transmission of data between the sender and the receiver, which is not limited herein.

[0206] Wherein, the invalid channel usually refers to the channel that is not suitable or cannot work properly in the communication system, which is not limited herein.

[0207] Wherein, the PC channel is used to place PC (Parity Check) bits. The PC bit is an additional bit used for parity check. In parity check, in order to detect single-bit errors during transmission, a parity check bit is usually appended to the data block.

[0208] Wherein, the second data sequence can be an initialization data sequence with the same encoding length as the target encoding. For example, if the length of the target encoding is 1024, the second data sequence can be an array with a length of 1024, and each value in the array is 0, which is not limited herein.

[0209] It can be understood that the channels in the second data sequence can be classified in advance. For example, they can be classified according to data channels, invalid channels, and PC channels, so as to determine the type tag to which each channel belongs.

[0210] As a possible implementation, the type tag can be embodied in the form of a bitmap. For example, if the bitmap corresponding to channel x1 is 0, the type tag of this channel x1 is an invalid channel; if the bitmap corresponding to channel x2 is 1, the type tag of this channel x2 is a data channel; if the bitmap corresponding to channel x3 is 2, the type tag of this channel x3 is a PC channel, which is not limited here.

[0211] As a possible implementation, when determining the initial coding according to the type tags of the channels in the second data sequence and the first data sequence, it can be implemented according to the following steps:

[0212] First, initialize the cyclic shift register, then read the type tags of the channels in the second data sequence in sequence. After that, when the type tag of any channel is an invalid channel, set the output of the cyclic shift register to zero. Or, when the type tag of any channel is a PC channel, use the value of the first bit in the cyclic shift register as the output value. Or, when the type tag of any channel is a data channel, read the second value from the first data sequence in order as the output value. Then, in response to traversing each channel in the second data sequence, determine the initial coding according to the output values of the cyclic shift register.

[0213] Optionally, after reading the second value from the first data sequence in order as the output value, the second value and the value of the current first bit in the cyclic shift register can also be subjected to an exclusive OR operation to obtain an operation result, and then the operation result is stored in the original position of the cyclic shift register.

[0214] Among them, the second value can be the value read from the first data sequence when encoding through the cyclic shift register.

[0215] Among them, the cyclic shift register is characterized in that when performing a shift operation, the shifted data will be reloaded to the other end of the register, forming a closed data channel. In this way, the data will perform cyclic shift inside the register. Its working principle can be described as: when the clock signal changes, each bit of data in the register will move one bit in the specified direction (left or right), and the shifted data will be reloaded to the other end of the register.

[0216] Exemplarily, in the embodiments of the present disclosure, the cyclic shift register can be a 5-bit cyclic right shift register, which is not limited here.

[0217] The following will give an example to illustrate the above process. Assume that the selected cyclic shift register is a 5-bit cyclic right shift register, the length of the second data sequence is 5, the bitmaps corresponding to the 5 channels are 1, 2, 0, 0, 2 respectively, and the first data sequence is "10111010".

[0218] First, initialize the cyclic shift register. At this time, the state of the cyclic shift register is "00000".

[0219] Round 1: First, read the bitmap of the first channel in the second data sequence, which is 1. This channel is a data channel, so the value of the first bit in the first data sequence can be read in order as the output value. The value of the first bit in the first data sequence is "1", so the first output value is "1".

[0220] Then, perform an exclusive OR operation on the output value "1" and the value "0" of the first bit in the cyclic shift register to get "1". Then, update the value of the first bit in the cyclic shift register based on this value "1". At this time, the state of the cyclic shift register is "10000", and it is shifted right by 1 bit. At this time, the state of the cyclic shift register is "01000".

[0221] Round 2: Read the bitmap of the second channel in the second data sequence, which is 2. This channel is a PC channel, so the value of the first bit in the cyclic shift register can be used as the output value. At this time, the value of the first bit in the cyclic shift register is "0", so the second output value is "0".

[0222] Then, shift the cyclic shift register right by 1 bit. At this time, the state of the cyclic shift register is "00100".

[0223] Round 3: Read the bitmap of the third channel in the second data sequence, which is 0. This channel is an invalid channel, so the output value of the cyclic shift register can be set to zero. Therefore, the third output value is "0".

[0224] Then, shift the cyclic shift register right by 1 bit. At this time, the state of the cyclic shift register is "00010".

[0225] Round 4: Read the bitmap of the fourth channel in the second data sequence, which is 0. This channel is an invalid channel, so the output value of the cyclic shift register can be set to zero. Therefore, the fourth output value is "0".

[0226] Then, shift the cyclic shift register right by 1 bit. At this time, the state of the cyclic shift register is "00001".

[0227] Round 5: Read the bitmap of the 5th channel in the second data sequence, which is 2. This channel is a PC channel. Therefore, the value of the 1st bit in the cyclic shift register can be used as the output value. At this time, the value of the 1st bit in the cyclic shift register is "0". Therefore, the 5th output value obtained is "0".

[0228] Then, shift the cyclic shift register to the right by 1 bit. At this time, the state of the cyclic shift register is "10000".

[0229] In summary, after traversing the type tags of the channels in the second data sequence, the obtained output values are "1", "0", "0", "0", "0" respectively. At this time, the initial coding is 10000.

[0230] It should be noted that in actual coding, the lengths of the target coding and the initial coding are usually relatively long. The above example is only for illustrative purposes and does not limit the present disclosure.

[0231] S403: Process the initial coding based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target coding, where the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

[0232] It should be noted that the specific implementation manner of step S403 can refer to the above embodiments and will not be elaborated here.

[0233] In the embodiments of the present disclosure, first, a first data sequence after cyclic redundancy check is determined. Then, based on the type tags of the channels in the second data sequence and the first data sequence, an initial coding is determined. Then, the initial coding is processed based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target coding, where the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold. Thus, through cyclic redundancy check, errors in transmission can be effectively detected and in some cases corrected, improving the reliability of data transmission. Thus, through CRC check, the transmission quality of the first data sequence is first ensured. The use of channel type tags further ensures data processing and optimization under different channel conditions, improving the accuracy and reliability of data transmission.

[0234] Figure 9 It is a diagram of an application scenario of Polar coding in 5G-NR. As Figure 9As shown, the part within the dashed box is the main process of Polar coding. Among them, the Polar enc stage includes Polar_pre (pre - processing before Polar coding) and Polar coding calculation. Among them, the Rate Matching stage includes sub - block interleaving, rate matching, and channel interleaving. Among them, Multiplexing represents time - frequency domain resource multiplexing. After that, it also needs to go through the processes of Modulation and IFFT (Inverse Fast Fourier Transform).

[0235] Figure 10 It is a schematic flowchart of an encoding method for a polar code provided according to the fifth embodiment of the present disclosure.

[0236] As Figure 10 shown, the method includes:

[0237] S501: Determine a first data sequence after cyclic redundancy check.

[0238] It should be noted that the specific implementation manner of step S501 can refer to the above - mentioned embodiments and will not be elaborated here.

[0239] S502: Based on a preset judgment condition, judge whether each channel in the second data sequence is a valid channel to obtain a judgment result.

[0240] Among them, the preset judgment condition can be a condition pre - configured for judging whether a channel is a valid channel.

[0241] Among them, the judgment result can be a judgment result that the channel is an invalid channel or a valid channel.

[0242] As a possible implementation manner, it is possible to first judge whether the index value of each channel in the second data sequence exceeds a threshold value. If it does not exceed the threshold value, the channel corresponding to the index value is regarded as an invalid channel. In addition, during the rate matching process, situations of shortening or "puncturing" may occur, that is, some positions may be deleted or set to zero after coding. If the interleaved channel index value is located at these deleted or zero - set positions, then this channel can be regarded as an invalid channel.

[0243] For example, if the threshold value is 200, each channel with an index value less than 200 can be regarded as an invalid channel. For instance, if the index value corresponding to channel A is 80, it can be determined that the judgment result corresponding to channel A is an invalid channel, which is not limited here.

[0244] For example, assume that during the encoding process, among the interleaved channel index values, the channel B corresponding to the index value "322" may be punctured and removed, and the channel C corresponding to the index value "350" may be deleted due to rate matching shortening. The channels corresponding to these positions will thus be deleted or set to zero. Therefore, channels B and C can be regarded as invalid channels and are not limited herein.

[0245] Among them, the threshold value can be preset and can be determined according to the code length after rate matching and the length after encoding, which is not limited herein. Generally speaking, the code length after rate matching and the length after encoding can determine the minimum value that the channel index value needs to reach.

[0246] It should be noted that through the above judgment method, it is possible to judge whether each channel in the second data sequence is a valid channel or an invalid channel.

[0247] S503: Based on the reference channel reliability information and the judgment result, determine the type label corresponding to each channel in the second data sequence.

[0248] Among them, the reference channel reliability information may contain the reliability information corresponding to different channels. Among them, the manifestation form of the reference channel reliability information can be an array, a table, or a line chart, which can pre-record the reliability corresponding to each channel and is not limited herein.

[0249] As an example, the reference channel reliability information can be a channel reliability list.

[0250] The following takes the channel reliability list as an example for illustration. Different channel reliabilities can be recorded in the channel reliability list.

[0251] Among them, the higher the reliability of the channel, the better the quality and performance of the channel. The lower the reliability of the channel, the worse the quality and performance of the channel.

[0252] For example, assume that the reliabilities recorded in the channel reliability list are as follows:

[0253] Index value 0: Reliability 0.85

[0254] Index value 1: Reliability 0.92

[0255] Index value 2: Reliability 0.78

[0256] Index value 3: Reliability 0.91

[0257] Index value 4: Reliability 0.87

[0258] Index value 5: Reliability 0.89

[0259] Since it can be determined from the judgment result that the index values 1, 4, and 5 are valid channels, their corresponding channel reliabilities can be directly found according to the channel reliability list: the reliability of channel index value 1 is 0.92, the reliability of channel index value 4 is 0.87, and the reliability of channel index value 5 is 0.89.

[0260] Furthermore, the type label corresponding to each channel can be determined according to the channel reliability corresponding to the valid channel.

[0261] As a possible implementation, the type label corresponding to the invalid channel can be determined as the invalid channel according to the judgment result. After that, according to the reliability of each valid channel, when the channel reliability is low (for example, less than the set threshold), its type label can be determined as the invalid channel, and when the channel reliability is high (for example, greater than or equal to the set threshold), its type label can be determined as the data channel, which is not limited here.

[0262] S504: Determine the initial encoding according to the type label of the channel in the second data sequence and the first data sequence.

[0263] S505: Process the initial encoding based on a preset encoding rule, a first encoder, and at most a first number of first XOR gates to obtain a target encoding, where the first encoder uses a combinational logic circuit, and the number of input and output terminals of the first encoder is greater than the first threshold.

[0264] It should be noted that the specific implementation manners of steps S504 and S505 can refer to the above embodiments and will not be elaborated here.

[0265] In the embodiments of the present disclosure, first, a first data sequence after cyclic redundancy check is determined. Then, based on a preset judgment condition, it is judged whether each channel in the second data sequence is a valid channel to obtain a judgment result. After that, based on the reference channel reliability information and the judgment result, the type label corresponding to each channel in the second data sequence is determined. Then, based on the type label of the channel in the second data sequence and the first data sequence, an initial encoding is determined. Finally, based on a preset encoding rule, a first encoder, and at most a first number of first exclusive-OR gates, the initial encoding is processed to obtain a target encoding, where the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold. Thus, through CRC check and channel validity judgment, the integrity and reliability of data during transmission are ensured, and data corruption or loss caused by transmission errors is reduced. Since at most a first number of first exclusive-OR gates are required to process the initial encoding, fewer exclusive-OR gate resources can be used to ensure the performance of high-speed encoding calculation, improving the utilization rate of hardware resources and balancing the calculation speed and hardware resource consumption. According to the channel type label and the preset encoding rule, the data is optimized, making the data transmission more efficient and adaptable to the requirements of different application scenarios. In summary, this encoding process not only improves the reliability and efficiency of data transmission by combining CRC check, channel judgment, type label assignment, and optimized encoding processing, but also effectively manages and utilizes system resources, thereby achieving the purpose of improving the overall performance of the system.

[0266] Figure 11 FIG. 4 is a schematic flowchart of an encoding method for a polar code according to the sixth embodiment of the present disclosure.

[0267] As Figure 11 shown, the method includes:

[0268] S601: Determine a first data sequence after cyclic redundancy check.

[0269] S602: Based on a preset judgment condition, judge whether each channel in the second data sequence is a valid channel to obtain a judgment result.

[0270] It should be noted that the specific implementation manners of steps S601 and S602 can refer to the above embodiments and will not be elaborated herein.

[0271] S603: In the case where the judgment results corresponding to one or more channels in the second data sequence are non-valid channels, determine the type labels of the one or more channels as invalid channels.

[0272] For example, if the channels included in the second data sequence are S1, S2, S3, S4, S5, S6, S7, S8, S9, and S10 respectively. Among them, the judgment results corresponding to S9 and S10 are non-effective channels, then the type tags of S9 and S10 can be determined as invalid channels. Among them, the type tags corresponding to S1, S2, S3, S4, S5, S6, S7, and S8 can be further judged through the following steps.

[0273] S604: According to the reference channel reliability information, sort the effective channels in the second data sequence according to the reliability level from high to low, and obtain the sorted effective channel sequence.

[0274] Among them, the effective channel sequence can be a sequence of numbers obtained by sorting each effective channel according to the reliability level from high to low. It can be arranged in the order of reliability from high to low or from low to high, which is not limited here.

[0275] Among them, the reference channel reliability information may contain the reliability information corresponding to different channels. Among them, the manifestation form of the reference channel reliability information can be an array, a table or a line chart, which can pre-record the reliability corresponding to each channel, which is not limited here.

[0276] As an example, the reference channel reliability information can be a channel reliability list.

[0277] The following takes the channel reliability list as an example to illustrate. The channel reliability list can record the reliability of different channels.

[0278] Among them, the higher the reliability of the channel, the better the quality and performance of the channel. The lower the reliability of the channel, the worse the quality and performance of the channel.

[0279] For example, assume that the reliabilities corresponding to the effective channels S1, S2, S3, S4, S5, S6, S7, and S8 in the channel reliability list are as follows:

[0280] S1: Reliability 0.85

[0281] S2: Reliability 0.92

[0282] S3: Reliability 0.78

[0283] S4: Reliability 0.91

[0284] S5: Reliability 0.87

[0285] S6: Reliability 0.89

[0286] S7: Reliability 0.65

[0287] S8: Reliability 0.74

[0288] Further, according to the reliabilities of the above respective effective channels, they can be sorted in descending order of reliability, that is, the effective channel sequence: S2, S4, S6, S5, S1, S3, S8, S7.

[0289] It should be noted that the above example is only for illustrative purposes and does not limit the present disclosure.

[0290] S605: Determine the first value corresponding to the minimum row weight parity check PC bit.

[0291] Among them, the minimum row weight parity check bit refers to the minimum number of 1s in the check bits in the parity check code. Its value is usually 0 or 1, depending on the parity of the number of 1s in the data word.

[0292] Specifically: If the number of 1s in the data word is even, the minimum row weight parity check bit can be 0. If the number of 1s in the data word is odd, the minimum row weight parity check bit can be 1. The function of this parity check is to ensure that even or odd numbers of "1" errors can be detected during data transmission, so as to improve the reliability and integrity of data transmission.

[0293] Among them, the first value can be the value corresponding to the minimum row weight PC bit, that is, "0" or "1".

[0294] S606: Based on the first value, determine the type labels of each effective channel in the effective channel sequence.

[0295] Among them, the first preset value and the second preset value are different. As an example, the first preset value can be 0 and the second preset value can be 1, which is not limited herein.

[0296] Optionally, when the first value is the first preset value, determine that the type labels of the first K effective channels in the effective channel sequence are data channels, and determine that the type labels of the other effective channels are PC channels.

[0297] For example, if the data length of the effective channel sequence is 40, the first value is 0, and K = 35. Since the first value is equal to the first preset value, the type labels of the first 35 effective channels in the effective channel sequence can be determined as data channels. For the remaining effective channels, that is, the last 5 effective channels with relatively low reliability, their corresponding type labels can be used as PC channels, which is not limited herein.

[0298] Optionally, when the first value is the second preset value, determine the type label corresponding to each effective channel based on the coding length of the first data sequence.

[0299] It should be noted that for different coding lengths, the rules for selecting PC channels may be different. For example, a threshold value can be set. When the coding length is less than or equal to this threshold value, the preset first rule is used to determine the PC channels in the valid channel sequence. When the coding length is greater than this threshold value, the preset second rule is used to determine the PC channels in the valid channel sequence.

[0300] For example, if the valid channel sequence is S1, S2, S3, S4, S5 and the threshold value is 21, when the coding length of the first data sequence is less than or equal to 21, S4 and S5 are taken as PC channels, and S1, S2 and S3 are taken as data channels. For example, when the coding length of the first data sequence is greater than 21, S1 and S5 are taken as PC channels, and S2, S3 and S4 are taken as data channels.

[0301] Among them, the first rule and the second rule can be determined according to specific communication protocols. Only examples are given here and it is not a limitation to the present disclosure.

[0302] S607: Determine the initial coding according to the type tags of the channels in the second data sequence and the first data sequence.

[0303] S608: Process the initial coding based on a preset coding rule, a first encoder and at most a first number of first XOR gates to obtain a target coding, wherein the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold value.

[0304] It should be noted that the specific implementation manners of steps S607 and S608 can refer to the above embodiments and will not be elaborated here.

[0305] In the embodiments of the present disclosure, first, a first data sequence after cyclic redundancy check is determined. Then, based on a preset judgment condition, it is judged whether each channel in the second data sequence is a valid channel to obtain a judgment result. After that, in the case where the judgment results corresponding to one or more channels in the second data sequence are non-valid channels, the type tags of the one or more channels are determined as invalid channels. Then, according to the reference channel reliability information, the valid channels in the second data sequence are sorted according to the reliability level from high to low to obtain a sorted valid channel sequence. After that, a first value corresponding to the minimum row weight parity check PC bit is determined. Then, based on the first value, the type tag of each valid channel in the valid channel sequence is determined. Then, according to the type tags of the channels in the second data sequence and the first data sequence, an initial coding is determined. Finally, based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates, the initial coding is processed to obtain a target coding, where the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold. In summary, first, the first data sequence is checked by CRC to detect and correct transmission errors and ensure the integrity and accuracy of the data. According to the channel information in the second data sequence, it is judged whether each channel is a valid channel. This step ensures that only valid channels are included in subsequent processing and avoids invalid data from affecting the coding result. According to the reference channel reliability information, the valid channels are sorted from high to low according to the reliability. This helps to preferentially process the data of more reliable channels and improve the overall transmission quality and efficiency. According to the first data sequence and the type tags of the channels in the second data sequence determined to be valid channels, an initial coding is determined. This step ensures that a suitable coding method is selected according to the channel characteristics to maximize the efficiency and reliability of data transmission. During the coding process, the exclusive-OR gate resources used are controlled below a preset first threshold. This indicates that the effective utilization of hardware resources is considered when designing the coding scheme, reducing system overhead and energy consumption while maintaining the efficiency of the coding process. According to the result of the parity check, the data integrity and correctness of each valid channel are further ensured. This method can improve the security of data transmission and reduce the probability of transmission errors. It not only improves the reliability and security of data transmission but also optimizes the resource utilization of the system and is applicable to application scenarios with high requirements for data transmission quality.

[0306] Figure 12 It is a schematic flowchart of an encoding method of a polar code according to the seventh embodiment of the present disclosure.

[0307] As Figure 12 shown, the method includes:

[0308] S701: Determine a first data sequence after cyclic redundancy check.

[0309] S702: Based on the preset judgment conditions, determine whether each channel in the second data sequence is a valid channel to obtain a judgment result.

[0310] S703: In the case where the judgment results corresponding to one or more channels in the second data sequence are non-valid channels, determine the type labels of the one or more channels as invalid channels.

[0311] S704: According to the reference channel reliability information, sort the valid channels in the second data sequence in descending order of reliability to obtain a sorted valid channel sequence.

[0312] S705: Determine the first value corresponding to the minimum row weight parity check PC bit.

[0313] It should be noted that the specific implementation manners of steps S701 - S705 can refer to the above embodiments and will not be elaborated here.

[0314] S706: In the case where the coding length of the first data sequence is less than or equal to the third threshold, determine the type label of the channel corresponding to the first channel index as the PC channel.

[0315] Among them, the third threshold can be the threshold of the coding length of the first data sequence.

[0316] As an example, the third threshold can be 21, which is not limited herein.

[0317] Among them, the first channel index is the specified channel index value. In the embodiments of the present disclosure, the first channel index can be 252, which is not limited herein.

[0318] For example, denote the coding length of the first data sequence as K, the third threshold as 12, and the first channel index as 252. If K ≤ 12, then the type label of the channel with the index value of "252" can be determined as the PC channel.

[0319] S707: Determine the type labels of the last N valid channels in the valid channel sequence as the PC channels, where N is the third preset value.

[0320] Among them, N is the third preset value. In the embodiments of the present disclosure, the third preset value can be 2, which is not limited herein.

[0321] For example, if N = 2, then the last 2 valid channels in the valid channel sequence, that is, the 2 channels with the lowest reliability, can be used as the PC channels.

[0322] S708: Determine the type labels of each valid channel other than the PC channels in the valid channel sequence as data channels.

[0323] For example, if the effective channel sequence includes channels S1, S2, S3, S4, S5, S6, S7, S8, and among them, S6, S7, S8 have been determined as PC channels, then the type tags of S1, S2, S3, S4, S5 can be determined as data channels.

[0324] It should be noted that the above example is only an illustrative explanation and does not constitute a limitation to the present disclosure.

[0325] S709: When the coding length of the first data sequence is greater than the third threshold, determine the type tag of the channel corresponding to the second channel index as a PC channel, where the second channel index is less than the first channel index.

[0326] Among them, the second channel index is a specified channel index value. In the embodiments of the present disclosure, the second channel index can be 248, which is not limited herein.

[0327] For example, denote the coding length of the first data sequence as K, the third threshold as 12, and the first channel index as 248. If K > 12, then the type tag of the channel with the index value of "248" can be determined as a PC channel.

[0328] S710: Determine the type tags of the last N effective channels in the effective channel sequence as PC channels.

[0329] Among them, N is the third preset value. In the embodiments of the present disclosure, the third preset value can be 2, which is not limited herein.

[0330] For example, if N = 2, then the last 2 effective channels in the effective channel sequence, that is, the 2 channels with the lowest reliability, can be used as PC channels.

[0331] S711: Determine the type tags of each effective channel other than the PC channels in the effective channel sequence as data channels.

[0332] For example, if the effective channel sequence includes channels S1, S2, S3, S4, S5, S6, S7, S8, and among them, S6, S7, S8 have been determined as PC channels, then the type tags of S1, S2, S3, S4, S5 can be determined as data channels.

[0333] S712: Determine the initial coding according to the type tags of the channels in the second data sequence and the first data sequence.

[0334] S713: Process the initial coding based on a preset coding rule, a first encoder, and at most a first number of first XOR gates to obtain a target coding, where the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than the first threshold.

[0335] It should be noted that the specific implementation manners of steps S710 - S713 may refer to the above embodiments, and will not be elaborated herein.

[0336] In the embodiments of the present disclosure, first, a first data sequence after cyclic redundancy check is determined. Then, based on a preset judgment condition, it is judged whether each channel in the second data sequence is a valid channel to obtain a judgment result. After that, when the judgment results corresponding to one or more channels in the second data sequence are non-valid channels, the type labels of the one or more channels are determined as invalid channels. Then, according to the reference channel reliability information, the valid channels in the second data sequence are sorted in descending order of reliability to obtain a sorted valid channel sequence. After that, a first value corresponding to the minimum row weight parity check PC bit is determined. Then, when the coding length of the first data sequence is less than or equal to a third threshold, the type label of the channel corresponding to the first channel index is determined as the PC channel. Then, the type labels of the last N valid channels in the valid channel sequence are determined as the PC channels. After that, the type labels of each valid channel other than the PC channels in the valid channel sequence are determined as data channels. When the coding length of the first data sequence is greater than the third threshold, the type label of the channel corresponding to the second channel index is determined as the PC channel, where the second channel index is less than the first channel index. Then, the type labels of the last N valid channels in the valid channel sequence are determined as the PC channels. Then, the type labels of each valid channel other than the PC channels in the valid channel sequence are determined as data channels. Finally, according to the type labels of the channels in the second data sequence and the first data sequence, an initial coding is determined. Based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates, the initial coding is processed to obtain a target coding, where the first encoder uses a combinational logic circuit, and the number of input and output terminals of the first encoder is greater than a first threshold. Thus, first, the first data sequence is verified by CRC to ensure that errors can be detected and corrected during data transmission, thereby guaranteeing the integrity and accuracy of the data. According to the preset judgment condition, the effectiveness of each channel in the second data sequence is judged. This step ensures that only valid channels are included in subsequent processing, excluding the influence of invalid channels. In the second data sequence, if a certain channel is judged to be invalid, its type label is determined as an invalid channel and will no longer be processed. According to the reliability list of the channels, the valid channels in the second data sequence are sorted in descending order of reliability. This helps to preferentially process the data of the most reliable channels and improve the overall quality of data transmission. By parity check, the data of each valid channel is checked to ensure its integrity and correctness, which helps to reduce errors during transmission and enhance the security of data transmission. Based on the first data sequence and the type labels of the channels in the second data sequence determined to be valid channels, an initial coding scheme is determined, which ensures that a suitable coding method is selected according to the characteristics of each channel to optimize the efficiency and reliability of data transmission to the greatest extent.Since at most the first quantity of first exclusive-OR gates are required to implement the processing of the initial encoding, fewer exclusive-OR gate resources can be used to ensure the performance of high-speed encoding calculation, improve the utilization rate of hardware resources, and balance the calculation speed and hardware resource consumption.

[0337] Figure 13 It is a schematic flowchart of an encoding method for a polar code provided according to the eighth embodiment of the present disclosure.

[0338] As Figure 13 shown, the method includes:

[0339] S801: In response to the completion of the first execution stage of the first task, start the second execution stage of the first task and the first execution stage of the second task,

[0340] wherein, the first execution stage of the task is used to determine the first data sequence after cyclic redundancy check, and the type label of the channel in the second data sequence,

[0341] The second execution stage of the task is used to determine the initial encoding according to the type label of the channel in the second data sequence and the first data sequence, and the first task and the second task are different.

[0342] It should be noted that the specific implementation manners of the first execution stage and the second execution stage can refer to the descriptions in the above respective embodiments, and will not be elaborated here.

[0343] Among them, both the first task and the second task are used to obtain the initial encoding, and the first task and the second task belong to different tasks.

[0344] Optionally, the first execution stage includes a first sub-stage and a second sub-stage,

[0345] The first sub-stage is used to: based on a preset judgment condition, judge whether each channel in the second data sequence is a valid channel to obtain a judgment result, and store the judgment results corresponding to each channel in the second register group;

[0346] The second sub-stage is used to: determine the first data sequence after cyclic redundancy check;

[0347] Among them, during the execution of a single task, the second sub-stage is started after the first sub-stage.

[0348] Optionally, the first execution stage further includes a third sub-stage, and the second sub-stage and the third sub-stage are processed in parallel,

[0349] The third sub-stage is used to: based on the reference channel reliability information and the judgment result, determine the type label corresponding to each channel in the second data sequence.

[0350] It should be noted that the specific implementation manners of the first sub-stage, the second sub-stage, and the third sub-stage can refer to the above embodiments, and will not be elaborated here.

[0351] Figure 14 It is a timing flowchart of polar_pre for multi-tasks, where polar_pre refers to the preprocessing stage of polar coding. As Figure 14 shown, task0 and task1 can be processed in parallel. Denote task0 as the first task and task1 as the second task. Among them, in the first execution stage of the first task, that is, the stage where task0 executes get_vld_chl, get_mot_chl, and cb_crc. After the first execution stage ends, task0 needs to start the pc_enc stage, that is, the second execution stage. At this time, the second execution stage of task0 can be started simultaneously with the first execution stage of task1, that is, start at the same time.

[0352] Figure 15 It is a schematic diagram of the read-write relationship of a register bank. Among them, crc_reg_cb is the first register bank, and chl_vld_reg is the second register bank. chl_vld_reg is used to store the type tags of the channels, that is, the bitmap corresponding to the channels.

[0353] Among them, crc_reg_cb0 / 1 is used to store the data after CRC verification of two code blocks.

[0354] As a possible implementation manner, for the convenience of being read by 16 parallel coding calculation modules, the width can be set to 16bit. It can be understood that if the maximum length after adding CRC to each code block is 1024 points, then the depth of the first register bank can be 1024 / 16 = 64. Figure 15 The 2*64w*16b in represents two crc_reg_cb with a width of 16 and a depth of 64.

[0355] As a possible implementation manner, the type tag of the channel, that is, the bitmap corresponding to the channel, is 2bit. If the maximum number of channels is 1024, then the depth of the second register bank chl_vld_reg can be 1024 and the width can be 2. Figure 15 The 1024w*2b in represents chl_vld_reg with a width of 2 and a depth of 1024.

[0356] Figure 15The read-write relationship shown is that based on crc_reg_cb0 / 1, the data processed by cb_crc is stored, and based on chl_vld_reg, the data processed by get_vld_chl is stored. get_mot_vld reads data from chl_vld_reg and then writes data. pc_enc reads the data in crc_reg_cb0 / 1 and the data after get_vld_chl is updated.

[0357] As Figure 16 shown, Figure 16 it is a flowchart of an overall Polar coding scheme. Among them, the first sub-stage corresponds to get_vld_chl in the figure, the second sub-stage corresponds to cb_crc in the figure, and the third sub-stage corresponds to get_mot_chl in the figure.

[0358] Among them, cb_crc can be started after get_vld_chl. Since get_vld_chl may be processed in parallel with pc_enc of the previous task, and pc_enc needs to use the data of cb_crc, so cb_crc cannot be processed in parallel with get_vld_chl.

[0359] It should be noted that since the maximum calculation delay of cb_crc and get_mot_vld is the same, in a single task, cb_crc and get_mot_vld can be processed in parallel.

[0360] As a possible implementation method, in a single task, the parallelism of the first sub-stage get_vld_chl and the third stage get_mot_chl can be 4-way parallel, that is, 4-bit data can be processed in 1 clock cycle. Among them, the parallelism of the second sub-stage cb_crc can be 8-way parallel, that is, 8-bit data can be processed in 1 clock cycle.

[0361] Figure 16 The parallelism of pc_enc in can be 16-way parallel, that is, 16-bit data can be processed in 1 clock cycle.

[0362] It can be understood that when multiple tasks are executed, pc_enc of the previous task and get_vld_chl of the next task can be processed in parallel. This is because, in the second execution stage, the read and write of pc_enc and the first sub-stage get_vld_chl to the second register group chl_vld_reg are both in address order, and the read parallelism of pc_enc is higher and it reads faster.

[0363] Therefore, after starting pc_enc, get_vld_chl can be started simultaneously. The data in chl_vld_reg is always read first and then written, so that the situation where the data that pc_enc needs to read has not been read yet and is overwritten by the data written by get_vld_chl of the next task will not occur.

[0364] Among them, after the previous task starts pc_enc, get_vld_chl in the next uci-level task in the pipeline can be started simultaneously.

[0365] It should be noted that in polar_pre, get_vld_chl and get_mot_chl share the register bank, and the required number of register bits is reduced by 1024 bits. Within a single task, cb_crc and chl_mot_vld are processed in parallel, and between tasks, get_vld_chl and pc_enc are processed in parallel, reducing the calculation delay by 256 + 64 = 320 clock cycles compared to serial processing.

[0366] Next, Figure 16 the overall process of the overall Polar coding scheme flowchart shown will be described.

[0367] First, after receiving the input information UCI payload, the first data sequence is obtained through cb_crc, then the second data sequence is used as the input of get_vld_chl, and then it is processed through get_mot_chl. pc_enc obtains the initial coding based on the first data sequence determined by cb_crc and the type tags of each channel in the second data sequence determined by get_mot_chl, and then obtains the target coding through polar_enc. Further, it enters the Rate Matching (rate matching module), and finally writes the Polar coding into the storage unit through blk_itl, rm, chl_itl, and multiplexing.

[0368] Among them, blk_itl, rm, chl_itl, and multiplexing respectively represent sub-block interleaving, rate matching, channel interleaving, and time-frequency domain resource multiplexing.

[0369] In an embodiment of the present disclosure, in response to the completion of the first execution stage of the first task, the second execution stage of the first task and the first execution stage of the second task are started, where the first execution stage of the task is used to determine the first data sequence after cyclic redundancy check and the type label of the channel in the second data sequence, and the second execution stage of the task is used to determine the initial coding according to the type label of the channel in the second data sequence and the first data sequence, and the first task and the second task are different. Thus, multi-parallel processing within the task and pipeline processing between tasks for the preprocessing of polar coding are realized, the coding speed is improved, it is applicable to the high-performance requirements in industrial implementation, and while improving the parallelism, resource reuse is fully considered.

[0370] Figure 17 is a schematic diagram of an encoding device for a polar code according to an embodiment of the present disclosure. As Figure 17 shown, the encoding device 900 of the polar code includes:

[0371] An acquisition module 910, configured to acquire an initial coding;

[0372] A processing module 920, configured to process the initial coding based on a preset coding rule, a first encoder, and at most a first number of first exclusive-OR gates to obtain a target coding,

[0373] wherein, the first encoder adopts a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

[0374] Optionally, the processing module includes:

[0375] A first processing unit, configured to input at least one initial coding into the first encoder according to a first clock order to obtain a first coding result corresponding to the initial coding;

[0376] A first determination unit, configured to determine a target coding based on at least one of the first coding results and the at most first number of first exclusive-OR gates.

[0377] Optionally, the first determination unit is specifically configured to:

[0378] If the index value of any clock cycle in the first clock order satisfies a first condition, determine that the any clock cycle is a target clock cycle;

[0379] Determine the adjacent previous clock cycles of at least one of the target clock cycles;

[0380] Perform an exclusive-OR operation on the first coding result corresponding to the adjacent previous clock cycle and the first coding result of the target clock cycle to obtain a second coding result corresponding to the target clock cycle;

[0381] Determine a target encoding based on at least one of the first encoding results, the at most first number of exclusive-OR gates, and the second encoding result corresponding to the target clock cycle.

[0382] Optionally, the first determination unit is further configured to:

[0383] Construct a first encoder according to an encoding matrix corresponding to the encoding length of the initial encoding.

[0384] Optionally, the acquisition module includes:

[0385] A second determination unit for determining a first data sequence after cyclic redundancy check;

[0386] A third determination unit for determining an initial encoding according to the type label of the channel in the second data sequence and the first data sequence.

[0387] Optionally, the second determination unit is specifically configured to:

[0388] In the case where the code length of the input information is greater than a second threshold, divide the input information into at least one code block according to the code length of the input information and the rate-matched code length;

[0389] Perform cyclic redundancy check on the code block to obtain the first data sequence corresponding to the code block.

[0390] Optionally, the third determination unit further includes:

[0391] A first judgment subunit for judging whether each channel in the second data sequence is a valid channel based on a preset judgment condition to obtain a judgment result;

[0392] A first determination subunit for determining the type label corresponding to each channel in the second data sequence based on the reference channel reliability information and the judgment result.

[0393] Optionally, the first determination subunit includes:

[0394] A first determination sub-module for determining the type label of one or more channels as an invalid channel in the case where the judgment result corresponding to one or more channels in the second data sequence is a non-valid channel;

[0395] A sorting sub-module for sorting the valid channels in the second data sequence according to the reference channel reliability information in descending order of reliability to obtain a sorted valid channel sequence;

[0396] A first numerical value determination sub-module for determining a first numerical value corresponding to the minimum row weight parity check PC bit;

[0397] A second determination sub-module, configured to determine a type label of each valid channel in the valid channel sequence based on the first value.

[0398] Optionally, the second determination sub-module is specifically configured to:

[0399] When the first value is a first preset value, determine that the type labels of the first K valid channels in the valid channel sequence are data channels, and determine that the type labels of other valid channels are PC channels, where K is a positive integer;

[0400] Or,

[0401] When the first value is a second preset value, determine the type label of each valid channel based on the coding length of the first data sequence.

[0402] Optionally, the second determination sub-module is specifically configured to:

[0403] When the coding length of the first data sequence is less than or equal to a second threshold, determine that the type label of the channel corresponding to the first channel index is a PC channel;

[0404] Determine that the type labels of the last N valid channels in the valid channel sequence are PC channels, where N is a third preset value;

[0405] Determine that the type labels of each valid channel other than the PC channels in the valid channel sequence are data channels.

[0406] Optionally, the second determination sub-module is specifically configured to:

[0407] When the coding length of the first data sequence is greater than the second threshold, determine that the type label of the channel corresponding to the second channel index is a PC channel, where the second channel index is less than the first channel index;

[0408] Determine that the type labels of the last N valid channels in the valid channel sequence are PC channels;

[0409] Determine that the type labels of each valid channel other than the PC channels in the valid channel sequence are data channels.

[0410] Optionally, the third determination unit includes:

[0411] An initialization subunit, configured to initialize a cyclic shift register;

[0412] A reading subunit, configured to sequentially read the type labels of each channel in the second data sequence in order;

[0413] The first output subunit is configured to set the output of the cyclic shift register to zero when the type tag of any channel is an invalid channel;

[0414] The second output subunit is configured to use the value of the first bit in the cyclic shift register as the output value when the type tag of any channel is a PC channel, or, when the type tag of any channel is a data channel, read the second value from the first data sequence in order as the output value, or, in response to traversing each channel in the second data sequence, determine an initial encoding according to the respective output values of the cyclic shift register.

[0415] Optionally, the second output subunit is further configured to:

[0416] Perform an exclusive OR operation on the second value and the value of the current first bit in the cyclic shift register to obtain an operation result;

[0417] Store the operation result at the original position of the cyclic shift register.

[0418] Optionally, the apparatus further includes:

[0419] A start module, configured to start the second execution phase of the first task and the first execution phase of the second task in response to the completion of the first execution phase of the first task,

[0420] wherein the first execution phase of the task is used to determine a first data sequence after cyclic redundancy check and the type tags of the channels in the second data sequence,

[0421] The second execution phase of the task is used to determine an initial encoding according to the type tags of the channels in the second data sequence and the first data sequence, and the first task and the second task are different.

[0422] Optionally, the first data sequence is stored in a first register bank, and the type tags of the channels in the second data sequence are stored in a second register bank,

[0423] The task parallelism corresponding to the second execution phase is higher than that of the first execution phase.

[0424] Optionally, the first sub-phase is used to: based on a preset judgment condition, judge whether each channel in the second data sequence is a valid channel to obtain a judgment result, and store the judgment results corresponding to the respective channels in the second register bank;

[0425] The second sub-phase is used to: determine a first data sequence after cyclic redundancy check;

[0426] Among them, during the execution of a single task, the second sub-phase is started after the first sub-phase.

[0427] Optionally, the first execution phase further includes a third sub-phase, and the second sub-phase and the third sub-phase are processed in parallel.

[0428] The third sub-phase is used to: determine the type label corresponding to each channel in the second data sequence based on the reference channel reliability information and the judgment result.

[0429] In the embodiments of the present disclosure, first, an initial encoding is obtained, and then the initial encoding is processed based on a preset encoding rule, a first encoder, and at most a first number of first XOR gates to obtain a target encoding. Among them, the first encoder adopts a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold. Therefore, since the first encoder adopts a combinational logic circuit, it can respond promptly to changes in the input. This characteristic of instant response ensures low latency, making the first encoder very effective in processing high-speed signals. Since the number of input terminals and output terminals is greater than the first threshold, the first encoder can process multiple data bits simultaneously, thereby improving data throughput and being applicable to scenarios that require high-speed data transmission or processing. Since at most a first number of first XOR gates are required to implement the processing of the initial encoding, fewer XOR gate resources can be used to ensure the performance of high-speed encoding calculation, improving the utilization rate of hardware resources and balancing the calculation speed and hardware resource consumption.

[0430] To implement the above embodiments, the present disclosure also proposes a chip, which includes a processor configured to execute the method provided in the foregoing embodiments.

[0431] Figure 18 It is a schematic structural diagram of a communication device proposed in the embodiments of the present disclosure. The communication device 7100 can be a terminal, a network device, a chip, a chip system, or a processor that supports the terminal to implement any of the above methods, or a chip, a chip system, or a processor that supports the network device to implement any of the above methods. The communication device 7100 can be used to implement the methods described in the above method embodiments, and specific reference can be made to the descriptions in the above method embodiments.

[0432] Such as Figure 18As shown, the communication device 7100 includes one or more processors 7101. The processor 7101 can be a general-purpose processor or a dedicated processor, etc. For example, it can be a baseband processor or a central processing unit. The baseband processor can be used to process communication protocols and communication data, and the central processing unit can be used to control a communication device (such as a base station, a baseband chip, a terminal device, a terminal device chip, a DU or a CU, etc.), execute programs, and process program data. The communication device 7100 is used to execute any of the above methods.

[0433] In some embodiments, the communication device 7100 further includes one or more memories 7102 for storing instructions. Optionally, all or part of the memories 7102 can also be outside the communication device 7100.

[0434] In some embodiments, the communication device 7100 further includes one or more transceivers 7103. When the communication device 7100 includes one or more transceivers 7103, the transceivers 7103 perform at least one of the communication steps such as sending and / or receiving in the above method, and the processor 7101 performs other steps.

[0435] In some embodiments, the transceiver can include a receiver and / or a transmitter. The receiver and the transmitter can be separate or integrated together. Optionally, terms such as transceiver, transceiver unit, transceiver machine, transceiver circuit, etc. can be replaced with each other, terms such as transmitter, transmitter unit, transmitter machine, transmitter circuit, etc. can be replaced with each other, and terms such as receiver, receiver unit, receiver machine, receiver circuit, etc. can be replaced with each other.

[0436] In some embodiments, the communication device 7100 can include one or more interface circuits 7104. Optionally, the interface circuit 7104 is connected to the memory 7102. The interface circuit 7104 can be used to receive signals from the memory 7102 or other devices, and can be used to send signals to the memory 7102 or other devices. For example, the interface circuit 7104 can read the instructions stored in the memory 7102 and send the instructions to the processor 7101.

[0437] The communication device 7100 described in the above embodiments can be a terminal or a network device or a third entity, but the scope of the communication device 7100 described in the present disclosure is not limited thereto, and the structure of the communication device 7100 can be unrestricted Figure 18Limitations. The communication device can be a stand-alone device or can be part of a larger device. For example, the communication device can be: 1) a stand-alone integrated circuit (IC), or chip, or system-on-chip or subsystem; (2) a collection of one or more ICs, optionally, the above IC collection can also include storage components for storing data and programs; (3) an ASIC, such as a modem; (4) a module that can be embedded in other devices; (5) a receiver, a terminal device, a smart terminal device, a cellular phone, a wireless device, a handset, a mobile unit, a vehicle-mounted device, a network device, a cloud device, an artificial intelligence device, etc.; (6) others, etc.

[0438] Figure 19 is a schematic structural diagram of the chip proposed in the embodiments of the present disclosure. For the case where the communication device 7100 can be a chip or a system-on-chip, reference can be made to Figure 19 the schematic structural diagram of the chip 7200 shown, but not limited thereto.

[0439] The chip 7200 includes one or more processors 7201, and the chip 7200 is used to execute any of the above methods.

[0440] In some embodiments, the chip 7200 further includes one or more interface circuits 7202. Optionally, the interface circuit 7202 is connected to the memory 7203. The interface circuit 7202 can be used to receive signals from the memory 7203 or other devices, and the interface circuit 7202 can be used to send signals to the memory 7203 or other devices. For example, the interface circuit 7202 can read the instructions stored in the memory 7203 and send the instructions to the processor 7201.

[0441] In some embodiments, the interface circuit 7202 executes at least one of the communication steps such as sending and / or receiving in the above method, and the processor 7201 executes other steps.

[0442] In some embodiments, terms such as interface circuit, interface, transceiver pin, transceiver, etc. can be used interchangeably.

[0443] In some embodiments, the chip 7200 further includes one or more memories 7203 for storing instructions. Optionally, all or part of the memory 7203 can be outside the chip 7200.

[0444] The present disclosure also provides a storage medium. Instructions are stored on the storage medium. When the instructions run on the communication device 7100, the communication device 7100 is caused to execute any one of the above methods. Optionally, the storage medium is an electronic storage medium. Optionally, the storage medium is a computer-readable storage medium, but is not limited thereto, and it may also be other device-readable storage mediums. Optionally, the storage medium may be a non-transitory storage medium, but is not limited thereto, and it may also be a transitory storage medium.

[0445] The present disclosure also provides a program product. When the program product is executed by the communication device 7100, the communication device 7100 is caused to execute any one of the above methods. Optionally, the program product is a computer program product.

[0446] The present disclosure also provides a computer program. When it runs on a computer, the computer is caused to execute any one of the above methods.

[0447] In the above embodiments, it may be implemented in whole or in part by software, hardware, firmware, or any combination thereof. When implemented using software, it may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer programs. When the computer program is loaded and executed on a computer, the processes or functions described in the embodiments of the present disclosure are generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable devices. The computer program may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer program may be transmitted from one website, computer, server, or data center to another website, computer, server, or data center by wire (such as coaxial cable, optical fiber, digital subscriber line (DSL)) or wirelessly (such as infrared, wireless, microwave, etc.). The computer-readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server or a data center that includes one or more integrated available media. The available medium may be a magnetic medium (such as a floppy disk, a hard disk, a magnetic tape), an optical medium (such as a high-definition digital video disc (DVD)), or a semiconductor medium (such as a solid state disk (SSD)), etc.

[0448] Those of ordinary skill in the art can realize that the units and algorithm steps of each example described in combination with the embodiments disclosed herein can be implemented by electronic hardware, or a combination of computer software and electronic hardware. Whether these functions are executed in a hardware or software manner depends on the specific application and design constraints of the technical solution. Professional technicians can use different methods to implement the described functions for each specific application, but such implementation should not be considered to exceed the scope of this disclosure.

[0449] Those skilled in the art can clearly understand that for the convenience and brevity of description, the specific working processes of the systems, devices, and units described above can refer to the corresponding processes in the foregoing method embodiments, and will not be elaborated herein.

[0450] As described above, the above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A coding method for polar codes, characterized in that, Including: Obtain an initial encoding; Based on a preset encoding rule, a first encoder, and at most a first number of first XOR gates, process the initial encoding to obtain a target encoding, wherein the first encoder uses a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

2. The method according to claim 1, wherein The processing the initial encoding based on a preset encoding rule, a first encoder, and at most a first number of first XOR gates to obtain a target encoding includes: According to a first clock sequence, input at least one initial encoding into the first encoder to obtain a first encoding result corresponding to the initial encoding; Based on at least one of the first encoding results and the at most first number of first XOR gates, determine the target encoding.

3. The method according to claim 2, wherein The determining the target encoding based on at least one of the first encoding results and the at most first number of first XOR gates includes: If the index value of any clock cycle in the first clock order satisfies a first condition, determine the any clock cycle as a target clock cycle; Determine the adjacent previous clock cycles of at least one of the target clock cycles; Perform an XOR operation on the first encoding result corresponding to the adjacent previous clock cycle and the first encoding result of the target clock cycle to obtain a second encoding result corresponding to the target clock cycle; Based on at least one of the first encoding results, the at most first number of first XOR gates, and the second encoding result corresponding to the target clock cycle, determine the target encoding.

4. The method according to claim 1, wherein Before the processing the initial encoding based on a preset encoding rule, a first encoder, and at most a first number of first XOR gates to obtain a target encoding, it further includes: Construct a first encoder according to an encoding matrix corresponding to the encoding length of the initial encoding.

5. The method according to claim 1, wherein The obtaining the initial encoding includes: Determine a first data sequence after cyclic redundancy check; According to the type label of the channel in the second data sequence and the first data sequence, determine the initial encoding.

6. The method according to claim 5, characterized in that, The determining the first data sequence after cyclic redundancy check includes: When the code length of the input information is greater than a second threshold, divide the input information into at least one code block according to the code length of the input information and the code length after rate matching; Perform cyclic redundancy check on the code block to obtain the first data sequence corresponding to the code block.

7. The method according to claim 5, wherein Before the determining the initial encoding according to the type label of the channel in the second data sequence and the first data sequence, it further includes: Based on a preset judgment condition, judge whether each channel in the second data sequence is a valid channel to obtain a judgment result; Based on the reference channel reliability information and the judgment result, determine the type label corresponding to each channel in the second data sequence.

8. The method according to claim 7, characterized in that The determining the type label corresponding to each channel in the second data sequence based on the channel reliability list and the judgment result includes: When the judgment result corresponding to one or more channels in the second data sequence is a non-valid channel, determine the type label of the one or more channels as an invalid channel; According to the reference channel reliability information, sort the valid channels in the second data sequence according to the reliability level from high to low to obtain a sorted valid channel sequence; Determine a first value corresponding to the minimum row weight parity check PC bit; Based on the first value, determine the type label of each valid channel in the valid channel sequence.

9. The method according to claim 8, wherein Wherein, The valid channel sequence is sorted in descending order of reliability. Based on the first value, determining the type label of each valid channel in the valid channel sequence includes: When the first value is a first preset value, determine that the type labels of the first K valid channels in the valid channel sequence are data channels, and determine that the type labels of other valid channels are PC channels, where K is a positive integer; Or, When the first value is a second preset value, based on the coding length of the first data sequence, determine the type label of each valid channel.

10. The method according to claim 9, characterized in that, The determining the type label of each valid channel based on the coding length of the first data sequence includes: When the coding length of the first data sequence is less than or equal to a third threshold, determine that the type label of the channel corresponding to the first channel index is a PC channel; Determine that the type labels of the last N valid channels in the valid channel sequence are PC channels, where N is a third preset value; Determine that the type labels of each valid channel other than the PC channels in the valid channel sequence are data channels.

11. The method according to claim 9, characterized in that, The determining the type label of each valid channel based on the coding length of the first data sequence includes: When the coding length of the first data sequence is greater than the third threshold, determine that the type label of the channel corresponding to the second channel index is a PC channel, where the second channel index is less than the first channel index; Determine that the type labels of the last N valid channels in the valid channel sequence are PC channels; Determine that the type labels of each valid channel other than the PC channels in the valid channel sequence are data channels.

12. The method according to claim 5, wherein The determining the initial coding according to the type labels of the channels in the second data sequence and the first data sequence includes: Initialize the cyclic shift register; Read the type labels of the channels in the second data sequence in sequence; When the type label of any channel is an invalid channel, set the output of the cyclic shift register to zero, or when the type label of any channel is a PC channel, use the value of the first bit in the cyclic shift register as the output value, or when the type label of any channel is a data channel, read a second value from the first data sequence in order as the output value; In response to traversing each channel in the second data sequence, determine the initial coding according to the output values of the cyclic shift register.

13. The method according to claim 12, characterized in that, After reading the second value from the first data sequence in order, further includes: Perform an exclusive OR operation on the second value and the value of the current first bit in the cyclic shift register to obtain an operation result; Store the operation result in the original position of the cyclic shift register.

14. The method according to claim 1, characterized in that, It further includes: In response to the completion of the first execution stage of the first task, start the second execution stage of the first task and the first execution stage of the second task. Wherein, the first execution stage of the task is used to determine the first data sequence after cyclic redundancy check and the type label of the channel in the second data sequence. The second execution stage of the task is used to determine the initial coding according to the type label of the channel in the second data sequence and the first data sequence, and the first task and the second task are different.

15. The method according to claim 14, characterized in that, Wherein, The first data sequence is stored in the first register bank, and the type label of the channel in the second data sequence is stored in the second register bank. The task parallelism corresponding to the second execution stage is higher than that of the first execution stage.

16. The method according to claim 14, characterized in that The first execution stage includes a first sub-stage and a second sub-stage. The first sub-stage is used to: based on a preset judgment condition, judge whether each channel in the second data sequence is a valid channel to obtain a judgment result, and store the judgment results corresponding to the respective channels in the second register bank. The second sub-stage is used to: determine the first data sequence after cyclic redundancy check. Wherein, during the execution of a single task, the second sub-stage is started after the first sub-stage.

17. The method according to claim 16, wherein The first execution stage further includes a third sub-stage, and the second sub-stage and the third sub-stage are processed in parallel. The third sub-stage is used to: based on the reference channel reliability information and the judgment result, determine the type label corresponding to each channel in the second data sequence.

18. An encoding device for a polar code, characterized in that, It includes: An acquisition module, used to acquire the initial coding. A processing module, used to process the initial coding based on a preset coding rule, a first encoder and at most a first number of first exclusive-OR gates to obtain a target coding. Wherein, the first encoder adopts a combinational logic circuit, and the number of input terminals and output terminals of the first encoder is greater than a first threshold.

19. A communication device, characterized in that, It includes: One or more processors; Wherein, the processor is used to execute the encoding method of the polar code according to any one of claims 1-17.

20. A storage medium storing instructions, characterized in that, When the instruction runs on the communication device, the communication device is caused to execute the encoding method of the polar code according to any one of claims 1-17.

21. A chip, characterized in that, It includes a processor and an interface; The processor is used to read the instruction to execute the encoding method of the polar code according to any one of claims 1-17.

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