Display device

Abstract

The invention relates to a display device. The display device has a display area in which an emission area is arranged and a non-display area around the display area, and includes: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer and including light-emitting elements respectively located in the emission regions, in which the circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements and arranged side by side with each other along a first direction and a second direction; a data line extending in a second direction and transmitting a data signal to the light emitting pixel driver; a first auxiliary line extending in a first direction; a second auxiliary line extending in the second direction and adjacent to the data line in the first direction; third auxiliary lines extending in the second direction and located between the second auxiliary lines in the first direction; and first connection auxiliary electrodes in the light emitting pixel drivers, respectively, having an island shape, and spaced apart from the first auxiliary lines.

Description

Technical Field

[0001] The present disclosure relates to a display device. Background Art

[0002] With the development of the information-oriented society, there has been an increasing demand for display devices for displaying images in various ways. For example, display devices are used in various electronic devices such as smart phones, digital cameras, laptop computers, navigation devices, and smart TVs.

[0003] The display device may be a flat panel display device such as a liquid crystal display device, a field emission display device, and a light-emitting display device. Examples of the light-emitting display device may include an organic light-emitting display device including an organic light-emitting element, an inorganic light-emitting display device including an inorganic light-emitting element such as an inorganic semiconductor, and a micro light-emitting display device including a micro light-emitting element.

[0004] The organic light-emitting display device displays an image using a light-emitting element, and each light-emitting element includes a light-emitting layer made of an organic light-emitting material. As described above, the organic light-emitting display device uses a self-luminous element to implement image display, and thus may have relatively superior performance in terms of power consumption, response speed, luminous efficiency, brightness, and wide viewing angle compared to other display devices.

[0005] One surface of the display device may be a display surface including a display area in which an image is displayed and a non-display area surrounding the display area. Emission areas that emit light having corresponding brightness and colors may be arranged in the display area. Summary of the Invention

[0006] The display device may include light-emitting elements respectively provided in the emission areas, and light-emitting pixel drivers respectively electrically connected to the light-emitting elements.

[0007] The light-emitting pixel driver may provide a driving current corresponding to a data signal of the emission area to the light-emitting element.

[0008] However, in order to provide the driving current more uniformly and stably, the light-emitting pixel driver may include not only a driving transistor that generates the driving current, but also a transistor for initializing the potential of a node connected to the driving transistor and / or the light-emitting element and a constant voltage line connected thereto. As a result, the width of each of the light-emitting pixel drivers increases, and thus there is a problem in that improvement in resolution is limited.

[0009] In addition, due to the wiring resistance, it may be difficult to uniformly transmit the constant voltage for driving current generation and initialization to the entire display area, and in this case, there is a problem in that image quality deteriorates due to a brightness difference between regions.

[0010] In view of the above, aspects and features of embodiments of the present disclosure provide a display device in which the width of each of the light-emitting pixel drivers can be reduced, while a constant voltage can be transmitted to the light-emitting pixel drivers through wiring in a mesh shape having a relatively low resistance, thereby desirably achieving high resolution.

[0011] However, aspects and features of embodiments of the present disclosure are not limited to the aspects and features set forth herein. Through reference to the following detailed description of the present disclosure, the above and other aspects and features of embodiments of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

[0012] According to one or more embodiments of the present disclosure, there is provided a display device having a display area in which emission areas are arranged and a non-display area around the display area, and including: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer and including light-emitting elements respectively located in the emission areas, wherein the circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements and arranged side by side with each other along a first direction and a second direction; data lines extending in the second direction and transmitting data signals to the light-emitting pixel drivers; a first auxiliary line extending in the first direction; a second auxiliary line extending in the second direction and adjacent to the data lines in the first direction; a third auxiliary line extending in the second direction and located between the second auxiliary lines in the first direction; and first connection auxiliary electrodes respectively located in the light-emitting pixel drivers, having an island shape, and spaced apart from the first auxiliary line.

[0013] The circuit layer further includes second connection auxiliary electrodes having an island shape and respectively overlapping the first connection auxiliary electrodes, and respectively electrically connected to the first connection auxiliary electrodes through first auxiliary connection holes, and wherein the second connection auxiliary electrodes are electrically connected to the second auxiliary lines through second auxiliary connection holes.

[0014] The circuit layer further includes: a first initialization voltage line electrically connected to an initialization voltage extension line that transmits a first initialization voltage and extends in the first direction, having an island shape, and spaced apart from the first connection auxiliary electrode; a second initialization voltage line extending in the first direction, spaced apart from the first connection auxiliary electrode, and transmitting a second initialization voltage; and a third connection auxiliary electrode overlapping the third auxiliary line and having an island shape, and spaced apart from the second connection auxiliary electrode, wherein the third connection auxiliary electrode is electrically connected to the third auxiliary line through a third auxiliary connection hole.

[0015] The light-emitting pixel driver includes a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in a first direction. One of the first auxiliary lines overlaps with the first light-emitting pixel driver and the second light-emitting pixel driver. The second auxiliary line includes one second auxiliary line overlapping with the first light-emitting pixel driver and another second auxiliary line overlapping with the second light-emitting pixel driver. The third auxiliary line includes one third auxiliary line adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver. And the first initialization voltage line is located between the first connection auxiliary electrode in the first light-emitting pixel driver and the first connection auxiliary electrode in the second light-emitting pixel driver in the first direction and overlaps with one third auxiliary line.

[0016] Each of the first connection auxiliary electrode in the first light-emitting pixel driver and the first connection auxiliary electrode in the second light-emitting pixel driver is electrically connected to one of the first auxiliary lines, the first initialization voltage line, or the second initialization voltage line through a first connection auxiliary line.

[0017] The third connection auxiliary electrode includes one third connection auxiliary electrode electrically connected to one third auxiliary line, and one of the second connection auxiliary electrode in the first light-emitting pixel driver or the second connection auxiliary electrode in the second light-emitting pixel driver is electrically connected to the third connection auxiliary electrode through a second connection auxiliary line among the third connection auxiliary electrodes between the second connection auxiliary electrode in the first light-emitting pixel driver and the second connection auxiliary electrode in the second light-emitting pixel driver.

[0018] The bypass area on one side of the display area includes: a bypass intermediate area; a first bypass side area spaced apart from the bypass intermediate area in the first direction and in contact with the non-display area in the first direction; and a second bypass side area located between the bypass intermediate area and the first bypass side area. The data line includes a first data line in the first bypass side area and a second data line in the second bypass side area. The first auxiliary line includes: a first bypass auxiliary line electrically connected to the first data line; and a power auxiliary horizontal line configured to transmit the second power among the first power and the second power for driving the light-emitting element. The second auxiliary line includes a second bypass auxiliary line adjacent to the second data line and electrically connected to the first bypass auxiliary line, and the second auxiliary line further includes an auxiliary vertical line. The auxiliary vertical line is the remaining part of the second auxiliary line except the second bypass auxiliary line and includes: a first auxiliary vertical line configured to transmit the second power; a second auxiliary vertical line configured to transmit the first initialization voltage; and a third auxiliary vertical line configured to transmit the second initialization voltage.

[0019] A first bypass auxiliary line among the first auxiliary lines is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers through a first connection auxiliary line, and a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a second bypass auxiliary line among the second auxiliary lines through a second auxiliary connection hole.

[0020] A power auxiliary horizontal line among the first auxiliary lines is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers through a first connection auxiliary line, and a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a first auxiliary vertical line among the second auxiliary lines through a second auxiliary connection hole.

[0021] A first initialization voltage line is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers through a first connection auxiliary line, and a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a second auxiliary vertical line among the second auxiliary lines through a second auxiliary connection hole.

[0022] A second initialization voltage line is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers through a first connection auxiliary line, and a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a third auxiliary vertical line among the second auxiliary lines through a second auxiliary connection hole.

[0023] The third auxiliary line includes: a power additional line configured to transmit a second power; a first initialization voltage additional line configured to transmit a first initialization voltage; and a second initialization voltage additional line configured to transmit a second initialization voltage.

[0024] A power auxiliary horizontal line among the first auxiliary lines is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers through a first connection auxiliary line, a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a third connection auxiliary electrode overlapping with the power additional line among the third auxiliary lines through a second connection auxiliary line, and a third connection auxiliary electrode is electrically connected to the power additional line through a third auxiliary connection hole.

[0025] A first initialization voltage line is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers through a first connection auxiliary line, a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a third connection auxiliary electrode overlapping with the first initialization voltage additional line among the third auxiliary lines through a second connection auxiliary line, and a third connection auxiliary electrode is electrically connected to the first initialization voltage additional line through a third auxiliary connection hole.

[0026] The second initialization voltage line is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a first connection auxiliary line, wherein a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to a third connection auxiliary electrode that overlaps a second initialization voltage additional line among the third auxiliary lines through a second connection auxiliary line, and wherein a third connection auxiliary electrode is electrically connected to the second initialization voltage additional line through a third auxiliary connection hole.

[0027] In the display area, there are also arranged: a non-emitting area, which is a separation area between the emitting areas; and a photosensing area, in a part of the non-emitting area, wherein the element layer further includes photosensing elements respectively located in the photosensing area, and wherein the circuit layer further includes: a photosensing pixel driver electrically connected to the photosensing elements; a reset control line extending in a first direction and configured to transmit a reset control signal for resetting the photosensing pixel driver; and a reset voltage line configured to transmit a reset voltage to the photosensing pixel driver, wherein the auxiliary vertical line of the second auxiliary line further includes at least one of a fourth auxiliary vertical line configured to transmit a reset voltage and a fifth auxiliary vertical line configured to transmit a reset control signal.

[0028] The reset voltage line is electrically connected to a second connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a third connection auxiliary line, and wherein a second connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver is electrically connected to the fourth auxiliary vertical line among the second auxiliary lines through a second auxiliary connection hole.

[0029] The reset control line is electrically connected to a first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a reset control connection hole and a first connection auxiliary line, and wherein a second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to the fifth auxiliary vertical line among the second auxiliary lines through a second auxiliary connection hole.

[0030] The circuit layer further includes: a first semiconductor layer on the substrate; a first gate insulating layer covering the first semiconductor layer; a first gate conductive layer on the first gate insulating layer; a second gate insulating layer covering the first gate conductive layer; a second gate conductive layer on the second gate insulating layer; an additional interlayer insulating layer covering the second gate conductive layer; a second semiconductor layer on the additional interlayer insulating layer; a third gate insulating layer covering the second semiconductor layer; a third gate conductive layer on the third gate insulating layer; an interlayer insulating layer covering the third gate conductive layer; a first source-drain conductive layer on the interlayer insulating layer; a first planarization layer covering the first source-drain conductive layer; a second source-drain conductive layer on the first planarization layer; a second planarization layer covering the second source-drain conductive layer; a third source-drain conductive layer on the second planarization layer; and a third planarization layer covering the third source-drain conductive layer, wherein a first auxiliary line, a first connection auxiliary electrode, a first initialization voltage line, and a second initialization voltage line are in the first source-drain conductive layer, wherein a second connection auxiliary electrode and a third connection auxiliary electrode are in the second source-drain conductive layer, and wherein a second auxiliary line and a third auxiliary line are in the third source-drain conductive layer.

[0031] In one or more embodiments, a display device has a display area in which emission areas are arranged and a non-display area around the display area, and includes: a substrate; a circuit layer on the substrate; and an element layer on the circuit layer and including light-emitting elements respectively located in the emission areas, wherein the circuit layer includes: light-emitting pixel drivers electrically connected to the light-emitting elements and arranged side by side with each other in a first direction and a second direction; data lines extending in the second direction and configured to transmit data signals to the light-emitting pixel drivers; a first auxiliary line extending in the first direction; a second auxiliary line extending in the second direction and adjacent to the data lines in the first direction; a third auxiliary line extending in the second direction and located between the second auxiliary lines in the first direction; first connection auxiliary electrodes respectively located in the light-emitting pixel drivers, having an island shape and spaced apart from the first auxiliary line; second connection auxiliary electrodes having an island shape and respectively overlapping the first connection auxiliary electrodes, electrically connected to the first connection auxiliary electrodes through first auxiliary connection holes respectively, and electrically connected to the second auxiliary line through second auxiliary connection holes; third connection auxiliary electrodes overlapping the third auxiliary line, having an island shape and spaced apart from the second connection auxiliary electrodes, and electrically connected to the third auxiliary line through third auxiliary connection holes; a first initialization voltage line electrically connected to an initialization voltage extension line configured to transmit a first initialization voltage and extending in the first direction, having an island shape and spaced apart from the first connection auxiliary electrode; and a second initialization voltage line extending in the first direction, spaced apart from the first connection auxiliary electrode, and configured to transmit a second initialization voltage, wherein the first auxiliary line includes: a first bypass auxiliary line electrically connected to a first data line among the data lines adjacent to the non-display area in the first direction; and a power auxiliary horizontal line configured to transmit a second power among a first power and a second power for driving the light-emitting elements, and wherein the second auxiliary line includes: a second bypass auxiliary line electrically connected to the first bypass auxiliary line and adjacent to a second data line among the data lines, the second data line being spaced apart from the non-display area in the first direction compared with the first data line; and an auxiliary vertical line, the auxiliary vertical line being the remaining part of the second auxiliary line except the second bypass auxiliary line, wherein the second bypass auxiliary line is electrically connected to the first bypass auxiliary line through a bypass connection overlapping a light-emitting pixel driver at an intersection of the first bypass auxiliary line and the second bypass auxiliary line and electrically connecting a first connection auxiliary electrode, a first connection auxiliary line, and a second connection auxiliary electrode in the light-emitting pixel driver, and wherein the auxiliary vertical line includes: a first auxiliary vertical line electrically connected to the power auxiliary horizontal line through a power connection located in the light-emitting pixel driver and electrically connecting a first connection auxiliary electrode, a first connection auxiliary line, and a second connection auxiliary electrode in the light-emitting pixel driver;A second auxiliary vertical line configured to transmit a first initialization voltage is electrically connected to a first initialization voltage line through a first connection auxiliary electrode, a first connection auxiliary line, and a second connection auxiliary electrode in a light-emitting pixel driver; and a third auxiliary vertical line is electrically connected to a second initialization voltage line through a second initialization connection in the light-emitting pixel driver, the first connection auxiliary electrode, the first connection auxiliary line, and the second connection auxiliary electrode.

[0032] Therefore, in one of the first light-emitting pixel driver and the second light-emitting pixel driver, a wiring among a first auxiliary line, a first initialization voltage line, and a second initialization voltage line connected to the first connection auxiliary electrode can be electrically connected to a third auxiliary line through the first connection auxiliary electrode, the second connection auxiliary electrode, and the third connection auxiliary electrode.

[0033] As described above, according to one or more embodiments, a first connection auxiliary electrode spaced apart from the first auxiliary line, a second connection auxiliary electrode overlapping the first connection auxiliary electrode, and a part of a third connection auxiliary electrode spaced apart from the second connection auxiliary electrode can be provided in each of the light-emitting pixel drivers. In addition, by selectively providing a first connection auxiliary line connecting one of the first initialization voltage line and the second initialization voltage line to the first connection auxiliary electrode and a second connection auxiliary line connecting the second connection auxiliary electrode to the third connection auxiliary electrode, a grid-shaped wiring including an electrical connection portion between a wiring extending in a first direction and a wiring extending in a second direction can be provided.

[0034] In other words, even without providing a protrusion with a hole for electrical connection between a wiring extending in a first direction and a wiring extending in a second direction for each of the wirings, a grid-shaped wiring can be provided, thereby reducing the width of each of the light-emitting pixel drivers, which is advantageous for achieving high resolution.

[0035] However, the effects, aspects, and features according to one or more embodiments of the present disclosure are not limited to those illustrated above, and various other effects, aspects, and features are incorporated herein. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other aspects and features of the embodiments of the present disclosure will become more apparent by referring to the drawings in which the embodiments of the present disclosure are described in detail:

[0037] Figure 1 is a perspective view of an electronic device according to one or more embodiments;

[0038] Figure 2 is Figure 1 an exploded perspective view of the electronic device shown;

[0039] Figure 3 is a plan view of a display device showing Figure 2 ;

[0040] Figure 4 is a cross-sectional view taken along line A-A' of Figure 3 ;

[0041] Figure 5 is a layout view of part B showing Figure 3 ;

[0042] Figure 6 is a view showing the scanning function of a light sensing area shown by Figure 5 ;

[0043] Figure 7 is a block diagram of a circuit layer showing Figure 4 ;

[0044] Figure 8 is an equivalent circuit diagram of a light emitting pixel driver and a light sensing pixel driver shown by Figure 7 ;

[0045] Figure 9 is a cross-sectional view showing a first transistor, a second transistor, a fourth transistor, a sixth transistor, and a light emitting element of Figure 8 ;

[0046] Figure 10 is a plan view of a substrate according to one or more embodiments showing Figure 4 ;

[0047] Figure 11 is a layout view of part C showing Figure 10 ;

[0048] Figure 12 is a cross-sectional view taken along line E-E' of Figure 11 ;

[0049] Figure 13 is a plan view of part D according to one or more embodiments showing Figure 10 ;

[0050] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 is a plan view of a part of each of a first light emitting pixel driver and a second light emitting pixel driver according to one or more embodiments showing Figure 13 ;

[0051] Figure 19 is a view showing according to one or more embodimentsFigure 10 A plan view of part D; and

[0052] Figure 20 and Figure 21 are plan views showing a part of each of a first light-emitting pixel driver and a second light-emitting pixel driver according to one or more embodiments. Figure 19 A plan view of a part of each of a first light-emitting pixel driver and a second light-emitting pixel driver according to one or more embodiments. Detailed embodiments

[0053] Embodiments of the present disclosure will now be described more fully hereinafter with reference to the accompanying drawings. However, the embodiments may be provided in different forms and should not be construed as limited. Throughout the present disclosure, the same reference numerals denote the same components. In the drawings, the thicknesses of layers and regions may be exaggerated for clarity.

[0054] To describe the embodiments of the present disclosure, parts that are not relevant to the description may not be provided.

[0055] It will also be understood that when a layer is referred to as being "on" another layer or substrate, it may be directly on the other layer or substrate, or intervening layers may also be present. Conversely, when an element is referred to as being "directly on" another element, no intervening element may be present.

[0056] In addition, the phrase "in a plan view" means when observing an object part from above, and the phrase "in a schematic cross-sectional view" means when observing a schematic cross-section obtained by vertically cutting an object part from the side. The term "overlap" or "overlapped" means that a first object may be above or below a second object, or on one side of the second object, and vice versa. Additionally, the term "overlap" may include laminating, stacking, facing or confronting, extending throughout, covering or partially covering, or any other suitable term that those of ordinary skill in the art will understand and appreciate. The expression "not overlapping" may include meanings such as "separated from...", "set beside...", or "offset from...", as well as any other suitable equivalents that those of ordinary skill in the art will understand and appreciate. The terms "facing" and "confronting" may mean that a first object may be directly or indirectly opposite a second object. In the case where a third object is interposed between the first object and the second object, the first object and the second object may be understood as being indirectly opposite each other but still facing each other.

[0057] For ease of description, in this document, spatial relative terms such as "below", "beneath", "under", "above", "upper", etc. may be used to describe the relationship between one element or component and another as shown in the figures. It will be understood that, in addition to the orientation depicted in the figures, spatial relative terms are intended to encompass different orientations of the device during use or operation. For example, in the case where the device shown in the figure is flipped, a device positioned "below" or "beneath" another device may be placed "above" the other device. Thus, the exemplary term "below" can include both a lower position and an upper position. The device may also be oriented in other directions, and thus the spatial relative terms may be interpreted differently depending on the orientation.

[0058] When an element is referred to as being "connected" or "coupled" to another element, the element can be "directly connected" or "directly coupled" to the other element, or "electrically connected" or "electrically coupled" to the other element, with one or more intermediate elements interposed therebetween. It will also be understood that when the terms "comprises", "comprising", "has", "have", "having", "includes", and / or "including" are used, they may specify the presence of the stated features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of other features, wholes, steps, operations, elements, components, and / or any combination thereof.

[0059] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another or for ease of description and explanation. For example, without departing from the teachings herein, when discussing a "first element" in the specification, it may be referred to as a "second element" or a "third element", and the "second element" and "third element" may be referred to in a similar manner.

[0060] In view of the measurements discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation range of a particular value determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ±30%, ±20%, ±10%, ±5% of the stated value.

[0061] In the specification and claims, for purposes of their meaning and interpretation, the term "and / or" is intended to include any combination of the terms "and" and "or". For example, "A and / or B" can be understood to mean "A, B, or A and B". The terms "and" and "or" can be used in the sense of conjunctions or disjunctions, and can be understood as equivalent to "and / or". In the specification and claims, for purposes of their meaning and interpretation, the phrase "at least one of..." is intended to include the meaning of "at least one selected from the group of...". For example, "at least one of A and B" can each be understood to mean "A, B, or A and B".

[0062] Unless otherwise defined or implied, all terms used herein (including technical and scientific terms) have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning consistent with their meaning in the context of the relevant art, and will not be interpreted in an idealized or overly formal sense unless expressly defined in the specification.

[0063] Taking the present disclosure as a whole, one of ordinary skill in the art will understand that each suitable feature of the various embodiments of the present disclosure can be partially or fully combined with each other, and can interact technically and operate in various suitable ways, and each embodiment can be implemented independently of each other or in combination with each other in any suitable way, unless otherwise stated or implied.

[0064] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0065] Figure 1 is a perspective view showing an electronic device according to one or more embodiments. Figure 2 is Figure 1 an exploded perspective view of the shown electronic device.

[0066] Referring Figure 1 , an electronic device 10 according to one or more embodiments is a device having a function of displaying an image in a display area. The electronic device 10 can provide portability. For example, the electronic device 10 can be a portable electronic device, such as a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a mobile communication terminal, an electronic notebook, an e-book, a portable multimedia player (PMP), a navigation device, and / or an ultra-mobile PC (UMPC).

[0067] However, the electronic device 10 according to one or more embodiments is not limited to a portable electronic device, and can be a large device such as a television, a laptop computer, a monitor, a billboard, and / or an Internet of Things (IoT) device.

[0068] An electronic device 10 according to one or more embodiments may include a cover window 11 and a lower cover 12, which are provided as a housing to protect a display device 100 (see Figure 2 ).

[0069] Reference Figure 2 , the electronic device 10 may further include a display device 100, a bracket 13, and a main circuit board 14 accommodated between the cover window 11 and the lower cover 12.

[0070] The display device 100 may include a main area MA and a sub - area SBA. The main area MA includes a display area DA for displaying an image and a non - display area NDA around the display area DA along the edge or periphery of the display area DA. The sub - area SBA protrudes from one side of the main area MA.

[0071] The display device 100 may further include a display driving circuit 200 provided in the sub - area SBA, a display circuit board 300 coupled to one side of the sub - area SBA, a touch driving circuit 400 and a scan driving circuit 500 mounted on the display circuit board 300, and a cable 600 extending from one side of the display circuit board 300.

[0072] In the present disclosure, a first direction DR1 may be a direction parallel to the short side of the electronic device 10 in a plan view, that is, the horizontal direction of the electronic device 10. A second direction DR2 may be a direction parallel to the long side of the electronic device 10 in a plan view, that is, the vertical direction of the electronic device 10. A third direction DR3 may be the thickness direction of the electronic device 10.

[0073] The electronic device 10 may have a shape that is approximately rectangular in a plan view. For example, the electronic device 10 may have a rectangular shape in a plan view, which has a short side extending in the first direction DR1 and a long side extending in the second direction DR2. The corners where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be right - angled or may be rounded to have a suitable curvature (e.g., a predetermined curvature). The planar shape of the electronic device 10 is not limited to a rectangular shape and may be formed into another polygonal shape, a circular shape, and / or an elliptical shape.

[0074] The cover window 11 may be provided on the display device 100 to cover the top surface of the display device 100. The cover window 11 may be used to protect the top surface of the display device 100.

[0075] The cover window 11 may include a light - transmissive portion and a light - blocking portion. The light - transmissive portion is transparent and the light - blocking portion is opaque.

[0076] The light-transmitting portion may overlap with the display area DA of the display device 100 in the third direction DR3, and the light-blocking portion may overlap with the non-display area NDA of the display device 100 in the third direction DR3.

[0077] The cover window 11 may include a top surface portion forming the top surface of the electronic device 10, a left surface portion forming the left side surface of the electronic device 10, and a right surface portion forming the right side surface of the electronic device 10. The left surface portion of the cover window 11 may extend from the left side of the top surface portion, and its right surface portion may extend from the right side of the top surface portion.

[0078] Each of the top surface portion, the left surface portion, and the right surface portion of the cover window 11 may include a light-transmitting portion and a light-blocking portion.

[0079] The light-transmitting portion of the cover window 11 may be disposed on most of each of the top surface portion, the left surface portion, and the right surface portion of the cover window 11.

[0080] The light-blocking portion of the cover window 11 may be disposed at the upper edge and the lower edge of the top surface portion of the cover window 11, the upper edge, the left edge, and the lower edge of the left surface portion of the cover window 11, and the upper edge, the right edge, and the lower edge of the right surface portion of the cover window 11.

[0081] The display device 100 may be disposed below the cover window 11.

[0082] That is, the cover window 11 may be disposed on the display device 100.

[0083] The display device 100 may include a main area MA serving as a display surface and a sub-area SBA protruding from one side of the main area MA.

[0084] The main area MA may include a display area DA for displaying an image and a non-display area NDA that is a peripheral area of the display area DA.

[0085] The display area DA may be disposed in most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0086] The non-display area NDA may be disposed outside the display area DA. The non-display area NDA may be an edge area of the main area MA.

[0087] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2.

[0088] The length of the sub-region SBA in the first direction DR1 can be less than or equal to the length of the main region MA in the first direction DR1. The length of the sub-region SBA in the second direction DR2 can be less than the length of the main region MA in the second direction DR2, but is not limited thereto.

[0089] Since a part of the sub-region SBA is deformed to be bent, another part of the sub-region SBA can overlap with the main region MA in the third direction DR3.

[0090] The display driving circuit 200 can be arranged in the sub-region SBA.

[0091] The display device 100 can include a top surface portion facing the top surface portion of the cover window 11, a left surface portion facing the left surface portion of the cover window 11, and a right surface portion facing the right surface portion of the cover window 11. The left surface portion of the display device 100 can extend from the left side of the top surface portion of the display device 100, and the right surface portion of the display device 100 can extend from the right side of the top surface portion of the display device 100.

[0092] Each of the top surface portion, the left surface portion, and the right surface portion of the display device 100 can include a display area DA and a non-display area NDA.

[0093] The display area DA can be provided on most of each of the top surface portion, the left surface portion, and the right surface portion of the display device 100.

[0094] The non-display area NDA can be provided at the upper and lower edges of the top surface portion of the display device 100, the upper edge, the left edge, and the lower edge of the left surface portion of the display device 100, and the upper edge, the right edge, and the lower edge of the right surface portion of the display device 100.

[0095] The display driving circuit 200 can be mounted on the sub-region SBA of the display device 100, and the display circuit board 300 can be attached thereto.

[0096] One end of the display circuit board 300 can be attached to a pad provided on the lower edge of the sub-region SBA of the display device 100 by using an anisotropic conductive film.

[0097] The display circuit board 300 can be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that maintains a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0098] Based on the control signal and the power voltage provided from the display circuit board 300, the display driving circuit 200 can apply the light-emitting pixel driver EPD to be applied to the display area DA (seeFigure 7 ) The data signal Vdata (see Figure 8 ) is transmitted to the data line DL (see Figure 7 ).

[0099] The display driving circuit 200 may be configured as an integrated circuit (IC) and mounted on the sub-region SBA of the display device 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, and / or an ultrasonic method. However, this is merely an example, and the present disclosure is not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0100] According to one or more embodiments, the touch driving circuit 400 and the scan driving circuit 500 may also be mounted in the sub-region SBA of the display device 100.

[0101] Optionally, as Figure 2 shown, the touch driving circuit 400 and the scan driving circuit 500 may be mounted on the display circuit board 300.

[0102] The touch driving circuit 400 may be electrically connected to the touch sensor layer 150 of the display device 100 (see Figure 4 ).

[0103] The scan driving circuit 500 may be electrically connected to the photosensing element PD (see Figure 7 ) through the photosensing pixel driver DPD (see Figure 7 ) of the display area DA and the readout line ROL (see Figure 8 ).

[0104] The bracket 13 may be disposed below the display device 100.

[0105] The bracket 13 may include plastic, metal, or both plastic and metal. The bracket 13 may include a first camera hole CMH1 into which the camera 16 is inserted, a battery hole BH in which the battery 18 is disposed, and a cable hole CAH through which the cable 600 connected to the display circuit board 300 passes.

[0106] The main circuit board 14 and the battery 18 may be disposed below the bracket 13. The main circuit board 14 may be a rigid printed circuit board (PCB) or a flexible printed circuit board (FPCB).

[0107] The main processor 15, the camera 16, and the main connector 17 may be disposed on the main circuit board 14. The main processor 15 may be formed as an integrated circuit.

[0108] The camera 16 can be disposed on both the top surface and the bottom surface of the main circuit board 14, the main processor 15 can be disposed on the top surface of the main circuit board 14, and the main connector 17 can be disposed on the bottom surface of the main circuit board 14.

[0109] The main processor 15 can control all functions of the electronic device 10.

[0110] For example, the main processor 15 can output digital video data to the display driving circuit 200 through the display circuit board 300, so that the display device 100 displays an image. In addition, the main processor 15 can receive touch data including the touch coordinates of the user from the touch driving circuit 400, determine whether the user has touched and / or approached, and then perform an operation corresponding to the touch input and / or approach input of the user. For example, the main processor 15 can perform an operation or run an application program indicated by an icon touched by the user.

[0111] In addition, the main processor 15 can receive scan data from the scan driving circuit 500, and perform an operation or run an application program based on whether the scan data is valid.

[0112] The main processor 15 can be an application processor formed by an integrated circuit, a central processing unit (CPU), and / or a system-on-chip.

[0113] The camera 16 can process image frames of still images and / or videos obtained by the image sensor in the camera mode, and output them to the main processor 15.

[0114] The cable 600 passing through the cable hole CAH of the bracket 13 can be connected to the main connector 17. Therefore, the main circuit board 14 can be electrically connected to the display circuit board 300.

[0115] The battery 18 can be disposed so as not to overlap with the main circuit board 14 in the third direction DR3. The battery 18 can overlap with the battery hole BH of the bracket 13 in the third direction DR3.

[0116] In addition, the main circuit board 14 can also be equipped with a mobile communication module that can transmit and receive radio signals with at least one of a base station, an external terminal, and a server in a mobile communication network. The radio signals can include various types of data according to the transmission and reception of voice signals, video call signals, and / or text / multimedia messages.

[0117] The lower cover 12 can be disposed below the main circuit board 14 and the battery 18. The lower cover 12 can be fixed by being fastened to the bracket 13. The lower cover 12 can form the upper side surface, the lower side surface, and the bottom surface of the electronic device 10. The lower cover 12 can include plastic, metal, or both plastic and metal.

[0118] The lower cover 12 may include a second camera hole CMH2 through which the bottom surface of the camera 16 is exposed. The positions of the camera 16 and the first camera hole CMH1 and the second camera hole CMH2 corresponding to the camera 16 are not limited to Figure 2 the illustrated embodiments.

[0119] Next, a display device 100 according to one or more embodiments will be described.

[0120] Figure 3 is a plan view of the display device shown Figure 2 . Figure 4 is a cross-sectional view taken along line A-A' of Figure 3 . Figure 5 is a layout view of a portion B of the display device shown Figure 3 .

[0121] Figure 3 and Figure 4 show the display device 100, in which a part of the sub-region SBA is in a curved state.

[0122] The display device 100 may be a light-emitting display device, such as an organic light-emitting display using an organic light-emitting diode (OLED), a quantum dot light-emitting display including a quantum dot light-emitting layer, an inorganic light-emitting display including an inorganic semiconductor, and a micro light-emitting display using a micron- or nano-sized light-emitting diode (LED). In the following description, it is assumed that the display device 100 is an organic light-emitting display device. However, the present disclosure is not limited thereto, and may be applied to a display device including an organic insulating material, an organic light-emitting material, and a metal material.

[0123] The display device 100 may be formed flat, but is not limited thereto. For example, the display device 100 may include curved portions formed at the left and right ends and having a constant curvature or a varying curvature. In addition, the display device 100 may be formed flexible so that it can be curved, bent, folded, and / or curled.

[0124] Referring to Figure 3 , at least one surface of the display device 100 includes a main region MA from which light for displaying an image is emitted.

[0125] In a plan view, the display area DA may be formed in a rectangular shape having a short side extending in a first direction DR1 and a long side extending in a second direction DR2 intersecting the first direction DR1. The corners where the short side extending in the first direction DR1 and the long side extending in the second direction DR2 intersect may be rounded to have a suitable curvature (e.g., a predetermined curvature), or may be right-angled. The planar shape of the display area DA is not limited to a rectangular shape, and may be formed in another polygonal shape, a circular shape, or an elliptical shape.

[0126] The display area DA may occupy most of the main area MA. The display area DA may be disposed at the center of the main area MA.

[0127] Reference Figure 4 , the display device 100 further includes a sub-area SBA protruding from one side of the main area MA.

[0128] The sub-area SBA may be an area protruding from the non-display area NDA of the main area MA toward one side in the second direction DR2.

[0129] Because a part of the sub-area SBA is deformed into a curved shape, another part of the sub-area SBA may be disposed on the rear surface of the display device 100.

[0130] The display device 100 according to one or more embodiments includes a substrate 110, a circuit layer 120 disposed on the substrate 110, and an element layer 130 disposed on the circuit layer 120.

[0131] According to one or more embodiments, the display device 100 may further include a packaging layer 140 disposed on the element layer 130, and a touch sensor layer 150 disposed on the packaging layer 140. In addition, the display device 100 may further include a polarization layer 160 disposed on the touch sensor layer 150 to reduce reflection of external light.

[0132] The substrate 110 may include a main area MA corresponding to the display surface, and a sub-area SBA protruding from one side of the main area MA in the second direction DR2. The display driving circuit 200 may be directly disposed on the substrate 110. Both the substrate 110 and the circuit layer 120 may be bent in the sub-area SBA.

[0133] The main area MA of the substrate 110 may include a display area DA and a non-display area NDA. The display area DA occupies most of the main area MA at the center of the main area MA, and the non-display area NDA is the periphery of the display area DA.

[0134] The sub-area SBA may protrude from one side of the main area MA in the second direction DR2.

[0135] Reference Figure 5 , the display area DA includes an emission area EA, a non-emission area NEA which is a separation area between the emission areas EA, and a light sensing area ODA disposed in a part of the non-emission area NEA.

[0136] Each of the emission areas EA may be a unit that emits light in a wavelength band corresponding to one of two or more different colors with a brightness corresponding to an image signal.

[0137] Each of the emission regions EA may have a rhombic planar shape or a rectangular planar shape. However, this is merely an example, and the planar shape of the emission region EA according to the embodiment is not limited to Figure 5 as shown. That is, in the plan view, the emission region EA may have a polygonal shape (such as a rhombic shape or a hexagonal shape), a circular shape, or an elliptical shape different from the rectangular shape.

[0138] The emission region EA may include a first emission region EA1 that emits light of a first color having a suitable wavelength band (e.g., a predetermined wavelength band), a second emission region EA2 that emits light of a second color having a wavelength band lower than that of the first color, and a third emission region EA3 that emits light of a third color having a wavelength band lower than that of the second color.

[0139] For example, the first color may be red having a wavelength band of about 600 nm to about 750 nm, the second color may be green having a wavelength band of about 480 nm to about 560 nm, and the third color may be blue having a wavelength band of about 370 nm to about 460 nm. However, this is merely an example, and the wavelength bands of the first color, the second color, and the third color according to one or more embodiments are not limited thereto.

[0140] Since the emission region EA includes the first emission region EA1, the second emission region EA2, and the third emission region EA3, each of the unit pixels UPX may be set by a combination of one or more first emission regions EA1, one or more second emission regions EA2, and one or more third emission regions EA3 adjacent to each other among the emission regions EA.

[0141] Each of the unit pixels UPX may be a unit for presenting various colors including white. That is, the light of various colors presented by the unit pixel UPX may be realized as a mixture of light emitted from two or more emission regions EA included in each unit pixel UPX.

[0142] In the case where the first color of the first emission region EA1, the second color of the second emission region EA2, and the third color of the third emission region EA3 are red, green, and blue, respectively, the third emission region EA3 may have a width larger than that of the first emission region EA1, and the second emission region EA2 may have a width smaller than that of the first emission region EA1. However, this is merely an example, and the width of each of the emission regions EA is not limited to Figure 5 as shown.

[0143] The first emission region EA1 and the third emission region EA3 may be alternately arranged along the first direction DR1 and / or the second direction DR2. In addition, the second emission region EA2 may be arranged side by side along the first direction DR1 and / or the second direction DR2. The second emission region EA2 may be disposed between the first emission region EA1 and the third emission region EA3 in the fourth direction DR4 or the fifth direction DR5. The fourth direction DR4 may be a diagonal direction between the first direction DR1 and the second direction DR2, and the fifth direction DR5 may be orthogonal to the fourth direction DR4.

[0144] In this case, each of the unit pixels UPX may include one first emission region EA1 and one third emission region EA3 adjacent to each other in the second direction DR2, and two second emission regions EA2 adjacent to each other in the second direction DR2. However, this is only an example, and the arrangement pattern of the emission regions EA and the components of the unit pixel UPX according to one or more embodiments are not limited to Figure 5 those shown in

[0145] According to one or more embodiments, the display region DA includes a light sensing region ODA provided in a part of the non-emission region NEA.

[0146] For example, the light sensing region ODA may be disposed between the second emission regions EA2 having a relatively small width in the second direction DR2. One or more emission regions EA may be disposed between the light sensing regions ODA in each of the first direction DR1 and the second direction DR2.

[0147] According to one or more embodiments, as Figure 4 shown, the element layer 130 includes light emitting elements LE (see Figure 8 ) respectively provided in the emission regions EA, and light sensing elements PD (see Figure 8 ) respectively provided in the light sensing regions ODA.

[0148] According to one or more embodiments, the circuit layer 120 may include a light emitting pixel driver EPD (see Figure 7 ) respectively electrically connected to the light emitting elements LE of the element layer 130, a light sensing pixel driver DPD (see Figure 7 ) respectively electrically connected to the light sensing elements PD of the element layer 130, a data line DL (see Figure 7 ) electrically connected to the light emitting pixel driver EPD, and a readout line ROL (see Figure 7 ) electrically connected to the light sensing pixel driver DPD.

[0149] The encapsulation layer 140 may cover the element layer 130 and may extend into the non-display area NDA to contact the circuit layer 120. The encapsulation layer 140 may include a structure in which two or more inorganic layers and at least one organic layer are alternately stacked.

[0150] The touch sensor layer 150 may be disposed on the encapsulation layer 140 and may correspond to the main area MA. The touch sensor layer 150 may include touch electrodes for sensing the touch of a person or an object, and the touch sensor layer 150 may extend into the non-display area NDA to contact the circuit layer 120.

[0151] The polarization layer 160 blocks external light reflected from the touch sensor layer 150, the encapsulation layer 140, the element layer 130, the circuit layer 120, and their interfaces, and this will prevent the deterioration of the visibility of the image due to external light reflection.

[0152] In one or more embodiments, as a part of the sub-region SBA is deformed into a curved shape, the display driving circuit 200 mounted in the sub-region SBA and the display circuit board 300 connected to one side of the sub-region SBA may be disposed under the substrate 110.

[0153] The display driving circuit 200 may be electrically connected to the data line DL of the circuit layer 120. The display driving circuit 200 may transmit the data signal Vdata (see Figure 7 ) to be applied to the light-emitting pixel driver EPD (see Figure 8 ) to the data line DL based on the control signal and the power voltage provided from the display circuit board 300.

[0154] The display driving circuit 200 may be set as an integrated circuit (IC) and may be mounted on the sub-region SBA of the display device 100 by a chip-on-glass (COG) method, a chip-on-plastic (COP) method, or an ultrasonic method. However, this is only an example, and the embodiments are not limited thereto. For example, the display driving circuit 200 may be mounted on the display circuit board 300.

[0155] One end of the display circuit board 300 may be attached to a pad provided on one edge of the sub-region SBA of the display device 100 by using an anisotropic conductive film.

[0156] The display circuit board 300 may be a flexible printed circuit board (FPCB) that can be bent, a rigid printed circuit board (PCB) that maintains a flat shape, or a composite printed circuit board having both a rigid printed circuit board and a flexible printed circuit board.

[0157] The display circuit board 300 may be connected to a signal pad SPD (see Figure 10 ) provided on one side of the sub-region SBA.

[0158] The touch driving circuit 400 and the scan driving circuit 500 can be mounted on the display circuit board 300.

[0159] The touch driving circuit 400 can be electrically connected to the touch sensor layer 150 of the display device 100.

[0160] The touch driving circuit 400 can apply a touch driving signal to the driving lines of the touch sensor layer 150 and receive a touch sensing signal from the sensing lines. In addition, the touch driving circuit 400 can detect the amount of change in the charge of the capacitance based on the touch sensing signal, thereby determining whether a user has touched or approached. A user's touch means that an object such as a pen or the user's finger directly contacts the top surface of the cover window provided on the touch sensor layer. A user's approach means that an object such as a pen or the user's finger hovers over the top surface of the cover window. The touch driving circuit 400 can output touch data including the touch coordinates of the user to the main processor 15.

[0161] The scan driving circuit 500 can be electrically connected to the readout line ROL of the circuit layer 120.

[0162] The scan driving circuit 500 can collect the light sensing signals of the light sensing elements PD provided in the light sensing area ODA of the main area MA through the photosensing pixel driver DPD and the readout line ROL. In addition, based on the collected light sensing signals, the scan driving circuit 500 can output scan data regarding the shape of the object in contact with the screen to the main processor 15 by detecting the difference in the amount of light reflected by the object in contact with the screen.

[0163] Figure 6 is a diagram showing the scanning function of the light sensing area shown by Figure 5 as shown.

[0164] Refer to Figure 6 , the display device 100 according to one or more embodiments may include light sensing elements PD (e.g., Figure 8 ) provided in the light sensing area ODA, and thus can provide a scanning function to detect the shape of an object in contact with the screen.

[0165] The fingerprint of the user's finger FG in contact with the cover window 11 includes ridges RID and valleys VAL between the ridges RID. The ridges RID in the fingerprint are in contact with the cover window 11. However, the valleys VAL in the fingerprint are spaced apart from the cover window 11 (e.g., separated). That is, the top surface of the cover window 11 facing the valleys VAL is in contact with the air.

[0166] Light emitted from the emission area EA can be reflected by the finger FG of a user in contact with the cover window 11 and detected by the photosensing element PD of the photosensing area ODA. However, since the refractive index of the finger FG is different from that of air, the amount of light reflected from the ridge RID may be different from the amount of light reflected from the valley VAL.

[0167] Therefore, based on the difference in the amount of light incident on the photosensing element PD, the ridges RID and valleys VAL of the fingerprint of the finger FG can be deduced, and thus the fingerprint pattern of the finger FG can be detected.

[0168] Figure 7 Is a block diagram showing Figure 4 of the circuit layer.

[0169] Reference Figure 7 , the circuit layer 120 of the display device 100 according to one or more embodiments may include a light-emitting pixel driver EPD corresponding to the emission area EA of the display area DA, a photosensing pixel driver DPD corresponding to the photosensing area ODA of the display area DA, a data line DL electrically connected to the light-emitting pixel driver EPD, and a readout line ROL electrically connected to the photosensing pixel driver DPD.

[0170] The display device 100 according to one or more embodiments may include: a display driving circuit (e.g., a data driver) 200 that transmits a data signal Vdata (see Figure 8 ) to be applied to the light-emitting pixel driver EPD to the data line DL; and a scan driving circuit (e.g., a readout IC) 500 that collects the photosensing signals of the photosensing pixel driver DPD through the readout line ROL.

[0171] The display device 100 according to one or more embodiments may further include: a gate driving circuit (e.g., a gate driver) 101 that provides one or more gate signals to the light-emitting pixel driver EPD and the photosensing pixel driver DPD; an emission control circuit (e.g., an emission driver) 102 that provides an emission control signal EC to the light-emitting pixel driver EPD (see Figure 8 ); a power supply unit 700 that provides various powers and voltages to the light-emitting pixel driver EPD and the photosensing pixel driver DPD; and a timing controller 800 that controls the driving timing.

[0172] The timing controller 800 receives an image signal provided from outside the display device 100. The timing controller 800 can output image data DATA and a data control signal DCS to the display driving circuit 200. In addition, the timing controller 800 can generate a scan control signal SCS for controlling the operation timing of the gate driving circuit 101 and a transmit control driving signal ECS for controlling the operation timing of the transmit control circuit 102. For example, the timing controller 800 can generate the scan control signal SCS and the transmit control driving signal ECS, output the scan control signal SCS to the gate driving circuit 101 through a scan control line, and output the transmit control driving signal ECS to the transmit control circuit 102 through a transmit control driving line.

[0173] The display driving circuit 200 can convert the image data DATA into analog data voltages and output them to the data lines DL.

[0174] The gate driving circuit 101 can generate gate signals in response to the scan control signal SCS and sequentially output the gate signals to the gate lines GL. The gate lines GL can include a scan write-in line GWL for transmitting a scan write-in signal GW (see Figure 8 ), a scan initialization line GIL for transmitting a scan initialization signal GI (see Figure 8 ), a gate control line GCL for transmitting a gate control signal GC (see Figure 8 ), a bias control line GBL for transmitting a bias control signal GB (see Figure 8 ), a reset control line GRL for transmitting a reset control signal GR (see Figure 8 ), and a reset control line GRL for transmitting a reset control signal GR (see Figure 8 ). Figure 8 ), a bias control line GBL for transmitting a bias control signal GB (see Figure 8 ), and a reset control line GRL for transmitting a reset control signal GR (see Figure 8 ). Figure 8 )

[0175] The transmit control circuit 102 can sequentially output a transmit control signal EC (see Figure 8 ) to the transmit control lines ECL in response to the transmit control driving signal ECS. The transmit control signal EC of the transmit control circuit 102 can have pulses of a first level voltage or a second level voltage. In one or more embodiments, the transmit control circuit 102 can be provided without being separated from the gate driving circuit 101 and can be incorporated into the gate driving circuit 101.

[0176] The power supply unit 700 can provide various types of power required to drive the light-emitting pixel driver EPD and the light-sensing pixel driver DPD.

[0177] For example, the power supply unit 700 may provide a first power ELVDD (see Figure 8 ) for driving the light-emitting element LE and a second power ELVSS (see Figure 8 ), as well as a first initialization voltage VINT (see Figure 8 ) and a second initialization voltage VAINT (see Figure 8 ) for initializing the light-emitting pixel driver EPD.

[0178] In addition, the power supply unit 700 may also provide a reset voltage VRST (see Figure 8 ) for resetting the light-sensing pixel driver DPD.

[0179] The scan driving circuit 500 may be electrically connected to the light-sensing element PD through the readout line ROL and the light-sensing pixel driver DPD.

[0180] Each of the light-sensing elements PD may generate a photocurrent corresponding to the amount of light incident on the light-sensing element PD, and the scan driving circuit 500 may detect the shape of the user's fingerprint based on the photocurrent of each of the light-sensing elements PD.

[0181] The scan driving circuit 500 may generate scan data according to the amplitude of the photocurrent detected by the light-sensing element PD and transmit it to the main processor 15, and the main processor 15 may compare the scan data with the reference data and run an application program based on whether the scan data matches the user's fingerprint.

[0182] Figure 8 Is Figure 7 The equivalent circuit diagrams of the light-emitting pixel driver and the light-sensing pixel driver shown.

[0183] Refer to Figure 8 , one of the light-emitting elements LE of the element layer 130 may be electrically connected between one of the light-emitting pixel drivers EPD of the circuit layer 120 and the second power ELVSS.

[0184] That is, the anode electrode 131 (see Figure 9 ) of the light-emitting element LE may be electrically connected to the light-emitting pixel driver EPD, and the cathode electrode 134 (see Figure 9 ) of the light-emitting element LE may be applied with the second power ELVSS having a voltage level lower than that of the first power ELVDD.

[0185] The capacitor Cel connected in parallel with the light-emitting element LE represents the parasitic capacitance between the anode electrode 131 and the cathode electrode 134.

[0186] The circuit layer 120 may further include a first power line VDL for transmitting a first power ELVDD, a first initialization voltage line VIL for transmitting a first initialization voltage VINT, a second initialization voltage line VAIL for transmitting a second initialization voltage VAINT, and a bias power line VBL for transmitting a bias voltage VBS.

[0187] The circuit layer 120 may further include a scan write line GWL for transmitting a scan write signal GW, a scan initialization line GIL for transmitting a scan initialization signal GI, a transmission control line ECL for transmitting a transmission control signal EC, a gate control line GCL for transmitting a gate control signal GC, and a bias control line GBL for transmitting a bias control signal GB.

[0188] One light-emitting pixel driver EPD of the circuit layer 120 may include a first transistor T1 configured to generate a driving current for driving a light-emitting element LE, two or more transistors T2 to T8 electrically connected to the first transistor T1, and at least one first capacitor PC1.

[0189] The first transistor T1 is connected in series with the light-emitting element LE between the first power ELVDD and the second power ELVSS.

[0190] That is, a first electrode (e.g., a source electrode) of the first transistor T1 may be electrically connected to the first power line VDL through a fifth transistor T5. In addition, a second electrode (e.g., a drain electrode) of the first transistor T1 may be electrically connected to an anode electrode 131 of the light-emitting element LE through a sixth transistor T6.

[0191] The first electrode of the first transistor T1 may be electrically connected to the data line DL through a second transistor T2.

[0192] A gate electrode of the first transistor T1 may be electrically connected to the first power line VDL through the first capacitor PC1. That is, the first capacitor PC1 may be electrically connected between the gate electrode of the first transistor T1 and the first power line VDL.

[0193] Therefore, the potential of the gate electrode of the first transistor T1 may be maintained by the first power ELVDD of the first power line VDL.

[0194] In addition, when a data signal Vdata of the data line DL is transmitted to the first electrode of the first transistor T1 through the turned-on second transistor T2, a voltage difference corresponding to the data signal Vdata and the first power ELVDD may be generated between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1.

[0195] In this case, when the voltage difference between the gate electrode of the first transistor T1 and the first electrode of the first transistor T1 (i.e., the gate-source voltage difference) becomes equal to or greater than the threshold voltage, the first transistor T1 can be turned on, thereby generating a drain-source current of the first transistor T1 corresponding to the data signal Vdata.

[0196] Then, when the fifth transistor T5 and the sixth transistor T6 are turned on, the first transistor T1 can be connected in series with the light-emitting element LE between the first power line VDL and the second power line VSL. Therefore, the drain-source current of the first transistor T1 corresponding to the data signal Vdata can be provided as the drive current of the light-emitting element LE.

[0197] Therefore, the light-emitting element LE can emit light having a brightness corresponding to the data signal Vdata.

[0198] In one or more embodiments, the first transistor T1 may include a second gate electrode connected to the first power line VDL.

[0199] The second transistor T2 may be electrically connected between the first electrode of the first transistor T1 and the data line DL. The second transistor T2 may be turned on by a scan write signal GW of the scan write line GWL.

[0200] The third transistor T3 may be electrically connected between the gate electrode of the first transistor T1 and the second electrode of the first transistor T1. The third transistor T3 may be turned on by a gate control signal GC of the gate control line GCL and may connect the gate electrode of the first transistor T1 to the second electrode of the first transistor T1. In this way, when the third transistor T3 is turned on, the first transistor T1 can act as a diode (for example, the first transistor T1 can be diode-connected).

[0201] The fourth transistor T4 may be connected between the gate electrode of the first transistor T1 and the first initialization voltage line VIL. The fourth transistor T4 may be turned on by a scan initialization signal GI of the scan initialization line GIL and may initialize the gate electrode of the first transistor T1.

[0202] The third transistor T3 and the fourth transistor T4 may be provided as N-type MOSFETs and may be dual-gate transistors.

[0203] The fifth transistor T5 may be electrically connected between the first electrode of the first transistor T1 and the first power line VDL.

[0204] The sixth transistor T6 may be electrically connected between the second electrode of the first transistor T1 and the anode electrode 131 of the light-emitting element LE.

[0205] The fifth transistor T5 and the sixth transistor T6 can be turned on by an emission control signal EC transmitted through an emission control line ECL.

[0206] The seventh transistor T7 can be electrically connected between an anode electrode 131 of a light-emitting element LE and a second initialization voltage line VAIL. The seventh transistor T7 can be turned on by a bias control signal GB transmitted through a bias control line GBL.

[0207] The eighth transistor T8 can be connected between a first electrode of the first transistor T1 and a bias power line VBL.

[0208] The eighth transistor T8 can be turned on by a bias control signal GB transmitted through a bias control line GBL.

[0209] Among the first transistor T1 to the eighth transistor T8, the transistors T1, T2, and T5 to T8 other than the third transistor T3 and the fourth transistor T4 can be set as P-type MOSFETs.

[0210] In addition, one of the photosensing elements PD in the element layer 130 can be electrically connected between an element output node NOP of one of the photosensing pixel drivers DPD in the circuit layer 120 and a second power supply ELVSS.

[0211] The circuit layer 120 may further include: a reset control line GRL for transmitting a reset control signal GR for starting the reset of the photosensing pixel driver DPD; a reset voltage line VRL for transmitting a reset voltage VRST for resetting the photosensing pixel driver DPD; and a readout line ROL for electrically connecting the photosensing pixel driver DPD to the scan drive circuit 500.

[0212] Each of the photosensing pixel drivers DPD may include at least one transistor among transistors T9, T10, and T11.

[0213] The photosensing element PD may be a photoelectric conversion element that converts incident light into an electrical signal by generating a photocurrent corresponding to the amount of incident light and outputs a photosensing signal.

[0214] The photosensing element PD may be a photodiode, which includes a sensing anode electrode, a sensing cathode electrode, and a photoelectric conversion layer provided between the sensing anode electrode and the sensing cathode electrode.

[0215] The photosensing element PD may be a phototransistor or an inorganic photodiode formed of a p-n type or p-i-n type inorganic material. Optionally, the photosensing element PD may also be an organic photodiode, which includes an electron-donating material that generates donor ions and an electron-accepting material that generates acceptor ions.

[0216] When light is incident on the photosensing element PD, the photoelectric conversion layer can react with the incident light to generate photo charges, and the photo charges generated in the photoelectric conversion layer can move, thereby generating a photocurrent between the sensing anode electrode and the sensing cathode electrode.

[0217] As an example, the photo charges generated in the photoelectric conversion layer by the light incident on the photosensing element PD can accumulate in the sensing anode electrode. In addition, the potential of the element output node NOP electrically connected to the sensing anode electrode can increase due to the photo charges accumulated in the sensing anode electrode. When the photosensing element PD and the readout line ROL are connected to each other at the element output node NOP through the conduction of the ninth transistor T9 and the eleventh transistor T11, a sensing voltage proportional to the voltage of the element output node NOP where the charge is accumulated can be accumulated at the node N3 between the readout line ROL and the eleventh transistor T11.

[0218] The ninth transistor T9 can include a gate electrode electrically connected to the element output node NOP, and can be electrically connected between the second initialization voltage line VAIL and the eleventh transistor T11.

[0219] The ninth transistor T9 can be a source follower amplifier that generates a source-drain current proportional to the amount of charge of the element output node NOP input to its gate electrode.

[0220] That is, when the potential of the element output node NOP increases due to the photo charges accumulated in the photosensing element PD and the voltage difference between the second initialization voltage VAINT and the potential of the element output node NOP becomes equal to or greater than the threshold voltage of the ninth transistor T9, the ninth transistor T9 can be turned on. In this case, a photosensing signal corresponding to the voltage difference between the second initialization voltage VAINT and the potential of the element output node NOP can be generated by the turned-on ninth transistor T9.

[0221] Although Figure 8 it is shown that the first electrode of the ninth transistor T9 is connected to the second initialization voltage line VAIL, the present disclosure is not limited to Figure 8 the illustration. That is, the first electrode of the ninth transistor T9 can be connected to one of the first power line VDL and the first initialization voltage line VIL instead of the second initialization voltage line VAIL.

[0222] The tenth transistor T10 can be electrically connected between the element output node NOP and the reset voltage line VRL, and can be turned on by the reset control signal GR of the reset control line GRL. Therefore, when the tenth transistor T10 is turned on by the reset control signal GR, the potential of the element output node NOP can be reset to the reset voltage VRST of the reset voltage line VRL.

[0223] The eleventh transistor T11 may be electrically connected between the second electrode of the ninth transistor T9 and the readout line ROL, and may be turned on by a sweep write signal GW of the sweep write line GWL. Accordingly, the source-drain current of the ninth transistor T9 (i.e., the light sensing signal) may be transmitted to the readout line ROL through the eleventh transistor T11 turned on by the sweep write signal GW.

[0224] The ninth transistor T9 and the eleventh transistor T11 may be configured as P-type MOSFETs, and the tenth transistor T10 may be configured as an N-type MOSFET.

[0225] Figure 9 is a cross-sectional view showing Figure 8 the first transistor, the second transistor, the fourth transistor, the sixth transistor, and a light-emitting element.

[0226] Reference Figure 9, according to one or more embodiments, the circuit layer 120 of the display device 100 may include a buffer layer 121 covering the first light blocking layer LB1 on the substrate 110, a first semiconductor layer CH1, S1, D1, CH2, S2, D2, CH6, S6, and D6 disposed on the buffer layer 121, a first gate insulating layer 122 covering the first semiconductor layer CH1, S1, D1, CH2, S2, D2, CH6, S6, and D6 and the buffer layer 121, a first gate conductive layer G1, G2, and G6 disposed on the first gate insulating layer 122, a second gate insulating layer 123 covering the first gate conductive layer G1, G2, and G6 and the first gate insulating layer 122, a second gate conductive layer CPE and LB2 disposed on the second gate insulating layer 123, an additional interlayer insulating layer 124 covering the second gate conductive layer CPE and LB2 and the second gate insulating layer 123, a second semiconductor layer CH4, S4, and D4 disposed on the additional interlayer insulating layer 124, a third gate insulating layer 125 covering the second semiconductor layer CH4, S4, and D4 and the additional interlayer insulating layer 124, a third gate conductive layer G4 disposed on the third gate insulating layer 125, an interlayer insulating layer 126 covering the third gate conductive layer G4 and the third gate insulating layer 125, a first source-drain conductive layer SDCDL1 disposed on the interlayer insulating layer 126, a first planarization layer 127 covering the first source-drain conductive layer SDCDL1 and the interlayer insulating layer 126, a second source-drain conductive layer SDCDL2 disposed on the first planarization layer 127, a second planarization layer 128 covering the second source-drain conductive layer SDCDL2 and the first planarization layer 127, a third source-drain conductive layer SDCDL3 disposed on the second planarization layer 128, and a third planarization layer 129 covering the third source-drain conductive layer SDCDL3 and the second planarization layer 128. The first source-drain conductive layer SDCDL1 may include a first anode connection electrode ANCE1, a first data connection electrode DCE1, a gate connection electrode GCNE, and a first initialization voltage line VIL. The second source-drain conductive layer SDCDL2 may include a second anode connection electrode ANCE2 and a second data connection electrode DCE2. The third source-drain conductive layer SDCDL3 may include a third anode connection electrode ANCE3 and a data line DL.

[0227] The first transistor T1 may include a channel portion CH1, a source portion S1, and a drain portion D1 formed of the first semiconductor layer on the buffer layer 121, and a gate electrode G1 disposed on the first gate insulating layer 122 and overlapping the channel portion CH1 in the third direction DR3 (e.g., the thickness direction of the substrate 110).

[0228] The channel portion CH1 of the first transistor T1 may overlap with the first light blocking layer LB1 on the substrate 110 in the third direction DR3.

[0229] The second transistor T2 may include a channel portion CH2, a source portion S2, and a drain portion D2 formed of a first semiconductor layer on the buffer layer 121, and a gate electrode G2 disposed on the first gate insulating layer 122 and overlapping with the channel portion CH2 in the third direction DR3.

[0230] The sixth transistor T6 may include a channel portion CH6, a source portion S6, and a drain portion D6 formed of a first semiconductor layer on the buffer layer 121, and a gate electrode G6 disposed on the first gate insulating layer 122 and overlapping with the channel portion CH6 in the third direction DR3.

[0231] The source portion S2 of the second transistor T2 may be electrically connected to the data line DL through the first data connection electrode DCE1 and the second data connection electrode DCE2.

[0232] The first data connection electrode DCE1 may be disposed on the interlayer insulating layer 126 and may be electrically connected to the source portion S2 of the second transistor T2 through a first data contact hole DCH1 that penetrates the interlayer insulating layer 126, the third gate insulating layer 125, the additional interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0233] The second data connection electrode DCE2 may be disposed on the first planarization layer 127 and may be electrically connected to the first data connection electrode DCE1 through a second data contact hole DCH2 that penetrates the first planarization layer 127.

[0234] The data line DL may be disposed on the second planarization layer 128 and may be electrically connected to the second data connection electrode DCE2 through a third data contact hole DCH3 that penetrates the second planarization layer 128.

[0235] The drain portion D2 of the second transistor T2 may be connected to the source portion S1 of the first transistor T1.

[0236] The drain portion D1 of the first transistor T1 may be connected to the source portion S6 of the sixth transistor T6.

[0237] The drain portion D6 of the sixth transistor T6 may be electrically connected to the anode electrode 131 through the first anode connection electrode ANCE1, the second anode connection electrode ANCE2, and the third anode connection electrode ANCE3.

[0238] The first anode connection electrode ANCE1 can be disposed on the interlayer insulating layer 126 and can be electrically connected to the drain portion D6 of the sixth transistor T6 through a first anode contact hole ANCH1 that penetrates the interlayer insulating layer 126, the third gate insulating layer 125, the additional interlayer insulating layer 124, the second gate insulating layer 123, and the first gate insulating layer 122.

[0239] The second anode connection electrode ANCE2 can be disposed on the first planarization layer 127 and can be electrically connected to the first anode connection electrode ANCE1 through a second anode contact hole ANCH2 that penetrates the first planarization layer 127.

[0240] The third anode connection electrode ANCE3 can be disposed on the second planarization layer 128 and can be electrically connected to the second anode connection electrode ANCE2 through a third anode contact hole ANCH3 that penetrates the second planarization layer 128.

[0241] The anode electrode 131 can be disposed on the third planarization layer 129 and can be electrically connected to the third anode connection electrode ANCE3 through a fourth anode contact hole ANCH4 that penetrates the third planarization layer 129.

[0242] The first capacitor PC1 can be provided by an overlapping region between a capacitor electrode CPE disposed on the second gate insulating layer 123 and the gate electrode G1 of the first transistor T1.

[0243] The fourth transistor T4 can include a channel portion CH4, a source portion S4, and a drain portion D4 formed of a second semiconductor layer on the additional interlayer insulating layer 124, and a gate electrode G4 disposed on the third gate insulating layer 125 and overlapping the channel portion CH4 in the third direction DR3.

[0244] The channel portion CH4 of the fourth transistor T4 can overlap a second light blocking layer LB2 on the second gate insulating layer 123 in the third direction DR3.

[0245] The source portion S4 of the fourth transistor T4 can be electrically connected to a first initialization voltage line VIL on the interlayer insulating layer 126 through a hole VICH that penetrates the interlayer insulating layer 126 and the third gate insulating layer 125.

[0246] The drain portion D4 of the fourth transistor T4 can be electrically connected to the gate electrode G1 of the first transistor T1 through a gate connection electrode GCNE on the interlayer insulating layer 126.

[0247] The gate connection electrode GCNE can be electrically connected to the drain portion D4 of the fourth transistor T4 through a first gate contact hole GCH1 that penetrates the interlayer insulating layer 126 and the third gate insulating layer 125.

[0248] The gate connection electrode GCNE can be electrically connected to the gate electrode G1 of the first transistor T1 through a second gate contact hole GCH2 that penetrates the interlayer insulating layer 126, the third gate insulating layer 125, the additional interlayer insulating layer 124, and the second gate insulating layer 123.

[0249] Since the third transistor T3 and the tenth transistor T10 are structurally similar to the fourth transistor T4 and the fifth transistor T5, the seventh transistor T7, the ninth transistor T9, and the eleventh transistor T11 are structurally similar to the second transistor T2 and the sixth transistor T6, redundant descriptions are omitted below.

[0250] In addition, the circuit layer 120 of the display device 100 according to one or more embodiments may further include wirings that are electrically connected between some of the data lines DL and the display driving circuit 200 and are disposed in the display area DA, and wirings that are electrically connected between some of the readout lines ROL and the scan driving circuit 500 and are disposed in the display area DA, so as to reduce the width of the non-display area NDA.

[0251] In one or more embodiments, the element layer 130 includes an anode electrode 131 connected to the third anode connection electrode ANCE3 through a fourth anode contact hole ANCH4 that penetrates the third planarization layer 129, a pixel defining layer (PDL) 132 disposed on the third planarization layer 129 and covering the edge of the anode electrode 131, an intermediate layer (e.g., a light-emitting layer) 133 that directly contacts the anode electrode 131 and also overlaps with the pixel defining layer 132 at the edge, and a cathode electrode 134 that covers the intermediate layer 133 and the pixel defining layer 132. A packaging layer 140 may be disposed on the element layer 130.

[0252] Figure 10 is a plan view of a Figure 4 substrate according to one or more embodiments.

[0253] Refer to Figure 10 , the substrate 110 of the display device 100 according to one or more embodiments may include a main area MA corresponding to the display surface, and a sub-area SBA protruding from one side of the main area MA.

[0254] The main area MA may include a display area DA disposed at its center and occupying most of it, and a non-display area NDA disposed at the periphery to surround (e.g., around) the display area DA.

[0255] The display area DA may include a bypass area DEA disposed on one side adjacent to the sub-area SBA, and a normal area GA disposed in the remaining area except the bypass area DEA.

[0256] The bypass region DEA may include a bypass intermediate region MDDA disposed at the center in a first direction DR1, a first bypass side region SDA1 spaced apart from the bypass intermediate region MDDA in the first direction DR1 and in contact with the non-display region NDA, and a second bypass side region SDA2 disposed between the bypass intermediate region MDDA and the first bypass side region SDA1.

[0257] Compared with the bypass intermediate region MDDA and the second bypass side region SDA2, the first bypass side region SDA1 may be disposed adjacent to the bent corner of the substrate 110.

[0258] The first bypass side region SDA1 and the second bypass side region SDA2 may be disposed between one side of the bypass intermediate region MDDA in the first direction DR1 and the non-display region NDA, and between the other side of the bypass intermediate region MDDA in the first direction DR1 and the non-display region NDA.

[0259] The general region GA may include a general intermediate region GMA connected to the bypass intermediate region MDDA of the bypass region DEA in a second direction DR2, a first general side region GSA1 connected to the first bypass side region SDA1 in the second direction DR2, and a second general side region GSA2 connected to the second bypass side region SDA2 in the second direction DR2.

[0260] The non-display region NDA may include a gate driving circuit region GDRA in which the gate driving circuit 101 and the emission control circuit 102 are disposed.

[0261] The gate driving circuit region GDRA may be disposed in a portion of the non-display region NDA adjacent to at least one side of the display region DA in the first direction DR1.

[0262] The sub-region SBA may include a bent region BA deformed into a bent shape, a first sub-region SB1 disposed between one side of the bent region BA and the main region MA, and a second sub-region SB2 connected to the other side of the bent region BA.

[0263] When the bent region BA is deformed into a bent shape, the second sub-region SB2 is disposed under the substrate 110 and overlaps with the main region MA.

[0264] The display driving circuit 200 may be disposed in the second sub-region SB2.

[0265] The signal pad SPD coupled to the display circuit board 300 may be disposed at one edge of the second sub-region SB2.

[0266] Figure 11 Is shownFigure 10 Layout diagram of part C. Figure 12 is a cross-sectional view taken along Figure 11 line E-E' of

[0267] Referring to Figure 11 , according to one or more embodiments, the circuit layer 120 of the display device 100 may include: a light-emitting pixel driver EPD, which is electrically connected to the light-emitting element LE of the element layer 130 and arranged side by side along a first direction DR1 and a second direction DR2; a data line DL, which extends in the second direction DR2 and transmits a data signal Vdata (see Figure 8 ) to the light-emitting pixel driver EPD; a first auxiliary line ASL1, which extends in the first direction DR1; a second auxiliary line ASL2, which extends in the second direction DR2 and is adjacent to the data line DL; and a third auxiliary line ASL3, which extends in the second direction DR2 and is disposed between the second auxiliary lines ASL2 in the first direction DR1.

[0268] According to one or more embodiments, the circuit layer 120 may further include a light-sensing pixel driver DPD that is electrically connected to the light-sensing element PD of the element layer 130, respectively.

[0269] In this case, the circuit layer 120 may further include a readout line ROL that extends in the second direction DR2, the readout line ROL being electrically connected to the light-sensing pixel driver DPD and transmitting a light-sensing signal.

[0270] In one example, the readout lines ROL may be arranged in pairs between the data lines DL in the first direction DR1. That is, one of two adjacent readout lines ROL may be adjacent to one data line DL on one side of the first direction DR1, and the other of the two adjacent readout lines ROL may be adjacent to another data line DL on the other side of the first direction DR1.

[0271] The light-emitting pixel driver EPD may include a first light-emitting pixel driver EPD1 (see Figure 13 ) and a second light-emitting pixel driver EPD2 (see Figure 13 ) that are adjacent to each other.

[0272] The first light-emitting pixel driver EPD1 (see Figure 13 ) and the second light-emitting pixel driver EPD2 (see Figure 13 ) may overlap with one first auxiliary line ASL1.

[0273] The first light-emitting pixel driver EPD1 may overlap with one data line DL and one second auxiliary line ASL2.

[0274] The second light-emitting pixel driver EPD2 may overlap with another data line DL and another second auxiliary line ASL2.

[0275] A third auxiliary line ASL3 may be arranged adjacent to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0276] The first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2 may be symmetrical with respect to the boundary between the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0277] That is, in the first light-emitting pixel driver EPD1, a second auxiliary line ASL2 may be arranged between a data line DL and a third auxiliary line ASL3.

[0278] In addition, in the second light-emitting pixel driver EPD2, another second auxiliary line ASL2 may be arranged between another data line DL and a third auxiliary line ASL3.

[0279] According to one or more embodiments, the data line DL may include a first data line DL1 arranged in the first bypass side region SDA1 and a second data line DL2 arranged in the second bypass side region SDA2.

[0280] The first auxiliary line ASL1 may include a first bypass auxiliary line TASL1 electrically connected to the first data line DL1 in the first bypass side region SDA1.

[0281] The second auxiliary line ASL2 may include a second bypass auxiliary line TASL2 adjacent to the second data line DL2 in the second bypass side region SDA2 and electrically connected to the first bypass auxiliary line TASL1.

[0282] According to one or more embodiments, the circuit layer 120 may further include a data supply line DSPL arranged in the non-display area NDA and electrically connected to the display driving circuit 200 and the data line DL.

[0283] The data supply line DSPL may include a first data supply line DSPL1 for transmitting the data signal of the first data line DL1 and a second data supply line DSPL2 for transmitting the data signal of the second data line DL2.

[0284] According to one or more embodiments, the data supply line DSPL may extend to the second bypass side region SDA2 and the bypass intermediate region MDDA.

[0285] Therefore, the first data supply line DSPL1 can extend to the second bypass auxiliary line TASL2 of the second bypass side region SDA2, and can be electrically connected to the first data line DL1 through the second bypass auxiliary line TASL2 and the first bypass auxiliary line TASL1.

[0286] On the other hand, the second data supply line DSPL2 can extend to the second bypass side region SDA2, and can be directly electrically connected to the second data line DL2.

[0287] The data line DL can further include a third data line DL3 provided in the bypass intermediate region MDDA, and the data supply line DSPL can further include a third data supply line DSPL3 that transmits the data signal of the third data line DL3.

[0288] The third data supply line DSPL3 can extend to the bypass intermediate region MDDA, and can be directly electrically connected to the third data line DL3.

[0289] In this way, since the first data supply line DSPL1 does not extend to the first data line DL1 of the first bypass side region SDA1, but extends to the second bypass auxiliary line TASL2 of the second bypass side region SDA2, the extension length of the first data supply line DSPL1 can be shortened. As a result, the width of the region required to set the data supply line DSPL can be reduced, and thus the width of the non-display region NDA can be reduced.

[0290] In addition, since the data supply line DSPL is not provided in the portion of the non-display region NDA between the bent corner of the substrate 110 and the first bypass side region SDA1, the width of the non-display region NDA can be further reduced.

[0291] The first bypass auxiliary line TASL1 extends from the second bypass auxiliary line TASL2 to the first data line DL1.

[0292] The second bypass auxiliary line TASL2 extends from the first data supply line DSPL1 of the non-display region NDA to the first bypass auxiliary line TASL1.

[0293] In this way, since the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2 are restrictedly arranged in the bypass region DEA, the ends of the first bypass auxiliary line TASL1 and the ends of the second bypass auxiliary line TASL2 are regularly arranged. Therefore, the visibility of the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2 may be increased.

[0294] To prevent this situation, the first auxiliary line ASL1 can further include not only the first bypass auxiliary line TASL1, but also the power auxiliary horizontal line VSAHL. In addition, the second auxiliary line ASL2 can further include not only the second bypass auxiliary line TASL2, but also the auxiliary vertical line DCASL.

[0295] In other words, the remaining part of the first auxiliary line ASL1 except the first bypass auxiliary line TASL1 can be the power auxiliary horizontal line VSAHL.

[0296] In addition, the remaining part of the second auxiliary line ASL2 except the second bypass auxiliary line TASL2 can be the auxiliary vertical line DCASL.

[0297] Two of the power auxiliary horizontal lines VSAHL can extend from both ends of the first bypass auxiliary line TASL1 to the non-display area NDA.

[0298] One of the auxiliary vertical lines DCASL can extend from one end of the second bypass auxiliary line TASL2 to the non-display area NDA in a direction away from the sub-area SBA.

[0299] Therefore, a part of each second data line DL2 is adjacent to the second bypass auxiliary line TASL2, and another part of the second data line DL2 can be adjacent to one auxiliary vertical line DCASL extending from one end of the second bypass auxiliary line TASL2.

[0300] Since the second bypass auxiliary line TASL2 is only provided in the second bypass side area SDA2, each of the first data line DL1 in the first bypass side area SDA1 and the third data line DL3 in the bypass intermediate area MDDA can be adjacent to the auxiliary vertical line DCASL.

[0301] The circuit layer 120 can further include a first power supply line VDSPL and a second power supply line VSSPL, which respectively transmit the first power ELVDD (see Figure 8 ) for driving the light-emitting element LE (see Figure 8 ) and the second power ELVSS (see Figure 8 ).

[0302] The first power supply line VDSPL and the second power supply line VSSPL can be provided in the non-display area NDA and can extend to the sub-area SBA.

[0303] The first power supply line VDSPL can be electrically connected to the signal pad SPD (see Figure 10 ) provided in the second sub-area SB2 for transmitting the first power ELVDD (see Figure 8The first power pad of ().

[0304] The second power supply line VSSPL can be electrically connected to the signal pad SPD disposed in the second sub-region SB2 (see Figure 10 ) among the second power pads for transmitting the second power ELVSS (see Figure 8 ).

[0305] The power assist horizontal line VSAHL can be electrically connected to the second power supply line VSSPL and can transmit the second power ELVSS (see Figure 8 ).

[0306] According to one or more embodiments, each of the auxiliary vertical lines DCASL can transmit one of the second power ELVSS (see Figure 8 ), the first initialization voltage VINT (see Figure 8 ), and the second initialization voltage VAINT (see Figure 8 ).

[0307] In addition, each of the third auxiliary lines ASL3 can transmit one of the second power ELVSS (see Figure 8 ), the first initialization voltage VINT (see Figure 8 ), and the second initialization voltage VAINT (see Figure 8 ).

[0308] Thus, by electrically connecting each of the auxiliary vertical lines DCASL and the third auxiliary lines ASL3 to one of the power assist horizontal line VSAHL, the first initialization voltage line VIL, and the second initialization voltage line VAIL, the second power ELVSS (see Figure 8 ), the first initialization voltage VINT (see Figure 8 ), and the second initialization voltage VAINT (see Figure 8 ) can be transmitted to the display area DA through a grid-shaped wiring having a relatively low resistance.

[0309] This will be described later with reference to Figure 13 .

[0310] Referring to Figure 12 , the data line DL, the second auxiliary line ASL2, the third auxiliary line ASL3, and the readout line ROL can be disposed on at least one insulating layer (e.g., the first planarization layer 127 and the second planarization layer 128) covering the first auxiliary line ASL1.

[0311] For example, the first auxiliary line ASL1 can be disposed on the first source-drain conductive layer SDCDL1 on the interlayer insulating layer 126 (see Figure 9) in (or at the first source-drain conductive layer SDCDL1), and is covered by the first planarization layer 127.

[0312] The data line DL, the second auxiliary line ASL2, the third auxiliary line ASL3, and the readout line ROL may be provided in the third source-drain conductive layer SDCDL3 on the second planarization layer 128 (see Figure 9 ) in (or at the third source-drain conductive layer SDCDL3).

[0313] In this case, the first data line DL1 may be electrically connected to the first bypass auxiliary line TASL1 through a contact hole penetrating the second planarization layer 128 and the first planarization layer 127.

[0314] The second bypass auxiliary line TASL2 may also be electrically connected to the first bypass auxiliary line TASL1 through a contact hole penetrating the second planarization layer 128 and the first planarization layer 127.

[0315] Figure 13 is a plan view showing part D according to one or more embodiments Figure 10 of.

[0316] As Figure 13 shown, according to one or more embodiments, the auxiliary vertical line DCASL (which is the remaining part of the second auxiliary line ASL2 except the second bypass auxiliary line TASL2) may include a first auxiliary vertical line DCASL1 for transmitting the second power supply ELVSS (see Figure 8 ), a second auxiliary vertical line DCASL2 for transmitting the first initialization voltage VINT (see Figure 8 ), and a third auxiliary vertical line DCASL3 for transmitting the second initialization voltage VAINT (see Figure 8 ).

[0317] In addition, according to one or more embodiments, the third auxiliary line ASL3 provided between the second auxiliary lines ASL2 may include a power supply additional line ASL31 for transmitting the second power supply ELVSS (see Figure 8 ), a first initialization voltage additional line ASL32 for transmitting the first initialization voltage VINT (see Figure 8 ), and a second initialization voltage additional line ASL33 for transmitting the second initialization voltage VAINT (see Figure 8 ).

[0318] In one example, the first initialization voltage additional line ASL32 and the second initialization voltage additional line ASL33 may be arranged repeatedly. Optionally, the first initialization voltage additional line ASL32, the power additional line ASL31, the second initialization voltage additional line ASL33, and the power additional line ASL31 may be arranged repeatedly in this order. However, this is only an example, and the arrangement of the third auxiliary line ASL3 is not limited to Figure 13 the illustration of.

[0319] Each of the third auxiliary lines ASL3 may be disposed between two second auxiliary lines ASL2.

[0320] The third auxiliary line ASL3 and the two second auxiliary lines ASL2 adjacent to its two sides may transmit the data signal Vdata of the first data line DL1 (see Figure 8 ), the second power ELVSS (see Figure 8 ), and the first initialization voltage VINT of different voltages (see Figure 8 ) and the second initialization voltage VAINT (see Figure 8 ). However, this is only an example, and the arrangement of the second auxiliary line ASL2 is not limited to Figure 13 the illustration of.

[0321] As Figure 13 shown, according to one or more embodiments, for each pair of adjacent light-emitting pixel drivers EPD among the light-emitting pixel drivers EPD (and the third auxiliary line ASL3 is interposed between the adjacent light-emitting pixel drivers EPD), two electrical connection portions may be provided between the wiring extending in the first direction DR1 and the wiring extending in the second direction DR2.

[0322] The light-emitting pixel driver EPD may include a first light-emitting pixel driver EPD1 and a second light-emitting pixel driver EPD2 adjacent in the first direction DR1.

[0323] One of the first auxiliary lines ASL1 extending in the first direction DR1 may overlap with the first light-emitting pixel driver EPD1 and the second light-emitting pixel driver EPD2.

[0324] The second auxiliary line ASL2 extending in the second direction DR2 and adjacent to the data line DL may include one second auxiliary line ASL2 overlapping with the first light-emitting pixel driver EPD1 and another second auxiliary line ASL2 overlapping with the second light-emitting pixel driver EPD2.

[0325] The third auxiliary lines ASL3 extending in the second direction DR2 may include one third auxiliary line ASL3 adjacent to a boundary between the first and second light emitting pixel drivers EPD1 and EPD2. The third auxiliary line ASL3 may be disposed between one and another second auxiliary line ASL2.

[0326] Through electrical connection between the wiring extending in the first direction DR1 and the wiring extending in the second direction DR2, a first auxiliary line ASL1 ( Figure 11 One of the first initialization voltage line VIL and the second initialization voltage line VAIL may be electrically connected to one of the second auxiliary line ASL2 and the third auxiliary line ASL3.

[0327] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 is a diagram showing a method according to one or more embodiments Figure 13 A plan view of a portion of each of a first light-emitting pixel driver and a second light-emitting pixel driver.

[0328] Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 1 is a diagram showing electrical connections between wirings extending in a first direction DR1 and wirings extending in a second direction DR2 according to one or more embodiments. Figure 14 , Figure 15 , Figure 16 , Figure 17 and Figure 18 In the example, the first bypass auxiliary line TASL1 (see Figure 11 ) and the power auxiliary level VSAHL (see Figure 11 ) can be collectively referred to as the first auxiliary line ASL1, and the second bypass auxiliary line TASL2 (see Figure 11 ) and auxiliary vertical line DCASL (see Figure 13 ) can be collectively referred to as the second auxiliary line ASL2. Here, the auxiliary vertical line DCASL (see Figure 13 ) includes the first auxiliary vertical line DCASL1 (see Figure 13 ), the second auxiliary vertical line DCASL2 (see Figure 13 ) and the third auxiliary vertical line DCASL3 (see Figure 13 ). In addition, Figure 14 , Figure 15 , Figure 16 , Figure 17 andFigure 18 Among them, the power additional line ASL31, the first initialization voltage additional line ASL32, and the second initialization voltage additional line ASL33 can be collectively referred to as the third auxiliary line ASL3.

[0329] As Figure 14 shown, according to one or more embodiments, in each of the light-emitting pixel drivers EPD1 and EPD2, the circuit layer 120 may include a first connection auxiliary electrode CASE1, which has an island shape and is separated (e.g., spaced apart) from the first auxiliary line ASL1.

[0330] As Figure 14 and Figure 15 shown, according to one or more embodiments, the circuit layer 120 may further include a first initialization voltage line VIL and a second initialization voltage line VAIL. The first initialization voltage line VIL has an island shape and is located between the first connection auxiliary electrodes CASE1 in the first light-emitting pixel driver EPD1 and the first connection auxiliary electrodes CASE1 in the second light-emitting pixel driver EPD2. The second initialization voltage line VAIL extends in a first direction DR1, is separated (e.g., spaced apart) from the first connection auxiliary electrode CASE1, and transmits a second initialization voltage VAINT (see Figure 8 ).

[0331] The first initialization voltage line VIL may be electrically connected to an initialization voltage extension line VIEXL through an initialization extension connection hole VIECH. The initialization voltage extension line VIEXL extends in the first direction DR1 and transmits a first initialization voltage VINT (see Figure 8 ). For reference, Figure 13 the first initialization voltage line VIL of Figure 15 schematically represents the first initialization voltage line VIL and the initialization voltage extension line VIEXL of

[0332] The first connection auxiliary electrodes CASE1 in the first light-emitting pixel driver EPD1, the first connection auxiliary electrodes CASE1 in the second light-emitting pixel driver EPD2, and the first initialization voltage line VIL may be disposed between the second initialization voltage line VAIL and the first auxiliary line ASL1 in a second direction DR2.

[0333] In one or more embodiments, the first connection auxiliary electrodes CASE1 in the first light-emitting pixel driver EPD1 and the first connection auxiliary electrodes CASE1 in the second light-emitting pixel driver EPD2 may each be electrically connected to one of a first auxiliary line ASL1, a first initialization voltage line VIL, and a second initialization voltage line VAIL through a first connection auxiliary line CAL1.

[0334] In one or more embodiments, a first connection assist line CAL1 may extend from a first connection assist electrode CASE1 to one of a first assist line ASL1, a first initialization voltage line VIL, and a second initialization voltage line VAIL.

[0335] In one example, as Figure 14 shown, the first connection assist electrode CASE1 in the first light-emitting pixel driver EPD1 may be electrically connected to the first assist line ASL1 through the first connection assist line CAL1, and the first connection assist electrode CASE1 in the second light-emitting pixel driver EPD2 may be electrically connected to the second initialization voltage line VAIL through the first connection assist line CAL1.

[0336] In another example, as Figure 15 shown, the first connection assist electrode CASE1 in the first light-emitting pixel driver EPD1 may be electrically connected to the second initialization voltage line VAIL through the first connection assist line CAL1, and the first connection assist electrode CASE1 in the second light-emitting pixel driver EPD2 may be electrically connected to the first initialization voltage line VIL through the first connection assist line CAL1.

[0337] However, Figure 14 and Figure 15 the illustrations of are only examples, and the settings and shapes of the first connection assist lines CAL1 in each light-emitting pixel driver EPD may vary.

[0338] As Figure 15 and Figure 16 shown, according to one or more embodiments, the circuit layer 120 may further include a second connection assist electrode CASE2, the second connection assist electrode CASE2 having an island shape and overlapping with the first connection assist electrode CASE1 respectively.

[0339] The second connection assist electrode CASE2 may be electrically connected to the first connection assist electrode CASE1 through a first assist connection hole ASCH1.

[0340] As Figure 17 shown, the second connection assist electrode CASE2 may be electrically connected to the second assist line ASL2 through a second assist connection hole ASCH2.

[0341] According to one or more embodiments, the circuit layer 120 may further include a third connection assist electrode CASE3, the third connection assist electrode CASE3 having an island shape, overlapping with the third assist line ASL3 and spaced apart from (e.g., separated from) the second connection assist electrode CASE2.

[0342] One of the third connection auxiliary electrodes CASE3 may be disposed between the second connection auxiliary electrode CASE2 in the first light-emitting pixel driver EPD1 and the second connection auxiliary electrode CASE2 in the second light-emitting pixel driver EPD2.

[0343] According to one or more embodiments, the first power line VDL for transmitting the first power ELVDD (see Figure 8 ) in the circuit layer 120 may be separated (e.g., spaced apart) from the second connection auxiliary electrode CASE2 and the third connection auxiliary electrode CASE3.

[0344] The first auxiliary line ASL1, the first initialization voltage line VIL, the second initialization voltage line VAIL, the first connection auxiliary electrode CASE1, and the first connection auxiliary line CAL1 may be disposed in the first source-drain conductive layer SDCDL1 on the interlayer insulating layer 126 (see Figure 9 ).

[0345] The second connection auxiliary electrode CASE2, the third connection auxiliary electrode CASE3, and the first power line VDL may be disposed in the second source-drain conductive layer SDCDL2 on the first planarization layer 127 (see Figure 9 ).

[0346] The data line DL, the second auxiliary line ASL2, and the third auxiliary line ASL3 may be disposed in the third source-drain conductive layer SDCDL3 on the second planarization layer 128 (see Figure 9 ).

[0347] In this case, the first auxiliary connection hole ASCH1 for the electrical connection between the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 may penetrate the first planarization layer 127 (see Figure 9 ). Further, the second auxiliary connection hole ASCH2 for the electrical connection between the second connection auxiliary electrode CASE2 and the second auxiliary line ASL2 may penetrate the second planarization layer 128 (see Figure 9 ).

[0348] Therefore, in one of the light-emitting pixel drivers EPD, among the first auxiliary line ASL1, the first initialization voltage line VIL, and the second initialization voltage line VAIL, a wiring connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1 in the first direction DR1 may be electrically connected to the second auxiliary line ASL2 through the second connection auxiliary electrode CASE2.

[0349] Optionally, as Figure 17 and Figure 18As shown, one of the second connection auxiliary electrodes CASE2 in the first light-emitting pixel driver EPD1 and the second connection auxiliary electrode CASE2 in the second light-emitting pixel driver EPD2 can be electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary line CAL2, without being electrically connected to the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2.

[0350] In one example, as Figure 17 shown, the second connection auxiliary electrode CASE2 in the first light-emitting pixel driver EPD1 can be electrically connected to a second auxiliary line ASL2 through the second auxiliary connection hole ASCH2, and the second connection auxiliary electrode CASE2 in the second light-emitting pixel driver EPD2 can be electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary line CAL2.

[0351] In another example, as Figure 18 shown, the second connection auxiliary electrode CASE2 in the first light-emitting pixel driver EPD1 can be electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary line CAL2, and the second connection auxiliary electrode CASE2 in the second light-emitting pixel driver EPD2 can be electrically connected to another second auxiliary line ASL2 through the second auxiliary connection hole ASCH2.

[0352] The third connection auxiliary electrode CASE3 can be electrically connected to the third auxiliary line ASL3 through the third auxiliary connection hole ASCH3.

[0353] Therefore, in another one of the light-emitting pixel drivers EPD, among the first auxiliary line ASL1, the first initialization voltage line VIL, and the second initialization voltage line VAIL, a wiring connected to the first connection auxiliary electrode CASE1 in the first direction DR1 through the first connection auxiliary line CAL1 can be electrically connected to the third auxiliary line ASL3 through the second connection auxiliary electrode CASE2 and the third connection auxiliary electrode CASE3.

[0354] Refer to Figure 11 、 Figure 14 and Figure 16, in the first auxiliary line ASL1, the first bypass auxiliary line TASL1 for transmitting the data signal Vdata of the first data line DL1 can be electrically connected to the second bypass auxiliary line TASL2 of the second auxiliary line ASL2 by bypassing and connecting the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 in the light-emitting pixel driver EPD that overlap with the intersection between the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2. That is, the first bypass auxiliary line TASL1 is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, and the second connection auxiliary electrode CASE2 is electrically connected to the second bypass auxiliary line TASL2 of the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2. Therefore, the electrical connection between the first bypass auxiliary line TASL1 and the second bypass auxiliary line TASL2 can be achieved in the bypass connection of the light-emitting pixel driver.

[0355] Reference Figure 13 , Figure 14 and Figure 16 , in the first auxiliary line ASL1, the power auxiliary horizontal line VSAHL for transmitting the second power ELVSS (see Figure 8 ) can be electrically connected to the first auxiliary vertical line DCASL1 of the second auxiliary line ASL2 by electrically connecting the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 in the light-emitting pixel driver EPD through a power connection. That is, the power auxiliary horizontal line VSAHL is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, and the second connection auxiliary electrode CASE2 is electrically connected to the first auxiliary vertical line DCASL1 of the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2. Therefore, the electrical connection between the power auxiliary horizontal line VSAHL and the first auxiliary vertical line DCASL1 can be achieved in the power connection of the light-emitting pixel driver.

[0356] Optionally, refer to Figure 13 , Figure 15 , Figure 17 and Figure 18 , in the first auxiliary line ASL1, the power auxiliary horizontal line VSAHL for transmitting the second power ELVSS (see Figure 8)'s power-assisted horizontal line VSAHL can be electrically connected to the power additional line ASL31 of the third auxiliary line ASL3 through another power connection in the light-emitting pixel driver EPD to the first connection auxiliary electrode CASE1, the second connection auxiliary electrode CASE2, and the third connection auxiliary electrode CASE3 in the light-emitting pixel driver. That is, the power-assisted horizontal line VSAHL is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, the second connection auxiliary electrode CASE2 is electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary line CAL2, and the third connection auxiliary electrode CASE3 is electrically connected to the power additional line ASL31 of the third auxiliary line ASL3 through the third auxiliary connection hole ASCH3. Therefore, the electrical connection between the power-assisted horizontal line VSAHL and the power additional line ASL31 can be achieved in another power connection light-emitting pixel driver.

[0357] Reference Figure 13 、 Figure 15 and Figure 16 , the first initialization voltage line VIL for transmitting the first initialization voltage VINT (see Figure 8 ) can be electrically connected to the second auxiliary vertical line DCASL2 of the second auxiliary line ASL2 through a first initialization connection in the light-emitting pixel driver EPD to the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 in the light-emitting pixel driver. That is, the first initialization voltage line VIL is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, and the second connection auxiliary electrode CASE2 is electrically connected to the second auxiliary vertical line DCASL2 of the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2. Therefore, the electrical connection between the first initialization voltage line VIL and the second auxiliary vertical line DCASL2 can be achieved in a first initialization connection light-emitting pixel driver.

[0358] Optionally, reference Figure 13 、 Figure 15 、 Figure 17 and Figure 18 , the first initialization voltage line VIL for transmitting the first initialization voltage VINT (see Figure 8) The first initialization voltage additional line ASL32 of the third auxiliary line ASL3 can be electrically connected to the first connection auxiliary electrode CASE1, the second connection auxiliary electrode CASE2, and the third connection auxiliary electrode CASE3 in another first initialization connection light-emitting pixel driver among the light-emitting pixel drivers EPD. That is, the first initialization voltage line VIL is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, the second connection auxiliary electrode CASE2 is electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary line CAL2, and the third connection auxiliary electrode CASE3 is electrically connected to the first initialization voltage additional line ASL32 of the third auxiliary line ASL3 through the third auxiliary connection hole ASCH3. Therefore, the electrical connection between the first initialization voltage line VIL and the first initialization voltage additional line ASL32 can be achieved in another first initialization connection light-emitting pixel driver.

[0359] Reference Figure 13 、 Figure 14 、 Figure 15 And Figure 16 , the second initialization voltage line VAIL for transmitting the second initialization voltage VAINT (see Figure 8 ) can be electrically connected to the third auxiliary vertical line DCASL3 of the second auxiliary line ASL2 through the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 in a second initialization connection light-emitting pixel driver among the light-emitting pixel drivers EPD. That is, the second initialization voltage line VAIL is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, and the second connection auxiliary electrode CASE2 is electrically connected to the third auxiliary vertical line DCASL3 of the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2. Therefore, the electrical connection between the second initialization voltage line VAIL and the third auxiliary vertical line DCASL3 can be achieved in a second initialization connection light-emitting pixel driver.

[0360] Optionally, reference Figure 13 、 Figure 14 、 Figure 15 、 Figure 17 And Figure 18 , the second initialization voltage line VAIL for transmitting the second initialization voltage VAINT (see Figure 8)The second initialization voltage additional line ASL33 of the third auxiliary line ASL3 can be electrically connected to the first connection auxiliary electrode CASE1, the second connection auxiliary electrode CASE2, and the third connection auxiliary electrode CASE3 in the light-emitting pixel driver EPD through another second initialization connection in the light-emitting pixel driver. That is, the second initialization voltage line VAIL is electrically connected to the first connection auxiliary electrode CASE1 through the first connection auxiliary line CAL1, the first connection auxiliary electrode CASE1 is electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, the second connection auxiliary electrode CASE2 is electrically connected to the third connection auxiliary electrode CASE3 through the second connection auxiliary line CAL2, and the third connection auxiliary electrode CASE3 is electrically connected to the second initialization voltage additional line ASL33 of the third auxiliary line ASL3 through the third auxiliary connection hole ASCH3. Therefore, the electrical connection between the second initialization voltage line VAIL and the second initialization voltage additional line ASL33 can be achieved in another second initialization connection light-emitting pixel driver.

[0361] As described above, according to one or more embodiments, by selectively setting the first connection auxiliary electrode CASE1, the second connection auxiliary electrode CASE2, the first connection auxiliary line CAL1, and the second connection auxiliary line CAL2 provided in each light-emitting pixel driver EPD, an electrical connection can be achieved between one of the first auxiliary line ASL1, the first initialization voltage line VIL, and the second initialization voltage line VAIL and one of the second auxiliary line ASL2 and the third auxiliary line ASL3, thereby providing a grid-shaped wiring.

[0362] Therefore, a grid-shaped wiring can be provided while reducing the number of connection holes provided in each light-emitting pixel driver EPD. Therefore, the width of each of the light-emitting pixel drivers EPD can be reduced while preventing image quality deterioration, which may be advantageous for achieving high resolution.

[0363] Figure 19 is a plan view showing part D according to one or more embodiments Figure 10 of. Figure 20 and Figure 21 is a plan view showing a part of each of the first light-emitting pixel driver and the second light-emitting pixel driver according to one or more embodiments Figure 19 of.

[0364] In addition to the wirings extending in the first direction DR1 including not only the first auxiliary line ASL1, the first initialization voltage line VIL, and the second initialization voltage line VAIL but also the reset voltage line VRL and the reset control line GRL, Figure 19 , Figure 20 and Figure 21One embodiment of is substantially the same as Figures 13 to 18 's embodiment, and thus, redundant descriptions will be omitted hereinafter.

[0365] As Figure 19 shown, according to one or more embodiments, in addition to the first auxiliary vertical line DCASL1 for transmitting the second power ELVSS (see Figure 8 ), the second auxiliary vertical line DCASL2 for transmitting the first initialization voltage VINT (see Figure 8 ), and the third auxiliary vertical line DCASL3 for transmitting the second initialization voltage VAINT (see Figure 8 ), the auxiliary vertical line DCASL of the second auxiliary line ASL2 may further include a fourth auxiliary vertical line DCASL4 for transmitting a reset voltage VRST (see Figure 8 ) and a fifth auxiliary vertical line DCASL5 for transmitting a reset control signal GR (see Figure 8 ).

[0366] As Figure 20 shown, according to one or more embodiments, the circuit layer 120 may further include a first power connection electrode VDCE, a first anode connection electrode ANCE1, a second anode connection electrode ANCE2 provided in each light-emitting pixel driver EPD, and a reset voltage line VRL that extends in the first direction DR1 and transmits a reset voltage VRST (see Figure 8 ).

[0367] The first power connection electrode VDCE may be electrically connected to the first power line VDL.

[0368] The second anode connection electrode ANCE2 may be electrically connected to the first anode connection electrode ANCE1 through a second anode contact hole ANCH2.

[0369] The reset voltage line VRL, the first power connection electrode VDCE, and the first anode connection electrode ANCE1 may be provided in a first source-drain conductive layer SDCDL1 on an interlayer insulating layer 126 (see Figure 9 ).

[0370] In one example, the first power connection electrode VDCE and the first anode connection electrode ANCE1 may be spaced apart from each other (e.g., separated) and disposed between the reset voltage line VRL and the second initialization voltage line VAIL in the second direction DR2.

[0371] According to one or more embodiments, the reset voltage line VRL may be electrically connected to a second connection auxiliary electrode CASE2 in one of the light-emitting pixel drivers EPD through a third connection auxiliary line CAL3.

[0372] Since the second initialization voltage line VAIL is disposed between the reset voltage line VRL and the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2, the third connection auxiliary line CAL3 intersects the second initialization voltage line VAIL. Accordingly, the third connection auxiliary line CAL3 can be disposed in a conductive layer different from the second initialization voltage line VAIL.

[0373] In one example, the third connection auxiliary line CAL3 can be disposed in the second source-drain conductive layer SDCDL2 on the first planarization layer 127 (see Figure 9 ).

[0374] The third connection auxiliary line CAL3 can be electrically connected to the reset voltage line VRL through a reset voltage connection hole VRCH and can extend to the second connection auxiliary electrode CASE2.

[0375] Refer to Figure 16 and Figure 20 , the reset voltage line VRL for transmitting the reset voltage VRST (see Figure 8 ) can be electrically connected to the fourth auxiliary vertical line DCASL4 of the second auxiliary line ASL2 through the second connection auxiliary electrode CASE2 in the light-emitting pixel driver EPD among the light-emitting pixel drivers. That is, the reset voltage line VRL can be electrically connected to the second connection auxiliary electrode CASE2 through the third connection auxiliary line CAL3, and the second connection auxiliary electrode CASE2 can be electrically connected to the fourth auxiliary vertical line DCASL4 of the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2. Accordingly, the electrical connection between the reset voltage line VRL and the fourth auxiliary vertical line DCASL4 can be implemented in one reset voltage connection light-emitting pixel driver.

[0376] As Figure 21 shown, according to one or more embodiments, the circuit layer 120 may further include a reset control line GRL that extends in the first direction DR1 and transmits a reset control signal GR (see Figure 8 ).

[0377] The reset of the element output node NOP by the reset voltage VRST can be performed consistently in all the photosensing pixel drivers DPD. That is, the reset control signal GR can be transmitted to the photosensing pixel drivers DPD in the display area DA simultaneously (e.g., synchronously).

[0378] According to one or more embodiments, in order to prevent the delay caused by the resistance in the reset control line GRL, the reset control signal GR (see Figure 8) can be provided to the photosensing pixel driver DPD through a grid-shaped wiring including a reset control line GRL and a fifth auxiliary vertical line DCASL5.

[0379] Reference Figure 16 and Figure 21 , the reset control line GRL for transmitting the reset control signal GR (see Figure 8 ) can be electrically connected to the fifth auxiliary vertical line DCASL5 of the second auxiliary line ASL2 through a reset control connection in the light-emitting pixel driver EPD to electrically connect the first connection auxiliary electrode CASE1 and the second connection auxiliary electrode CASE2 in the light-emitting pixel driver. That is, the reset control line GRL can be electrically connected to the first connection auxiliary line CAL1 through a reset control connection hole, the first connection auxiliary line CAL1 can be electrically connected to the first connection auxiliary electrode CASE1, the first connection auxiliary electrode CASE1 can be electrically connected to the second connection auxiliary electrode CASE2 through the first auxiliary connection hole ASCH1, and the second connection auxiliary electrode CASE2 can be electrically connected to the fifth auxiliary vertical line DCASL5 of the second auxiliary line ASL2 through the second auxiliary connection hole ASCH2. Therefore, an electrical connection between the reset control line GRL and the fifth auxiliary vertical line DCASL5 can be achieved in one reset control connection light-emitting pixel driver.

[0380] As described above, according to one or more embodiments, by selectively setting the first connection auxiliary electrode CASE1, the second connection auxiliary electrode CASE2, the first connection auxiliary line CAL1, and the third connection auxiliary line CAL3 provided in each of the light-emitting pixel drivers EPD, the reset voltage VRST (see Figure 8 ) and the reset control signal GR (see Figure 8 ) can be provided through the grid-shaped wiring. Therefore, the reset voltage VRST (see Figure 8 ) and the reset control signal GR (see Figure 8 ) can be provided through the grid-shaped wiring without increasing the number of connection holes arranged in each light-emitting pixel driver EPD, thereby improving the accuracy of photosensing, which is advantageous for achieving high resolution.

[0381] However, the effects, aspects, and features of the present disclosure are not limited to those described herein. By referring to the claims, the above and other effects, aspects, and features of the present disclosure will become more apparent to those of ordinary skill in the art to which the present disclosure pertains.

Claims

1. A display device having a display area in which emission areas are arranged and a non-display area around the display area, and comprising: A substrate; A circuit layer on the substrate; And An element layer on the circuit layer and including light-emitting elements respectively located in the emission areas, Wherein the circuit layer includes: Light-emitting pixel drivers electrically connected to the light-emitting elements and arranged side by side with each other in a first direction and a second direction; Data lines extending in the second direction and transmitting data signals to the light-emitting pixel drivers; A first auxiliary line extending in the first direction; A second auxiliary line extending in the second direction and adjacent to the data lines in the first direction; A third auxiliary line extending in the second direction and located between the second auxiliary lines in the first direction; and First connection auxiliary electrodes respectively located in the light-emitting pixel drivers, having an island shape and spaced apart from the first auxiliary line.

2. The display device according to claim 1, wherein, The circuit layer further includes second connection auxiliary electrodes having an island shape and respectively overlapping the first connection auxiliary electrodes, and respectively electrically connected to the first connection auxiliary electrodes through first auxiliary connection holes, and Wherein the second connection auxiliary electrodes are electrically connected to the second auxiliary lines through second auxiliary connection holes.

3. The display device according to claim 2, wherein, The circuit layer further includes: A first initialization voltage line electrically connected to an initialization voltage extension line transmitting a first initialization voltage and extending in the first direction, having an island shape and spaced apart from the first connection auxiliary electrode; A second initialization voltage line extending in the first direction, spaced apart from the first connection auxiliary electrode, and transmitting a second initialization voltage; and A third connection auxiliary electrode overlapping the third auxiliary line and having an island shape, and spaced apart from the second connection auxiliary electrode, Wherein the third connection auxiliary electrode is electrically connected to the third auxiliary line through a third auxiliary connection hole.

4. The display device according to claim 3, wherein, The light-emitting pixel drivers include a first light-emitting pixel driver and a second light-emitting pixel driver adjacent to each other in the first direction, Wherein one of the first auxiliary lines overlaps the first light-emitting pixel driver and the second light-emitting pixel driver, Wherein the second auxiliary lines include one second auxiliary line overlapping the first light-emitting pixel driver and another second auxiliary line overlapping the second light-emitting pixel driver, Wherein the third auxiliary lines include one third auxiliary line adjacent to the boundary between the first light-emitting pixel driver and the second light-emitting pixel driver, and The first initialization voltage line is located between the first connection auxiliary electrode in the first light-emitting pixel driver and the first connection auxiliary electrode in the second light-emitting pixel driver in the first direction and overlaps the one third auxiliary line.

5. The display device according to claim 4, wherein, Each of the first connection auxiliary electrodes in the first light-emitting pixel driver and the first connection auxiliary electrodes in the second light-emitting pixel driver is electrically connected to one of the first auxiliary lines, the first initialization voltage line, or the second initialization voltage line through a first connection auxiliary line.

6. The display device according to claim 4, wherein, The third connection auxiliary electrode includes one third connection auxiliary electrode electrically connected to one of the third auxiliary lines, and The second connection auxiliary electrode in the first light-emitting pixel driver or the second connection auxiliary electrode in the second light-emitting pixel driver is electrically connected through a second connection auxiliary line to one of the third connection auxiliary electrodes between the second connection auxiliary electrode in the first light-emitting pixel driver and the second connection auxiliary electrode in the second light-emitting pixel driver.

7. The display device according to claim 3, wherein, The bypass area on one side of the display area includes: A bypass intermediate area; A first bypass side area spaced apart from the bypass intermediate area in the first direction and in contact with the non-display area in the first direction; and A second bypass side area located between the bypass intermediate area and the first bypass side area, The data line includes a first data line in the first bypass side area and a second data line in the second bypass side area, The first auxiliary line includes: A first bypass auxiliary line electrically connected to the first data line; and A power auxiliary horizontal line configured to transmit the second power among the first power and the second power for driving the light-emitting element, The second auxiliary line includes a second bypass auxiliary line adjacent to the second data line and electrically connected to the first bypass auxiliary line, and The second auxiliary line further includes an auxiliary vertical line, which is the remaining part of the second auxiliary line except the second bypass auxiliary line, and includes: A first auxiliary vertical line configured to transmit the second power; A second auxiliary vertical line configured to transmit the first initialization voltage; and A third auxiliary vertical line configured to transmit the second initialization voltage.

8. The display device according to claim 7, wherein, The first bypass auxiliary line among the first auxiliary lines is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a first connection auxiliary line, and The second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to the second bypass auxiliary line among the second auxiliary lines through the second auxiliary connection hole.

9. The display device according to claim 7, wherein, The power auxiliary horizontal line among the first auxiliary lines is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a first connection auxiliary line, and Wherein, the second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to the first auxiliary vertical line among the second auxiliary lines through the second auxiliary connection hole.

10. The display device according to claim 7, wherein, The first initialization voltage line is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a first connection auxiliary line, and Among them, the second connection auxiliary electrode in the one light-emitting pixel driver is electrically connected to the second auxiliary vertical line among the second auxiliary lines through the second auxiliary connection hole.

11. The display device according to claim 7, wherein, The second initialization voltage line is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through the first connection auxiliary line, and The second connection auxiliary electrode in the one light-emitting pixel driver is electrically connected to the third auxiliary vertical line among the second auxiliary lines through the second auxiliary connection hole.

12. The display device according to claim 7, wherein, The third auxiliary line includes: A power addition line configured to transmit the second power; A first initialization voltage addition line configured to transmit the first initialization voltage; and A second initialization voltage addition line configured to transmit the second initialization voltage.

13. The display device according to claim 12, wherein, The power auxiliary horizontal line among the first auxiliary lines is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through the first connection auxiliary line, Among them, the second connection auxiliary electrode in the one light-emitting pixel driver is electrically connected to one of the third connection auxiliary electrodes that overlaps with the power addition line among the third auxiliary lines through the second connection auxiliary line, and Among them, the one third connection auxiliary electrode is electrically connected to the power addition line through the third auxiliary connection hole.

14. The display device according to claim 12, wherein, The first initialization voltage line is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through the first connection auxiliary line, Among them, the second connection auxiliary electrode in the one light-emitting pixel driver is electrically connected to one of the third connection auxiliary electrodes that overlaps with the first initialization voltage addition line among the third auxiliary lines through the second connection auxiliary line, and Among them, the one third connection auxiliary electrode is electrically connected to the first initialization voltage addition line through the third auxiliary connection hole.

15. The display device according to claim 12, wherein, The second initialization voltage line is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through the first connection auxiliary line, Among them, the second connection auxiliary electrode in the one light-emitting pixel driver is electrically connected to one of the third connection auxiliary electrodes that overlaps with the second initialization voltage addition line among the third auxiliary lines through the second connection auxiliary line, and Among them, the one third connection auxiliary electrode is electrically connected to the second initialization voltage addition line through the third auxiliary connection hole.

16. The display device according to claim 7, wherein, A non-emitting area, which is a separation area between the emitting areas, and a light sensing area are also arranged in the display area. In a part of the non-emitting area, Among them, the element layer further includes light sensing elements respectively located in the light sensing area, Among them, the circuit layer further includes: A light sensing pixel driver electrically connected to the light sensing element; A reset control line extending in the first direction and configured to transmit a reset control signal for resetting the photosensing pixel driver; and A reset voltage line configured to transmit a reset voltage to the photosensing pixel driver, wherein the auxiliary vertical line of the second auxiliary line further includes at least one of a fourth auxiliary vertical line configured to transmit the reset voltage and a fifth auxiliary vertical line configured to transmit the reset control signal.

17. The display device according to claim 16, wherein, The reset voltage line is electrically connected to the second connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a third connection auxiliary line, and wherein the second connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver is electrically connected to the fourth auxiliary vertical line among the second auxiliary lines through the second auxiliary connection hole.

18. The display device according to claim 16, wherein, The reset control line is electrically connected to the first connection auxiliary electrode in one of the light-emitting pixel drivers in the light-emitting pixel driver through a reset control connection hole and a first connection auxiliary line, and wherein the second connection auxiliary electrode in one of the light-emitting pixel drivers is electrically connected to the fifth auxiliary vertical line among the second auxiliary lines through the second auxiliary connection hole.

19. The display device according to claim 3, wherein, The circuit layer further includes: A first semiconductor layer on the substrate; A first gate insulating layer covering the first semiconductor layer; A first gate conductive layer on the first gate insulating layer; A second gate insulating layer covering the first gate conductive layer; A second gate conductive layer on the second gate insulating layer; An additional interlayer insulating layer covering the second gate conductive layer; A second semiconductor layer on the additional interlayer insulating layer; A third gate insulating layer covering the second semiconductor layer; A third gate conductive layer on the third gate insulating layer; An interlayer insulating layer covering the third gate conductive layer; A first source-drain conductive layer on the interlayer insulating layer; A first planarization layer covering the first source-drain conductive layer; A second source-drain conductive layer on the first planarization layer; A second planarization layer covering the second source-drain conductive layer; A third source-drain conductive layer on the second planarization layer; and A third planarization layer covering the third source-drain conductive layer, wherein the first auxiliary line, the first connection auxiliary electrode, the first initialization voltage line, and the second initialization voltage line are in the first source-drain conductive layer, wherein the second connection auxiliary electrode and the third connection auxiliary electrode are in the second source-drain conductive layer, and wherein the second auxiliary line and the third auxiliary line are in the third source-drain conductive layer.

20. A display device having a display area in which an emission area is arranged and a non-display area around the display area, and including: A substrate; A circuit layer on the substrate; And An element layer on the circuit layer and including light-emitting elements respectively located in the emission area, wherein the circuit layer includes: Light-emitting pixel drivers, electrically connected to the light-emitting elements and arranged side by side with each other in a first direction and a second direction; Data lines, extending in the second direction and configured to transmit data signals to the light-emitting pixel drivers; First auxiliary lines, extending in the first direction; Second auxiliary lines, extending in the second direction and adjacent to the data lines in the first direction; Third auxiliary lines, extending in the second direction and located between the second auxiliary lines in the first direction; First connection auxiliary electrodes, respectively located in the light-emitting pixel drivers, having an island shape and spaced apart from the first auxiliary lines; Second connection auxiliary electrodes, having an island shape and respectively overlapping the first connection auxiliary electrodes, electrically connected to the first connection auxiliary electrodes through first auxiliary connection holes, and electrically connected to the second auxiliary lines through second auxiliary connection holes; Third connection auxiliary electrodes, overlapping the third auxiliary lines, having an island shape and spaced apart from the second connection auxiliary electrodes, and electrically connected to the third auxiliary lines through third auxiliary connection holes; First initialization voltage lines, electrically connected to initialization voltage extension lines configured to transmit a first initialization voltage and extending in the first direction, having an island shape and spaced apart from the first connection auxiliary electrodes; and Second initialization voltage lines, extending in the first direction, spaced apart from the first connection auxiliary electrodes, and configured to transmit a second initialization voltage, wherein the first auxiliary lines include: First bypass auxiliary lines, electrically connected to first data lines among the data lines adjacent to the non-display area in the first direction; and Power auxiliary horizontal lines, configured to transmit the second power among the first power and the second power for driving the light-emitting elements, and wherein the second auxiliary lines include: Second bypass auxiliary lines, electrically connected to the first bypass auxiliary lines and adjacent to second data lines among the data lines, the second data lines being spaced apart from the non-display area in the first direction compared with the first data lines; and Auxiliary vertical lines, the auxiliary vertical lines being the remaining part of the second auxiliary lines except the second bypass auxiliary lines, wherein the second bypass auxiliary lines are electrically connected to the first bypass auxiliary lines through the first connection auxiliary electrodes, the first connection auxiliary lines and the second connection auxiliary electrodes in the light-emitting pixel drivers overlapping the intersection points of the first bypass auxiliary lines and the second bypass auxiliary lines, and wherein the auxiliary vertical lines include: First auxiliary vertical lines, electrically connected to the power auxiliary horizontal lines through the first connection auxiliary electrodes, the first connection auxiliary lines and the second connection auxiliary electrodes in the light-emitting pixel drivers located therein; A second auxiliary vertical line configured to transmit the first initialization voltage is electrically connected to the first initialization voltage line through a first connection auxiliary electrode, a first connection auxiliary line, and a second connection auxiliary electrode in the light-emitting pixel driver via a first initialization connection among the light-emitting pixel drivers; and A third auxiliary vertical line is electrically connected to the second initialization voltage line through a first connection auxiliary electrode, a first connection auxiliary line, and a second connection auxiliary electrode in the light-emitting pixel driver via a second initialization connection among the light-emitting pixel drivers.

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