Display panel and display device including the same

Abstract

Disclosed are a display panel and a display device including the same, the display panel including: a substrate including an area corresponding to positions of a plurality of pixels; a light emitting structure over the substrate for emitting light in a substantially perpendicular direction to the substrate; a color filter layer over the light emitting structure and configured to filter and selectively output light emitted from the light emitting structure; and a lens array over the color filter layer and including a plurality of lenses for outputting light passing through the color filter layer to a desired path, the plurality of lenses having respective different shapes corresponding to different ones of the plurality of pixels.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0010901, filed with the Korean Intellectual Property Office on January 24, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a display panel and a display device including the display panel. Background art

[0004] With the development of the information society, the demand for display devices for displaying images has increased in various forms, and in recent years, various display devices such as liquid crystal display devices, plasma display devices, and organic light - emitting display devices have been used.

[0005] However, traditional display devices may have difficulties in ensuring an emission area for image display and improving brightness.

[0006] The above - described content is only intended to help understand the background art of the technical idea of the present disclosure, and thus, may not correspond to the prior art known to those skilled in the field of the present disclosure. Summary of the invention

[0007] Embodiments of the present disclosure provide a display panel and a display device including the display panel, which can improve light output efficiency by varying the shape of a lens or a color filter in the display panel for each position.

[0008] According to one or more embodiments of the present disclosure, a display panel includes: a substrate including regions corresponding to positions of a plurality of pixels; a light - emitting structure above the substrate for emitting light in a direction substantially perpendicular to the substrate; a color - filter layer above the light - emitting structure and configured to filter and selectively output light emitted from the light - emitting structure; and a lens array above the color - filter layer and including a plurality of lenses for outputting light passing through the color - filter layer to an intended path, the plurality of lenses having respective different shapes corresponding to different pixels among the plurality of pixels.

[0009] The plurality of pixels may include a first sub - pixel, a second sub - pixel, and a third sub - pixel, wherein the color - filter layer includes a plurality of color filters corresponding to the first sub - pixel, the second sub - pixel, and the third sub - pixel respectively, wherein the plurality of lenses respectively correspond to the first sub - pixel, the second sub - pixel, and the third sub - pixel, and wherein when observed in a direction substantially perpendicular to the substrate, centers of the plurality of color filters respectively overlap with centers of the plurality of lenses.

[0010] The color filters among the multiple color filters corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel of the multiple pixels can be configured to filter the light emitted from the light-emitting structure respectively, and configured to output red light, green light, and blue light respectively in a direction substantially perpendicular to the substrate.

[0011] The shape of one lens among the multiple lenses corresponding to one pixel located in one area of the display panel among the multiple pixels can be symmetric, wherein the shape of another lens among the multiple lenses corresponding to another pixel located in another area of the display panel among the multiple pixels is asymmetric.

[0012] The shapes of the lenses among the multiple lenses corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel of the same pixel among the multiple pixels can be substantially the same.

[0013] The light passing through one lens among the multiple lenses corresponding to one pixel located in one area of the display panel among the multiple pixels can be emitted in a direction substantially perpendicular to the substrate, wherein the light passing through another lens among the multiple lenses corresponding to another pixel located in another area of the display panel among the multiple pixels is emitted in a direction inclined from the direction substantially perpendicular to the substrate.

[0014] The multiple pixels can include a first pixel and a second pixel located in another area of the display panel, the first pixel being closer to the non-display area of the display panel than the second pixel, wherein the respective lights passing through the lenses corresponding to the first pixel and the second pixel among the multiple lenses travel while forming a first angle and a second angle respectively with the normal line, the normal line extending in a direction substantially perpendicular to the substrate, and the magnitude of the first angle being greater than the magnitude of the second angle.

[0015] The multiple lenses can include an acrylic-based material.

[0016] According to one or more embodiments of the present disclosure, a display device includes: a substrate including an area corresponding to the position of a pixel; a light-emitting structure above the substrate for emitting light in a direction substantially perpendicular to the substrate; and a color filter layer above the light-emitting structure and including multiple color filters for filtering and selecting the light emitted from the light-emitting structure and for outputting the selected light to an intended path, the shapes of the multiple color filters corresponding to different pixels among the multiple pixels respectively.

[0017] The multiple pixels can include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the color filters among the multiple color filters corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel are configured to filter the light emitted from the light-emitting structure respectively and output red light, green light, and blue light respectively.

[0018] The display panel may further include a lens array, the lens array being above the color filter layer and including a plurality of lenses for outputting light passing through the color filter layer, wherein the shape of one lens among the plurality of lenses corresponding to one pixel located in one area of the display panel among the plurality of pixels is symmetric, and wherein the shape of another lens among the plurality of lenses corresponding to another pixel located in another area of the display panel among the plurality of pixels is asymmetric.

[0019] The plurality of pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the shapes of the lenses among the plurality of lenses corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel of the same pixel among the plurality of pixels are substantially the same.

[0020] The light passing through the color filter among the plurality of color filters corresponding to one pixel in one area of the display panel among the plurality of pixels may be emitted in a direction substantially perpendicular to the substrate, and wherein the light passing through the other color filters among the plurality of color filters corresponding to another pixel located in another area of the display panel among the plurality of pixels is emitted in a direction inclined from the direction substantially perpendicular to the substrate.

[0021] The plurality of pixels may include a first pixel and a second pixel located in another area of the display panel, the first pixel being closer to the non-display area of the display panel than the second pixel, wherein the respective light passing through the respective color filters among the plurality of color filters corresponding to the first pixel and the second pixel travels while forming a first angle and a second angle with the normal, respectively, the normal extending in a direction substantially perpendicular to the substrate, and the magnitude of the first angle being greater than the magnitude of the second angle.

[0022] According to one or more other embodiments of the present disclosure, a display panel includes: a display panel including a plurality of pixels; a gate driver configured to apply a gate signal to the display panel through a first gate line to an m-th (where m is a positive integer) gate line; and a data driver configured to apply a data signal to the display panel through a first data line to an n-th (where n is a positive integer) data line, wherein the display panel further includes: a substrate including an area where a plurality of pixels are located; a light-emitting structure above the substrate for emitting light in a direction substantially perpendicular to the substrate; a color filter layer above the light-emitting structure and configured to filter and selectively output the light emitted from the light-emitting structure; and a lens array above the color filter layer and including a plurality of lenses for outputting the light passing through the color filter layer to an intended path, and wherein the shapes of the lenses among the plurality of lenses corresponding to different pixels among the plurality of pixels are different from each other.

[0023] A plurality of pixels may include a first sub-pixel, a second sub-pixel, and a third sub-pixel, where a color filter layer includes a plurality of color filters respectively corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, where a plurality of lenses respectively correspond to the first sub-pixel, the second sub-pixel, and the third sub-pixel, and where when observed in a direction substantially perpendicular to the substrate, centers of the plurality of color filters respectively overlap with centers of the plurality of lenses.

[0024] A shape of one lens among the plurality of lenses corresponding to one pixel among the plurality of pixels located in one area of the display panel may be symmetric, where a shape of another lens among the plurality of lenses corresponding to another pixel among the plurality of pixels located in another area of the display panel is asymmetric.

[0025] Shapes of lenses among the plurality of lenses respectively corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel included in the same pixel among the plurality of pixels may be substantially the same.

[0026] Light passing through one lens among the plurality of lenses corresponding to one pixel among the plurality of pixels located in one area of the display panel may be emitted in a direction substantially perpendicular to the substrate, where light passing through another lens among the plurality of lenses corresponding to another pixel among the plurality of pixels located in another area of the display panel is emitted in a direction inclined from a direction substantially perpendicular to the substrate.

[0027] A plurality of pixels may include a first pixel and a second pixel located in another area of the display panel, where the first pixel is closer to a non-display area of the display panel than the second pixel, where light passing through the lenses among the plurality of lenses respectively corresponding to the first pixel and the second pixel travels while forming a first angle and a second angle respectively with a normal line extending in a direction substantially perpendicular to the substrate, and a magnitude of the first angle is greater than a magnitude of the second angle.

[0028] According to an embodiment of the present disclosure, a display panel and a display device including the display panel can be provided, which can improve light output efficiency by changing shapes of lenses or color filters at each position in the display panel.

[0029] Aspects according to the embodiment are not limited to the above, and various effects are also included in this specification. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] The above and other aspects of the present disclosure will become more apparent by describing embodiments of the present disclosure in further detail with reference to the accompanying drawings, in which:

[0031] Figure 1 is a block diagram showing a display device according to an embodiment;

[0032] Figure 2 is a block diagram showing one or more embodiments of a sub-pixel among the sub-pixels of Figure 1 ;

[0033] Figure 3 is a plan view of a display panel of Figure 1 according to an embodiment;

[0034] Figure 4 is an exploded perspective view of a magnified partial X of Figure 3 according to one or more embodiments;

[0035] Figure 5 is a detailed view of a color filter layer and a lens array of Figure 4 viewed from a first direction;

[0036] Figure 6 is a detailed view of a color filter layer and a lens array of Figure 4 viewed from a second direction;

[0037] Figure 7 is a diagram showing one or more embodiments of Figure 5 ;

[0038] Figure 8 is an exploded perspective view of a magnified partial X of Figure 3 according to one or more other embodiments;

[0039] Figure 9 is a detailed view of a packaging layer and a color filter layer of Figure 8 viewed from a first direction;

[0040] Figure 10 is a detailed view of a packaging layer and a color filter layer of Figure 8 viewed from a second direction;

[0041] Figure 11 is a diagram showing one or more embodiments of Figure 9 ;

[0042] Figure 12 is a plan view showing one or more embodiments of a pixel among the pixels of Figure 4 and Figure 8 ;

[0043] Figure 13 is a cross-sectional view taken along line I-I' of Figure 12 according to one or more embodiments;

[0044] Figure 14 is a cross-sectional view taken along line I-I' of Figure 12 according to one or more other embodiments;

[0045] Figure 15 is a cross-sectional view showing one or more embodiments of a light-emitting structure of Figure 13 and Figure 14 ;

[0046] Figure 16 is a cross-sectional view showing one or more other embodiments of a light-emitting structure of Figure 13 and Figure 14 ;

[0047] Figure 17 is a plan view showing one or more other embodiments of one pixel in a pixel of Figure 4 and Figure 8 ;

[0048] Figure 18 is a plan view showing yet one or more other embodiments of one pixel in a pixel of Figure 4 and Figure 8 ;

[0049] Figure 19 is a block diagram showing one or more embodiments of a display system;

[0050] Figure 20 is a perspective view showing an application example of a display system of Figure 19 ; and

[0051] Figure 21 is a view showing a head-mounted display device worn by a user of Figure 20 ; DETAILED DESCRIPTION

[0052] Aspects of some embodiments of the present disclosure and methods of implementing the present disclosure can be more easily understood by referring to the detailed description of the embodiments and the drawings. The described embodiments are provided as examples so that the present disclosure will be thorough and complete, and will fully convey the aspects of the present disclosure to those skilled in the art. Accordingly, processes, elements, and techniques that are redundant, unrelated to the description of the embodiments, or unnecessary for a complete understanding of the aspects of the present disclosure by those of ordinary skill in the art may be omitted. Unless otherwise noted, the same reference numerals, characters, or combinations thereof represent the same elements throughout all the drawings and the written description, and thus, their repeated description may be omitted.

[0053] The described embodiments may have various modifications and may be implemented in different forms, and should not be construed as being limited to the embodiments shown herein. The "may", "can", or "may not" used in the description of the embodiments corresponds to one or more embodiments of the present disclosure.

[0054] Considering the overall content of the present disclosure, those of ordinary skill in the art will understand that the present disclosure covers all modifications, equivalents, and substitutions within the concept and technical scope of the present disclosure. Each of the features of the embodiments of the present disclosure can be partially or wholly combined with each other, and various tight combinations and drivings are possible technically. And unless otherwise stated or implied, each embodiment can be implemented independently of each other or can be implemented in association with each other.

[0055] In the drawings, for clarity and / or for the purpose of description, the relative dimensions of elements, layers, and regions may be exaggerated. Additionally, cross-hatching and / or shading are generally used in the drawings to make the boundaries between adjacent elements clear. Thus, unless otherwise stated, the presence or absence of cross-hatching or shading does not convey or indicate any preference or requirement for a particular material, material property, dimension, ratio, commonality between the elements shown, and / or any other characteristic, attribute, property, etc. of the elements.

[0056] Various embodiments are described herein with reference to cross-sectional views that are schematic illustrations of embodiments and / or intermediate structures. As such, deviations from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are to be expected. Additionally, the specific structural or functional descriptions disclosed herein are merely illustrative for the purpose of describing embodiments in accordance with the concept of the present disclosure. Thus, the embodiments disclosed herein should not be construed as being limited to the shown shapes of the elements, layers, or regions, but will include, for example, shape deviations resulting from manufacturing.

[0057] For example, an implantation region shown as rectangular will generally have rounded or curved features at its edges and / or a gradient of implantation concentration, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs.

[0058] For ease of explanation, spatial relative terms such as "below", "beneath", "lower", "underside", "under", "above", "upper", "upside" etc. may be used herein to describe the relationship of one element or feature shown in the figures to another element or feature. It will be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. For example, if the device in the figures is flipped, an element described as "below", "beneath" or "under" another element or feature will then be oriented "above" the other element or feature. Thus, the exemplary terms "below" and "beneath" can encompass both an upper and a lower orientation. The device may have additional orientations (e.g., rotated 90 degrees or at other orientations), and the spatial relative descriptors used herein should be interpreted accordingly. Similarly, when a first part is described as being disposed "on" a second part, this indicates that the first part is disposed at the upper side or the lower side of the second part, and is not limited to the upper side based on the direction of gravity.

[0059] In addition, the phrase "in a plan view" means when the object part is viewed from above, and the phrase "in a schematic cross-sectional view" means when the schematic cross-section obtained by vertically cutting the object part is viewed from the side. The term "overlap" or "overlapping" means that the first object may be above or below or on one side of the second object, and conversely, the second object may be above or below or on one side of the first object. Additionally, the term "overlap" may include stacking, facing or facing towards, extending throughout, covering or partially covering or any other suitable term as would be understood and appreciated by those of ordinary skill in the art. The expression "non-overlapping" may include meanings such as "separate from", "set beside", "offset from" and any other suitable equivalents as would be understood and appreciated by those of ordinary skill in the art. The terms "face" and "face towards" may mean that the first object may be directly or indirectly opposite the second object. In a case where a third object is interposed between the first object and the second object, the first object and the second object may be understood as being indirectly opposite each other, but still facing each other.

[0060] It will be understood that when an element, layer, region or component is referred to as being "formed on", "on", "connected to" or "(operatively or communicatively) coupled to" another element, layer, region or component, it can be directly formed on, directly on, directly connected to or directly coupled to another element, layer, region or component, or indirectly formed on, indirectly on, indirectly connected to or indirectly coupled to another element, layer, region or component such that one or more intervening elements, layers, regions or components can exist. Additionally, this can generally mean direct or indirect coupling or connection and integral or non-integral coupling or connection. For example, when a layer, region or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region or component, it can be directly electrically connected or directly electrically coupled to another layer, region and / or component, or one or more intervening layers, regions or components can exist. One or more intervening components can include switches, resistors, capacitors, etc. In the description of embodiments, unless explicitly described as a direct connection, the expression of connection indicates an electrical connection, and "direct connection / direct coupling" or "directly on" means that one component is directly connected or coupled to another component or directly on another component without an intermediate component.

[0061] Furthermore, in this specification, when a part of a layer, film, region, plate, etc. is formed on another part, the forming direction is not limited to the upward direction and includes forming the part on a side surface or in the downward direction. On the contrary, when a part of a layer, film, region, plate, etc. is formed "below" another part, this includes not only the case where the part is "directly under" the other part, but also the case where there is another part between the part and the other part. Meanwhile, other expressions describing the relationship between components, such as "between" and "directly between" or "adjacent to" and "directly adjacent to", can be similarly interpreted. It will be understood that when an element or layer is referred to as being "between" two elements or layers, it can be the only element or layer between the two elements or layers, or one or more intervening elements or layers can also exist.

[0062] For the purposes of the present disclosure, when following the elements of a list, expressions such as "at least one of...", "any one of...", or "one or more of..." modify the elements of the entire list rather than individual elements of the list. For example, "at least one of X, Y, and Z" and "at least one selected from the group consisting of X, Y, and Z" can be interpreted as: only X; only Y; only Z; any combination of two or more of X, Y, and Z (such as, by way of example, XYZ, XY, YZ, and XZ), or any variation thereof. Similarly, the expression "at least one of A and B" can include A, B, or A and B. As used herein, "or" generally means "and / or", and the term "and / or" includes any and all combinations of one or more of the associated listed items. For example, the expression "A and / or B" can include A, B, or A and B. Similarly, when preceding or following the elements of a list, expressions such as "at least one of...", "a plurality of", "one of...", and other prepositional phrases modify the elements of the entire list rather than individual elements of the list.

[0063] It will be understood that although the terms "first", "second", "third", etc. may be used herein to describe various elements, components, regions, layers, and / or sections, these elements, components, regions, layers, and / or sections should not be limited by these terms. These terms do not correspond to a particular order, position, or priority, but are only used to distinguish one element, member, component, region, area, layer, section, or part from another element, member, component, region, area, layer, section, or part. Thus, without departing from the spirit and scope of the present disclosure, the first element, first component, first region, first layer, or first section described below may be referred to as the second element, second component, second region, second layer, or second section. The description of an element as a "first" element may not require or imply the existence of a second element or other elements. The terms "first", "second", etc. may also be used herein to distinguish different categories or different groups of elements. For the sake of brevity, the terms "first", "second", etc. may represent "first category (or first group)", "second category (or second group)", etc., respectively.

[0064] In an example, the first direction DR1, the second direction DR2, and / or the third direction DR3 are not limited to the three axes of a rectangular coordinate system and can be interpreted in a broader sense. For example, the first direction DR1, the second direction DR2, and the third direction DR3 can be perpendicular to each other, or can represent different directions that are not perpendicular to each other. This also applies to the first direction, the second direction, and / or the third direction.

[0065] The terms used in this disclosure are for the purpose of describing embodiments only and are not intended to limit the present disclosure. As used herein, the singular forms "a" and "an" are intended to also include the plural forms, and the plural forms are intended to also include the singular forms, unless the context clearly indicates otherwise. It will also be understood that when used in this specification, the terms "comprises," "comprising," "has," "having," "includes," and "including" specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or combinations thereof.

[0066] As used herein, the terms "substantially," "about," "approximately," and similar terms are used as approximate terms and not as terms of degree, and are intended to account for the inherent deviations in the values being measured or calculated that would be recognized by a person of ordinary skill in the art. For example, "substantially" may include a range of + / - 5% of the corresponding value. Given the measurements being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system), as used herein, "about" or "approximately" includes the stated value and means within an acceptable deviation of the particular value determined by a person of ordinary skill in the art. For example, "about" may mean within one or more standard deviations, or within ± 30%, ± 20%, ± 10%, ± 5% of the stated value. Additionally, "may" as used in describing embodiments of the present disclosure means "one or more embodiments of the present disclosure."

[0067] In some embodiments, well-known structures and devices may be described in the drawings with respect to one or more functional blocks (e.g., block diagrams), units, and / or modules to avoid unnecessarily obscuring the various embodiments. Those skilled in the art will understand that such blocks, units, and / or modules are physically implemented by logic circuits, discrete components, microprocessors, hardwired circuits, memory elements, wire connections, and other electronic circuits. This may be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. Blocks, units, and / or modules implemented by a microprocessor or other similar hardware may be programmed and controlled using software to perform the various functions discussed herein, and optionally, may be driven by firmware and / or software. In addition, each block, unit, and / or module may be implemented by dedicated hardware or a combination of dedicated hardware that performs some functions and a processor (e.g., one or more programmed microprocessors and associated circuits) that performs functions different from the functions of the dedicated hardware. In addition, in some embodiments, without departing from the scope of the present disclosure, a block, unit, and / or module may be physically divided into two or more interacting discrete blocks, units, and / or modules. In addition, in some embodiments, without departing from the scope of the present disclosure, a block, unit, and / or module may be physically combined into a more complex block, unit, and / or module.

[0068] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure pertains. It will also be understood that terms such as those defined in commonly used dictionaries should be interpreted as having a meaning that is consistent with their meaning in the relevant art and / or the context of this specification, and should not be interpreted in an idealized or overly formal sense unless expressly so defined herein.

[0069] Figure 1 is a block diagram showing a display device according to an embodiment.

[0070] Referring to Figure 1 , the display device 100 may include a display panel DP, a gate driver 120, a data driver 130, a voltage generator 140, and a controller 150.

[0071] The display panel DP may include sub-pixels SP. The sub-pixels SP may be connected to the gate driver 120 through a first gate line GL1 to an m-th gate line GLm. The sub-pixels SP may be connected to the data driver 130 through a first data line DL1 to an n-th data line DLn.

[0072] Each of the sub-pixels SP may include at least one light-emitting element configured to generate light. Accordingly, each of the sub-pixels SP may generate light of a corresponding color such as red, green, blue, cyan, magenta, or yellow. Two or more of the sub-pixels SP among the sub-pixels SP may configure one pixel PXL. For example, as Figure 1 shown, three sub-pixels SP may configure one pixel PXL.

[0073] The gate driver 120 is connected to the sub-pixels SP arranged in the row direction through the first gate line GL1 to the m-th gate line GLm. The gate driver 120 may output a gate signal to the first gate line GL1 to the m-th gate line GLm in response to a gate control signal GCS. In an embodiment, the gate control signal GCS may include a start signal indicating the start of each frame, a horizontal synchronization signal for outputting the gate signal in synchronization with the timing of applying the data signal, and the like.

[0074] In an embodiment, the first emission control lines EL1 to the m-th emission control lines ELm connected to the sub-pixels SP in the row direction may also be provided. In this case, the gate driver 120 may include an emission control driver configured to control the first emission control lines EL1 to the m-th emission control lines ELm, and the emission control driver may operate under the control of the controller 150.

[0075] The gate driver 120 may be located on one side of the display panel DP. However, the embodiment is not limited thereto. For example, the gate driver 120 may be physically and / or logically divided into two or more, and such drivers may be located on the corresponding sides of the display panel DP. As described above, according to an embodiment, the gate driver 120 may be located around the display panel DP in various shapes.

[0076] The data driver 130 is connected to the sub-pixels SP arranged in the column direction through the first data line DL1 to the n-th data line DLn. The data driver 130 receives image data DATA and a data control signal DCS from the controller 150. The data driver 130 operates in response to the data control signal DCS. In an embodiment, the data control signal DCS may include a source start pulse signal, a source shift clock signal, a source output enable signal, and the like.

[0077] The data driver 130 can apply data signals having gray-scale voltages corresponding to the image data DATA to the first data lines DL1 to the nth data lines DLn by using voltages from the voltage generator 140. When the gate signals are applied to each of the first gate lines GL1 to the mth gate lines GLm, the data signals corresponding to the image data DATA can be applied to the data lines DL1 to DLn. Accordingly, the corresponding sub-pixels SP can generate light corresponding to the data signals. Accordingly, an image is displayed on the display panel DP.

[0078] In an embodiment, the gate driver 120 and the data driver 130 may include complementary metal oxide semiconductor (CMOS) circuit elements.

[0079] The voltage generator 140 may operate in response to a voltage control signal VCS from the controller 150. The voltage generator 140 is configured to generate a plurality of voltages and supply the generated voltages to components of the display device 100. For example, the voltage generator 140 may be configured to generate a plurality of voltages by receiving an input voltage from outside the display device 100, adjusting the received voltage, and regulating the adjusted voltage.

[0080] The voltage generator 140 may generate a first power supply voltage VDD and a second power supply voltage VSS, and the generated first power supply voltage VDD and second power supply voltage VSS may be supplied to the sub-pixels SP. The first power supply voltage VDD may have a relatively high voltage level, and the second power supply voltage VSS has a voltage level lower than the voltage level of the first power supply voltage VDD. In other embodiments, the first power supply voltage VDD or the second power supply voltage VSS may be provided by an external device of the display device 100.

[0081] In addition, the voltage generator 140 may generate various voltages. For example, the voltage generator 140 may generate an initialization voltage applied to the sub-pixels SP. For example, during a sensing operation for sensing electrical characteristics of transistors and / or light-emitting elements of the sub-pixels SP, a reference voltage (e.g., a predetermined reference voltage) may be applied to the first data lines DL1 to the nth data lines DLn, and the voltage generator 140 may generate such a reference voltage.

[0082] The controller 150 controls the overall operation of the display device 100. The controller 150 receives input image data IMG and a control signal CTRL for controlling the display of the input image data IMG from the outside. The controller 150 may provide a gate control signal GCS, a data control signal DCS, and a voltage control signal VCS in response to the control signal CTRL.

[0083] The controller 150 may convert the input image data IMG such that the input image data IMG is suitable for the display device 100 or the display panel DP, and may output the image data DATA. In an embodiment, the controller 150 may output the image data DATA by adjusting the input image data IMG such that the input image data IMG is suitable for the sub-pixels SP of the row unit.

[0084] Two or more of the data driver 130, the voltage generator 140, and the controller 150 may be mounted on one integrated circuit. As Figure 1 shown, the data driver 130, the voltage generator 140, and the controller 150 may be included in the driver integrated circuit DIC. In this case, the data driver 130, the voltage generator 140, and the controller 150 may be functionally divided components in one driver integrated circuit DIC. In other embodiments, at least one of the data driver 130, the voltage generator 140, and the controller 150 may be provided as a component different from the driver integrated circuit DIC.

[0085] The display device 100 may include at least one temperature sensor 160. The temperature sensor 160 is configured to sense the temperature around the temperature sensor 160 and generate temperature data TEP indicating the sensed temperature. In an embodiment, the temperature sensor 160 may be positioned adjacent to the display panel DP and / or the driver integrated circuit DIC.

[0086] The controller 150 may control various operations of the display device 100 in response to the temperature data TEP. In an embodiment, the controller 150 may adjust the brightness of the image output from the display panel DP in response to the temperature data TEP. For example, the controller 150 may control the data signal and the first power supply voltage VDD and the second power supply voltage VSS by controlling components such as the data driver 130 and / or the voltage generator 140.

[0087] Figure 2 is a block diagram showing an example of any one of the sub-pixels of Figure 1 . In Figure 2 , as an example, there is shown a sub-pixel SPij arranged on the i-th row (i is a positive integer greater than or equal to 1 and less than or equal to m) and the j-th column (j is a positive integer greater than or equal to 1 and less than or equal to n) among the sub-pixels SP of Figure 1 .

[0088] Referring to Figure 2 , the sub-pixel SPij may include a sub-pixel circuit SPC and a light-emitting element LD.

[0089] The light-emitting element LD is connected between a first power supply voltage node VDDN and a second power supply voltage node VSSN. At this time, the first power supply voltage node VDDN is a node that transmits Figure 1 the first power supply voltage VDD, and the second power supply voltage node VSSN is a node that transmits Figure 1 the second power supply voltage VSS.

[0090] The anode electrode AE of the light-emitting element LD can be connected to the first power supply voltage node VDDN through the sub-pixel circuit SPC, and the cathode electrode CE of the light-emitting element LD can be connected to the second power supply voltage node VSSN. For example, the anode electrode AE of the light-emitting element LD can be connected to the first power supply voltage node VDDN through one or more transistors included in the sub-pixel circuit SPC.

[0091] The sub-pixel circuit SPC can be connected to Figure 1 the i-th gate line GLi among the first gate line GL1 to the m-th gate line GLm of Figure 1 the first emission control line EL1 to the m-th emission control line ELm of Figure 1 and the j-th data line DLj among the first data line DL1 to the n-th data line DLn of. The sub-pixel circuit SPC is configured to control the light-emitting element LD according to signals received through such signal lines.

[0092] The sub-pixel circuit SPC can operate in response to a gate signal received through the i-th gate line GLi. The i-th gate line GLi may include one or more sub-gate lines. In an embodiment, as Figure 2 shown in, the i-th gate line GLi may include a first sub-gate line SGL1 and a second sub-gate line SGL2. The sub-pixel circuit SPC can operate in response to gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. As described above, when the i-th gate line GLi includes two or more sub-gate lines, the sub-pixel circuit SPC can operate in response to gate signals received through the corresponding sub-gate lines.

[0093] The sub-pixel circuit SPC can operate in response to an emission control signal received through the i-th emission control line ELi. In an embodiment, the i-th emission control line ELi may include one or more sub-emission control lines. When the i-th emission control line ELi includes two or more sub-emission control lines, the sub-pixel circuit SPC can operate in response to emission control signals received through the corresponding sub-emission control lines.

[0094] The sub-pixel circuit SPC may receive a data signal through the j-th data line DLj. The sub-pixel circuit SPC may store a voltage corresponding to the data signal in response to at least one of the gate signals received through the first sub-gate line SGL1 and the second sub-gate line SGL2. The sub-pixel circuit SPC may adjust a current flowing from the first power voltage node VDDN through the light-emitting element LD to the second power voltage node VSSN according to the stored voltage in response to the emission control signal received through the i-th emission control line ELi. Accordingly, the light-emitting element LD may generate light having a brightness corresponding to the data signal.

[0095] Figure 3 is a plan view of a Figure 1 display panel according to an embodiment.

[0096] Referring to Figure 3 , Figure 1 one or more embodiments of the display panel DP may include a display area DA and a non-display area NDA. The display panel DP displays an image through the display area DA. The non-display area NDA (e.g., in a plan view) is located around the display area DA.

[0097] The display panel DP may include a substrate SUB, sub-pixels SP, and pads PD. When the display panel DP is used as a display screen of a head-mounted display (HMD), a virtual reality (VR) device, a mixed reality (MR) device, an augmented reality (AR) device, etc., the display panel DP may be positioned very close to a user's eyes. In this case, a relatively high integration degree of the sub-pixels SP is required. To increase the integration degree of the sub-pixels SP, the substrate SUB may be provided as a silicon substrate. The sub-pixels SP and / or the display panel DP may be formed on (e.g., above) the substrate SUB which is a silicon substrate. A display device 100 including the display panel DP formed on the substrate SUB which is a silicon substrate (refer to Figure 1 ) may be referred to as an organic light-emitting diode on silicon (OLEDoS) display device.

[0098] The sub-pixels SP are located in the display area DA on the substrate SUB. The sub-pixels SP may be arranged in a matrix shape along a first direction DR1 and along a second direction DR2 intersecting the first direction DR1. However, the embodiment is not limited thereto. For example, the sub-pixels SP may be arranged in a zigzag along the first direction DR1 and the second direction DR2. For example, the sub-pixels SP may be arranged in a shape (e.g., matrix structure, which is a registered trademark of Samsung Display Co., Ltd. of Korea)

[0099] Two or more of the plurality of sub-pixels SP may configure one pixel PXL.

[0100] Components for controlling the sub-pixels SP may be located in the non-display area NDA on the substrate SUB (e.g., above the substrate SUB). For example, lines connected to the sub-pixels SP (such as Figure 1 the first gate line GL1 to the m-th gate line GLm and the first data line DL1 to the n-th data line DLn) may be located in the non-display area NDA.

[0101] Figure 1 At least one of the gate driver 120, data driver 130, voltage generator 140, controller 150, and temperature sensor 160 of Figure 1 may be integrated in the non-display area NDA of the display panel DP. In an embodiment,

[0102] The pads PD are located in the non-display area NDA on the substrate SUB. The pads PD may be electrically connected to the sub-pixels SP through lines. For example, the pads PD may be connected to the sub-pixels SP through the first data line DL1 to the n-th data line DLn.

[0103] The pads PD may connect the display panel DP to other components of the display device 100 (refer to Figure 1 ). In an embodiment, voltages and signals suitable for the operation of the components included in the display panel DP may be provided from Figure 1 the driver integrated circuit DIC of

[0104] In an embodiment, the circuit board may be electrically connected to the pads PD using a conductive adhesive member such as an anisotropic conductive film. At this time, the circuit board may be a flexible printed circuit board (FPCB) or a flexible film having a flexible material. The driver integrated circuit DIC may be mounted on the circuit board to be electrically connected to the pads PD.

[0105] In an embodiment, the display area DA may have various shapes. The display area DA may have a closed-loop shape including straight edges and / or curved edges. For example, the display area DA may have shapes such as a polygon, a circle, a semi-circle, and an ellipse.

[0106] In an embodiment, the display panel DP may have a flat display surface. In other embodiments, the display panel DP may have a display surface that is at least partially rounded. In an embodiment, the display panel DP may be bendable, foldable, or rollable. In these cases, the display panel DP and / or the substrate SUB may include materials having a flexible property.

[0107] Figure 4 is an exploded perspective view of a partial X of Figure 3 enlarged according to one or more embodiments. In Figure 4 for the sake of clear and concise description, a part of the display panel DP corresponding to five pixels PXL1 to PXL5 among the Figure 1 pixels PXL is schematically shown. The part of the display panel DP corresponding to the remaining pixels PXL may be configured similarly.

[0108] Referring to Figure 3 and Figure 4 each of the first pixel PXL1 to the fifth pixel PXL5 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3. However, the embodiment is not limited thereto. For example, each of the first pixel PXL1 and the second pixel PXL2 may include four sub-pixels SP or two sub-pixels SP.

[0109] In Figure 4 when viewed in a third direction DR3 intersecting the first direction DR1 and the second direction DR2, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 have a quadrilateral shape and have equal sizes to each other. However, the embodiment is not limited thereto. The first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may be modified to have various shapes.

[0110] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, an optical function layer OFL, an outer coating OC, and a cover window CW.

[0111] In an embodiment, the substrate SUB may include a silicon wafer substrate formed using semiconductor processes. The substrate SUB may include a semiconductor material suitable for forming circuit elements. For example, the semiconductor material may include silicon, germanium, and / or silicon germanium. The substrate SUB may be provided by a bulk wafer, an epitaxial layer, a silicon-on-insulator (SOI) layer, a semiconductor-on-insulator (SeOI) layer, etc. In other embodiments, the substrate SUB may include a polyimide (PI) substrate.

[0112] The pixel circuit layer PCL is located on the substrate SUB (as used herein, "located on" may mean "above"). The substrate SUB and / or the pixel circuit layer PCL may include an insulating layer and conductive patterns located between the insulating layers. The conductive patterns of the pixel circuit layer PCL may be used as at least a part of circuit elements, wires, etc. The conductive patterns may include copper, but the embodiments are not limited thereto.

[0113] The circuit elements may include sub-pixel circuits SPC for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 (refer to Figure 2 ). The sub-pixel circuit SPC may include transistors and one or more capacitors. Each transistor may include a semiconductor portion including a source region, a drain region, and a channel region, and a gate electrode overlapping the semiconductor portion. In an embodiment, when the substrate SUB is provided as a silicon substrate, the semiconductor portion may be included in the substrate SUB, and the gate electrode may be included in the pixel circuit layer PCL as a conductive pattern of the pixel circuit layer PCL. In an embodiment, when the substrate SUB is provided as a glass substrate or a PI substrate, the semiconductor portion and the gate electrode may be included in the pixel circuit layer PCL. Each capacitor may include electrodes spaced apart from each other. For example, each capacitor may include electrodes spaced apart from each other on a plane defined by a first direction DR1 and a second direction DR2. For example, each capacitor may include electrodes spaced apart from each other in a third direction DR3, and an insulating layer is interposed between the electrodes spaced apart from each other.

[0114] The wires of the pixel circuit layer PCL may include signal wires connected to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, such as gate wires, emission control wires, data wires, etc. The wires may also include wires connected to Figure 2 the first power voltage node VDDN. In addition, the wires may also include wires connected to Figure 2 the second power voltage node VSSN.

[0115] The light-emitting element layer LDL may include an anode electrode AE, a pixel defining layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0116] The anode electrode AE can be located on the pixel circuit layer PCL. The anode electrode AE can be in contact with the circuit elements of the pixel circuit layer PCL. The anode electrode AE can include an opaque conductive material capable of reflecting light, but the embodiments are not limited thereto.

[0117] The pixel defining layer PDL is located on the anode electrode AE. The pixel defining layer PDL can include or define openings OP that expose portions of each of the anode electrodes AE. The openings OP of the pixel defining layer PDL or the openings OP defined by the pixel defining layer PDL can be understood as emission regions corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively.

[0118] In an embodiment, the pixel defining layer PDL can include an inorganic material. In this case, the pixel defining layer PDL can include a plurality of stacked inorganic layers. For example, the pixel defining layer PDL can include silicon oxide (SiO x ) and silicon nitride (SiN x ). In other embodiments, the pixel defining layer PDL can include an organic material. However, the material of the pixel defining layer PDL is not limited thereto.

[0119] The light emitting structure EMS can be located on the anode electrode AE exposed by the opening OP of the pixel defining layer PDL. The light emitting structure EMS can include a light emitting layer configured to generate light, an electron transport layer configured to transport electrons, a hole transport layer configured to transport holes, etc. The light emitting structure EMS can emit light in a direction perpendicular to the substrate SUB (or the third direction DR3).

[0120] In an embodiment, the light emitting structure EMS can fill the opening OP of the pixel defining layer PDL and can be entirely located on the pixel defining layer PDL. In other words, the light emitting structure EMS can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. In this case, at least a portion of the layers in the light emitting structure EMS can be disconnected or bent at the boundaries between the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. However, the embodiments are not limited thereto. For example, the portions of the light emitting structure EMS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be separated from each other, and each of these portions can be located in the opening OP of the pixel defining layer PDL.

[0121] The cathode electrode CE can be located on the light emitting structure EMS. The cathode electrode CE can extend across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. As described above, the cathode electrode CE can be provided as a common electrode for the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0122] The cathode electrode CE can be a thin metal layer having a thickness sufficient to transmit light emitted from the light-emitting structure EMS. The cathode electrode CE can be formed of a metal material or a transparent conductive material to have a relatively thin thickness. In an embodiment, the cathode electrode CE can include at least one of various transparent conductive materials including indium tin oxide, indium zinc oxide, indium tin zinc oxide, aluminum zinc oxide, gallium zinc oxide, zinc tin oxide, and gallium tin oxide. In other embodiments, the cathode electrode CE can include at least one of silver (Ag), magnesium (Mg), and mixtures thereof. However, the material of the cathode electrode CE is not limited thereto.

[0123] It can be understood that any one of the anode electrodes AE, the portion of the light-emitting structure EMS overlapping with the any one of the anode electrodes AE, and the portion of the cathode electrode CE overlapping with the any one of the anode electrodes AE configure a light-emitting element LD (for example, refer to Figure 2 ). In other words, each of the light-emitting elements in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can include an anode electrode AE, the portion of the light-emitting structure EMS overlapping with the one anode electrode AE, and the portion of the cathode electrode CE overlapping with the one anode electrode AE. In each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, holes injected from the anode electrode AE and electrons injected from the cathode electrode CE can be transmitted into the light-emitting layer of the light-emitting structure EMS to form excitons, and when the excitons transition from the excited state to the ground state, light can be generated. The brightness of the light can be determined according to the amount of current flowing through the light-emitting layer. The wavelength range of the generated light can be determined according to the configuration of the light-emitting layer.

[0124] The encapsulation layer TFE is located on the cathode electrode CE. The encapsulation layer TFE can cover the light-emitting element layer LDL and / or the pixel circuit layer PCL. The encapsulation layer TFE can be configured to reduce or prevent the penetration of oxygen, moisture, etc. into the light-emitting element layer LDL. In an embodiment, the encapsulation layer TFE can include a structure in which one or more inorganic layers and one or more organic layers are alternately stacked. For example, the inorganic layer can include silicon nitride, silicon oxide, silicon oxynitride (SiO x N y ), etc. For example, the organic layer can include organic insulating materials such as acrylic resin, epoxy resin, phenolic resin, polyamide resin, polyimide resin, unsaturated polyester resin, polyphenylene ether resin, polyphenylene sulfide resin, or benzocyclobutene (BCB). However, the materials of the organic layer and the inorganic layer of the encapsulation layer TFE are not limited thereto.

[0125] To improve the encapsulation efficiency of the encapsulation layer TFE, the encapsulation layer TFE can also include aluminum oxide (AlO x) The thin film. The thin film containing aluminum oxide can be positioned on the upper surface of the encapsulation layer TFE facing the optical functional layer OFL and / or on the lower surface of the encapsulation layer TFE facing the light-emitting element layer LDL.

[0126] The thin film including aluminum oxide can be formed by an atomic layer deposition (ALD) method. However, the embodiment is not limited thereto. The encapsulation layer TFE may also include a thin film formed of at least one of various materials suitable for improving the encapsulation efficiency.

[0127] The optical functional layer OFL is located on the encapsulation layer TFE. The optical functional layer OFL may include a color filter layer CFL and a lens array LA.

[0128] The color filter layer CFL is located between the encapsulation layer TFE and the lens array LA. The color filter layer CFL is configured to filter the light emitted from the light-emitting structure EMS and selectively output light in a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL may include color filters CF corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively, and each of the color filters CF may transmit light in a wavelength range corresponding to the respective sub-pixel. For example, the color filter CF corresponding to the first sub-pixel SP1 may transmit red light, the color filter CF corresponding to the second sub-pixel SP2 may transmit green light, and the color filter CF corresponding to the third sub-pixel SP3 may transmit blue light. At least a part of the color filter CF may be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel.

[0129] The lens array LA is located on the color filter layer CFL. The lens array LA may include lenses LS corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. Each of the lenses LS can improve the light output efficiency by receiving the light emitted from the light-emitting structure EMS and outputting the light to an intended path (e.g., an intentional path). The lens array LA may have a relatively high refractive index. For example, the lens array LA may have a refractive index greater than that of the outer coating OC. In an embodiment, the lens LS may include an organic material. In an embodiment, the lens LS may include an acrylic material. However, the material of the lens LS is not limited thereto.

[0130] In an embodiment, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF of the color filter layer CFL and the corresponding lens LS of the lens array LA. In other words, when observed in the third direction DR3, the center of the color filter CF coincides with the sub-pixel SP (reference Figure 1) can be aligned with the center of the lens LS of one of them, or can overlap with the center of the opening OP of the pixel definition layer PDL of the corresponding sub-pixel. For example, when observed in the third direction DR3 (or the direction perpendicular to the substrate SUB), the center of the color filter CF corresponding to the first sub-pixel SP1 of the first pixel PXL1 and the center of the lens LS corresponding to the first sub-pixel SP1 of the first pixel PXL1 can overlap.

[0131] In an embodiment, the shape of the lens LS corresponding to each of the pixels can be different according to the position of each of the pixels in the display area DA. For example, the shape of the lens LS corresponding to the pixels located at the center of the display area DA can be symmetric. For example, the shape of the lens LS corresponding to the pixels located in an area other than the center of the display area DA (for example, an area adjacent to the non-display area NDA) can be asymmetric. However, the present disclosure is not limited thereto. The corresponding shapes of each of the lenses LS will be described in detail later with reference to Figure 5 the corresponding shape of each of the lenses LS.

[0132] The outer coating OC can be located on the lens array LA. The outer coating OC can cover the optical function layer OFL, the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layers from foreign substances such as dust or moisture. For example, the outer coating OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC can include an epoxy resin, but the embodiment is not limited thereto. The outer coating OC can have a refractive index lower than that of the lens array LA.

[0133] The cover window CW can be located on the outer coating OC. The cover window CW is configured to protect the underlying layers. The cover window CW can have a refractive index greater than that of the outer coating OC. The cover window CW can include glass, but the embodiment is not limited thereto. For example, the cover window CW can be a packaging glass configured to protect the components located thereunder. In other embodiments, the cover window CW can be omitted.

[0134] Figure 5 when viewed from the first direction Figure 4 detailed view of the color filter layer and the lens array.

[0135] Reference Figure 4 and Figure 5, the third pixel PXL3 can be a pixel positioned at the center of the display area DA of the display panel DP. The first pixel PXL1, the second pixel PXL2, the fourth pixel PXL4, and the fifth pixel PXL5 can be pixels positioned in areas other than the center of the display area DA of the display panel DP. For example, the first pixel PXL1, the second pixel PXL2, the fourth pixel PXL4, and the fifth pixel PXL5 can be pixels positioned in areas adjacent to the non-display area NDA of the display panel DP.

[0136] The lens array LA can be located on the color filter layer CFL. The lens array LA can include lenses LS. The lenses LS can include first-first lenses LS11, second-first lenses LS21, third-first lenses LS31, fourth-first lenses LS41, and fifth-first lenses LS51.

[0137] The first-first lens LS11 can be located in an area corresponding to the first sub-pixel SP1 of the first pixel PXL1. The second-first lens LS21 can be located in an area corresponding to the first sub-pixel SP1 of the second pixel PXL2. The third-first lens LS31 can be located in an area corresponding to the first sub-pixel SP1 of the third pixel PXL3. The fourth-first lens LS41 can be located in an area corresponding to the first sub-pixel SP1 of the fourth pixel PXL4. The fifth-first lens LS51 can be located in an area corresponding to the first sub-pixel SP1 of the fifth pixel PXL5.

[0138] Some of the color filters CF (refer to Figure 4 ) can be located in areas corresponding to the respective sub-pixels of the first pixel PXL1 to the fifth pixel PXL5. The center of the color filter located in the area corresponding to the sub-pixel of one of the first pixel PXL1 to the fifth pixel PXL5 and the center of the lens LS located in this area can overlap in the third direction DR3. For example, the center of the first-first lens LS11 located in the area corresponding to the first sub-pixel SP1 of the first pixel PXL1 and the center of the color filter located in this area can overlap in the third direction DR3. This will be described in detail later with reference to Figure 13 for details.

[0139] The shapes of the lenses LS located in areas corresponding to different pixels among the pixels PXL (refer to Figure 1 ) can be different.

[0140] The shape of the lens LS corresponding to the pixel positioned at the center of the display area DA can be symmetric. For example, the shape of the third-first lens LS31 can be symmetric (e.g., symmetric in the first direction DR1 and the second direction DR2).

[0141] On the other hand, the shape of the lens LS corresponding to the pixels located in the respective regions outside the center of the display area DA may be asymmetric. For example, the shapes of the first-first lens LS11, the second-first lens LS21, the fourth-first lens LS41, and the fifth-first lens LS51 may be asymmetric (e.g., asymmetric in the first direction DR1 and the second direction DR2).

[0142] In addition, as the lens LS is positioned closer to the non-display area NDA of the display panel DP, the degree of asymmetry of the shape of the lens LS may increase. For example, the first pixel PXL1 may be positioned closer to the non-display area NDA than the second pixel PXL2, and the degree of asymmetry or irregularity of the shape of the first-first lens LS11 may be greater than the degree of asymmetry or irregularity of the shape of the second-first lens LS21.

[0143] According to one or more embodiments of the present disclosure, by forming the shape of the lens LS as described above, the light passing through the lens LS can be focused. By focusing the light passing through the lens LS, the light output efficiency of the display device 100 can be improved, and the visibility can be improved. The optical path of the light passing through the lens LS will be described in detail later with reference to Figure 7 Describe the optical path of the light passing through the lens LS in detail.

[0144] In Figure 5 , although the third-first lens LS31 is shown as having a trapezoidal shape, the embodiment is not limited thereto. For example, the third-first lens LS31 may have various shapes such as a quadrilateral shape or an elliptical shape that are symmetric in the first direction DR1 and the second direction DR2.

[0145] Similarly, the shapes of the first-first lens LS11, the second-first lens LS21, the fourth-first lens LS41, and the fifth-first lens LS51 are not limited to Figure 5 the shapes shown in. The first-first lens LS11, the second-first lens LS21, the fourth-first lens LS41, and the fifth-first lens LS51 may have various shapes that are asymmetric in the first direction DR1 and the second direction DR2.

[0146] Figure 6 is a detailed view of the color filter layer and the lens array viewed from the second direction Figure 4 Hereinafter, the lens included in the fifth pixel PXL5 is described as an example, but the same applies to other pixels.

[0147] Refer to Figure 4 and Figure 6, the fifth-first lens LS51 may be located in a region corresponding to the first sub-pixel SP1 of the fifth pixel PXL5. The fifth-second lens LS52 may be located in a region corresponding to the second sub-pixel SP2 of the fifth pixel PXL5. The fifth-third lens LS53 may be located in a region corresponding to the third sub-pixel SP3 of the fifth pixel PXL5.

[0148] Some of the color filters CF may be located in regions corresponding to the respective first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 of the fifth pixel PXL5. The centers of the color filters located in regions corresponding to each of the first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 of the fifth pixel PXL5 and the centers of the lenses located in those regions may overlap in the third direction DR3. For example, the center of the fifth-first lens LS51 located in the region corresponding to the first sub-pixel SP1 of the fifth pixel PXL5 and the center of the color filter located in that region may overlap in the third direction DR3. This will be described in detail later with reference to Figure 13 is described in detail.

[0149] The shapes of the lenses corresponding to the respective first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 included in one of the pixels PXL may be the same (or substantially the same). For example, the shapes of the lenses LS51, LS52, and LS53 corresponding to the respective first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 included in the fifth pixel PXL5 may be the same (or substantially the same).

[0150] Figure 7 is a diagram showing one or more embodiments corresponding to Figure 5 corresponding.

[0151] Reference Figure 5 and Figure 7 , the light-emitting structure EMS may emit light in a direction substantially perpendicular to the substrate SUB (or in the third direction DR3) toward the color filter layer CFL and the lens array LA.

[0152] The light emitted from the light-emitting structure EMS (refer to Figure 4 ) may pass through the color filter layer CFL and may reach the lens LS. The optical path of the light passing through the lens LS is as follows.

[0153] The light passing through the lens corresponding to the pixel located at the center of the display area DA may be guided in the third direction DR3 (or the direction perpendicular to the substrate SUB). For example, the light passing through the third-first lens LS31 may be guided in the third direction DR3 (or the direction perpendicular to the substrate SUB).

[0154] On the other hand, the light passing through the lenses corresponding to the pixels located in the respective regions outside the center of the display area DA can be guided in a direction inclined from the third direction DR3 (or the direction perpendicular to the substrate SUB). For example, the light passing through the first-first lens LS11 and the second-first lens LS21 can be guided in a direction inclined clockwise from the third direction DR3. For example, the light passing through the fourth-first lens LS41 and the fifth-first lens LS51 can be guided in a direction inclined counterclockwise from the third direction DR3.

[0155] In addition, as the lenses are positioned closer to the non-display area NDA of the display panel DP, the light passing through the lenses can be guided in a direction more inclined from the third direction DR3. For example, the first pixel PXL1 can be closer to the non-display area NDA than the second pixel PXL2. The optical path of the light passing through the first-first lens LS11 can form a first angle AG1 with the normal extending in the third direction DR3. The optical path of the light passing through the second-first lens LS21 can form a second angle AG2 with the normal extending in the third direction DR3. The size of the first angle AG1 can be larger than the size of the second angle AG2.

[0156] According to one or more embodiments of the present disclosure, without adjusting the relative position between the lens LS and the color filter CF, the light passing through the lens LS can have the above-described optical path. When the light passing through the lens LS has such an optical path, the light can be focused on a certain point, as Figure 7 shown. In this way, the light output efficiency of the display device 100 (refer to Figure 1 ) can be improved, and the visibility can be improved.

[0157] Figure 8 is an exploded perspective view of a partial X of Figure 3 according to one or more other embodiments. In Figure 8 , compared with Figure 4 , the display panel DP may not include the lens array LA. In addition, Figure 8 the color filter layer CFL' and the color filter CF' in Figure 4 may be partially different from the color filter layer CFL and the color filter CF in Figure 4 . Hereinafter, the content overlapping with the description of the reference Figure 4 will not be repeated.

[0158] The display panel DP may include a substrate SUB, a pixel circuit layer PCL, a light-emitting element layer LDL, a packaging layer TFE, a color filter layer CFL', an outer coating OC, and a cover window CW. In addition, the color filter layer CFL' may include a color filter CF'.

[0159] The color filter layer CFL' is located between the encapsulation layer TFE and the outer coating OC. The color filter layer CFL' is configured to filter light emitted from the light-emitting structure EMS and can selectively output light in a wavelength range or color corresponding to each sub-pixel. The color filter layer CFL' may include color filters CF' corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively, and each of the color filters CF' may transmit light in a wavelength range corresponding to the respective sub-pixel. For example, the color filter CF' corresponding to the first sub-pixel SP1 may transmit red light, the color filter CF' corresponding to the second sub-pixel SP2 may transmit green light, and the color filter CF' corresponding to the third sub-pixel SP3 may transmit blue light. At least a portion of the color filter CF' may be omitted according to the light emitted from the light-emitting structure EMS of each sub-pixel.

[0160] In addition, each of the color filters CF' may filter and select light emitted from the light-emitting structure EMS and may output the selected light to an intended path, thereby improving the light output efficiency. The color filter layer CFL' may have a relatively high refractive index. For example, the color filter layer CFL' may have a refractive index greater than that of the outer coating OC. In an embodiment, the color filter CF' may include an organic material. In an embodiment, the color filter CF' may include an acrylic material. However, the material of the color filter CF' is not limited thereto.

[0161] In an embodiment, the opening OP of the pixel defining layer PDL may completely overlap with the corresponding color filter CF' of the color filter layer CFL'. In other words, when viewed in the third direction DR3, the center of the color filter CF' may be aligned or overlapped with the center of the opening OP of the corresponding pixel defining layer PDL.

[0162] In an embodiment, the shape of the color filter CF' corresponding to each of the pixels may be different according to the position of each of the pixels in the display area DA. For example, the shape of the color filter corresponding to the pixel located at the center of the display area DA may be symmetric. For example, the shape of the color filter corresponding to the pixel located in an area other than the center of the display area DA (e.g., an area adjacent to the non-display area NDA) may be asymmetric. The corresponding shape of each of the color filters CF' will be described in detail later with reference to Figure 9 the corresponding shape of each of the color filters CF'.

[0163] The outer coating OC can be located on the color filter layer CFL'. The outer coating OC can cover the color filter layer CFL', the encapsulation layer TFE, the light-emitting structure EMS, and / or the pixel circuit layer PCL. The outer coating OC can include various materials suitable for protecting the underlying layers from foreign substances such as dust or moisture. For example, the outer coating OC can include at least one of an inorganic insulating layer and an organic insulating layer. For example, the outer coating OC can include an epoxy resin, but the embodiments are not limited thereto. The outer coating OC can have a refractive index lower than that of the color filter layer CFL'.

[0164] The cover window CW can be located on the outer coating OC. The cover window CW is configured to protect the underlying layers. The cover window CW can have a refractive index greater than that of the outer coating OC. The cover window CW can include glass, but the embodiments are not limited thereto. For example, the cover window CW can be an encapsulation glass configured to protect the components located thereunder. In other embodiments, the cover window CW can be omitted.

[0165] Figure 9 is a detailed view of the encapsulation layer and the color filter layer viewed from the first direction Figure 8 thereof.

[0166] Reference Figure 8 and Figure 9 , the third pixel PXL3 can be a pixel positioned at the center of the display area DA of the display panel DP. The first pixel PXL1, the second pixel PXL2, the fourth pixel PXL4, and the fifth pixel PXL5 can be pixels positioned in respective regions other than the center of the display area DA of the display panel DP. For example, the first pixel PXL1, the second pixel PXL2, the fourth pixel PXL4, and the fifth pixel PXL5 can be pixels positioned in regions adjacent to the non-display area NDA of the display panel DP.

[0167] The color filter layer CFL' can be located on the encapsulation layer TFE. In an embodiment, the color filter layer CFL' can be attached to the encapsulation layer TFE through an adhesive layer APL. For example, the color filter layer CFL' can be manufactured separately and attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform the function of protecting the underlying layers including the encapsulation layer TFE.

[0168] The color filter layer CFL' can include color filters CF'. The color filters CF' can include first-first color filters CF11', second-first color filters CF21', third-first color filters CF31', fourth-first color filters CF41', and fifth-first color filters CF51'.

[0169] The first-first color filter CF11' may be located in a region corresponding to the first sub-pixel SP1 of the first pixel PXL1. The second-first color filter CF21' may be located in a region corresponding to the first sub-pixel SP1 of the second pixel PXL2. The third-first color filter CF31' may be located in a region corresponding to the first sub-pixel SP1 of the third pixel PXL3. The fourth-first color filter CF41' may be located in a region corresponding to the first sub-pixel SP1 of the fourth pixel PXL4. The fifth-first color filter CF51' may be located in a region corresponding to the first sub-pixel SP1 of the fifth pixel PXL5.

[0170] The color filters CF' located in regions corresponding to different pixels among the pixels PXL (refer to Figure 8 ) may have different shapes. The shape of the color filter CF' corresponding to the pixel located at the center of the display area DA may be symmetric. For example, the shape of the third-first color filter CF31' may be symmetric (e.g., symmetric in the first direction DR1 and the second direction DR2).

[0171] On the other hand, the shape of the color filter CF' corresponding to the pixel located in the corresponding region other than the center of the display area DA may be asymmetric. For example, the shapes of the first-first color filter CF11', the second-first color filter CF21', the fourth-first color filter CF41', and the fifth-first color filter CF51' may be asymmetric (e.g., asymmetric in the first direction DR1 and / or the second direction DR2).

[0172] In addition, as the color filter CF' is positioned closer to the non-display area NDA of the display area DA, the degree of asymmetry of the shape of the color filter CF' may increase. For example, the first pixel PXL1 may be positioned closer to the non-display area NDA than the second pixel PXL2, and the degree of asymmetry of the shape of the first-first color filter CF11' may be greater than the degree of asymmetry of the shape of the second-first color filter CF21'.

[0173] According to one or more embodiments of the present disclosure, by forming the shape of the color filter CF' as described above, the light passing through the color filter CF' can be aggregated. By aggregating the light passing through the color filter CF', the light output efficiency of the display device 100 can be improved, and the visibility can be improved. The optical path of the light passing through the color filter CF' will be described later with reference to Figure 11 Describe the optical path of the light passing through the color filter CF'.

[0174] In Figure 9In [the figure], the third-first color filter CF31' is shown as having a trapezoidal shape, but the embodiment is not limited thereto. For example, the third-first color filter CF31' may have various shapes such as a quadrilateral shape or an elliptical shape that are symmetric in the first direction DR1 and the second direction DR2.

[0175] Similarly, the shapes of the first-first color filter CF11', the second-first color filter CF21', the fourth-first color filter CF41', and the fifth-first color filter CF51' are not limited to Figure 9 the shapes shown in [the figure]. The first-first color filter CF11', the second-first color filter CF21', the fourth-first color filter CF41', and the fifth-first color filter CF51' may have various shapes that are asymmetric in the first direction DR1 and the second direction DR2.

[0176] Figure 10 is a detailed view of the encapsulation layer and the color filter layer viewed from the second direction Figure 8 Hereinafter, a lens included in the fifth pixel PXL5 is described as an example, but the same applies to other pixels.

[0177] Referring to Figure 8 and Figure 10 , the fifth-first color filter CF51' may be located in a region corresponding to the first sub-pixel SP1 of the fifth pixel PXL5. The fifth-second color filter CF52' may be located in a region corresponding to the second sub-pixel SP2 of the fifth pixel PXL5. The fifth-third color filter CF53' may be located in a region corresponding to the third sub-pixel SP3 of the fifth pixel PXL5.

[0178] The shapes of the color filters corresponding to the respective first sub-pixel to third sub-pixels included in one of the pixels PXL may be the same (or substantially the same). For example, the shapes of the color filters CF51', CF52', and CF53' corresponding to the respective first sub-pixel SP1, second sub-pixel SP2, and third sub-pixel SP3 included in the fifth pixel PXL5 may be the same (or substantially the same).

[0179] Figure 11 is a diagram showing one or more embodiments corresponding to Figure 9 [the figure].

[0180] Referring to Figure 9 and Figure 11 , the light-emitting structure EMS (refer to Figure 8 ) may emit light toward the color filter layer CFL' in a direction perpendicular to the substrate SUB (or in the third direction DR3).

[0181] Light emitted from the light-emitting structure EMS can reach the color filter CF'. The optical path of the light passing through the color filter CF' is as follows.

[0182] Light passing through the color filter CF' corresponding to a pixel located at the center of the display area DA can be guided in the third direction DR3 (or the direction perpendicular to the substrate SUB). For example, the light passing through the third-first color filter CF31' can be guided in the third direction DR3 (or the direction perpendicular to the substrate SUB).

[0183] On the other hand, light passing through the color filter CF' corresponding to a pixel located in a corresponding area other than the center of the display area DA can be guided in a direction inclined from the third direction DR3 (or the direction perpendicular to the substrate SUB). For example, the light passing through the first-first color filter CF11' and the second-first color filter CF21' can be guided in a direction inclined clockwise from the third direction DR3. For example, the light passing through the fourth-first color filter CF41' and the fifth-first color filter CF51' can be guided in a direction inclined counterclockwise from the third direction DR3.

[0184] In addition, as the color filter CF' is positioned closer to the non-display area NDA of the display panel DP, the light passing through the color filter CF' can be guided in a direction inclined more from the third direction DR3. For example, the first pixel PXL1 can be positioned closer to the non-display area NDA than the second pixel PXL2. The optical path of the light passing through the first-first color filter CF11' can form a third angle AG3 with the normal extending in the third direction DR3. The optical path of the light passing through the second-first color filter CF21' can form a fourth angle AG4 with the normal extending in the third direction DR3. The size of the third angle AG3 can be larger than the size of the fourth angle AG4.

[0185] According to one or more embodiments of the present disclosure, through the shape of the color filter CF', the light passing through the color filter CF' can have the optical path as described above. When the light passing through the color filter CF' has such an optical path, the light can be focused on a certain point, as Figure 11 shown. In this way, the light output efficiency of the display device 100 can be improved, and the visibility can be improved.

[0186] Figure 12 is a plan view showing one or more embodiments of a pixel of Figure 4 and Figure 8 . In Figure 12 , for clear and concise description, the third pixel PXL3 among the pixels of Figure 4 and Figure 8 is schematically shown. The remaining pixels can be configured similarly to the third pixel PXL3.

[0187] The third pixel PXL3 may include a first sub-pixel SP1, a second sub-pixel SP2, and a third sub-pixel SP3 arranged in a first direction DR1.

[0188] The first sub-pixel SP1 may include a first emission area EMA1 and a non-emission area NEA around the first emission area EMA1. The second sub-pixel SP2 may include a second emission area EMA2 and a non-emission area NEA around the second emission area EMA2. The third sub-pixel SP3 may include a third emission area EMA3 and a non-emission area NEA around the third emission area EMA3.

[0189] The first emission area EMA1 may be an area where light is emitted from a portion of the light-emitting structure EMS (refer to Figure 4 and Figure 8 ) corresponding to the first sub-pixel SP1. The second emission area EMA2 may be an area where light is emitted from a portion of the light-emitting structure EMS corresponding to the second sub-pixel SP2. The third emission area EMA3 may be an area where light is emitted from a portion of the light-emitting structure EMS corresponding to the third sub-pixel SP3. As described in reference Figure 4 and Figure 8 , each emission area may be understood as an opening OP of the pixel defining layer PDL corresponding to each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0190] Figure 13 is a cross-sectional view taken along line I-I' of Figure 12 .

[0191] Refer to Figure 13 , a substrate SUB and a pixel circuit layer PCL located on the substrate SUB are provided.

[0192] The substrate SUB may include a silicon wafer substrate formed using a semiconductor process. For example, the substrate SUB may include silicon, germanium, and / or silicon-germanium.

[0193] The pixel circuit layer PCL is located on the substrate SUB. The substrate SUB and the pixel circuit layer PCL may include circuit elements for each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. For example, the substrate SUB and the pixel circuit layer PCL may include a transistor T_SP1 of the first sub-pixel SP1, a transistor T_SP2 of the second sub-pixel SP2, and a transistor T_SP3 of the third sub-pixel SP3. The transistor T_SP1 of the first sub-pixel SP1 may be included in the sub-pixel circuit SPC of the first sub-pixel SP1 (refer to Figure 2) Any one of the transistors in, the transistor T_SP2 of the second sub-pixel SP2 can be any one of the transistors included in the sub-pixel circuit SPC of the second sub-pixel SP2, and the transistor T_SP3 of the third sub-pixel SP3 can be any one of the transistors included in the sub-pixel circuit SPC of the third sub-pixel SP3. In Figure 6 For the sake of clear and concise description, one of the transistors of each sub-pixel is shown, and the remaining circuit elements are omitted.

[0194] The transistor T_SP1 of the first sub-pixel SP1 may include a source region SRA, a drain region DRA, and a gate electrode GE.

[0195] The source region SRA and the drain region DRA may be located (e.g., embedded) in the substrate SUB. The well WL formed by an ion implantation process may be located in the substrate SUB, and the source region SRA and the drain region DRA may be positioned in the well WL to be spaced apart from each other. The region between the source region SRA and the drain region DRA in the well WL may be defined as a channel region.

[0196] The gate electrode GE may overlap with the channel region between the source region SRA and the drain region DRA, and may be located in the pixel circuit layer PCL. The gate electrode GE may be spaced apart from the well WL or the channel region by an insulating material such as a gate insulating layer GI. The gate electrode GE may include a conductive material.

[0197] The plurality of layers included in the pixel circuit layer PCL may include insulating layers and conductive patterns located between the insulating layers, and such conductive patterns may include a first conductive pattern CP1 and a second conductive pattern CP2. The first conductive pattern CP1 may be electrically connected to the drain region DRA through a drain connection portion DRC passing through one or more insulating layers. The second conductive pattern CP2 may be electrically connected to the source region SRA through a source connection portion SRC passing through one or more insulating layers.

[0198] When the gate electrode GE and the first conductive pattern CP1 and the second conductive pattern CP2 are connected to different circuit elements and / or lines, the transistor T_SP1 of the first sub-pixel SP1 may be set as any one of the transistors of the first sub-pixel SP1.

[0199] Each of the transistor T_SP2 of the second sub-pixel SP2 and the transistor T_SP3 of the third sub-pixel SP3 may be configured similarly to the transistor T_SP1 of the first sub-pixel SP1.

[0200] As described above, the substrate SUB and the pixel circuit layer PCL may include the circuit elements of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3.

[0201] The via layer VIAL is located on the pixel circuit layer PCL. The via layer VIAL may cover the pixel circuit layer PCL and may have an overall flat surface. The via layer VIAL is configured to planarize the steps on the pixel circuit layer PCL. The via layer VIAL may include at least one of silicon oxide (SiO x ), silicon nitride (SiN x ), and silicon carbonitride (SiCN), but the embodiments are not limited thereto.

[0202] The light-emitting element layer LDL is located on the via layer VIAL. The light-emitting element layer LDL may include a first reflective electrode RE1, a second reflective electrode RE2, and a third reflective electrode RE3, a planarization layer PLNL, a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3, a pixel definition layer PDL, a light-emitting structure EMS, and a cathode electrode CE.

[0203] On the via layer VIAL, the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 are respectively located in or correspond to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. Each of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may contact a circuit element located in the pixel circuit layer PCL through a via passing through the via layer VIAL.

[0204] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may serve as total reflection mirrors for reflecting light emitted from the light-emitting structure EMS toward the display surface (or cover window CW). The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may include a metal material suitable for reflecting light. The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may include at least one of aluminum (Al), silver (Ag), magnesium (Mg), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr), titanium (Ti), and alloys of two or more materials selected from them, but the embodiments are not limited thereto.

[0205] In an embodiment, the connection electrode may be located below each of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The connection electrode may improve the electrical connection characteristics between the corresponding reflective electrode and the circuit elements of the pixel circuit layer PCL. The connection electrode may have a multilayer structure. The multilayer structure may include titanium (Ti), titanium nitride (TiN), tantalum nitride (TaN), etc., but the embodiment is not limited thereto. In an embodiment, the corresponding reflective electrode may be positioned between multiple layers of the connection electrode.

[0206] The buffer pattern BFP may be located below at least one of the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The buffer pattern BFP may include an inorganic material such as silicon carbonitride, but the embodiment is not limited thereto. By placing the buffer pattern BFP, the height of the corresponding reflective electrode in the third direction DR3 can be adjusted. For example, the buffer pattern BFP may be located between the first reflective electrode RE1 and the via layer VIAL to adjust the height of the first reflective electrode RE1.

[0207] The first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3 may be used as total reflectors, and the cathode electrode CE may be used as a half reflector. The light emitted from the light-emitting layer of the light-emitting structure EMS may be amplified by at least partially reciprocating between the corresponding reflective electrode and the cathode electrode CE, and the amplified light may be output through the cathode electrode CE. As described above, the distance between each reflective electrode and the cathode electrode CE can be understood as the resonance distance of the light emitted from the light-emitting layer of the corresponding light-emitting structure EMS.

[0208] The first sub-pixel SP1 may have a resonance distance shorter than that of the buffer pattern BFP of another sub-pixel. The resonance distance adjusted as described above may allow the light of the corresponding wavelength range (e.g., red) to be effectively and efficiently amplified. Therefore, the first sub-pixel SP1 can effectively and efficiently output the light of the corresponding wavelength range.

[0209] In Figure 13In this case, the buffer pattern BFP is provided to the first sub-pixel SP1 and not provided to the second sub-pixel SP2 and the third sub-pixel SP3, but the embodiment is not limited thereto. The buffer pattern may also be provided to at least one of the second sub-pixel SP2 and the third sub-pixel SP3 to adjust the resonance distance of at least one of the second sub-pixel SP2 and the third sub-pixel SP3. For example, the buffer pattern BFP may also be provided to the second sub-pixel SP2 and may adjust the resonance distance of the second sub-pixel SP2. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may correspond to red, green, and blue, respectively, and the distance between the first reflective electrode RE1 and the cathode electrode CE may be shorter than the distance between the second reflective electrode RE2 and the cathode electrode CE. The distance between the second reflective electrode RE2 and the cathode electrode CE may be shorter than the distance between the third reflective electrode RE3 and the cathode electrode CE.

[0210] To planarize the steps between the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, a planarization layer PLNL may be located on the via layer VIAL and the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The planarization layer PLNL may generally cover the first reflective electrode RE1, the second reflective electrode RE2, the third reflective electrode RE3, and the via layer VIAL and may have a flat surface. In an embodiment, the planarization layer PLNL may be omitted.

[0211] On the planarization layer PLNL, a first anode electrode AE1, a second anode electrode AE2, and a third anode electrode AE3 that overlap the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3, respectively, are positioned. When observed in the third direction DR3, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may have a shape similar to that of Figure 12 the first emission regions EMA1, the second emission regions EMA2, and the third emission regions EMA3. The first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 are respectively connected to the first reflective electrode RE1, the second reflective electrode RE2, and the third reflective electrode RE3. The first anode electrode AE1 may be connected to the first reflective electrode RE1 through a first via VIA1 that passes through the planarization layer PLNL. The second anode electrode AE2 may be connected to the second reflective electrode RE2 through a second via VIA2 that passes through the planarization layer PLNL. The third anode electrode AE3 may be connected to the third reflective electrode RE3 through a third via VIA3 that passes through the planarization layer PLNL.

[0212] In an embodiment, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may include at least one of transparent conductive materials such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO x ), indium gallium zinc oxide (IGZO), or indium tin zinc oxide (ITZO). However, the materials of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 are not limited thereto. For example, the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 may include titanium nitride.

[0213] In an embodiment, an insulating layer may also be provided for adjusting the height of one or more of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The insulating layer may be located between one or more of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 and the corresponding reflective electrode. In this case, the planarization layer PLNL and / or the buffer pattern BFP may be omitted. For example, the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 may correspond to red, green, and blue respectively, the distance between the first anode electrode AE1 and the cathode electrode CE may be shorter than the distance between the second anode electrode AE2 and the cathode electrode CE, and the distance between the second anode electrode AE2 and the cathode electrode CE may be shorter than the distance between the third anode electrode AE3 and the cathode electrode CE. The pixel defining layer PDL is located on a part of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3 and the planarization layer PLNL. The pixel defining layer PDL may include an opening OP that exposes a part of each of the first anode electrode AE1, the second anode electrode AE2, and the third anode electrode AE3. The opening OP of the pixel defining layer PDL may define the emission region of each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. As described above, the pixel defining layer PDL may be located in Figure 12 the non-emission region NEA and may define Figure 12 the first emission region EMA1, the second emission region EMA2, and the third emission region EMA3.

[0214] In an embodiment, the pixel defining layer PDL may include a plurality of inorganic insulating layers. Each of the plurality of inorganic insulating layers may include silicon oxide (SiO x ) and silicon nitride (SiN x) or at least one of the following. For example, the pixel defining layer PDL may include a first inorganic insulating layer to a third inorganic insulating layer stacked in sequence, and each of the first inorganic insulating layer to the third inorganic insulating layer may include silicon nitride, silicon oxide, and silicon nitride. However, the embodiments are not limited thereto. The first inorganic insulating layer to the third inorganic insulating layer may have a stepped cross-section in a region adjacent to the opening OP.

[0215] The separator SPR may be disposed in the boundary region BDA between adjacent sub-pixels. In other words, the separator SPR may be disposed in Figure 3 each of the boundary regions between the sub-pixels SP.

[0216] The separator SPR may cause a discontinuous portion (discontinuity) to be formed in the light-emitting structure EMS in the boundary region BDA. For example, the light-emitting structure EMS may be disconnected or bent in the boundary region BDA due to the separator SPR.

[0217] The separator SPR may be disposed in or on the pixel defining layer PDL. The pixel defining layer PDL may include one or more trenches TRCH1 and TRCH2 as the separator SPR in the boundary region BDA. In an embodiment, as Figure 13 shown, one or more trenches TRCH1 and TRCH2 may penetrate the pixel defining layer PDL and may partially penetrate or may penetrate the planarization layer PLNL. In other embodiments, one or more trenches TRCH1 and TRCH2 may penetrate the pixel defining layer PDL and the planarization layer PLNL and may partially penetrate the via layer VIAL. In other embodiments, one or more trenches TRCH1 and TRCH2 at least partially penetrate the planarization layer PLNL and / or the via layer VIAL, and a portion of the pixel defining layer PDL may be located in one or more trenches TRCH1 and TRCH2.

[0218] In Figure 13 it, two trenches TRCH1 and TRCH2 are disposed in the boundary region BDA. However, the embodiments are not limited thereto. For example, the pixel defining layer PDL may include one trench in the boundary region BDA. Alternatively, the pixel defining layer PDL may include three or more trenches in the boundary region BDA.

[0219] In the boundary region BDA, due to the first trench TRCH1 and the second trench TRCH2, discontinuous portions such as the first void VD1 and the second void VD2 can be formed in the light-emitting structure EMS. A part of the multiple layers stacked in the light-emitting structure EMS can be disconnected or bent through the first void VD1 and the second void VD2. For example, at least one charge generation layer included in the light-emitting structure EMS can be disconnected at the first void VD1 and the second void VD2. As described above, the portions of the light-emitting structure EMS included in the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be at least partially separated due to the first trench TRCH1 and the second trench TRCH2.

[0220] In Figure 13 In the boundary region BDA, the first void VD1 and the second void VD2 are formed in the light-emitting structure EMS, but this is only an example and the embodiments are not limited thereto. For example, in the boundary region BDA, a concave valley can be formed in the light-emitting structure EMS. The discontinuous portions formed in the light-emitting structure EMS can be variously changed according to the shapes of the first trench TRCH1 and the second trench TRCH2.

[0221] In an embodiment, the light-emitting structure EMS can be formed by processes such as vacuum deposition and inkjet printing. In this case, the same material as the light-emitting structure EMS can be positioned on the bottom surfaces of the first trench TRCH1 and the second trench TRCH2 adjacent to the via layer VIAL.

[0222] The separator SPR can be variously modified and arranged such that the light-emitting structure EMS can have discontinuous portions in the boundary region BDA. In an embodiment, an inorganic insulating pattern additionally stacked on the pixel defining layer PDL can be arranged in the boundary region BDA without the first trench TRCH1 and the second trench TRCH2. Among the additionally stacked inorganic insulating patterns, the width of the uppermost inorganic insulating pattern can be greater than the width of the inorganic insulating pattern directly beneath it. For example, in the boundary region BDA, the first inorganic insulating pattern to the third inorganic insulating pattern can be sequentially stacked from the pixel defining layer PDL, and the uppermost third inorganic insulating pattern can have a width greater than the width of the second inorganic insulating pattern. For example, the pixel defining layer PDL can have a "T" - shaped or "I" - shaped cross - section in the boundary region BDA. The multiple layers included in the light-emitting structure EMS can be at least partially disconnected or bent in the boundary region BDA according to the shape of the pixel defining layer PDL.

[0223] The light-emitting structure EMS can be located on the anode electrode AE exposed by the opening OP of the pixel-defining layer PDL. The light-emitting structure EMS can fill the opening OP of the pixel-defining layer PDL and can be positioned entirely across the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. As described above, the light-emitting structure EMS can be at least partially disconnected or bent by the spacer SPR in the boundary region BDA. Thus, when the display panel DP is operated, the current flowing out from each of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 to the adjacent sub-pixels through the layers included in the light-emitting structure EMS can be reduced. Accordingly, the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can operate with relatively high reliability.

[0224] The cathode electrode CE can be located on the light-emitting structure EMS. The cathode electrode CE can be commonly provided to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3. The cathode electrode CE can serve as a semi-reflecting mirror that partially transmits and partially reflects the light emitted from the light-emitting structure EMS.

[0225] The first anode electrode AE1, the portion of the light-emitting structure EMS overlapping with the first anode electrode AE1, and the portion of the cathode electrode CE overlapping with the first anode electrode AE1 can configure the first light-emitting element LD1. The second anode electrode AE2, the portion of the light-emitting structure EMS overlapping with the second anode electrode AE2, and the portion of the cathode electrode CE overlapping with the second anode electrode AE2 can configure the second light-emitting element LD2. The third anode electrode AE3, the portion of the light-emitting structure EMS overlapping with the third anode electrode AE3, and the portion of the cathode electrode CE overlapping with the third anode electrode AE3 can configure the third light-emitting element LD3.

[0226] The encapsulation layer TFE is located on the cathode electrode CE. The encapsulation layer TFE can reduce or prevent the penetration of oxygen, moisture, etc. into the light-emitting element layer LDL.

[0227] The optical function layer OFL is located on the encapsulation layer TFE. In an embodiment, the optical function layer OFL can be attached to the encapsulation layer TFE through the adhesive layer APL. For example, the optical function layer OFL can be separately manufactured and attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL can also perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0228] The optical function layer OFL may include a color filter layer CFL and a lens array LA. The color filter layer CFL may include a third-first color filter CF31, a third-second color filter CF32, and a third-third color filter CF33 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The third-first color filter CF31, the third-second color filter CF32, and the third-third color filter CF33 may transmit light in different wavelength ranges. For example, the third-first color filter CF31, the third-second color filter CF32, and the third-third color filter CF33 may transmit red, green, and blue light, respectively.

[0229] In an embodiment, the third-first color filter CF31, the third-second color filter CF32, and the third-third color filter CF33 may partially overlap in the boundary region BDA. In other embodiments, the third-first color filter CF31, the third-second color filter CF32, and the third-third color filter CF33 may be spaced apart from each other, and a black matrix may be disposed between the third-first color filter CF31, the third-second color filter CF32, and the third-third color filter CF33.

[0230] The lens array LA is located on the color filter layer CFL. The lens array LA may include a third-first lens LS31, a third-second lens LS32, and a third-third lens LS33 corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. When observed in the third direction DR3, the center of the color filter in the region corresponding to one of the sub-pixels SP (refer to Figure 1 ) and the center of the lens in that region may overlap. For example, when observed in the third direction DR3, the center of the third-first color filter CF31 and the center of the third-first lens LS31 may overlap. When observed in the third direction DR3, the center of the third-second color filter CF32 and the center of the third-second lens LS32 may overlap. When observed in the third direction DR3, the center of the third-third color filter CF33 and the center of the third-third lens LS33 may overlap.

[0231] The third-first lens LS31, the third-second lens LS32, and the third-third lens LS33 may improve the light output efficiency by outputting the light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 to the expected paths, respectively.

[0232] In Figure 13Among them, as an example, the third pixel PXL3, which is a pixel positioned at the center of the display area DA, is described. The shape, etc. of each lens array LA and lens LS of pixels (such as the first pixel PXL1, the second pixel PXL2, etc.) positioned in the corresponding areas outside the center of the display area DA are the same as those described in the reference Figure 5 and Figure 6 . In addition, the remaining configurations of pixels positioned in the corresponding areas outside the center of the display area DA can be the same as the configuration of the third pixel PXL3.

[0233] Figure 14 is a cross-sectional view taken along the line I-I' according to one or more other embodiments. Compared with Figure 12 , in Figure 13 , the third pixel PXL3 may not include the lens array LA (refer to Figure 14 Figure 13 ). In addition, ) In Figure 14 , the color filter layer CFL' may be partially different from the color filter layer CFL in Figure 13 . Hereinafter, the content overlapping with the description in the reference Figure 13 is omitted.

[0234] The color filter layer CFL' is located on the encapsulation layer TFE. In an embodiment, the color filter layer CFL' may be attached to the encapsulation layer TFE through the adhesive layer APL. For example, the color filter layer CFL' may be manufactured separately and may be attached to the encapsulation layer TFE through the adhesive layer APL. The adhesive layer APL may also perform the function of protecting the underlying layer including the encapsulation layer TFE.

[0235] The color filter layer CFL' may include a third-first color filter CF31', a third-second color filter CF32', and a third-third color filter CF33' corresponding to the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3, respectively. The third-first color filter CF31', the third-second color filter CF32', and the third-third color filter CF33' may transmit light in different wavelength ranges. For example, the third-first color filter CF31', the third-second color filter CF32', and the third-third color filter CF33' may transmit red, green, and blue light, respectively.

[0236] In an embodiment, the third-first color filter CF31', the third-second color filter CF32', and the third-third color filter CF33' may partially overlap in the boundary region BDA. In other embodiments, the third-first color filter CF31', the third-second color filter CF32', and the third-third color filter CF33' may be spaced apart from each other, and a black matrix may be provided between the third-first color filter CF31', the third-second color filter CF32', and the third-third color filter CF33'.

[0237] The third-first color filter CF31', the third-second color filter CF32', and the third-third color filter CF33' may improve the light output efficiency by respectively outputting the light emitted from the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 to an intended path.

[0238] Figure 15 is a cross-sectional view showing Figure 13 and Figure 14 one or more embodiments of the light-emitting structure.

[0239] Referring to Figure 15 , the light-emitting structure EMS may have a series structure in which the first light-emitting unit EU1 and the second light-emitting unit EU2 are stacked. The light-emitting structure EMS may be substantially equally configured in each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 of Figure 13 and Figure 14 .

[0240] Each of the first light-emitting unit EU1 and the second light-emitting unit EU2 may include at least one light-emitting layer that generates light according to the applied current. The first light-emitting unit EU1 may include a first light-emitting layer EML1, a first electron transport unit ETU1, and a first hole transport unit HTU1. The first light-emitting layer EML1 may be located between the first electron transport unit ETU1 and the first hole transport unit HTU1. The second light-emitting unit EU2 may include a second light-emitting layer EML2, a second electron transport unit ETU2, and a second hole transport unit HTU2. The second light-emitting layer EML2 may be located between the second electron transport unit ETU2 and the second hole transport unit HTU2.

[0241] Each of the first hole transport unit HTU1 and the second hole transport unit HTU2 may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., if appropriate. The first hole transport unit HTU1 and the second hole transport unit HTU2 may have the same or different configurations from each other.

[0242] Each of the first electron transport unit ETU1 and the second electron transport unit ETU2 may include at least one of an electron injection layer and an electron transport layer, and may also include, if appropriate, an electron buffer layer, a hole blocking layer, etc. The first electron transport unit ETU1 and the second electron transport unit ETU2 may have configurations that are equal to or different from each other.

[0243] A connection layer, which may be provided in the form of a charge generation layer CGL, may be located between the first light emitting unit EU1 and the second light emitting unit EU2 to connect the first light emitting unit EU1 and the second light emitting unit EU2 to each other. In an embodiment, the charge generation layer CGL may have a stacked structure of a p-type doped layer and an n-type doped layer. For example, the p-type doped layer may include p-type dopants such as HAT-CN, TCNQ, and NDP-9, and the n-type doped layer may include an alkali metal, an alkaline earth metal, a lanthanide metal, or a combination thereof. However, the embodiment is not limited thereto.

[0244] In an embodiment, the first light emitting layer EML1 and the second light emitting layer EML2 may emit light of different colors. The light emitted from each of the first light emitting layer EML1 and the second light emitting layer EML2 may be mixed and regarded as white light. For example, the first light emitting layer EML1 may emit blue light, and the second light emitting layer EML2 may emit yellow light. In an embodiment, the second light emitting layer EML2 may include a structure in which a first sub-light emitting layer configured to emit red light and a second sub-light emitting layer configured to emit green light are stacked. The red light and the green light may be mixed, and thus yellow light may be provided. In this case, an intermediate layer configured to perform the function of hole transport and / or blocking electron transport may also be located between the first sub-light emitting layer and the second sub-light emitting layer.

[0245] In other embodiments, the first light emitting layer EML1 and the second light emitting layer EML2 may emit light of the same color.

[0246] The light emitting structure EMS may be formed by methods such as vacuum deposition, inkjet printing, etc., but the embodiment is not limited thereto.

[0247] Figure 16 is a cross-sectional view showing Figure 13 and Figure 14 one or more other embodiments of the light emitting structure.

[0248] Referring to Figure 16 , the light emitting structure EMS' may have a series structure in which a first light emitting unit EU1', a second light emitting unit EU2', and a third light emitting unit EU3' are stacked. The light emitting structure EMS' may be in Figure 13 and Figure 14are substantially equally disposed in each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3.

[0249] Each of the first light-emitting unit EU1', the second light-emitting unit EU2', and the third light-emitting unit EU3' may include a light-emitting layer that generates light according to the applied current. The first light-emitting unit EU1' may include a first light-emitting layer EML1', a first electron transport unit ETU1', and a first hole transport unit HTU1'. The first light-emitting layer EML1' may be located between the first electron transport unit ETU1' and the first hole transport unit HTU1'. The second light-emitting unit EU2' may include a second light-emitting layer EML2', a second electron transport unit ETU2', and a second hole transport unit HTU2'. The second light-emitting layer EML2' may be located between the second electron transport unit ETU2' and the second hole transport unit HTU2'. The third light-emitting unit EU3' may include a third light-emitting layer EML3', a third electron transport unit ETU3', and a third hole transport unit HTU3'. The third light-emitting layer EML3' may be located between the third electron transport unit ETU3' and the third hole transport unit HTU3'.

[0250] Each of the first hole transport unit HTU1', the second hole transport unit HTU2', and the third hole transport unit HTU3' may include at least one of a hole injection layer and a hole transport layer, and may further include a hole buffer layer, an electron blocking layer, etc., if appropriate. The first hole transport unit HTU1', the second hole transport unit HTU2', and the third hole transport unit HTU3' may have configurations that are equal to or different from each other.

[0251] Each of the first electron transport unit ETU1', the second electron transport unit ETU2', and the third electron transport unit ETU3' may include at least one of an electron injection layer and an electron transport layer, and may further include an electron buffer layer, a hole blocking layer, etc., if appropriate. The first electron transport unit ETU1', the second electron transport unit ETU2', and the third electron transport unit ETU3' may have configurations that are equal to or different from each other.

[0252] The first charge generation layer CGL1' is located between the first light-emitting unit EU1' and the second light-emitting unit EU2'. The second charge generation layer CGL2' is located between the second light-emitting unit EU2' and the third light-emitting unit EU3'.

[0253] In an embodiment, the first light-emitting layer EML1', the second light-emitting layer EML2', and the third light-emitting layer EML3' can generate light of corresponding different colors. The light emitted from each of the first light-emitting layer EML1', the second light-emitting layer EML2', and the third light-emitting layer EML3' can be mixed and can be regarded as white light. For example, the first light-emitting layer EML1' can generate blue light, the second light-emitting layer EML2' can generate green light, and the third light-emitting layer EML3' can generate red light.

[0254] In other embodiments, two or more of the first light-emitting layer EML1', the second light-emitting layer EML2', and the third light-emitting layer EML3' can generate light of the same color.

[0255] Unlike Figure 15 and Figure 16 the light-emitting structures EMS and EMS' shown in Figure 13 and Figure 14 the light-emitting structure EMS can include one light-emitting unit in each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3. At this time, the light-emitting units included in each of the first light-emitting element LD1, the second light-emitting element LD2, and the third light-emitting element LD3 can be configured to emit light of different colors. For example, the light-emitting unit of the first light-emitting element LD1 can emit red light, the light-emitting unit of the second light-emitting element LD2 can emit green light, and the light-emitting unit of the third light-emitting element LD3 can emit blue light. In this case, unlike Figure 13 and Figure 14 the light-emitting units shown in

[0256] Figure 17 is a plan view showing one or more other embodiments of one pixel of the pixels of Figure 4 and Figure 8 the light-emitting units of the first sub-pixel SP1, the second sub-pixel SP2, and the third sub-pixel SP3 can be separated from each other, and each of them can be located in the opening OP of the pixel defining layer PDL. In this case, at least a part of the color filter can be omitted.

[0257] Referring to Figure 17 , the first pixel PXL1' can include a first sub-pixel SP1', a second sub-pixel SP2', and a third sub-pixel SP3'.

[0258] The first sub-pixel SP1' may include a first emission area EMA1' and a non-emission area NEA' surrounding the first emission area EMA1'. The second sub-pixel SP2' may include a second emission area EMA2' and a non-emission area NEA' surrounding the second emission area EMA2'. The third sub-pixel SP3' may include a third emission area EMA3' and a non-emission area NEA' surrounding the third emission area EMA3'.

[0259] The first sub-pixel SP1' and the second sub-pixel SP2' may be arranged in a second direction DR2 (e.g., arranged relative to each other in the second direction DR2). The third sub-pixel SP3' may be arranged in a first direction DR1 relative to each of the first sub-pixel SP1' and the second sub-pixel SP2' (e.g., commonly relative to the first sub-pixel SP1' and the second sub-pixel SP2').

[0260] The second sub-pixel SP2' may have an area larger than the area of the first sub-pixel SP1', and the third sub-pixel SP3' may have an area larger than the area of the second sub-pixel SP2'. Accordingly, the second emission area EMA2' may have an area larger than the area of the first emission area EMA1', and the third emission area EMA3' may have an area larger than the area of the second emission area EMA2'. However, the embodiments are not limited thereto. For example, the first sub-pixel SP1' and the second sub-pixel SP2' may have substantially the same area, and the third sub-pixel SP3' may have an area larger than the area of each of the first sub-pixel SP1' and the second sub-pixel SP2'. As described above, the area of the first sub-pixel SP1', the area of the second sub-pixel SP2', and the area of the third sub-pixel SP3' may vary according to embodiments.

[0261] Figure 18 is a diagram showing Figure 4 and Figure 8 a plan view of yet another one or more other embodiments of a pixel in.

[0262] Referring Figure 18 to, the first pixel PXL1” may include a first sub-pixel SP1”, a second sub-pixel SP2”, and a third sub-pixel SP3”. The first sub-pixel SP1” may include a first emission area EMA1” and a non-emission area NEA” surrounding the first emission area EMA1”. The second sub-pixel SP2” may include a second emission area EMA2” and a non-emission area NEA” surrounding the second emission area EMA2”. The third sub-pixel SP3” may include a third emission area EMA3” and a non-emission area NEA” surrounding the third emission area EMA3”.

[0263] When viewed in a third direction DR3, the first sub-pixel SP1”, the second sub-pixel SP2”, and the third sub-pixel SP3” may have a polygonal shape. For example, the shape of the first sub-pixel SP1”, the shape of the second sub-pixel SP2”, and the shape of the third sub-pixel SP3” may be a hexagonal shape as shown in Figure 2 as follows.

[0264] When viewed in a third direction DR3, the first emission area EMA1”, the second emission area EMA1”, and the third emission area EMA3” may have a circular shape. However, the embodiments are not limited thereto. For example, each of the first emission area EMA1”, the second emission area EMA1”, and the third emission area EMA3” may have a polygonal shape.

[0265] The first sub-pixel SP1”, the second sub-pixel SP2”, and the third sub-pixel SP3” may be arranged in a first direction DR1 (e.g., arranged relative to each other in a first direction DR1). The second sub-pixel SP2” may be located in a direction (or diagonal direction) inclined at an acute angle with respect to the first sub-pixel SP1” based on a second direction DR2.

[0266] Figure 12 , Figure 17 and Figure 18 The arrangements of the sub-pixels shown in are examples, and the embodiments are not limited thereto. Each pixel may include two or more sub-pixels, the sub-pixels may be arranged in various ways, the corresponding sub-pixels may have various shapes, and their corresponding emission areas may also have various shapes.

[0267] Figure 19 is a block diagram showing one or more embodiments of a display system.

[0268] Referring to Figure 19 , the display system 1000 may include a processor 1100 and one or more display devices 1210 and 1220.

[0269] The processor 1100 may perform various tasks and calculations. In an embodiment, the processor 1100 may include an application processor, a graphics processor, a microprocessor, a central processing unit (CPU), etc. The processor 1100 may be connected to other components of the display system 1000 through a bus system and may control other components.

[0270] In Figure 19 , the display system 1000 includes a first display device 1210 and a second display device 1220. The processor 1100 may be connected to the first display device 1210 through a first channel CH1 and may be connected to the second display device 1220 through a second channel CH2.

[0271] The processor 1100 may send first image data IMG1 and a first control signal CTRL1 to a first display device 1210 via a first channel CH1. The first display device 1210 may display an image based on the first image data IMG1 and the first control signal CTRL1. The first display device 1210 may be configured similarly to the display device 100 described with reference Figure 1 . In this case, the first image data IMG1 and the first control signal CTRL1 may be set to Figure 1 the input image data IMG and the control signal CTRL, respectively.

[0272] The processor 1100 may send second image data IMG2 and a second control signal CTRL2 to a second display device 1220 via a second channel CH2. The second display device 1220 may display an image based on the second image data IMG2 and the second control signal CTRL2. The second display device 1220 may be configured similarly to the display device 100 described with reference Figure 1 . In this case, the second image data IMG2 and the second control signal CTRL2 may be set to Figure 1 the input image data IMG and the control signal CTRL, respectively.

[0273] The display system 1000 may include a computing system that provides an image display function, such as a portable computer, a mobile phone, a smart phone, a tablet personal computer (PC), a smart watch, a watch phone, a portable multimedia player (PMP), a navigation device, and / or an ultra-mobile personal computer (UMPC). In addition, the display system 1000 may include at least one of a head-mounted display (HMD) device, a virtual reality (VR) device, a mixed reality (MR) device, and an augmented reality (AR) device.

[0274] Figure 20 is a perspective view showing an application example of the Figure 19 display system.

[0275] With reference to Figure 20 , Figure 19 the display system 1000 may be applied to the head-mounted display device 2000. The head-mounted display device 2000 may be a wearable electronic device that can be worn on a user's head.

[0276] The head-mounted display device 2000 may include a head-mounted strap 2100 and a display device housing 2200. The head-mounted strap 2100 may be connected to the display device housing 2200. The head-mounted strap 2100 may include a horizontal strap and / or a vertical strap for fixing the head-mounted display device 2000 to the user's head. The horizontal strap may be configured to surround the side portion of the user's head, and the vertical strap may be configured to surround the upper portion of the user's head. However, the embodiments are not limited thereto. For example, the head-mounted strap 2100 may be implemented in the form of a spectacle frame, a helmet form, etc.

[0277] The display device housing 2200 may accommodate Figure 19 the first display device 1210 and the second display device 1220. The display device housing 2200 may also accommodate Figure 19 the processor 1100.

[0278] Figure 21 is a diagram showing a head-mounted display device Figure 20 worn by a user.

[0279] Referring to Figure 21 , in the head-mounted display device 2000, the first display panel DP1 of the first display device 1210 and the second display panel DP2 of the second display device 1220 are positioned. The head-mounted display device 2000 may also include one or more lenses LLNS and RLNS.

[0280] Inside the display device housing 2200, the right-eye lens RLNS may be located between the first display panel DP1 and the user's right eye. Inside the display device housing 2200, the left-eye lens LLNS may be located between the second display panel DP2 and the user's left eye.

[0281] The image output from the first display panel DP1 may be displayed to the user's right eye through the right-eye lens RLNS. The right-eye lens RLNS may refract the light from the first display panel DP1 to guide it towards the user's right eye. The right-eye lens RLNS may perform an optical function for adjusting the viewing distance between the first display panel DP1 and the user's right eye.

[0282] The image output from the second display panel DP2 may be displayed to the user's left eye through the left-eye lens LLNS. The left-eye lens LLNS may refract the light from the second display panel DP2 to direct it towards the user's left eye. The left-eye lens LLNS may perform an optical function for adjusting the viewing distance between the second display panel DP2 and the user's left eye.

[0283] In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include an optical lens having a pie-shaped cross section. In an embodiment, each of the right-eye lens RLNS and the left-eye lens LLNS may include a multi-channel lens including sub-regions having different optical characteristics. In such a case, each display panel may output an image corresponding to a sub-region of the multi-channel lens, respectively, and the output image may pass through the corresponding sub-region and may be observed by a user.

[0284] Although specific embodiments and application examples are described herein, other embodiments and modifications can be obtained from the above description. Accordingly, the spirit of the present disclosure is not limited to such embodiments and extends to the scope of the claims set forth below and their functional equivalents included in the present disclosure.

Claims

1. A display panel, comprising: a substrate including regions corresponding to positions of a plurality of pixels; a light-emitting structure above the substrate for emitting light in a direction perpendicular to the substrate; a color filter layer above the light-emitting structure and configured to filter and selectively output the light emitted from the light-emitting structure; and a lens array above the color filter layer and including a plurality of lenses for outputting the light passing through the color filter layer to an intended path, the plurality of lenses having respective different shapes corresponding to different pixels among the plurality of pixels.

2. The display panel according to claim 1, wherein, The plurality of pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the color filter layer includes a plurality of color filters corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively, wherein the plurality of lenses respectively correspond to the first sub-pixel, the second sub-pixel, and the third sub-pixel, and wherein when observed in the direction perpendicular to the substrate, centers of the plurality of color filters respectively overlap with centers of the plurality of lenses.

3. The display panel according to claim 2, wherein, The color filters among the plurality of color filters corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel respectively are configured to respectively filter the light emitted from the light-emitting structure and are configured to respectively output red light, green light, and blue light in the direction perpendicular to the substrate.

4. The display panel according to claim 2, wherein, A shape of one lens among the plurality of lenses corresponding to one pixel located in one region of the display panel among the plurality of pixels is symmetric, and wherein a shape of another lens among the plurality of lenses corresponding to another pixel located in another region of the display panel among the plurality of pixels is asymmetric.

5. The display panel according to claim 2, wherein, Shapes of the lenses among the plurality of lenses corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel in the same pixel among the plurality of pixels are the same.

6. The display panel according to claim 1, wherein, The light passing through one lens among the plurality of lenses corresponding to one pixel located in one region of the display panel among the plurality of pixels is emitted in the direction perpendicular to the substrate, and wherein the light passing through another lens among the plurality of lenses corresponding to another pixel located in another region of the display panel among the plurality of pixels is emitted in a direction inclined from the direction perpendicular to the substrate.

7. The display panel according to claim 6, wherein, The plurality of pixels include a first pixel and a second pixel located in the another region of the display panel, the first pixel being closer to a non-display region of the display panel than the second pixel, and wherein the respective lights passing through the lenses corresponding to the first pixel and the second pixel among the plurality of lenses travel while forming a first angle and a second angle respectively with a normal line extending in the direction perpendicular to the substrate, and a magnitude of the first angle is greater than a magnitude of the second angle.

8. The display panel according to claim 1, wherein, The plurality of lenses include an acrylic-based material.

9. A display panel, comprising: a substrate including regions corresponding to positions of a plurality of pixels; A light-emitting structure, above the substrate, for emitting light in a direction perpendicular to the substrate; and A color filter layer, above the light-emitting structure, and including a plurality of color filters for filtering and selecting the light emitted from the light-emitting structure and for outputting the selected light to an intended path, the shapes of the plurality of color filters corresponding to different pixels among the plurality of pixels respectively.

10. The display panel according to claim 9, wherein, The plurality of pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, and wherein, the color filters among the plurality of color filters corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel are configured to filter the light emitted from the light-emitting structure respectively, and output red light, green light, and blue light respectively.

11. The display panel according to claim 9, further comprising a lens array, the lens array being above the color filter layer and including a plurality of lenses for outputting the light passing through the color filter layer, Among them, the shape of one lens among the plurality of lenses corresponding to one pixel located in one area of the display panel among the plurality of pixels is symmetric, and wherein, the shape of another lens among the plurality of lenses corresponding to another pixel located in another area of the display panel among the plurality of pixels is asymmetric.

12. The display panel according to claim 9, wherein, The plurality of pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, and wherein, the shapes of the lenses among the plurality of lenses corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel of the same pixel among the plurality of pixels are the same.

13. The display panel according to claim 9, wherein, The light passing through the color filter among the plurality of color filters corresponding to one pixel located in one area of the display panel is emitted in the direction perpendicular to the substrate, and wherein, the light passing through other color filters among the plurality of color filters corresponding to another pixel located in another area of the display panel is emitted in a direction inclined from the direction perpendicular to the substrate.

14. The display panel according to claim 13, wherein, The plurality of pixels include a first pixel and a second pixel located in the other area of the display panel, the first pixel being closer to the non-display area of the display panel than the second pixel, and wherein, the respective lights passing through the respective color filters corresponding to the first pixel and the second pixel among the plurality of color filters travel while forming a first angle and a second angle with the normal respectively, the normal extending in the direction perpendicular to the substrate, and the magnitude of the first angle is greater than the magnitude of the second angle.

15. A display device, comprising: A display panel, including a plurality of pixels; A gate driver, configured to apply a gate signal to the display panel through a first gate line to an m-th gate line, where m is a positive integer; and A data driver, configured to apply a data signal to the display panel through a first data line to an n-th data line, where n is a positive integer, wherein, the display panel further includes: A substrate, including an area where the plurality of pixels are located; A light-emitting structure, above the substrate, for emitting light in a direction perpendicular to the substrate; A color filter layer, above the light-emitting structure, and configured to filter and selectively output the light emitted from the light-emitting structure; and A lens array, above the color filter layer, and including a plurality of lenses for outputting the light passing through the color filter layer to an intended path, and wherein the shapes of the lenses among the plurality of lenses corresponding to different pixels of the plurality of pixels are different from each other.

16. The display device according to claim 15, wherein, The plurality of pixels include a first sub-pixel, a second sub-pixel, and a third sub-pixel, wherein the color filter layer includes a plurality of color filters corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, wherein the plurality of lenses correspond to the first sub-pixel, the second sub-pixel, and the third sub-pixel, respectively, and wherein when observed in the direction perpendicular to the substrate, the centers of the plurality of color filters overlap with the centers of the plurality of lenses, respectively.

17. The display device according to claim 16, wherein, The shape of one lens among the plurality of lenses corresponding to one pixel located in one area of the display panel among the plurality of pixels is symmetric, and wherein the shape of another lens among the plurality of lenses corresponding to another pixel located in another area of the display panel among the plurality of pixels is asymmetric.

18. The display device according to claim 16, wherein, The shapes of the lenses among the plurality of lenses corresponding to the first sub-pixel, the second sub-pixel, and the third sub-pixel included in the same pixel among the plurality of pixels are the same.

19. The display device according to claim 15, wherein, The light passing through one lens among the plurality of lenses corresponding to one pixel located in one area of the display panel among the plurality of pixels is emitted in the direction perpendicular to the substrate, and wherein the light passing through another lens among the plurality of lenses corresponding to another pixel located in another area of the display panel among the plurality of pixels is emitted in a direction inclined from the direction perpendicular to the substrate.

20. The display device according to claim 19, wherein, The plurality of pixels include a first pixel and a second pixel located in the another area of the display panel, the first pixel being closer to the non-display area of the display panel than the second pixel, and wherein the light passing through the lenses corresponding to the first pixel and the second pixel among the plurality of lenses travels while forming a first angle and a second angle with the normal, respectively, the normal extending in the direction perpendicular to the substrate, and the magnitude of the first angle is greater than the magnitude of the second angle.

Images