A data transmission system and method based on a dual-channel DMA controller and a hybrid interrupt mode
By using a dual-channel DMA controller and a hybrid interrupt mode, the problems of resource contention and inflexible interrupt mode caused by a single-channel DMA controller are solved, achieving efficient and reliable bidirectional data transmission.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- TAIZHOU YUNYONG ELECTRONICS
- Filing Date
- 2025-04-24
- Publication Date
- 2026-05-22
AI Technical Summary
In existing technologies, single-channel DMA controllers cause problems such as data transmission resource contention, channel congestion, low bandwidth utilization, large data transmission latency, and inability to dynamically adjust interrupt modes.
It adopts a dual-channel DMA controller group and a hybrid interrupt mode, connects the CPU and FPGA through an independent PCIe physical interface, and combines a data buffer module and a CRC check module to achieve physical isolation of bidirectional data streams and flexible interrupt control.
It improves data transmission efficiency, reduces latency and error risks, enhances bandwidth utilization, and achieves high reliability and flexible interruption adaptation.
Smart Images
Figure CN120386753B_ABST
Abstract
Description
Technical Field
[0001] This invention relates to the field of high-speed data transmission technology, and in particular to a data transmission system and method based on a dual-channel DMA controller and a hybrid interrupt mode. Background Technology
[0002] In computer architecture, high-speed data transmission technology based on the PCIe bus is widely used in servers, storage devices, and embedded systems. Existing systems often employ a single DMA controller to manage bidirectional data flows, resulting in upstream (CPU to peripheral) and downstream (peripheral to CPU) transmissions competing for the same channel resources. Especially in high-load bidirectional scenarios, this design is prone to channel congestion; actual measurements show that its effective bandwidth utilization is less than 60%. Furthermore, single-channel architectures struggle to support physical isolation between the sender and receiver, increasing data transmission latency and the risk of error propagation. Additionally, traditional interrupt modes typically employ fixed triggering strategies, failing to dynamically adjust according to data transmission scenarios. For example, during batch data transmission, frequent interrupts per message can lead to an "interrupt storm," causing a surge in CPU load; while in scenarios with high real-time requirements, merging interrupts may introduce uncontrollable latency, making it difficult to meet the demands of high real-time applications. Summary of the Invention
[0003] The purpose of this invention is to overcome the above-mentioned technical problems and provide a data transmission system based on a dual-channel DMA controller and a hybrid interrupt mode through hardware architecture innovation and interrupt mechanism optimization, thereby achieving efficient and reliable bidirectional data transmission.
[0004] To achieve the above objectives, the present invention adopts the following technical solution:
[0005] Dual-CPU architecture: The transmitting CPU and the receiving CPU are connected to the FPGA chip through independent PCIe physical interfaces for data transmission and reception.
[0006] The FPGA chip integrates the following functional modules through hardware logic:
[0007] Dual DMA controller group: This includes a transmitter DMA controller group and a receiver DMA controller group, controlled by the transmitter CPU and receiver CPU respectively, used to manage bidirectional data streams; wherein:
[0008] The transmitting end DMA controller group is responsible for the bidirectional data flow between the transmitting end CPU and the FPGA chip; the receiving end DMA controller group is responsible for the bidirectional data flow between the receiving end CPU and the FPGA chip.
[0009] PCIe interface module: Communicatively connected to the PCIe physical interface, used to realize data interaction and interrupt signal transmission between the FPGA chip and the CPU;
[0010] Data buffer module: contains a circular address queue, which is used to temporarily store the address and length of transmitted data and to reuse address resources cyclically during data transmission;
[0011] Hybrid interrupt control module: Dynamically selects the interrupt mode by configuring the interrupt control register and links with the interrupt mechanism of the PCIe interface module;
[0012] CRC check module: Attaches a check value during data transmission. The receiving end verifies the integrity of the data. If the check fails, it triggers an error interrupt and sends feedback to the corresponding CPU.
[0013] Furthermore, the interruption mode includes:
[0014] Step-by-step operation interrupt: An interrupt is triggered by writing length and address in steps;
[0015] Merge operation interrupt: The merge length and address are triggered by a single operation.
[0016] Clear interrupts by counting: Clear the interrupt queue in batches by reading the message count.
[0017] Furthermore, the address resources of the circular address queue are pre-configured and initialized, and are cyclically reused in the order of writing during transmission to form a circular buffer with a depth of 1024 items. Each address interval is 2048 bytes, which constitutes the basic unit of the circular buffer.
[0018] Furthermore, the hybrid interrupt control module adopts the MSI-X mechanism, which allocates independent interrupt information addresses and data registers to the read and write ends of each DMA controller, and provides real-time feedback on the interrupt suspension status through the status register.
[0019] Furthermore, the DMA controller group is implemented through hardware logic, and its control registers are mapped to the address space of the FPGA chip, supporting dynamic configuration of data transmission parameters, including message length, address offset, and interrupt trigger threshold.
[0020] Furthermore, the CRC check value covers the message header, length field, and message body. When the receiving end fails the check, it discards the data and triggers a bus error interrupt. The bus error interrupt is fed back to the corresponding CPU through the hybrid interrupt control module.
[0021] This invention also provides a data transmission method based on a dual-channel DMA controller and a hybrid interrupt mode, comprising the following steps:
[0022] S1: Initialization Configuration
[0023] Configure the control registers of the sending end DMA controller group and the receiving end DMA controller group to dynamically set the message length, address offset and interrupt trigger threshold;
[0024] A pre-configured circular address queue is used to initialize address resources at certain byte intervals, forming a circular buffer.
[0025] Configure the interrupt mode of the hybrid interrupt control module, and allocate independent MSI-X interrupt information address and data register for each DMA controller's read / write end based on the MSI-X mechanism;
[0026] S2: Data transmission from sender to receiver
[0027] (1) The transmitting CPU writes data into the transmitting address space of the FPGA chip through the PCIe interface module;
[0028] (2) The downlink controller of the transmitting end DMA controller group reads the data according to the address and length in the circular address queue, adds the CRC check value and stores it in the queue;
[0029] (3) The uplink controller of the receiving end DMA controller group reads data from the queue and verifies it. After successful verification, it is sent to the receiving end CPU through the PCIe interface module.
[0030] S3: Data transmission from receiver to transmitter
[0031] (1) The receiving CPU writes data into the receiving address space of the FPGA chip through the PCIe interface module;
[0032] (2) The downlink controller of the receiving end DMA controller group reads the data according to the address and length in the circular address queue, adds the CRC check value and stores it in the queue;
[0033] (3) The uplink controller of the DMA controller group at the transmitting end reads data from the queue and verifies it. After successful verification, it is sent to the CPU at the transmitting end through the PCIe interface module.
[0034] S4: Interruption and Feedback
[0035] When data transmission is completed or verification fails, the hybrid interrupt control module triggers an interrupt signal according to the configured interrupt mode. The interrupt signal is transmitted to the corresponding CPU through the PCIe interface module. The CPU reads the status register to confirm the interrupt type and clears the interrupt flag.
[0036] Furthermore, the pre-configured circular address queue initializes 1024 address resources at 2048-byte intervals to form a circular buffer.
[0037] Furthermore, the address reuse of the circular address queue includes the sending end queue and the receiving end queue using 1024 pre-configured addresses in the order of writing. After the addresses are exhausted, the first address is automatically reused to form a circular data flow path.
[0038] Furthermore, the MSI-X interrupt mechanism configuration includes: allocating interrupt information addresses and data registers to the read / write ends of the transmitting DMA controller group; and allocating interrupt information addresses and data registers to the read / write ends of the receiving DMA controller group.
[0039] The beneficial effects of this invention are:
[0040] 1. High-efficiency bidirectional transmission: The dual DMA controller group realizes physically isolated bidirectional data streams, avoids resource contention, and improves throughput by cyclically reusing addresses using a ring buffer.
[0041] 2. Flexible interrupt control: Hybrid interrupt mode dynamically adapts to different scenarios (e.g., step-by-step mode is suitable for low-latency requests, and merging mode reduces the number of interrupts), and the MSI-X mechanism reduces interrupt handling overhead;
[0042] 3. High reliability: CRC check covers all message fields, and erroneous data is discarded and reported in real time to ensure data integrity. Attached Figure Description
[0043] Figure 1 : This is a system architecture block diagram of the present invention. Detailed Implementation
[0044] The present invention will now be described in detail with reference to the accompanying drawings and embodiments.
[0045] like Figure 1 The system structure diagram shown has the following correspondences between the components:
[0046] Sender CPU: CPU0; Receiver CPU: CPU1.
[0047] The PCIe physical interfaces are PCIE0 and PCIE1. PCIE0 is the PCIe interface module connecting the transmitting CPU (CPU0) to the FPGA chip. PCIE1 is the PCIe interface module connecting the receiving CPU (CPU1) to the FPGA chip.
[0048] The AXI controllers are AXI_ctrl0 and AXI_ctrl1. AXI_ctrl0 is the AXI bus controller controlled by CPU0, managing the transmitting-side DMA controller groups (DMA_rd021, DMA_wt120). AXI_ctrl1 is the AXI bus controller controlled by CPU1, managing the receiving-side DMA controller groups (DMA_rd120, DMA_wt021).
[0049] The DMA controller group includes a transmitter DMA controller group and a receiver DMA controller group. The transmitter DMA controller groups are DMA_rd021 and DMA_wt120.
[0050] DMA_rd021: Responsible for the downlink data flow from CPU0 to FPGA (sender → FPGA);
[0051] DMA_wt120: Responsible for the uplink data flow from FPGA to CPU0 (FPGA → sender).
[0052] The receiver DMA controller group includes DMA_rd120 and DMA_wt021.
[0053] DMA_rd120: Responsible for the downlink data flow from CPU1 to FPGA (receiver → FPGA).
[0054] DMA_wt021: Responsible for the uplink data flow from FPGA to CPU1 (FPGA → receiver).
[0055] The data buffer module includes fifo-021 and fifo-120, wherein:
[0056] fifo-021: Transmitter circular address queue, storing the data address and length in the direction of CPU0→FPGA→CPU1;
[0057] FIFO-120: Receiver circular address queue, storing the data address and length in the direction of CPU1→FPGA→CPU0.
[0058] Hybrid interrupt control module: integrated into the FPGA logic, it works in conjunction with the PCIe interface module through the MSI-X mechanism.
[0059] CRC check module: Embedded in the DMA controller data path, it verifies the transmitted data in real time.
[0060] This embodiment uses the scenario where CPU0 sends 256 bytes of data to CPU1, and CPU1 processes the data and sends it back to CPU0, combined with the attached... Figure 1 The specific method is as follows:
[0061] Step 1.1: Register and Queue Configuration
[0062] ①Sender configuration (AXI_ctrl0)
[0063] Set the message length (DN_PKT_LEN=256) and starting address (DN_PKT_ADDR=0x0000_0000) of DMA_rd021; configure the merge operation interrupt (DN_CTRL[9:8]=1) and enable the MSI-X interrupt (Dma0_rd_msi_addr_l=0x8000_0000).
[0064] ② Receiver configuration (AXI_ctrl1)
[0065] Set the address interval of DMA_wt021 (2048 bytes) and initialize the address of the 1024th entry of the FIFO-120 queue (starting from 0x0010_0000).
[0066] Step 1.2: Pre-allocation of the circular address queue
[0067] Sending queue (fifo-021): 1024 addresses are pre-configured at 2048-byte intervals (0x0000_0000 to 0x0007_F800);
[0068] Receiver queue (fifo-120): Configured according to the same rules (0x0010_0000 to 0x0017_F800).
[0069] Step 1.3: MSI-X Interrupt Configuration
[0070] ① Step-by-step operation interruption (sender end)
[0071] Interrupt information addresses: Dma0_rd_msi_addr_l=0x8000_0000 (length write interrupt), Dma0_rd_msi_addr_l=0x8000_0010 (address write interrupt);
[0072] Interrupt data: Dma0_rd_msi_data=0x01 (length), Dma0_rd_msi_data=0x02 (address).
[0073] ② Merging operation interrupted (receiving end)
[0074] Interrupt information address: Dma1_wt_msi_addr_l=0x8000_1000;
[0075] Interrupted data: Dma1_wt_msi_data=0x03 (Transmission completed).
[0076] Step 2: Data transfer from CPU0 to CPU1
[0077] Step 2.1: Write the length field to CPU0
[0078] CPU0 writes 256 bytes to the DN_PKT_LEN register via AXI_ctrl0, triggering a length write interrupt (DN_STAT
[13] =1).
[0079] CPU0 reads the interrupt status register (DN_STAT) to confirm that the length has been received.
[0080] Step 2.2: Write the address field to CPU0
[0081] CPU0 writes address 0x0000_0000 to the DN_PKT_ADDR register, triggering an address write interrupt (DN_STAT
[12] =1); DMA_rd021 starts data transmission based on the address and length.
[0082] Step 2.3: DMA_rd021 reads data and appends CRC.
[0083] DMA_rd021 reads data from 0x0000_0000, calculates the CRC1021 value and fills it to the end of the message; it stores the data in the current address of the fifo-021 queue and the queue pointer jumps to the next address.
[0084] Step 2.4: Transmission completed but interrupted
[0085] After DMA_rd021 completes the data transfer, it triggers an interrupt (DN_STAT[0]=1), and CPU0 reads the DN_PKT_SIGMA register to confirm the count.
[0086] Step 2.5: DMA_wt021 reads and verifies data.
[0087] DMA_wt021 reads data from fifo-021. After verification, it sends the data to CPU1 via PCIE1. If the verification fails, it triggers a bus error interrupt (UP_STAT
[14] =1) and sends an error code (Dma1_wt_msi_data=0x04) to CPU0.
[0088] Step 3: Data transfer from CPU1 to CPU0
[0089] Step 3.1: CPU1 processes the data and sends it back.
[0090] CPU1 modifies the message body (such as adding a "processed" flag) and writes the data to the AXI_PCIE1 address space (0x0010_0000) via PCIE1.
[0091] Step 3.2: Read DMA_rd120 and append CRC
[0092] DMA_rd120 reads data from 0x0010_0000, appends a new CRC value, and stores it in the FIFO-120 queue;
[0093] Merge operation interrupt triggered: Length and address are merged and written (high 16 bits length + low 16 bits address offset), triggering Dma1_rd_msi_data=0x05 interrupt.
[0094] Step 3.3: Read and verify DMA_wt120
[0095] DMA_wt120 reads data from fifo-120, and after successful verification, sends it to CPU0 via PCIE0.
[0096] If the verification fails, the DN_STAT
[14] interrupt is triggered and fed back to CPU1.
[0097] Step 3.4: Count Clear Interrupt
[0098] CPU0 reads the UP_PKT_SIGMA register to get the number of transmitted messages, and writes 1 to clear the interrupt queue (UP_CTRL[3]=1);
[0099] The queue pointer is reset to the beginning address, ready for the next round of transmission.
[0100] Step 4: Interruption Feedback Closed Loop
[0101] Step-by-step interrupt response: CPU0 processes length write, address write and transmission completion interrupts sequentially through AXI_ctrl0 to ensure that data is transmitted in order.
[0102] Merge interrupt response: CPU1 handles the merge operation interrupt through AXI_ctrl1, and completes data transfer and verification in a single operation.
[0103] Error recovery mechanism: When verification fails, the sending CPU re-initiates transmission based on the error code (such as 0x04) to ensure data integrity.
[0104] In this embodiment, the transmitting end DMA group (DMA_rd021, DMA_wt120) and the receiving end DMA group (DMA_rd120, DMA_wt021) operate independently to avoid data contention. FIFO-021 and FIFO-120 use addresses cyclically at 2048-byte intervals, automatically resetting after exhaustion to ensure long-term stable transmission and efficient reuse of the circular queue. Merging operation interrupts reduces the number of CPU operations, and the MSI-X mechanism accurately locates the interrupt source, enabling dynamic adaptation to hybrid interrupts. The closed-loop design of transmitting end appending and receiving end verification, combined with bus error interrupt feedback, achieves highly reliable transmission.
[0105] Through testing, this embodiment demonstrates that by leveraging the division of labor and cooperation among the dual DMA controller groups, the efficient reuse of the circular address queue, and the dynamic adaptation of hybrid interrupts, the system achieves highly reliable transmission at a rate of 10Gbps.
[0106] Finally, it should be noted that the above embodiments are only used to illustrate the present invention and are not intended to limit the technical solutions described in the present invention. Therefore, although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that modifications or equivalent substitutions can still be made to the present invention. All technical solutions and improvements that do not depart from the spirit and scope of the present invention should be covered within the scope of the claims of the present invention.
Claims
1. A data transmission system based on a dual-channel DMA controller and a hybrid interrupt mode, characterized in that, include: Dual-CPU architecture: The transmitting CPU and the receiving CPU are connected to the FPGA chip through independent PCIe physical interfaces for data transmission and reception. The FPGA chip integrates the following functional modules through hardware logic: Dual DMA controller group: This includes a transmitter DMA controller group and a receiver DMA controller group, controlled by the transmitter CPU and receiver CPU respectively, used to manage bidirectional data streams; wherein: The transmitting end DMA controller group is responsible for the bidirectional data flow between the transmitting end CPU and the FPGA chip; the receiving end DMA controller group is responsible for the bidirectional data flow between the receiving end CPU and the FPGA chip. PCIe interface module: Communicatively connected to the PCIe physical interface, used to realize data interaction and interrupt signal transmission between the FPGA chip and the CPU; Data buffer module: contains a circular address queue, which is used to temporarily store the address and length of transmitted data and to reuse address resources cyclically during data transmission; Hybrid interrupt control module: Dynamically selects the interrupt mode by configuring the interrupt control register and links with the interrupt mechanism of the PCIe interface module; CRC check module: Applies a checksum during data transmission. The receiving end verifies data integrity. If the checksum fails, an error interrupt is triggered and fed back to the corresponding CPU. The interrupt modes include: Step-by-step operation interrupt: An interrupt is triggered by writing length and address in steps; Merge operation interrupt: The merge length and address are triggered by a single operation. Interrupt count clearing: The interrupt queue is cleared in batches by reading messages and counting. The hybrid interrupt control module adopts the MSI-X mechanism, which allocates independent interrupt information addresses and data registers to the read and write ends of each DMA controller, and provides real-time feedback on the interrupt suspension status through the status register.
2. The data transmission system according to claim 1, characterized in that: The address resources of the circular address queue are initialized through pre-configuration and reused cyclically in the order of writing during transmission, forming a circular buffer with a depth of 1024 items. Each address is spaced 2048 bytes apart, which constitutes the basic unit of the circular buffer.
3. The data transmission system according to claim 1, characterized in that: The DMA controller group is implemented through hardware logic, and its control registers are mapped to the address space of the FPGA chip, supporting dynamic configuration of data transmission parameters, including message length, address offset and interrupt trigger threshold.
4. The data transmission system according to claim 1, characterized in that: The CRC check module's check value covers the message header, length field, and message body. When the receiving end fails the check, it discards the data and triggers a bus error interrupt. The bus error interrupt is fed back to the corresponding CPU through the hybrid interrupt control module.
5. A data transmission method based on the system according to any one of claims 1-4, characterized in that, Includes the following steps: S1: Initialization Configuration Configure the control registers of the sending end DMA controller group and the receiving end DMA controller group to dynamically set the message length, address offset and interrupt trigger threshold; A pre-configured circular address queue is used to initialize address resources at certain byte intervals, forming a circular buffer. Configure the interrupt mode of the hybrid interrupt control module, and allocate independent MSI-X interrupt information address and data register for each DMA controller's read / write end based on the MSI-X mechanism; S2: Data transmission from sender to receiver a. The transmitting CPU writes data into the transmitting address space of the FPGA chip through the PCIe interface module; b. The downlink controller of the transmitting end DMA controller group reads the data according to the address and length in the circular address queue, adds a CRC check value, and stores it in the queue; c. The uplink controller of the receiver's DMA controller group reads data from the queue and verifies it. After successful verification, it is sent to the receiver's CPU through the PCIe interface module. S3: Data transmission from receiver to transmitter a. The receiving CPU writes data into the receiving address space of the FPGA chip through the PCIe interface module; b. The downlink controller of the receiver DMA controller group reads the data according to the address and length in the circular address queue, adds a CRC check value, and stores it in the queue; c. The uplink controller of the transmitter DMA controller group reads data from the queue and verifies it. After successful verification, it is sent to the transmitter CPU through the PCIe interface module. S4: Interruption and Feedback When data transmission is completed or verification fails, the hybrid interrupt control module triggers an interrupt signal according to the configured interrupt mode. The interrupt signal is transmitted to the corresponding CPU through the PCIe interface module. The CPU reads the status register to confirm the interrupt type and clears the interrupt flag.
6. The data transmission method according to claim 5, characterized in that: The pre-configured circular address queue initializes 1024 address resources at 2048-byte intervals to form a circular buffer.
7. The data transmission method according to claim 6, characterized in that: The address reuse of the circular address queue includes the sending end queue and the receiving end queue using 1024 pre-configured addresses in the order of writing. After the addresses are exhausted, the first address is automatically reused to form a circular data flow path.
8. The data transmission method according to claim 7, characterized in that, The MSI-X interrupt mechanism configuration includes: Assign interrupt information addresses and data registers to the read / write ends of the transmitting DMA controller group; assign interrupt information addresses and data registers to the read / write ends of the receiving DMA controller group.